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1/* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/pci_ids.h>
15#include <asm/pci-direct.h>
16#include <asm/dma.h>
17#include <asm/io_apic.h>
18#include <asm/apic.h>
19#include <asm/iommu.h>
20#include <asm/gart.h>
21
22static void __init fix_hypertransport_config(int num, int slot, int func)
23{
24 u32 htcfg;
25 /*
26 * we found a hypertransport bus
27 * make sure that we are broadcasting
28 * interrupts to all cpus on the ht bus
29 * if we're using extended apic ids
30 */
31 htcfg = read_pci_config(num, slot, func, 0x68);
32 if (htcfg & (1 << 18)) {
33 printk(KERN_INFO "Detected use of extended apic ids "
34 "on hypertransport bus\n");
35 if ((htcfg & (1 << 17)) == 0) {
36 printk(KERN_INFO "Enabling hypertransport extended "
37 "apic interrupt broadcast\n");
38 printk(KERN_INFO "Note this is a bios bug, "
39 "please contact your hw vendor\n");
40 htcfg |= (1 << 17);
41 write_pci_config(num, slot, func, 0x68, htcfg);
42 }
43 }
44
45
46}
47
48static void __init via_bugs(int num, int slot, int func)
49{
50#ifdef CONFIG_GART_IOMMU
51 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
52 !gart_iommu_aperture_allowed) {
53 printk(KERN_INFO
54 "Looks like a VIA chipset. Disabling IOMMU."
55 " Override with iommu=allowed\n");
56 gart_iommu_aperture_disabled = 1;
57 }
58#endif
59}
60
61#ifdef CONFIG_ACPI
62#ifdef CONFIG_X86_IO_APIC
63
64static int __init nvidia_hpet_check(struct acpi_table_header *header)
65{
66 return 0;
67}
68#endif /* CONFIG_X86_IO_APIC */
69#endif /* CONFIG_ACPI */
70
71static void __init nvidia_bugs(int num, int slot, int func)
72{
73#ifdef CONFIG_ACPI
74#ifdef CONFIG_X86_IO_APIC
75 /*
76 * All timer overrides on Nvidia are
77 * wrong unless HPET is enabled.
78 * Unfortunately that's not true on many Asus boards.
79 * We don't know yet how to detect this automatically, but
80 * at least allow a command line override.
81 */
82 if (acpi_use_timer_override)
83 return;
84
85 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
86 acpi_skip_timer_override = 1;
87 printk(KERN_INFO "Nvidia board "
88 "detected. Ignoring ACPI "
89 "timer override.\n");
90 printk(KERN_INFO "If you got timer trouble "
91 "try acpi_use_timer_override\n");
92 }
93#endif
94#endif
95 /* RED-PEN skip them on mptables too? */
96
97}
98
99#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
100static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
101{
102 u32 d;
103 u8 b;
104
105 b = read_pci_config_byte(num, slot, func, 0xac);
106 b &= ~(1<<5);
107 write_pci_config_byte(num, slot, func, 0xac, b);
108
109 d = read_pci_config(num, slot, func, 0x70);
110 d |= 1<<8;
111 write_pci_config(num, slot, func, 0x70, d);
112
113 d = read_pci_config(num, slot, func, 0x8);
114 d &= 0xff;
115 return d;
116}
117
118static void __init ati_bugs(int num, int slot, int func)
119{
120 u32 d;
121 u8 b;
122
123 if (acpi_use_timer_override)
124 return;
125
126 d = ati_ixp4x0_rev(num, slot, func);
127 if (d < 0x82)
128 acpi_skip_timer_override = 1;
129 else {
130 /* check for IRQ0 interrupt swap */
131 outb(0x72, 0xcd6); b = inb(0xcd7);
132 if (!(b & 0x2))
133 acpi_skip_timer_override = 1;
134 }
135
136 if (acpi_skip_timer_override) {
137 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
138 printk(KERN_INFO "Ignoring ACPI timer override.\n");
139 printk(KERN_INFO "If you got timer trouble "
140 "try acpi_use_timer_override\n");
141 }
142}
143
144static u32 __init ati_sbx00_rev(int num, int slot, int func)
145{
146 u32 d;
147
148 d = read_pci_config(num, slot, func, 0x8);
149 d &= 0xff;
150
151 return d;
152}
153
154static void __init ati_bugs_contd(int num, int slot, int func)
155{
156 u32 d, rev;
157
158 rev = ati_sbx00_rev(num, slot, func);
159 if (rev >= 0x40)
160 acpi_fix_pin2_polarity = 1;
161
162 /*
163 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
164 * SB700: revisions 0x39, 0x3a, ...
165 * SB800: revisions 0x40, 0x41, ...
166 */
167 if (rev >= 0x39)
168 return;
169
170 if (acpi_use_timer_override)
171 return;
172
173 /* check for IRQ0 interrupt swap */
174 d = read_pci_config(num, slot, func, 0x64);
175 if (!(d & (1<<14)))
176 acpi_skip_timer_override = 1;
177
178 if (acpi_skip_timer_override) {
179 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
180 printk(KERN_INFO "Ignoring ACPI timer override.\n");
181 printk(KERN_INFO "If you got timer trouble "
182 "try acpi_use_timer_override\n");
183 }
184}
185#else
186static void __init ati_bugs(int num, int slot, int func)
187{
188}
189
190static void __init ati_bugs_contd(int num, int slot, int func)
191{
192}
193#endif
194
195#define QFLAG_APPLY_ONCE 0x1
196#define QFLAG_APPLIED 0x2
197#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
198struct chipset {
199 u32 vendor;
200 u32 device;
201 u32 class;
202 u32 class_mask;
203 u32 flags;
204 void (*f)(int num, int slot, int func);
205};
206
207/*
208 * Only works for devices on the root bus. If you add any devices
209 * not on bus 0 readd another loop level in early_quirks(). But
210 * be careful because at least the Nvidia quirk here relies on
211 * only matching on bus 0.
212 */
213static struct chipset early_qrk[] __initdata = {
214 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
215 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
216 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
217 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
218 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
219 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
221 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
223 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
224 {}
225};
226
227/**
228 * check_dev_quirk - apply early quirks to a given PCI device
229 * @num: bus number
230 * @slot: slot number
231 * @func: PCI function
232 *
233 * Check the vendor & device ID against the early quirks table.
234 *
235 * If the device is single function, let early_quirks() know so we don't
236 * poke at this device again.
237 */
238static int __init check_dev_quirk(int num, int slot, int func)
239{
240 u16 class;
241 u16 vendor;
242 u16 device;
243 u8 type;
244 int i;
245
246 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
247
248 if (class == 0xffff)
249 return -1; /* no class, treat as single function */
250
251 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
252
253 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
254
255 for (i = 0; early_qrk[i].f != NULL; i++) {
256 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
257 (early_qrk[i].vendor == vendor)) &&
258 ((early_qrk[i].device == PCI_ANY_ID) ||
259 (early_qrk[i].device == device)) &&
260 (!((early_qrk[i].class ^ class) &
261 early_qrk[i].class_mask))) {
262 if ((early_qrk[i].flags &
263 QFLAG_DONE) != QFLAG_DONE)
264 early_qrk[i].f(num, slot, func);
265 early_qrk[i].flags |= QFLAG_APPLIED;
266 }
267 }
268
269 type = read_pci_config_byte(num, slot, func,
270 PCI_HEADER_TYPE);
271 if (!(type & 0x80))
272 return -1;
273
274 return 0;
275}
276
277void __init early_quirks(void)
278{
279 int slot, func;
280
281 if (!early_pci_allowed())
282 return;
283
284 /* Poor man's PCI discovery */
285 /* Only scan the root bus */
286 for (slot = 0; slot < 32; slot++)
287 for (func = 0; func < 8; func++) {
288 /* Only probe function 0 on single fn devices */
289 if (check_dev_quirk(0, slot, func))
290 break;
291 }
292}
1// SPDX-License-Identifier: GPL-2.0
2/* Various workarounds for chipset bugs.
3 This code runs very early and can't use the regular PCI subsystem
4 The entries are keyed to PCI bridges which usually identify chipsets
5 uniquely.
6 This is only for whole classes of chipsets with specific problems which
7 need early invasive action (e.g. before the timers are initialized).
8 Most PCI device specific workarounds can be done later and should be
9 in standard PCI quirks
10 Mainboard specific bugs should be handled by DMI entries.
11 CPU specific bugs in setup.c */
12
13#include <linux/pci.h>
14#include <linux/acpi.h>
15#include <linux/delay.h>
16#include <linux/pci_ids.h>
17#include <linux/bcma/bcma.h>
18#include <linux/bcma/bcma_regs.h>
19#include <linux/platform_data/x86/apple.h>
20#include <drm/i915_drm.h>
21#include <drm/i915_pciids.h>
22#include <asm/pci-direct.h>
23#include <asm/dma.h>
24#include <asm/io_apic.h>
25#include <asm/apic.h>
26#include <asm/hpet.h>
27#include <asm/iommu.h>
28#include <asm/gart.h>
29#include <asm/irq_remapping.h>
30#include <asm/early_ioremap.h>
31
32static void __init fix_hypertransport_config(int num, int slot, int func)
33{
34 u32 htcfg;
35 /*
36 * we found a hypertransport bus
37 * make sure that we are broadcasting
38 * interrupts to all cpus on the ht bus
39 * if we're using extended apic ids
40 */
41 htcfg = read_pci_config(num, slot, func, 0x68);
42 if (htcfg & (1 << 18)) {
43 printk(KERN_INFO "Detected use of extended apic ids "
44 "on hypertransport bus\n");
45 if ((htcfg & (1 << 17)) == 0) {
46 printk(KERN_INFO "Enabling hypertransport extended "
47 "apic interrupt broadcast\n");
48 printk(KERN_INFO "Note this is a bios bug, "
49 "please contact your hw vendor\n");
50 htcfg |= (1 << 17);
51 write_pci_config(num, slot, func, 0x68, htcfg);
52 }
53 }
54
55
56}
57
58static void __init via_bugs(int num, int slot, int func)
59{
60#ifdef CONFIG_GART_IOMMU
61 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
62 !gart_iommu_aperture_allowed) {
63 printk(KERN_INFO
64 "Looks like a VIA chipset. Disabling IOMMU."
65 " Override with iommu=allowed\n");
66 gart_iommu_aperture_disabled = 1;
67 }
68#endif
69}
70
71#ifdef CONFIG_ACPI
72#ifdef CONFIG_X86_IO_APIC
73
74static int __init nvidia_hpet_check(struct acpi_table_header *header)
75{
76 return 0;
77}
78#endif /* CONFIG_X86_IO_APIC */
79#endif /* CONFIG_ACPI */
80
81static void __init nvidia_bugs(int num, int slot, int func)
82{
83#ifdef CONFIG_ACPI
84#ifdef CONFIG_X86_IO_APIC
85 /*
86 * Only applies to Nvidia root ports (bus 0) and not to
87 * Nvidia graphics cards with PCI ports on secondary buses.
88 */
89 if (num)
90 return;
91
92 /*
93 * All timer overrides on Nvidia are
94 * wrong unless HPET is enabled.
95 * Unfortunately that's not true on many Asus boards.
96 * We don't know yet how to detect this automatically, but
97 * at least allow a command line override.
98 */
99 if (acpi_use_timer_override)
100 return;
101
102 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
103 acpi_skip_timer_override = 1;
104 printk(KERN_INFO "Nvidia board "
105 "detected. Ignoring ACPI "
106 "timer override.\n");
107 printk(KERN_INFO "If you got timer trouble "
108 "try acpi_use_timer_override\n");
109 }
110#endif
111#endif
112 /* RED-PEN skip them on mptables too? */
113
114}
115
116#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
117static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
118{
119 u32 d;
120 u8 b;
121
122 b = read_pci_config_byte(num, slot, func, 0xac);
123 b &= ~(1<<5);
124 write_pci_config_byte(num, slot, func, 0xac, b);
125
126 d = read_pci_config(num, slot, func, 0x70);
127 d |= 1<<8;
128 write_pci_config(num, slot, func, 0x70, d);
129
130 d = read_pci_config(num, slot, func, 0x8);
131 d &= 0xff;
132 return d;
133}
134
135static void __init ati_bugs(int num, int slot, int func)
136{
137 u32 d;
138 u8 b;
139
140 if (acpi_use_timer_override)
141 return;
142
143 d = ati_ixp4x0_rev(num, slot, func);
144 if (d < 0x82)
145 acpi_skip_timer_override = 1;
146 else {
147 /* check for IRQ0 interrupt swap */
148 outb(0x72, 0xcd6); b = inb(0xcd7);
149 if (!(b & 0x2))
150 acpi_skip_timer_override = 1;
151 }
152
153 if (acpi_skip_timer_override) {
154 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
155 printk(KERN_INFO "Ignoring ACPI timer override.\n");
156 printk(KERN_INFO "If you got timer trouble "
157 "try acpi_use_timer_override\n");
158 }
159}
160
161static u32 __init ati_sbx00_rev(int num, int slot, int func)
162{
163 u32 d;
164
165 d = read_pci_config(num, slot, func, 0x8);
166 d &= 0xff;
167
168 return d;
169}
170
171static void __init ati_bugs_contd(int num, int slot, int func)
172{
173 u32 d, rev;
174
175 rev = ati_sbx00_rev(num, slot, func);
176 if (rev >= 0x40)
177 acpi_fix_pin2_polarity = 1;
178
179 /*
180 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
181 * SB700: revisions 0x39, 0x3a, ...
182 * SB800: revisions 0x40, 0x41, ...
183 */
184 if (rev >= 0x39)
185 return;
186
187 if (acpi_use_timer_override)
188 return;
189
190 /* check for IRQ0 interrupt swap */
191 d = read_pci_config(num, slot, func, 0x64);
192 if (!(d & (1<<14)))
193 acpi_skip_timer_override = 1;
194
195 if (acpi_skip_timer_override) {
196 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
197 printk(KERN_INFO "Ignoring ACPI timer override.\n");
198 printk(KERN_INFO "If you got timer trouble "
199 "try acpi_use_timer_override\n");
200 }
201}
202#else
203static void __init ati_bugs(int num, int slot, int func)
204{
205}
206
207static void __init ati_bugs_contd(int num, int slot, int func)
208{
209}
210#endif
211
212static void __init intel_remapping_check(int num, int slot, int func)
213{
214 u8 revision;
215 u16 device;
216
217 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
218 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
219
220 /*
221 * Revision <= 13 of all triggering devices id in this quirk
222 * have a problem draining interrupts when irq remapping is
223 * enabled, and should be flagged as broken. Additionally
224 * revision 0x22 of device id 0x3405 has this problem.
225 */
226 if (revision <= 0x13)
227 set_irq_remapping_broken();
228 else if (device == 0x3405 && revision == 0x22)
229 set_irq_remapping_broken();
230}
231
232/*
233 * Systems with Intel graphics controllers set aside memory exclusively
234 * for gfx driver use. This memory is not marked in the E820 as reserved
235 * or as RAM, and so is subject to overlap from E820 manipulation later
236 * in the boot process. On some systems, MMIO space is allocated on top,
237 * despite the efforts of the "RAM buffer" approach, which simply rounds
238 * memory boundaries up to 64M to try to catch space that may decode
239 * as RAM and so is not suitable for MMIO.
240 */
241
242#define KB(x) ((x) * 1024UL)
243#define MB(x) (KB (KB (x)))
244
245static resource_size_t __init i830_tseg_size(void)
246{
247 u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
248
249 if (!(esmramc & TSEG_ENABLE))
250 return 0;
251
252 if (esmramc & I830_TSEG_SIZE_1M)
253 return MB(1);
254 else
255 return KB(512);
256}
257
258static resource_size_t __init i845_tseg_size(void)
259{
260 u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
261 u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
262
263 if (!(esmramc & TSEG_ENABLE))
264 return 0;
265
266 switch (tseg_size) {
267 case I845_TSEG_SIZE_512K: return KB(512);
268 case I845_TSEG_SIZE_1M: return MB(1);
269 default:
270 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
271 }
272 return 0;
273}
274
275static resource_size_t __init i85x_tseg_size(void)
276{
277 u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
278
279 if (!(esmramc & TSEG_ENABLE))
280 return 0;
281
282 return MB(1);
283}
284
285static resource_size_t __init i830_mem_size(void)
286{
287 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
288}
289
290static resource_size_t __init i85x_mem_size(void)
291{
292 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
293}
294
295/*
296 * On 830/845/85x the stolen memory base isn't available in any
297 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
298 */
299static resource_size_t __init i830_stolen_base(int num, int slot, int func,
300 resource_size_t stolen_size)
301{
302 return i830_mem_size() - i830_tseg_size() - stolen_size;
303}
304
305static resource_size_t __init i845_stolen_base(int num, int slot, int func,
306 resource_size_t stolen_size)
307{
308 return i830_mem_size() - i845_tseg_size() - stolen_size;
309}
310
311static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
312 resource_size_t stolen_size)
313{
314 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
315}
316
317static resource_size_t __init i865_stolen_base(int num, int slot, int func,
318 resource_size_t stolen_size)
319{
320 u16 toud = 0;
321
322 toud = read_pci_config_16(0, 0, 0, I865_TOUD);
323
324 return toud * KB(64) + i845_tseg_size();
325}
326
327static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
328 resource_size_t stolen_size)
329{
330 u32 bsm;
331
332 /* Almost universally we can find the Graphics Base of Stolen Memory
333 * at register BSM (0x5c) in the igfx configuration space. On a few
334 * (desktop) machines this is also mirrored in the bridge device at
335 * different locations, or in the MCHBAR.
336 */
337 bsm = read_pci_config(num, slot, func, INTEL_BSM);
338
339 return bsm & INTEL_BSM_MASK;
340}
341
342static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
343 resource_size_t stolen_size)
344{
345 u64 bsm;
346
347 bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
348 bsm &= INTEL_BSM_MASK;
349 bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
350
351 return bsm;
352}
353
354static resource_size_t __init i830_stolen_size(int num, int slot, int func)
355{
356 u16 gmch_ctrl;
357 u16 gms;
358
359 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
360 gms = gmch_ctrl & I830_GMCH_GMS_MASK;
361
362 switch (gms) {
363 case I830_GMCH_GMS_STOLEN_512: return KB(512);
364 case I830_GMCH_GMS_STOLEN_1024: return MB(1);
365 case I830_GMCH_GMS_STOLEN_8192: return MB(8);
366 /* local memory isn't part of the normal address space */
367 case I830_GMCH_GMS_LOCAL: return 0;
368 default:
369 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
370 }
371
372 return 0;
373}
374
375static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
376{
377 u16 gmch_ctrl;
378 u16 gms;
379
380 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
381 gms = gmch_ctrl & I855_GMCH_GMS_MASK;
382
383 switch (gms) {
384 case I855_GMCH_GMS_STOLEN_1M: return MB(1);
385 case I855_GMCH_GMS_STOLEN_4M: return MB(4);
386 case I855_GMCH_GMS_STOLEN_8M: return MB(8);
387 case I855_GMCH_GMS_STOLEN_16M: return MB(16);
388 case I855_GMCH_GMS_STOLEN_32M: return MB(32);
389 case I915_GMCH_GMS_STOLEN_48M: return MB(48);
390 case I915_GMCH_GMS_STOLEN_64M: return MB(64);
391 case G33_GMCH_GMS_STOLEN_128M: return MB(128);
392 case G33_GMCH_GMS_STOLEN_256M: return MB(256);
393 case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
394 case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
395 case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
396 case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
397 default:
398 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
399 }
400
401 return 0;
402}
403
404static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
405{
406 u16 gmch_ctrl;
407 u16 gms;
408
409 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
410 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
411
412 return gms * MB(32);
413}
414
415static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
416{
417 u16 gmch_ctrl;
418 u16 gms;
419
420 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
421 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
422
423 return gms * MB(32);
424}
425
426static resource_size_t __init chv_stolen_size(int num, int slot, int func)
427{
428 u16 gmch_ctrl;
429 u16 gms;
430
431 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
432 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
433
434 /*
435 * 0x0 to 0x10: 32MB increments starting at 0MB
436 * 0x11 to 0x16: 4MB increments starting at 8MB
437 * 0x17 to 0x1d: 4MB increments start at 36MB
438 */
439 if (gms < 0x11)
440 return gms * MB(32);
441 else if (gms < 0x17)
442 return (gms - 0x11) * MB(4) + MB(8);
443 else
444 return (gms - 0x17) * MB(4) + MB(36);
445}
446
447static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
448{
449 u16 gmch_ctrl;
450 u16 gms;
451
452 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
453 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
454
455 /* 0x0 to 0xef: 32MB increments starting at 0MB */
456 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
457 if (gms < 0xf0)
458 return gms * MB(32);
459 else
460 return (gms - 0xf0) * MB(4) + MB(4);
461}
462
463struct intel_early_ops {
464 resource_size_t (*stolen_size)(int num, int slot, int func);
465 resource_size_t (*stolen_base)(int num, int slot, int func,
466 resource_size_t size);
467};
468
469static const struct intel_early_ops i830_early_ops __initconst = {
470 .stolen_base = i830_stolen_base,
471 .stolen_size = i830_stolen_size,
472};
473
474static const struct intel_early_ops i845_early_ops __initconst = {
475 .stolen_base = i845_stolen_base,
476 .stolen_size = i830_stolen_size,
477};
478
479static const struct intel_early_ops i85x_early_ops __initconst = {
480 .stolen_base = i85x_stolen_base,
481 .stolen_size = gen3_stolen_size,
482};
483
484static const struct intel_early_ops i865_early_ops __initconst = {
485 .stolen_base = i865_stolen_base,
486 .stolen_size = gen3_stolen_size,
487};
488
489static const struct intel_early_ops gen3_early_ops __initconst = {
490 .stolen_base = gen3_stolen_base,
491 .stolen_size = gen3_stolen_size,
492};
493
494static const struct intel_early_ops gen6_early_ops __initconst = {
495 .stolen_base = gen3_stolen_base,
496 .stolen_size = gen6_stolen_size,
497};
498
499static const struct intel_early_ops gen8_early_ops __initconst = {
500 .stolen_base = gen3_stolen_base,
501 .stolen_size = gen8_stolen_size,
502};
503
504static const struct intel_early_ops gen9_early_ops __initconst = {
505 .stolen_base = gen3_stolen_base,
506 .stolen_size = gen9_stolen_size,
507};
508
509static const struct intel_early_ops chv_early_ops __initconst = {
510 .stolen_base = gen3_stolen_base,
511 .stolen_size = chv_stolen_size,
512};
513
514static const struct intel_early_ops gen11_early_ops __initconst = {
515 .stolen_base = gen11_stolen_base,
516 .stolen_size = gen9_stolen_size,
517};
518
519/* Intel integrated GPUs for which we need to reserve "stolen memory" */
520static const struct pci_device_id intel_early_ids[] __initconst = {
521 INTEL_I830_IDS(&i830_early_ops),
522 INTEL_I845G_IDS(&i845_early_ops),
523 INTEL_I85X_IDS(&i85x_early_ops),
524 INTEL_I865G_IDS(&i865_early_ops),
525 INTEL_I915G_IDS(&gen3_early_ops),
526 INTEL_I915GM_IDS(&gen3_early_ops),
527 INTEL_I945G_IDS(&gen3_early_ops),
528 INTEL_I945GM_IDS(&gen3_early_ops),
529 INTEL_VLV_IDS(&gen6_early_ops),
530 INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
531 INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
532 INTEL_I965G_IDS(&gen3_early_ops),
533 INTEL_G33_IDS(&gen3_early_ops),
534 INTEL_I965GM_IDS(&gen3_early_ops),
535 INTEL_GM45_IDS(&gen3_early_ops),
536 INTEL_G45_IDS(&gen3_early_ops),
537 INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
538 INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
539 INTEL_SNB_D_IDS(&gen6_early_ops),
540 INTEL_SNB_M_IDS(&gen6_early_ops),
541 INTEL_IVB_M_IDS(&gen6_early_ops),
542 INTEL_IVB_D_IDS(&gen6_early_ops),
543 INTEL_HSW_IDS(&gen6_early_ops),
544 INTEL_BDW_IDS(&gen8_early_ops),
545 INTEL_CHV_IDS(&chv_early_ops),
546 INTEL_SKL_IDS(&gen9_early_ops),
547 INTEL_BXT_IDS(&gen9_early_ops),
548 INTEL_KBL_IDS(&gen9_early_ops),
549 INTEL_CFL_IDS(&gen9_early_ops),
550 INTEL_GLK_IDS(&gen9_early_ops),
551 INTEL_CNL_IDS(&gen9_early_ops),
552 INTEL_ICL_11_IDS(&gen11_early_ops),
553 INTEL_EHL_IDS(&gen11_early_ops),
554 INTEL_JSL_IDS(&gen11_early_ops),
555 INTEL_TGL_12_IDS(&gen11_early_ops),
556 INTEL_RKL_IDS(&gen11_early_ops),
557 INTEL_ADLS_IDS(&gen11_early_ops),
558 INTEL_ADLP_IDS(&gen11_early_ops),
559 INTEL_ADLN_IDS(&gen11_early_ops),
560 INTEL_RPLS_IDS(&gen11_early_ops),
561 INTEL_RPLP_IDS(&gen11_early_ops),
562};
563
564struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
565EXPORT_SYMBOL(intel_graphics_stolen_res);
566
567static void __init
568intel_graphics_stolen(int num, int slot, int func,
569 const struct intel_early_ops *early_ops)
570{
571 resource_size_t base, size;
572 resource_size_t end;
573
574 size = early_ops->stolen_size(num, slot, func);
575 base = early_ops->stolen_base(num, slot, func, size);
576
577 if (!size || !base)
578 return;
579
580 end = base + size - 1;
581
582 intel_graphics_stolen_res.start = base;
583 intel_graphics_stolen_res.end = end;
584
585 printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
586 &intel_graphics_stolen_res);
587
588 /* Mark this space as reserved */
589 e820__range_add(base, size, E820_TYPE_RESERVED);
590 e820__update_table(e820_table);
591}
592
593static void __init intel_graphics_quirks(int num, int slot, int func)
594{
595 const struct intel_early_ops *early_ops;
596 u16 device;
597 int i;
598
599 /*
600 * Reserve "stolen memory" for an integrated GPU. If we've already
601 * found one, there's nothing to do for other (discrete) GPUs.
602 */
603 if (resource_size(&intel_graphics_stolen_res))
604 return;
605
606 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
607
608 for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
609 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
610
611 if (intel_early_ids[i].device != device)
612 continue;
613
614 early_ops = (typeof(early_ops))driver_data;
615
616 intel_graphics_stolen(num, slot, func, early_ops);
617
618 return;
619 }
620}
621
622static void __init force_disable_hpet(int num, int slot, int func)
623{
624#ifdef CONFIG_HPET_TIMER
625 boot_hpet_disable = true;
626 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
627#endif
628}
629
630#define BCM4331_MMIO_SIZE 16384
631#define BCM4331_PM_CAP 0x40
632#define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
633#define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
634
635static void __init apple_airport_reset(int bus, int slot, int func)
636{
637 void __iomem *mmio;
638 u16 pmcsr;
639 u64 addr;
640 int i;
641
642 if (!x86_apple_machine)
643 return;
644
645 /* Card may have been put into PCI_D3hot by grub quirk */
646 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
647
648 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
649 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
650 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
651 mdelay(10);
652
653 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
654 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
655 pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
656 bus, slot, func);
657 return;
658 }
659 }
660
661 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
662 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
663 addr &= PCI_BASE_ADDRESS_MEM_MASK;
664
665 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
666 if (!mmio) {
667 pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
668 bus, slot, func);
669 return;
670 }
671
672 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
673
674 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
675 udelay(10);
676
677 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
678 bcma_aread32(BCMA_RESET_CTL);
679 udelay(1);
680
681 bcma_awrite32(BCMA_RESET_CTL, 0);
682 bcma_aread32(BCMA_RESET_CTL);
683 udelay(10);
684
685 early_iounmap(mmio, BCM4331_MMIO_SIZE);
686}
687
688#define QFLAG_APPLY_ONCE 0x1
689#define QFLAG_APPLIED 0x2
690#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
691struct chipset {
692 u32 vendor;
693 u32 device;
694 u32 class;
695 u32 class_mask;
696 u32 flags;
697 void (*f)(int num, int slot, int func);
698};
699
700static struct chipset early_qrk[] __initdata = {
701 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
702 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
703 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
704 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
705 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
706 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
707 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
708 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
709 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
710 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
711 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
712 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
713 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
714 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
715 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
716 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
717 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
718 0, intel_graphics_quirks },
719 /*
720 * HPET on the current version of the Baytrail platform has accuracy
721 * problems: it will halt in deep idle state - so we disable it.
722 *
723 * More details can be found in section 18.10.1.3 of the datasheet:
724 *
725 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
726 */
727 { PCI_VENDOR_ID_INTEL, 0x0f00,
728 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
729 { PCI_VENDOR_ID_BROADCOM, 0x4331,
730 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
731 {}
732};
733
734static void __init early_pci_scan_bus(int bus);
735
736/**
737 * check_dev_quirk - apply early quirks to a given PCI device
738 * @num: bus number
739 * @slot: slot number
740 * @func: PCI function
741 *
742 * Check the vendor & device ID against the early quirks table.
743 *
744 * If the device is single function, let early_pci_scan_bus() know so we don't
745 * poke at this device again.
746 */
747static int __init check_dev_quirk(int num, int slot, int func)
748{
749 u16 class;
750 u16 vendor;
751 u16 device;
752 u8 type;
753 u8 sec;
754 int i;
755
756 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
757
758 if (class == 0xffff)
759 return -1; /* no class, treat as single function */
760
761 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
762
763 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
764
765 for (i = 0; early_qrk[i].f != NULL; i++) {
766 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
767 (early_qrk[i].vendor == vendor)) &&
768 ((early_qrk[i].device == PCI_ANY_ID) ||
769 (early_qrk[i].device == device)) &&
770 (!((early_qrk[i].class ^ class) &
771 early_qrk[i].class_mask))) {
772 if ((early_qrk[i].flags &
773 QFLAG_DONE) != QFLAG_DONE)
774 early_qrk[i].f(num, slot, func);
775 early_qrk[i].flags |= QFLAG_APPLIED;
776 }
777 }
778
779 type = read_pci_config_byte(num, slot, func,
780 PCI_HEADER_TYPE);
781
782 if ((type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) {
783 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
784 if (sec > num)
785 early_pci_scan_bus(sec);
786 }
787
788 if (!(type & PCI_HEADER_TYPE_MFD))
789 return -1;
790
791 return 0;
792}
793
794static void __init early_pci_scan_bus(int bus)
795{
796 int slot, func;
797
798 /* Poor man's PCI discovery */
799 for (slot = 0; slot < 32; slot++)
800 for (func = 0; func < 8; func++) {
801 /* Only probe function 0 on single fn devices */
802 if (check_dev_quirk(bus, slot, func))
803 break;
804 }
805}
806
807void __init early_quirks(void)
808{
809 if (!early_pci_allowed())
810 return;
811
812 early_pci_scan_bus(0);
813}