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1/* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/pci_ids.h>
15#include <asm/pci-direct.h>
16#include <asm/dma.h>
17#include <asm/io_apic.h>
18#include <asm/apic.h>
19#include <asm/iommu.h>
20#include <asm/gart.h>
21
22static void __init fix_hypertransport_config(int num, int slot, int func)
23{
24 u32 htcfg;
25 /*
26 * we found a hypertransport bus
27 * make sure that we are broadcasting
28 * interrupts to all cpus on the ht bus
29 * if we're using extended apic ids
30 */
31 htcfg = read_pci_config(num, slot, func, 0x68);
32 if (htcfg & (1 << 18)) {
33 printk(KERN_INFO "Detected use of extended apic ids "
34 "on hypertransport bus\n");
35 if ((htcfg & (1 << 17)) == 0) {
36 printk(KERN_INFO "Enabling hypertransport extended "
37 "apic interrupt broadcast\n");
38 printk(KERN_INFO "Note this is a bios bug, "
39 "please contact your hw vendor\n");
40 htcfg |= (1 << 17);
41 write_pci_config(num, slot, func, 0x68, htcfg);
42 }
43 }
44
45
46}
47
48static void __init via_bugs(int num, int slot, int func)
49{
50#ifdef CONFIG_GART_IOMMU
51 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
52 !gart_iommu_aperture_allowed) {
53 printk(KERN_INFO
54 "Looks like a VIA chipset. Disabling IOMMU."
55 " Override with iommu=allowed\n");
56 gart_iommu_aperture_disabled = 1;
57 }
58#endif
59}
60
61#ifdef CONFIG_ACPI
62#ifdef CONFIG_X86_IO_APIC
63
64static int __init nvidia_hpet_check(struct acpi_table_header *header)
65{
66 return 0;
67}
68#endif /* CONFIG_X86_IO_APIC */
69#endif /* CONFIG_ACPI */
70
71static void __init nvidia_bugs(int num, int slot, int func)
72{
73#ifdef CONFIG_ACPI
74#ifdef CONFIG_X86_IO_APIC
75 /*
76 * All timer overrides on Nvidia are
77 * wrong unless HPET is enabled.
78 * Unfortunately that's not true on many Asus boards.
79 * We don't know yet how to detect this automatically, but
80 * at least allow a command line override.
81 */
82 if (acpi_use_timer_override)
83 return;
84
85 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
86 acpi_skip_timer_override = 1;
87 printk(KERN_INFO "Nvidia board "
88 "detected. Ignoring ACPI "
89 "timer override.\n");
90 printk(KERN_INFO "If you got timer trouble "
91 "try acpi_use_timer_override\n");
92 }
93#endif
94#endif
95 /* RED-PEN skip them on mptables too? */
96
97}
98
99#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
100static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
101{
102 u32 d;
103 u8 b;
104
105 b = read_pci_config_byte(num, slot, func, 0xac);
106 b &= ~(1<<5);
107 write_pci_config_byte(num, slot, func, 0xac, b);
108
109 d = read_pci_config(num, slot, func, 0x70);
110 d |= 1<<8;
111 write_pci_config(num, slot, func, 0x70, d);
112
113 d = read_pci_config(num, slot, func, 0x8);
114 d &= 0xff;
115 return d;
116}
117
118static void __init ati_bugs(int num, int slot, int func)
119{
120 u32 d;
121 u8 b;
122
123 if (acpi_use_timer_override)
124 return;
125
126 d = ati_ixp4x0_rev(num, slot, func);
127 if (d < 0x82)
128 acpi_skip_timer_override = 1;
129 else {
130 /* check for IRQ0 interrupt swap */
131 outb(0x72, 0xcd6); b = inb(0xcd7);
132 if (!(b & 0x2))
133 acpi_skip_timer_override = 1;
134 }
135
136 if (acpi_skip_timer_override) {
137 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
138 printk(KERN_INFO "Ignoring ACPI timer override.\n");
139 printk(KERN_INFO "If you got timer trouble "
140 "try acpi_use_timer_override\n");
141 }
142}
143
144static u32 __init ati_sbx00_rev(int num, int slot, int func)
145{
146 u32 d;
147
148 d = read_pci_config(num, slot, func, 0x8);
149 d &= 0xff;
150
151 return d;
152}
153
154static void __init ati_bugs_contd(int num, int slot, int func)
155{
156 u32 d, rev;
157
158 rev = ati_sbx00_rev(num, slot, func);
159 if (rev >= 0x40)
160 acpi_fix_pin2_polarity = 1;
161
162 /*
163 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
164 * SB700: revisions 0x39, 0x3a, ...
165 * SB800: revisions 0x40, 0x41, ...
166 */
167 if (rev >= 0x39)
168 return;
169
170 if (acpi_use_timer_override)
171 return;
172
173 /* check for IRQ0 interrupt swap */
174 d = read_pci_config(num, slot, func, 0x64);
175 if (!(d & (1<<14)))
176 acpi_skip_timer_override = 1;
177
178 if (acpi_skip_timer_override) {
179 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
180 printk(KERN_INFO "Ignoring ACPI timer override.\n");
181 printk(KERN_INFO "If you got timer trouble "
182 "try acpi_use_timer_override\n");
183 }
184}
185#else
186static void __init ati_bugs(int num, int slot, int func)
187{
188}
189
190static void __init ati_bugs_contd(int num, int slot, int func)
191{
192}
193#endif
194
195#define QFLAG_APPLY_ONCE 0x1
196#define QFLAG_APPLIED 0x2
197#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
198struct chipset {
199 u32 vendor;
200 u32 device;
201 u32 class;
202 u32 class_mask;
203 u32 flags;
204 void (*f)(int num, int slot, int func);
205};
206
207/*
208 * Only works for devices on the root bus. If you add any devices
209 * not on bus 0 readd another loop level in early_quirks(). But
210 * be careful because at least the Nvidia quirk here relies on
211 * only matching on bus 0.
212 */
213static struct chipset early_qrk[] __initdata = {
214 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
215 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
216 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
217 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
218 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
219 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
221 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
223 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
224 {}
225};
226
227/**
228 * check_dev_quirk - apply early quirks to a given PCI device
229 * @num: bus number
230 * @slot: slot number
231 * @func: PCI function
232 *
233 * Check the vendor & device ID against the early quirks table.
234 *
235 * If the device is single function, let early_quirks() know so we don't
236 * poke at this device again.
237 */
238static int __init check_dev_quirk(int num, int slot, int func)
239{
240 u16 class;
241 u16 vendor;
242 u16 device;
243 u8 type;
244 int i;
245
246 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
247
248 if (class == 0xffff)
249 return -1; /* no class, treat as single function */
250
251 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
252
253 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
254
255 for (i = 0; early_qrk[i].f != NULL; i++) {
256 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
257 (early_qrk[i].vendor == vendor)) &&
258 ((early_qrk[i].device == PCI_ANY_ID) ||
259 (early_qrk[i].device == device)) &&
260 (!((early_qrk[i].class ^ class) &
261 early_qrk[i].class_mask))) {
262 if ((early_qrk[i].flags &
263 QFLAG_DONE) != QFLAG_DONE)
264 early_qrk[i].f(num, slot, func);
265 early_qrk[i].flags |= QFLAG_APPLIED;
266 }
267 }
268
269 type = read_pci_config_byte(num, slot, func,
270 PCI_HEADER_TYPE);
271 if (!(type & 0x80))
272 return -1;
273
274 return 0;
275}
276
277void __init early_quirks(void)
278{
279 int slot, func;
280
281 if (!early_pci_allowed())
282 return;
283
284 /* Poor man's PCI discovery */
285 /* Only scan the root bus */
286 for (slot = 0; slot < 32; slot++)
287 for (func = 0; func < 8; func++) {
288 /* Only probe function 0 on single fn devices */
289 if (check_dev_quirk(0, slot, func))
290 break;
291 }
292}
1// SPDX-License-Identifier: GPL-2.0
2/* Various workarounds for chipset bugs.
3 This code runs very early and can't use the regular PCI subsystem
4 The entries are keyed to PCI bridges which usually identify chipsets
5 uniquely.
6 This is only for whole classes of chipsets with specific problems which
7 need early invasive action (e.g. before the timers are initialized).
8 Most PCI device specific workarounds can be done later and should be
9 in standard PCI quirks
10 Mainboard specific bugs should be handled by DMI entries.
11 CPU specific bugs in setup.c */
12
13#include <linux/pci.h>
14#include <linux/acpi.h>
15#include <linux/delay.h>
16#include <linux/pci_ids.h>
17#include <linux/bcma/bcma.h>
18#include <linux/bcma/bcma_regs.h>
19#include <linux/platform_data/x86/apple.h>
20#include <drm/i915_drm.h>
21#include <asm/pci-direct.h>
22#include <asm/dma.h>
23#include <asm/io_apic.h>
24#include <asm/apic.h>
25#include <asm/hpet.h>
26#include <asm/iommu.h>
27#include <asm/gart.h>
28#include <asm/irq_remapping.h>
29#include <asm/early_ioremap.h>
30
31#define dev_err(msg) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
32
33static void __init fix_hypertransport_config(int num, int slot, int func)
34{
35 u32 htcfg;
36 /*
37 * we found a hypertransport bus
38 * make sure that we are broadcasting
39 * interrupts to all cpus on the ht bus
40 * if we're using extended apic ids
41 */
42 htcfg = read_pci_config(num, slot, func, 0x68);
43 if (htcfg & (1 << 18)) {
44 printk(KERN_INFO "Detected use of extended apic ids "
45 "on hypertransport bus\n");
46 if ((htcfg & (1 << 17)) == 0) {
47 printk(KERN_INFO "Enabling hypertransport extended "
48 "apic interrupt broadcast\n");
49 printk(KERN_INFO "Note this is a bios bug, "
50 "please contact your hw vendor\n");
51 htcfg |= (1 << 17);
52 write_pci_config(num, slot, func, 0x68, htcfg);
53 }
54 }
55
56
57}
58
59static void __init via_bugs(int num, int slot, int func)
60{
61#ifdef CONFIG_GART_IOMMU
62 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
63 !gart_iommu_aperture_allowed) {
64 printk(KERN_INFO
65 "Looks like a VIA chipset. Disabling IOMMU."
66 " Override with iommu=allowed\n");
67 gart_iommu_aperture_disabled = 1;
68 }
69#endif
70}
71
72#ifdef CONFIG_ACPI
73#ifdef CONFIG_X86_IO_APIC
74
75static int __init nvidia_hpet_check(struct acpi_table_header *header)
76{
77 return 0;
78}
79#endif /* CONFIG_X86_IO_APIC */
80#endif /* CONFIG_ACPI */
81
82static void __init nvidia_bugs(int num, int slot, int func)
83{
84#ifdef CONFIG_ACPI
85#ifdef CONFIG_X86_IO_APIC
86 /*
87 * Only applies to Nvidia root ports (bus 0) and not to
88 * Nvidia graphics cards with PCI ports on secondary buses.
89 */
90 if (num)
91 return;
92
93 /*
94 * All timer overrides on Nvidia are
95 * wrong unless HPET is enabled.
96 * Unfortunately that's not true on many Asus boards.
97 * We don't know yet how to detect this automatically, but
98 * at least allow a command line override.
99 */
100 if (acpi_use_timer_override)
101 return;
102
103 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
104 acpi_skip_timer_override = 1;
105 printk(KERN_INFO "Nvidia board "
106 "detected. Ignoring ACPI "
107 "timer override.\n");
108 printk(KERN_INFO "If you got timer trouble "
109 "try acpi_use_timer_override\n");
110 }
111#endif
112#endif
113 /* RED-PEN skip them on mptables too? */
114
115}
116
117#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
118static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
119{
120 u32 d;
121 u8 b;
122
123 b = read_pci_config_byte(num, slot, func, 0xac);
124 b &= ~(1<<5);
125 write_pci_config_byte(num, slot, func, 0xac, b);
126
127 d = read_pci_config(num, slot, func, 0x70);
128 d |= 1<<8;
129 write_pci_config(num, slot, func, 0x70, d);
130
131 d = read_pci_config(num, slot, func, 0x8);
132 d &= 0xff;
133 return d;
134}
135
136static void __init ati_bugs(int num, int slot, int func)
137{
138 u32 d;
139 u8 b;
140
141 if (acpi_use_timer_override)
142 return;
143
144 d = ati_ixp4x0_rev(num, slot, func);
145 if (d < 0x82)
146 acpi_skip_timer_override = 1;
147 else {
148 /* check for IRQ0 interrupt swap */
149 outb(0x72, 0xcd6); b = inb(0xcd7);
150 if (!(b & 0x2))
151 acpi_skip_timer_override = 1;
152 }
153
154 if (acpi_skip_timer_override) {
155 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
156 printk(KERN_INFO "Ignoring ACPI timer override.\n");
157 printk(KERN_INFO "If you got timer trouble "
158 "try acpi_use_timer_override\n");
159 }
160}
161
162static u32 __init ati_sbx00_rev(int num, int slot, int func)
163{
164 u32 d;
165
166 d = read_pci_config(num, slot, func, 0x8);
167 d &= 0xff;
168
169 return d;
170}
171
172static void __init ati_bugs_contd(int num, int slot, int func)
173{
174 u32 d, rev;
175
176 rev = ati_sbx00_rev(num, slot, func);
177 if (rev >= 0x40)
178 acpi_fix_pin2_polarity = 1;
179
180 /*
181 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
182 * SB700: revisions 0x39, 0x3a, ...
183 * SB800: revisions 0x40, 0x41, ...
184 */
185 if (rev >= 0x39)
186 return;
187
188 if (acpi_use_timer_override)
189 return;
190
191 /* check for IRQ0 interrupt swap */
192 d = read_pci_config(num, slot, func, 0x64);
193 if (!(d & (1<<14)))
194 acpi_skip_timer_override = 1;
195
196 if (acpi_skip_timer_override) {
197 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
198 printk(KERN_INFO "Ignoring ACPI timer override.\n");
199 printk(KERN_INFO "If you got timer trouble "
200 "try acpi_use_timer_override\n");
201 }
202}
203#else
204static void __init ati_bugs(int num, int slot, int func)
205{
206}
207
208static void __init ati_bugs_contd(int num, int slot, int func)
209{
210}
211#endif
212
213static void __init intel_remapping_check(int num, int slot, int func)
214{
215 u8 revision;
216 u16 device;
217
218 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
219 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
220
221 /*
222 * Revision <= 13 of all triggering devices id in this quirk
223 * have a problem draining interrupts when irq remapping is
224 * enabled, and should be flagged as broken. Additionally
225 * revision 0x22 of device id 0x3405 has this problem.
226 */
227 if (revision <= 0x13)
228 set_irq_remapping_broken();
229 else if (device == 0x3405 && revision == 0x22)
230 set_irq_remapping_broken();
231}
232
233/*
234 * Systems with Intel graphics controllers set aside memory exclusively
235 * for gfx driver use. This memory is not marked in the E820 as reserved
236 * or as RAM, and so is subject to overlap from E820 manipulation later
237 * in the boot process. On some systems, MMIO space is allocated on top,
238 * despite the efforts of the "RAM buffer" approach, which simply rounds
239 * memory boundaries up to 64M to try to catch space that may decode
240 * as RAM and so is not suitable for MMIO.
241 */
242
243#define KB(x) ((x) * 1024UL)
244#define MB(x) (KB (KB (x)))
245
246static resource_size_t __init i830_tseg_size(void)
247{
248 u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
249
250 if (!(esmramc & TSEG_ENABLE))
251 return 0;
252
253 if (esmramc & I830_TSEG_SIZE_1M)
254 return MB(1);
255 else
256 return KB(512);
257}
258
259static resource_size_t __init i845_tseg_size(void)
260{
261 u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
262 u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
263
264 if (!(esmramc & TSEG_ENABLE))
265 return 0;
266
267 switch (tseg_size) {
268 case I845_TSEG_SIZE_512K: return KB(512);
269 case I845_TSEG_SIZE_1M: return MB(1);
270 default:
271 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
272 }
273 return 0;
274}
275
276static resource_size_t __init i85x_tseg_size(void)
277{
278 u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
279
280 if (!(esmramc & TSEG_ENABLE))
281 return 0;
282
283 return MB(1);
284}
285
286static resource_size_t __init i830_mem_size(void)
287{
288 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
289}
290
291static resource_size_t __init i85x_mem_size(void)
292{
293 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
294}
295
296/*
297 * On 830/845/85x the stolen memory base isn't available in any
298 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
299 */
300static resource_size_t __init i830_stolen_base(int num, int slot, int func,
301 resource_size_t stolen_size)
302{
303 return i830_mem_size() - i830_tseg_size() - stolen_size;
304}
305
306static resource_size_t __init i845_stolen_base(int num, int slot, int func,
307 resource_size_t stolen_size)
308{
309 return i830_mem_size() - i845_tseg_size() - stolen_size;
310}
311
312static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
313 resource_size_t stolen_size)
314{
315 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
316}
317
318static resource_size_t __init i865_stolen_base(int num, int slot, int func,
319 resource_size_t stolen_size)
320{
321 u16 toud = 0;
322
323 toud = read_pci_config_16(0, 0, 0, I865_TOUD);
324
325 return toud * KB(64) + i845_tseg_size();
326}
327
328static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
329 resource_size_t stolen_size)
330{
331 u32 bsm;
332
333 /* Almost universally we can find the Graphics Base of Stolen Memory
334 * at register BSM (0x5c) in the igfx configuration space. On a few
335 * (desktop) machines this is also mirrored in the bridge device at
336 * different locations, or in the MCHBAR.
337 */
338 bsm = read_pci_config(num, slot, func, INTEL_BSM);
339
340 return bsm & INTEL_BSM_MASK;
341}
342
343static resource_size_t __init i830_stolen_size(int num, int slot, int func)
344{
345 u16 gmch_ctrl;
346 u16 gms;
347
348 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
349 gms = gmch_ctrl & I830_GMCH_GMS_MASK;
350
351 switch (gms) {
352 case I830_GMCH_GMS_STOLEN_512: return KB(512);
353 case I830_GMCH_GMS_STOLEN_1024: return MB(1);
354 case I830_GMCH_GMS_STOLEN_8192: return MB(8);
355 /* local memory isn't part of the normal address space */
356 case I830_GMCH_GMS_LOCAL: return 0;
357 default:
358 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
359 }
360
361 return 0;
362}
363
364static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
365{
366 u16 gmch_ctrl;
367 u16 gms;
368
369 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
370 gms = gmch_ctrl & I855_GMCH_GMS_MASK;
371
372 switch (gms) {
373 case I855_GMCH_GMS_STOLEN_1M: return MB(1);
374 case I855_GMCH_GMS_STOLEN_4M: return MB(4);
375 case I855_GMCH_GMS_STOLEN_8M: return MB(8);
376 case I855_GMCH_GMS_STOLEN_16M: return MB(16);
377 case I855_GMCH_GMS_STOLEN_32M: return MB(32);
378 case I915_GMCH_GMS_STOLEN_48M: return MB(48);
379 case I915_GMCH_GMS_STOLEN_64M: return MB(64);
380 case G33_GMCH_GMS_STOLEN_128M: return MB(128);
381 case G33_GMCH_GMS_STOLEN_256M: return MB(256);
382 case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
383 case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
384 case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
385 case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
386 default:
387 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
388 }
389
390 return 0;
391}
392
393static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
394{
395 u16 gmch_ctrl;
396 u16 gms;
397
398 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
399 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
400
401 return gms * MB(32);
402}
403
404static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
405{
406 u16 gmch_ctrl;
407 u16 gms;
408
409 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
410 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
411
412 return gms * MB(32);
413}
414
415static resource_size_t __init chv_stolen_size(int num, int slot, int func)
416{
417 u16 gmch_ctrl;
418 u16 gms;
419
420 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
421 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
422
423 /*
424 * 0x0 to 0x10: 32MB increments starting at 0MB
425 * 0x11 to 0x16: 4MB increments starting at 8MB
426 * 0x17 to 0x1d: 4MB increments start at 36MB
427 */
428 if (gms < 0x11)
429 return gms * MB(32);
430 else if (gms < 0x17)
431 return (gms - 0x11) * MB(4) + MB(8);
432 else
433 return (gms - 0x17) * MB(4) + MB(36);
434}
435
436static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
437{
438 u16 gmch_ctrl;
439 u16 gms;
440
441 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
442 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
443
444 /* 0x0 to 0xef: 32MB increments starting at 0MB */
445 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
446 if (gms < 0xf0)
447 return gms * MB(32);
448 else
449 return (gms - 0xf0) * MB(4) + MB(4);
450}
451
452struct intel_early_ops {
453 resource_size_t (*stolen_size)(int num, int slot, int func);
454 resource_size_t (*stolen_base)(int num, int slot, int func,
455 resource_size_t size);
456};
457
458static const struct intel_early_ops i830_early_ops __initconst = {
459 .stolen_base = i830_stolen_base,
460 .stolen_size = i830_stolen_size,
461};
462
463static const struct intel_early_ops i845_early_ops __initconst = {
464 .stolen_base = i845_stolen_base,
465 .stolen_size = i830_stolen_size,
466};
467
468static const struct intel_early_ops i85x_early_ops __initconst = {
469 .stolen_base = i85x_stolen_base,
470 .stolen_size = gen3_stolen_size,
471};
472
473static const struct intel_early_ops i865_early_ops __initconst = {
474 .stolen_base = i865_stolen_base,
475 .stolen_size = gen3_stolen_size,
476};
477
478static const struct intel_early_ops gen3_early_ops __initconst = {
479 .stolen_base = gen3_stolen_base,
480 .stolen_size = gen3_stolen_size,
481};
482
483static const struct intel_early_ops gen6_early_ops __initconst = {
484 .stolen_base = gen3_stolen_base,
485 .stolen_size = gen6_stolen_size,
486};
487
488static const struct intel_early_ops gen8_early_ops __initconst = {
489 .stolen_base = gen3_stolen_base,
490 .stolen_size = gen8_stolen_size,
491};
492
493static const struct intel_early_ops gen9_early_ops __initconst = {
494 .stolen_base = gen3_stolen_base,
495 .stolen_size = gen9_stolen_size,
496};
497
498static const struct intel_early_ops chv_early_ops __initconst = {
499 .stolen_base = gen3_stolen_base,
500 .stolen_size = chv_stolen_size,
501};
502
503static const struct pci_device_id intel_early_ids[] __initconst = {
504 INTEL_I830_IDS(&i830_early_ops),
505 INTEL_I845G_IDS(&i845_early_ops),
506 INTEL_I85X_IDS(&i85x_early_ops),
507 INTEL_I865G_IDS(&i865_early_ops),
508 INTEL_I915G_IDS(&gen3_early_ops),
509 INTEL_I915GM_IDS(&gen3_early_ops),
510 INTEL_I945G_IDS(&gen3_early_ops),
511 INTEL_I945GM_IDS(&gen3_early_ops),
512 INTEL_VLV_IDS(&gen6_early_ops),
513 INTEL_PINEVIEW_IDS(&gen3_early_ops),
514 INTEL_I965G_IDS(&gen3_early_ops),
515 INTEL_G33_IDS(&gen3_early_ops),
516 INTEL_I965GM_IDS(&gen3_early_ops),
517 INTEL_GM45_IDS(&gen3_early_ops),
518 INTEL_G45_IDS(&gen3_early_ops),
519 INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
520 INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
521 INTEL_SNB_D_IDS(&gen6_early_ops),
522 INTEL_SNB_M_IDS(&gen6_early_ops),
523 INTEL_IVB_M_IDS(&gen6_early_ops),
524 INTEL_IVB_D_IDS(&gen6_early_ops),
525 INTEL_HSW_IDS(&gen6_early_ops),
526 INTEL_BDW_IDS(&gen8_early_ops),
527 INTEL_CHV_IDS(&chv_early_ops),
528 INTEL_SKL_IDS(&gen9_early_ops),
529 INTEL_BXT_IDS(&gen9_early_ops),
530 INTEL_KBL_IDS(&gen9_early_ops),
531 INTEL_CFL_IDS(&gen9_early_ops),
532 INTEL_GLK_IDS(&gen9_early_ops),
533 INTEL_CNL_IDS(&gen9_early_ops),
534};
535
536struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
537EXPORT_SYMBOL(intel_graphics_stolen_res);
538
539static void __init
540intel_graphics_stolen(int num, int slot, int func,
541 const struct intel_early_ops *early_ops)
542{
543 resource_size_t base, size;
544 resource_size_t end;
545
546 size = early_ops->stolen_size(num, slot, func);
547 base = early_ops->stolen_base(num, slot, func, size);
548
549 if (!size || !base)
550 return;
551
552 end = base + size - 1;
553
554 intel_graphics_stolen_res.start = base;
555 intel_graphics_stolen_res.end = end;
556
557 printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
558 &intel_graphics_stolen_res);
559
560 /* Mark this space as reserved */
561 e820__range_add(base, size, E820_TYPE_RESERVED);
562 e820__update_table(e820_table);
563}
564
565static void __init intel_graphics_quirks(int num, int slot, int func)
566{
567 const struct intel_early_ops *early_ops;
568 u16 device;
569 int i;
570
571 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
572
573 for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
574 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
575
576 if (intel_early_ids[i].device != device)
577 continue;
578
579 early_ops = (typeof(early_ops))driver_data;
580
581 intel_graphics_stolen(num, slot, func, early_ops);
582
583 return;
584 }
585}
586
587static void __init force_disable_hpet(int num, int slot, int func)
588{
589#ifdef CONFIG_HPET_TIMER
590 boot_hpet_disable = true;
591 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
592#endif
593}
594
595#define BCM4331_MMIO_SIZE 16384
596#define BCM4331_PM_CAP 0x40
597#define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
598#define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
599
600static void __init apple_airport_reset(int bus, int slot, int func)
601{
602 void __iomem *mmio;
603 u16 pmcsr;
604 u64 addr;
605 int i;
606
607 if (!x86_apple_machine)
608 return;
609
610 /* Card may have been put into PCI_D3hot by grub quirk */
611 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
612
613 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
614 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
615 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
616 mdelay(10);
617
618 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
619 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
620 dev_err("Cannot power up Apple AirPort card\n");
621 return;
622 }
623 }
624
625 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
626 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
627 addr &= PCI_BASE_ADDRESS_MEM_MASK;
628
629 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
630 if (!mmio) {
631 dev_err("Cannot iomap Apple AirPort card\n");
632 return;
633 }
634
635 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
636
637 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
638 udelay(10);
639
640 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
641 bcma_aread32(BCMA_RESET_CTL);
642 udelay(1);
643
644 bcma_awrite32(BCMA_RESET_CTL, 0);
645 bcma_aread32(BCMA_RESET_CTL);
646 udelay(10);
647
648 early_iounmap(mmio, BCM4331_MMIO_SIZE);
649}
650
651#define QFLAG_APPLY_ONCE 0x1
652#define QFLAG_APPLIED 0x2
653#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
654struct chipset {
655 u32 vendor;
656 u32 device;
657 u32 class;
658 u32 class_mask;
659 u32 flags;
660 void (*f)(int num, int slot, int func);
661};
662
663static struct chipset early_qrk[] __initdata = {
664 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
665 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
666 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
667 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
668 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
669 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
670 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
671 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
672 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
673 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
674 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
675 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
676 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
677 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
678 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
679 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
680 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
681 QFLAG_APPLY_ONCE, intel_graphics_quirks },
682 /*
683 * HPET on the current version of the Baytrail platform has accuracy
684 * problems: it will halt in deep idle state - so we disable it.
685 *
686 * More details can be found in section 18.10.1.3 of the datasheet:
687 *
688 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
689 */
690 { PCI_VENDOR_ID_INTEL, 0x0f00,
691 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
692 { PCI_VENDOR_ID_BROADCOM, 0x4331,
693 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
694 {}
695};
696
697static void __init early_pci_scan_bus(int bus);
698
699/**
700 * check_dev_quirk - apply early quirks to a given PCI device
701 * @num: bus number
702 * @slot: slot number
703 * @func: PCI function
704 *
705 * Check the vendor & device ID against the early quirks table.
706 *
707 * If the device is single function, let early_pci_scan_bus() know so we don't
708 * poke at this device again.
709 */
710static int __init check_dev_quirk(int num, int slot, int func)
711{
712 u16 class;
713 u16 vendor;
714 u16 device;
715 u8 type;
716 u8 sec;
717 int i;
718
719 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
720
721 if (class == 0xffff)
722 return -1; /* no class, treat as single function */
723
724 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
725
726 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
727
728 for (i = 0; early_qrk[i].f != NULL; i++) {
729 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
730 (early_qrk[i].vendor == vendor)) &&
731 ((early_qrk[i].device == PCI_ANY_ID) ||
732 (early_qrk[i].device == device)) &&
733 (!((early_qrk[i].class ^ class) &
734 early_qrk[i].class_mask))) {
735 if ((early_qrk[i].flags &
736 QFLAG_DONE) != QFLAG_DONE)
737 early_qrk[i].f(num, slot, func);
738 early_qrk[i].flags |= QFLAG_APPLIED;
739 }
740 }
741
742 type = read_pci_config_byte(num, slot, func,
743 PCI_HEADER_TYPE);
744
745 if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
746 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
747 if (sec > num)
748 early_pci_scan_bus(sec);
749 }
750
751 if (!(type & 0x80))
752 return -1;
753
754 return 0;
755}
756
757static void __init early_pci_scan_bus(int bus)
758{
759 int slot, func;
760
761 /* Poor man's PCI discovery */
762 for (slot = 0; slot < 32; slot++)
763 for (func = 0; func < 8; func++) {
764 /* Only probe function 0 on single fn devices */
765 if (check_dev_quirk(bus, slot, func))
766 break;
767 }
768}
769
770void __init early_quirks(void)
771{
772 if (!early_pci_allowed())
773 return;
774
775 early_pci_scan_bus(0);
776}