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1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/acpi.h>
25#include <linux/kallsyms.h>
26#include <linux/dmi.h>
27#include <linux/pci-aspm.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/ktime.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h"
33
34/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
40static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
41{
42 dev->mmio_always_on = 1;
43}
44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
46
47/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
51static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
52{
53 dev->broken_parity_status = 1; /* This device gives false positives */
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
58/* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
60static void quirk_passive_release(struct pci_dev *dev)
61{
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75}
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
78
79/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
85
86static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
87{
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 }
92}
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
104
105/*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
109static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110{
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122}
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
125/*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
128static void __devinit quirk_nopcipci(struct pci_dev *dev)
129{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134}
135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
137
138static void __devinit quirk_nopciamd(struct pci_dev *dev)
139{
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147}
148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
149
150/*
151 * Triton requires workarounds to be used by the drivers
152 */
153static void __devinit quirk_triton(struct pci_dev *dev)
154{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159}
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
164
165/*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
169 * and http://www.georgebreese.com/net/software/#PCI
170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
176static void quirk_vialatency(struct pci_dev *dev)
177{
178 struct pci_dev *p;
179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
187 if (p->revision < 0x40 || p->revision > 0x42)
188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
193 /* Check for buggy part revisions */
194 if (p->revision < 0x10 || p->revision > 0x12)
195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
206 * both Linux and Windows this isn't enough, and we have seen
207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218exit:
219 pci_dev_put(p);
220}
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224/* Must restore this on a resume from RAM */
225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
228
229/*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
232static void __devinit quirk_viaetbf(struct pci_dev *dev)
233{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238}
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240
241static void __devinit quirk_vsfx(struct pci_dev *dev)
242{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247}
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
249
250/*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
256static void __init quirk_alimagik(struct pci_dev *dev)
257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262}
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
265
266/*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
270static void __devinit quirk_natoma(struct pci_dev *dev)
271{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276}
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
283
284/*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
288static void __devinit quirk_citrine(struct pci_dev *dev)
289{
290 dev->cfg_size = 0xA0;
291}
292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
293
294/*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
298static void __devinit quirk_s3_64M(struct pci_dev *dev)
299{
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306}
307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
309
310/*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
316static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
317{
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
327static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name)
329{
330 region &= ~(size-1);
331 if (region) {
332 struct pci_bus_region bus_region;
333 struct resource *res = dev->resource + nr;
334
335 res->name = pci_name(dev);
336 res->start = region;
337 res->end = region + size - 1;
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space. */
341 bus_region.start = res->start;
342 bus_region.end = res->end;
343 pcibios_bus_to_resource(dev, res, &bus_region);
344
345 if (pci_claim_resource(dev, nr) == 0)
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
347 res, name);
348 }
349}
350
351/*
352 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */
355static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
356{
357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
359 request_region(0x3b0, 0x0C, "RadeonIGP");
360 request_region(0x3d3, 0x01, "RadeonIGP");
361}
362DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
363
364/*
365 * Let's make the southbridge information explicit instead
366 * of having to worry about people probing the ACPI areas,
367 * for example.. (Yes, it happens, and if you read the wrong
368 * ACPI register it will put the machine to sleep with no
369 * way of waking it up again. Bummer).
370 *
371 * ALI M7101: Two IO regions pointed to by words at
372 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers)
374 */
375static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
376{
377 u16 region;
378
379 pci_read_config_word(dev, 0xE0, ®ion);
380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
381 pci_read_config_word(dev, 0xE2, ®ion);
382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
383}
384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
385
386static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
387{
388 u32 devres;
389 u32 mask, size, base;
390
391 pci_read_config_dword(dev, port, &devres);
392 if ((devres & enable) != enable)
393 return;
394 mask = (devres >> 16) & 15;
395 base = devres & 0xffff;
396 size = 16;
397 for (;;) {
398 unsigned bit = size >> 1;
399 if ((bit & mask) == bit)
400 break;
401 size = bit;
402 }
403 /*
404 * For now we only print it out. Eventually we'll want to
405 * reserve it (at least if it's in the 0x1000+ range), but
406 * let's get enough confirmation reports first.
407 */
408 base &= -size;
409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
410}
411
412static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413{
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 base = devres & 0xffff0000;
421 mask = (devres & 0x3f) << 16;
422 size = 128 << 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it, but let's get enough confirmation reports first.
432 */
433 base &= -size;
434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
435}
436
437/*
438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
439 * 0x40 (64 bytes of ACPI registers)
440 * 0x90 (16 bytes of SMB registers)
441 * and a few strange programmable PIIX4 device resources.
442 */
443static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
444{
445 u32 region, res_a;
446
447 pci_read_config_dword(dev, 0x40, ®ion);
448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
449 pci_read_config_dword(dev, 0x90, ®ion);
450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
451
452 /* Device resource A has enables for some of the other ones */
453 pci_read_config_dword(dev, 0x5c, &res_a);
454
455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
457
458 /* Device resource D is just bitfields for static resources */
459
460 /* Device 12 enabled? */
461 if (res_a & (1 << 29)) {
462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
464 }
465 /* Device 13 enabled? */
466 if (res_a & (1 << 30)) {
467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
469 }
470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
472}
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
475
476#define ICH_PMBASE 0x40
477#define ICH_ACPI_CNTL 0x44
478#define ICH4_ACPI_EN 0x10
479#define ICH6_ACPI_EN 0x80
480#define ICH4_GPIOBASE 0x58
481#define ICH4_GPIO_CNTL 0x5c
482#define ICH4_GPIO_EN 0x10
483#define ICH6_GPIOBASE 0x48
484#define ICH6_GPIO_CNTL 0x4c
485#define ICH6_GPIO_EN 0x10
486
487/*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{
494 u32 region;
495 u8 enable;
496
497 /*
498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
499 * with low legacy (and fixed) ports. We don't know the decoding
500 * priority and can't tell whether the legacy device or the one created
501 * here is really at that address. This happens on boards with broken
502 * BIOSes.
503 */
504
505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
506 if (enable & ICH4_ACPI_EN) {
507 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 if (region >= PCIBIOS_MIN_IO)
510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
511 "ICH4 ACPI/GPIO/TCO");
512 }
513
514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
515 if (enable & ICH4_GPIO_EN) {
516 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
517 region &= PCI_BASE_ADDRESS_IO_MASK;
518 if (region >= PCIBIOS_MIN_IO)
519 quirk_io_region(dev, region, 64,
520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
521 }
522}
523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
533
534static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
535{
536 u32 region;
537 u8 enable;
538
539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
540 if (enable & ICH6_ACPI_EN) {
541 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
542 region &= PCI_BASE_ADDRESS_IO_MASK;
543 if (region >= PCIBIOS_MIN_IO)
544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
545 "ICH6 ACPI/GPIO/TCO");
546 }
547
548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
549 if (enable & ICH6_GPIO_EN) {
550 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
551 region &= PCI_BASE_ADDRESS_IO_MASK;
552 if (region >= PCIBIOS_MIN_IO)
553 quirk_io_region(dev, region, 64,
554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
555 }
556}
557
558static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559{
560 u32 val;
561 u32 size, base;
562
563 pci_read_config_dword(dev, reg, &val);
564
565 /* Enabled? */
566 if (!(val & 1))
567 return;
568 base = val & 0xfffc;
569 if (dynsize) {
570 /*
571 * This is not correct. It is 16, 32 or 64 bytes depending on
572 * register D31:F0:ADh bits 5:4.
573 *
574 * But this gets us at least _part_ of it.
575 */
576 size = 16;
577 } else {
578 size = 128;
579 }
580 base &= ~(size-1);
581
582 /* Just print it out for now. We should reserve it after more debugging */
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584}
585
586static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
587{
588 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev);
590
591 /* ICH6-specific generic IO decode */
592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
594}
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597
598static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599{
600 u32 val;
601 u32 mask, base;
602
603 pci_read_config_dword(dev, reg, &val);
604
605 /* Enabled? */
606 if (!(val & 1))
607 return;
608
609 /*
610 * IO base in bits 15:2, mask in bits 23:18, both
611 * are dword-based
612 */
613 base = val & 0xfffc;
614 mask = (val >> 16) & 0xfc;
615 mask |= 3;
616
617 /* Just print it out for now. We should reserve it after more debugging */
618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
619}
620
621/* ICH7-10 has the same common LPC generic IO decode registers */
622static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
623{
624 /* We share the common ACPI/GPIO decode with ICH6 */
625 ich6_lpc_acpi_gpio(dev);
626
627 /* And have 4 ICH7+ generic decodes */
628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
632}
633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
646
647/*
648 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */
651static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
652{
653 u32 region;
654
655 if (dev->revision & 0x10) {
656 pci_read_config_dword(dev, 0x48, ®ion);
657 region &= PCI_BASE_ADDRESS_IO_MASK;
658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
659 }
660}
661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
662
663/*
664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
665 * 0x48 (256 bytes of ACPI registers)
666 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers)
668 */
669static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
670{
671 u16 hm;
672 u32 smb;
673
674 quirk_vt82c586_acpi(dev);
675
676 pci_read_config_word(dev, 0x70, &hm);
677 hm &= PCI_BASE_ADDRESS_IO_MASK;
678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
679
680 pci_read_config_dword(dev, 0x90, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
685
686/*
687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
688 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers)
690 */
691static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
692{
693 u16 pm, smb;
694
695 pci_read_config_word(dev, 0x88, &pm);
696 pm &= PCI_BASE_ADDRESS_IO_MASK;
697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
698
699 pci_read_config_word(dev, 0xd0, &smb);
700 smb &= PCI_BASE_ADDRESS_IO_MASK;
701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
702}
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
704
705/*
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment
708 */
709static void __devinit quirk_xio2000a(struct pci_dev *dev)
710{
711 struct pci_dev *pdev;
712 u16 command;
713
714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
715 "secondary bus fast back-to-back transfers disabled\n");
716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
717 pci_read_config_word(pdev, PCI_COMMAND, &command);
718 if (command & PCI_COMMAND_FAST_BACK)
719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
720 }
721}
722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
723 quirk_xio2000a);
724
725#ifdef CONFIG_X86_IO_APIC
726
727#include <asm/io_apic.h>
728
729/*
730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
731 * devices to the external APIC.
732 *
733 * TODO: When we have device-specific interrupt routers,
734 * this code will go away from quirks.
735 */
736static void quirk_via_ioapic(struct pci_dev *dev)
737{
738 u8 tmp;
739
740 if (nr_ioapics < 1)
741 tmp = 0; /* nothing routed to external APIC */
742 else
743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
744
745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
746 tmp == 0 ? "Disa" : "Ena");
747
748 /* Offset 0x58: External APIC IRQ output control */
749 pci_write_config_byte (dev, 0x58, tmp);
750}
751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
753
754/*
755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
756 * This leads to doubled level interrupt rates.
757 * Set this bit to get rid of cycle wastage.
758 * Otherwise uncritical.
759 */
760static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
761{
762 u8 misc_control2;
763#define BYPASS_APIC_DEASSERT 8
764
765 pci_read_config_byte(dev, 0x5B, &misc_control2);
766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
769 }
770}
771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
773
774/*
775 * The AMD io apic can hang the box when an apic irq is masked.
776 * We check all revs >= B0 (yet not in the pre production!) as the bug
777 * is currently marked NoFix
778 *
779 * We have multiple reports of hangs with this chipset that went away with
780 * noapic specified. For the moment we assume it's the erratum. We may be wrong
781 * of course. However the advice is demonstrably good even if so..
782 */
783static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
784{
785 if (dev->revision >= 0x02) {
786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
788 }
789}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791
792static void __init quirk_ioapic_rmw(struct pci_dev *dev)
793{
794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1;
796}
797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
798#endif /* CONFIG_X86_IO_APIC */
799
800/*
801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */
804static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{
806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
808 "disabling PCI-X MMRBC\n", dev->revision);
809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
810 }
811}
812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
813
814/*
815 * FIXME: it is questionable that quirk_via_acpi
816 * is needed. It shows up as an ISA bridge, and does not
817 * support the PCI_INTERRUPT_LINE register at all. Therefore
818 * it seems like setting the pci_dev's 'irq' to the
819 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik
821 */
822static void __devinit quirk_via_acpi(struct pci_dev *d)
823{
824 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
826 */
827 u8 irq;
828 pci_read_config_byte(d, 0x42, &irq);
829 irq &= 0xf;
830 if (irq && (irq != 2))
831 d->irq = irq;
832}
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
835
836
837/*
838 * VIA bridges which have VLink
839 */
840
841static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
842
843static void quirk_via_bridge(struct pci_dev *dev)
844{
845 /* See what bridge we have and find the device ranges */
846 switch (dev->device) {
847 case PCI_DEVICE_ID_VIA_82C686:
848 /* The VT82C686 is special, it attaches to PCI and can have
849 any device number. All its subdevices are functions of
850 that single device. */
851 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
852 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
853 break;
854 case PCI_DEVICE_ID_VIA_8237:
855 case PCI_DEVICE_ID_VIA_8237A:
856 via_vlink_dev_lo = 15;
857 break;
858 case PCI_DEVICE_ID_VIA_8235:
859 via_vlink_dev_lo = 16;
860 break;
861 case PCI_DEVICE_ID_VIA_8231:
862 case PCI_DEVICE_ID_VIA_8233_0:
863 case PCI_DEVICE_ID_VIA_8233A:
864 case PCI_DEVICE_ID_VIA_8233C_0:
865 via_vlink_dev_lo = 17;
866 break;
867 }
868}
869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
877
878/**
879 * quirk_via_vlink - VIA VLink IRQ number update
880 * @dev: PCI device
881 *
882 * If the device we are dealing with is on a PIC IRQ we need to
883 * ensure that the IRQ line register which usually is not relevant
884 * for PCI cards, is actually written so that interrupts get sent
885 * to the right place.
886 * We only do this on systems where a VIA south bridge was detected,
887 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 * above).
889 */
890
891static void quirk_via_vlink(struct pci_dev *dev)
892{
893 u8 irq, new_irq;
894
895 /* Check if we have VLink at all */
896 if (via_vlink_dev_lo == -1)
897 return;
898
899 new_irq = dev->irq;
900
901 /* Don't quirk interrupts outside the legacy IRQ range */
902 if (!new_irq || new_irq > 15)
903 return;
904
905 /* Internal device ? */
906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
908 return;
909
910 /* This is an internal VLink device on a PIC interrupt. The BIOS
911 ought to have set this but may not have, so we redo it */
912
913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
914 if (new_irq != irq) {
915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
916 irq, new_irq);
917 udelay(15); /* unknown if delay really needed */
918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
919 }
920}
921DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
922
923/*
924 * VIA VT82C598 has its device ID settable and many BIOSes
925 * set it to the ID of VT82C597 for backward compatibility.
926 * We need to switch it off to be able to recognize the real
927 * type of the chip.
928 */
929static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
930{
931 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
935
936/*
937 * CardBus controllers have a legacy base address that enables them
938 * to respond as i82365 pcmcia controllers. We don't want them to
939 * do this even if the Linux CardBus driver is not loaded, because
940 * the Linux i82365 driver does not (and should not) handle CardBus.
941 */
942static void quirk_cardbus_legacy(struct pci_dev *dev)
943{
944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945}
946DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
948DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
950
951/*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not
953 * sure what the designers were smoking but let's not inhale...
954 *
955 * To be fair to AMD, it follows the spec by default, its BIOS people
956 * who turn it off!
957 */
958static void quirk_amd_ordering(struct pci_dev *dev)
959{
960 u32 pcic;
961 pci_read_config_dword(dev, 0x4C, &pcic);
962 if ((pcic&6)!=6) {
963 pcic |= 6;
964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
965 pci_write_config_dword(dev, 0x4C, pcic);
966 pci_read_config_dword(dev, 0x84, &pcic);
967 pcic |= (1<<23); /* Required in this mode */
968 pci_write_config_dword(dev, 0x84, pcic);
969 }
970}
971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
973
974/*
975 * DreamWorks provided workaround for Dunord I-3000 problem
976 *
977 * This card decodes and responds to addresses not apparently
978 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it.
980 */
981static void __devinit quirk_dunord ( struct pci_dev * dev )
982{
983 struct resource *r = &dev->resource [1];
984 r->start = 0;
985 r->end = 0xffffff;
986}
987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
988
989/*
990 * i82380FB mobile docking controller: its PCI-to-PCI bridge
991 * is subtractive decoding (transparent), and does indicate this
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01.
994 */
995static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
996{
997 dev->transparent = 1;
998}
999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1001
1002/*
1003 * Common misconfiguration of the MediaGX/Geode PCI master that will
1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1005 * datasheets found at http://www.national.com/analog for info on what
1006 * these bits do. <christer@weinigel.se>
1007 */
1008static void quirk_mediagx_master(struct pci_dev *dev)
1009{
1010 u8 reg;
1011 pci_read_config_byte(dev, 0x41, ®);
1012 if (reg & 2) {
1013 reg &= ~2;
1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1015 pci_write_config_byte(dev, 0x41, reg);
1016 }
1017}
1018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1019DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1020
1021/*
1022 * Ensure C0 rev restreaming is off. This is normally done by
1023 * the BIOS but in the odd case it is not the results are corruption
1024 * hence the presence of a Linux check
1025 */
1026static void quirk_disable_pxb(struct pci_dev *pdev)
1027{
1028 u16 config;
1029
1030 if (pdev->revision != 0x04) /* Only C0 requires this */
1031 return;
1032 pci_read_config_word(pdev, 0x40, &config);
1033 if (config & (1<<6)) {
1034 config &= ~(1<<6);
1035 pci_write_config_word(pdev, 0x40, config);
1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1037 }
1038}
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041
1042static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1043{
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp;
1046
1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1048 if (tmp == 0x01) {
1049 pci_read_config_byte(pdev, 0x40, &tmp);
1050 pci_write_config_byte(pdev, 0x40, tmp|1);
1051 pci_write_config_byte(pdev, 0x9, 1);
1052 pci_write_config_byte(pdev, 0xa, 6);
1053 pci_write_config_byte(pdev, 0x40, tmp);
1054
1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1057 }
1058}
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1060DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1062DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1064DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1065
1066/*
1067 * Serverworks CSB5 IDE does not fully support native mode
1068 */
1069static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1070{
1071 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1073 if (prog & 5) {
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1077 /* PCI layer will sort out resources */
1078 }
1079}
1080DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1081
1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */
1085static void __init quirk_ide_samemode(struct pci_dev *pdev)
1086{
1087 u8 prog;
1088
1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1090
1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1093 prog &= ~5;
1094 pdev->class &= ~5;
1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1096 }
1097}
1098DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1099
1100/*
1101 * Some ATA devices break if put into D3
1102 */
1103
1104static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1105{
1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1107}
1108/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1109DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1113/* ALi loses some register settings that we cannot then restore */
1114DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1116/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */
1118DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1120
1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */
1124static void __init quirk_eisa_bridge(struct pci_dev *dev)
1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127}
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1129
1130
1131/*
1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1133 * is not activated. The myth is that Asus said that they do not want the
1134 * users to be irritated by just another PCI Device in the Win98 device
1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1136 * package 2.7.0 for details)
1137 *
1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1140 * becomes necessary to do this tweak in two steps -- the chosen trigger
1141 * is either the Host bridge (preferred) or on-board VGA controller.
1142 *
1143 * Note that we used to unhide the SMBus that way on Toshiba laptops
1144 * (Satellite A40 and Tecra M2) but then found that the thermal management
1145 * was done by SMM code, which could cause unsynchronized concurrent
1146 * accesses to the SMBus registers, with potentially bad effects. Thus you
1147 * should be very careful when adding new entries: if SMM is accessing the
1148 * Intel SMBus, this is a very good reason to leave it hidden.
1149 *
1150 * Likewise, many recent laptops use ACPI for thermal management. If the
1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1152 * natively, and keeping the SMBus hidden is the right thing to do. If you
1153 * are about to add an entry in the table below, please first disassemble
1154 * the DSDT and double-check that there is no code accessing the SMBus.
1155 */
1156static int asus_hides_smbus;
1157
1158static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1162 switch(dev->subsystem_device) {
1163 case 0x8025: /* P4B-LX */
1164 case 0x8070: /* P4B */
1165 case 0x8088: /* P4B533 */
1166 case 0x1626: /* L3C notebook */
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1170 switch(dev->subsystem_device) {
1171 case 0x80b1: /* P4GE-V */
1172 case 0x80b2: /* P4PE */
1173 case 0x8093: /* P4B533-V */
1174 asus_hides_smbus = 1;
1175 }
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1177 switch(dev->subsystem_device) {
1178 case 0x8030: /* P4T533 */
1179 asus_hides_smbus = 1;
1180 }
1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1182 switch (dev->subsystem_device) {
1183 case 0x8070: /* P4G8X Deluxe */
1184 asus_hides_smbus = 1;
1185 }
1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1187 switch (dev->subsystem_device) {
1188 case 0x80c9: /* PU-DLS */
1189 asus_hides_smbus = 1;
1190 }
1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x1751: /* M2N notebook */
1194 case 0x1821: /* M5N notebook */
1195 case 0x1897: /* A6L notebook */
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1199 switch (dev->subsystem_device) {
1200 case 0x184b: /* W1N notebook */
1201 case 0x186a: /* M6Ne notebook */
1202 asus_hides_smbus = 1;
1203 }
1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x80f2: /* P4P800-X */
1207 asus_hides_smbus = 1;
1208 }
1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1210 switch (dev->subsystem_device) {
1211 case 0x1882: /* M6V notebook */
1212 case 0x1977: /* A6VA notebook */
1213 asus_hides_smbus = 1;
1214 }
1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1217 switch(dev->subsystem_device) {
1218 case 0x088C: /* HP Compaq nc8000 */
1219 case 0x0890: /* HP Compaq nc6000 */
1220 asus_hides_smbus = 1;
1221 }
1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1223 switch (dev->subsystem_device) {
1224 case 0x12bc: /* HP D330L */
1225 case 0x12bd: /* HP D530 */
1226 case 0x006a: /* HP Compaq nx9500 */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x12bf: /* HP xw4100 */
1232 asus_hides_smbus = 1;
1233 }
1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch(dev->subsystem_device) {
1237 case 0xC00C: /* Samsung P35 notebook */
1238 asus_hides_smbus = 1;
1239 }
1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch(dev->subsystem_device) {
1243 case 0x0058: /* Compaq Evo N620c */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1247 switch(dev->subsystem_device) {
1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1249 /* Motherboard doesn't have Host bridge
1250 * subvendor/subdevice IDs, therefore checking
1251 * its on-board VGA controller */
1252 asus_hides_smbus = 1;
1253 }
1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1255 switch(dev->subsystem_device) {
1256 case 0x00b8: /* Compaq Evo D510 CMT */
1257 case 0x00b9: /* Compaq Evo D510 SFF */
1258 case 0x00ba: /* Compaq Evo D510 USDT */
1259 /* Motherboard doesn't have Host bridge
1260 * subvendor/subdevice IDs and on-board VGA
1261 * controller is disabled if an AGP card is
1262 * inserted, therefore checking USB UHCI
1263 * Controller #1 */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1267 switch (dev->subsystem_device) {
1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1269 /* Motherboard doesn't have host bridge
1270 * subvendor/subdevice IDs, therefore checking
1271 * its on-board VGA controller */
1272 asus_hides_smbus = 1;
1273 }
1274 }
1275}
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1286
1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1290
1291static void asus_hides_smbus_lpc(struct pci_dev *dev)
1292{
1293 u16 val;
1294
1295 if (likely(!asus_hides_smbus))
1296 return;
1297
1298 pci_read_config_word(dev, 0xF2, &val);
1299 if (val & 0x8) {
1300 pci_write_config_word(dev, 0xF2, val & (~0x8));
1301 pci_read_config_word(dev, 0xF2, &val);
1302 if (val & 0x8)
1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1304 else
1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1306 }
1307}
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1322
1323/* It appears we just have one such device. If not, we have a warning */
1324static void __iomem *asus_rcba_base;
1325static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1326{
1327 u32 rcba;
1328
1329 if (likely(!asus_hides_smbus))
1330 return;
1331 WARN_ON(asus_rcba_base);
1332
1333 pci_read_config_dword(dev, 0xF0, &rcba);
1334 /* use bits 31:14, 16 kB aligned */
1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1336 if (asus_rcba_base == NULL)
1337 return;
1338}
1339
1340static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1341{
1342 u32 val;
1343
1344 if (likely(!asus_hides_smbus || !asus_rcba_base))
1345 return;
1346 /* read the Function Disable register, dword mode only */
1347 val = readl(asus_rcba_base + 0x3418);
1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1349}
1350
1351static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1352{
1353 if (likely(!asus_hides_smbus || !asus_rcba_base))
1354 return;
1355 iounmap(asus_rcba_base);
1356 asus_rcba_base = NULL;
1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1358}
1359
1360static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1361{
1362 asus_hides_smbus_lpc_ich6_suspend(dev);
1363 asus_hides_smbus_lpc_ich6_resume_early(dev);
1364 asus_hides_smbus_lpc_ich6_resume(dev);
1365}
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1367DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1368DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1369DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1370
1371/*
1372 * SiS 96x south bridge: BIOS typically hides SMBus device...
1373 */
1374static void quirk_sis_96x_smbus(struct pci_dev *dev)
1375{
1376 u8 val = 0;
1377 pci_read_config_byte(dev, 0x77, &val);
1378 if (val & 0x10) {
1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1380 pci_write_config_byte(dev, 0x77, val & ~0x10);
1381 }
1382}
1383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1387DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1388DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1390DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1391
1392/*
1393 * ... This is further complicated by the fact that some SiS96x south
1394 * bridges pretend to be 85C503/5513 instead. In that case see if we
1395 * spotted a compatible north bridge to make sure.
1396 * (pci_find_device doesn't work yet)
1397 *
1398 * We can also enable the sis96x bit in the discovery register..
1399 */
1400#define SIS_DETECT_REGISTER 0x40
1401
1402static void quirk_sis_503(struct pci_dev *dev)
1403{
1404 u8 reg;
1405 u16 devid;
1406
1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1412 return;
1413 }
1414
1415 /*
1416 * Ok, it now shows up as a 96x.. run the 96x quirk by
1417 * hand in case it has already been processed.
1418 * (depends on link order, which is apparently not guaranteed)
1419 */
1420 dev->device = devid;
1421 quirk_sis_96x_smbus(dev);
1422}
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1425
1426
1427/*
1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1429 * and MC97 modem controller are disabled when a second PCI soundcard is
1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1431 * -- bjd
1432 */
1433static void asus_hides_ac97_lpc(struct pci_dev *dev)
1434{
1435 u8 val;
1436 int asus_hides_ac97 = 0;
1437
1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1439 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1440 asus_hides_ac97 = 1;
1441 }
1442
1443 if (!asus_hides_ac97)
1444 return;
1445
1446 pci_read_config_byte(dev, 0x50, &val);
1447 if (val & 0xc0) {
1448 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1449 pci_read_config_byte(dev, 0x50, &val);
1450 if (val & 0xc0)
1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1452 else
1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1454 }
1455}
1456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1457DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1458
1459#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1460
1461/*
1462 * If we are using libata we can drive this chip properly but must
1463 * do this early on to make the additional device appear during
1464 * the PCI scanning.
1465 */
1466static void quirk_jmicron_ata(struct pci_dev *pdev)
1467{
1468 u32 conf1, conf5, class;
1469 u8 hdr;
1470
1471 /* Only poke fn 0 */
1472 if (PCI_FUNC(pdev->devfn))
1473 return;
1474
1475 pci_read_config_dword(pdev, 0x40, &conf1);
1476 pci_read_config_dword(pdev, 0x80, &conf5);
1477
1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1479 conf5 &= ~(1 << 24); /* Clear bit 24 */
1480
1481 switch (pdev->device) {
1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1485 /* The controller should be in single function ahci mode */
1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1487 break;
1488
1489 case PCI_DEVICE_ID_JMICRON_JMB365:
1490 case PCI_DEVICE_ID_JMICRON_JMB366:
1491 /* Redirect IDE second PATA port to the right spot */
1492 conf5 |= (1 << 24);
1493 /* Fall through */
1494 case PCI_DEVICE_ID_JMICRON_JMB361:
1495 case PCI_DEVICE_ID_JMICRON_JMB363:
1496 case PCI_DEVICE_ID_JMICRON_JMB369:
1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1498 /* Set the class codes correctly and then direct IDE 0 */
1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1500 break;
1501
1502 case PCI_DEVICE_ID_JMICRON_JMB368:
1503 /* The controller should be in single function IDE mode */
1504 conf1 |= 0x00C00000; /* Set 22, 23 */
1505 break;
1506 }
1507
1508 pci_write_config_dword(pdev, 0x40, conf1);
1509 pci_write_config_dword(pdev, 0x80, conf5);
1510
1511 /* Update pdev accordingly */
1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1513 pdev->hdr_type = hdr & 0x7f;
1514 pdev->multifunction = !!(hdr & 0x80);
1515
1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1517 pdev->class = class >> 8;
1518}
1519DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1520DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1521DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1522DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1524DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1525DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1526DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1527DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1528DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1529DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1530DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1537
1538#endif
1539
1540#ifdef CONFIG_X86_IO_APIC
1541static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1542{
1543 int i;
1544
1545 if ((pdev->class >> 8) != 0xff00)
1546 return;
1547
1548 /* the first BAR is the location of the IO APIC...we must
1549 * not touch this (and it's already covered by the fixmap), so
1550 * forcibly insert it into the resource tree */
1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1552 insert_resource(&iomem_resource, &pdev->resource[0]);
1553
1554 /* The next five BARs all seem to be rubbish, so just clean
1555 * them out */
1556 for (i=1; i < 6; i++) {
1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1558 }
1559
1560}
1561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1562#endif
1563
1564static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1565{
1566 pci_msi_off(pdev);
1567 pdev->no_msi = 1;
1568}
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1572
1573
1574/*
1575 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems.
1577 */
1578static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1579{
1580 pci_msi_off(dev);
1581 dev->no_msi = 1;
1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1583}
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1589
1590/*
1591 * Some Intel PCI Express chipsets have trouble with downstream
1592 * device power management.
1593 */
1594static void quirk_intel_pcie_pm(struct pci_dev * dev)
1595{
1596 pci_pm_d3_delay = 120;
1597 dev->no_d1d2 = 1;
1598}
1599
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1621
1622#ifdef CONFIG_X86_IO_APIC
1623/*
1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1625 * remap the original interrupt in the linux kernel to the boot interrupt, so
1626 * that a PCI device's interrupt handler is installed on the boot interrupt
1627 * line instead.
1628 */
1629static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1630{
1631 if (noioapicquirk || noioapicreroute)
1632 return;
1633
1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1636 dev->vendor, dev->device);
1637}
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1647DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1648DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1649DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1650DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1654
1655/*
1656 * On some chipsets we can disable the generation of legacy INTx boot
1657 * interrupts.
1658 */
1659
1660/*
1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1662 * 300641-004US, section 5.7.3.
1663 */
1664#define INTEL_6300_IOAPIC_ABAR 0x40
1665#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1666
1667static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1668{
1669 u16 pci_config_word;
1670
1671 if (noioapicquirk)
1672 return;
1673
1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1677
1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1679 dev->vendor, dev->device);
1680}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1682DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1683
1684/*
1685 * disable boot interrupts on HT-1000
1686 */
1687#define BC_HT1000_FEATURE_REG 0x64
1688#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1689#define BC_HT1000_MAP_IDX 0xC00
1690#define BC_HT1000_MAP_DATA 0xC01
1691
1692static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1693{
1694 u32 pci_config_dword;
1695 u8 irq;
1696
1697 if (noioapicquirk)
1698 return;
1699
1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1702 BC_HT1000_PIC_REGS_ENABLE);
1703
1704 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1705 outb(irq, BC_HT1000_MAP_IDX);
1706 outb(0x00, BC_HT1000_MAP_DATA);
1707 }
1708
1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1710
1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1712 dev->vendor, dev->device);
1713}
1714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1716
1717/*
1718 * disable boot interrupts on AMD and ATI chipsets
1719 */
1720/*
1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1723 * (due to an erratum).
1724 */
1725#define AMD_813X_MISC 0x40
1726#define AMD_813X_NOIOAMODE (1<<0)
1727#define AMD_813X_REV_B1 0x12
1728#define AMD_813X_REV_B2 0x13
1729
1730static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1731{
1732 u32 pci_config_dword;
1733
1734 if (noioapicquirk)
1735 return;
1736 if ((dev->revision == AMD_813X_REV_B1) ||
1737 (dev->revision == AMD_813X_REV_B2))
1738 return;
1739
1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1741 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1743
1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745 dev->vendor, dev->device);
1746}
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1750DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1751
1752#define AMD_8111_PCI_IRQ_ROUTING 0x56
1753
1754static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1755{
1756 u16 pci_config_word;
1757
1758 if (noioapicquirk)
1759 return;
1760
1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1762 if (!pci_config_word) {
1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1764 "already disabled\n", dev->vendor, dev->device);
1765 return;
1766 }
1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770}
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1773#endif /* CONFIG_X86_IO_APIC */
1774
1775/*
1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed...
1779 */
1780static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1781{
1782 struct resource *r = &dev->resource[0];
1783
1784 if (r->start & 0x8) {
1785 r->start = 0;
1786 r->end = 0xf;
1787 }
1788}
1789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide);
1792
1793static void __devinit quirk_netmos(struct pci_dev *dev)
1794{
1795 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1796 unsigned int num_serial = dev->subsystem_device & 0xf;
1797
1798 /*
1799 * These Netmos parts are multiport serial devices with optional
1800 * parallel ports. Even when parallel ports are present, they
1801 * are identified as class SERIAL, which means the serial driver
1802 * will claim them. To prevent this, mark them as class OTHER.
1803 * These combo devices should be claimed by parport_serial.
1804 *
1805 * The subdevice ID is of the form 0x00PS, where <P> is the number
1806 * of parallel ports and <S> is the number of serial ports.
1807 */
1808 switch (dev->device) {
1809 case PCI_DEVICE_ID_NETMOS_9835:
1810 /* Well, this rule doesn't hold for the following 9835 device */
1811 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1812 dev->subsystem_device == 0x0299)
1813 return;
1814 case PCI_DEVICE_ID_NETMOS_9735:
1815 case PCI_DEVICE_ID_NETMOS_9745:
1816 case PCI_DEVICE_ID_NETMOS_9845:
1817 case PCI_DEVICE_ID_NETMOS_9855:
1818 if (num_parallel) {
1819 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1820 "%u serial); changing class SERIAL to OTHER "
1821 "(use parport_serial)\n",
1822 dev->device, num_parallel, num_serial);
1823 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1824 (dev->class & 0xff);
1825 }
1826 }
1827}
1828DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1829 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1830
1831static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1832{
1833 u16 command, pmcsr;
1834 u8 __iomem *csr;
1835 u8 cmd_hi;
1836 int pm;
1837
1838 switch (dev->device) {
1839 /* PCI IDs taken from drivers/net/e100.c */
1840 case 0x1029:
1841 case 0x1030 ... 0x1034:
1842 case 0x1038 ... 0x103E:
1843 case 0x1050 ... 0x1057:
1844 case 0x1059:
1845 case 0x1064 ... 0x106B:
1846 case 0x1091 ... 0x1095:
1847 case 0x1209:
1848 case 0x1229:
1849 case 0x2449:
1850 case 0x2459:
1851 case 0x245D:
1852 case 0x27DC:
1853 break;
1854 default:
1855 return;
1856 }
1857
1858 /*
1859 * Some firmware hands off the e100 with interrupts enabled,
1860 * which can cause a flood of interrupts if packets are
1861 * received before the driver attaches to the device. So
1862 * disable all e100 interrupts here. The driver will
1863 * re-enable them when it's ready.
1864 */
1865 pci_read_config_word(dev, PCI_COMMAND, &command);
1866
1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1868 return;
1869
1870 /*
1871 * Check that the device is in the D0 power state. If it's not,
1872 * there is no point to look any further.
1873 */
1874 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1875 if (pm) {
1876 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1878 return;
1879 }
1880
1881 /* Convert from PCI bus to resource space. */
1882 csr = ioremap(pci_resource_start(dev, 0), 8);
1883 if (!csr) {
1884 dev_warn(&dev->dev, "Can't map e100 registers\n");
1885 return;
1886 }
1887
1888 cmd_hi = readb(csr + 3);
1889 if (cmd_hi == 0) {
1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1891 "disabling\n");
1892 writeb(1, csr + 3);
1893 }
1894
1895 iounmap(csr);
1896}
1897DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1899
1900/*
1901 * The 82575 and 82598 may experience data corruption issues when transitioning
1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1903 */
1904static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1905{
1906 dev_info(&dev->dev, "Disabling L0s\n");
1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1923
1924static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1925{
1926 /* rev 1 ncr53c810 chips don't set the class at all which means
1927 * they don't get their resources remapped. Fix that here.
1928 */
1929
1930 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1932 dev->class = PCI_CLASS_STORAGE_SCSI;
1933 }
1934}
1935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1936
1937/* Enable 1k I/O space granularity on the Intel P64H2 */
1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939{
1940 u16 en1k;
1941 u8 io_base_lo, io_limit_lo;
1942 unsigned long base, limit;
1943 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1944
1945 pci_read_config_word(dev, 0x40, &en1k);
1946
1947 if (en1k & 0x200) {
1948 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1949
1950 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1951 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1952 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1953 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1954
1955 if (base <= limit) {
1956 res->start = base;
1957 res->end = limit + 0x3ff;
1958 }
1959 }
1960}
1961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1962
1963/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1964 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1965 * in drivers/pci/setup-bus.c
1966 */
1967static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1968{
1969 u16 en1k, iobl_adr, iobl_adr_1k;
1970 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1971
1972 pci_read_config_word(dev, 0x40, &en1k);
1973
1974 if (en1k & 0x200) {
1975 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1976
1977 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1978
1979 if (iobl_adr != iobl_adr_1k) {
1980 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1981 iobl_adr,iobl_adr_1k);
1982 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1983 }
1984 }
1985}
1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1987
1988/* Under some circumstances, AER is not linked with extended capabilities.
1989 * Force it to be linked by setting the corresponding control bit in the
1990 * config space.
1991 */
1992static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1993{
1994 uint8_t b;
1995 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1996 if (!(b & 0x20)) {
1997 pci_write_config_byte(dev, 0xf41, b | 0x20);
1998 dev_info(&dev->dev,
1999 "Linking AER extended capability\n");
2000 }
2001 }
2002}
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2004 quirk_nvidia_ck804_pcie_aer_ext_cap);
2005DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2006 quirk_nvidia_ck804_pcie_aer_ext_cap);
2007
2008static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2009{
2010 /*
2011 * Disable PCI Bus Parking and PCI Master read caching on CX700
2012 * which causes unspecified timing errors with a VT6212L on the PCI
2013 * bus leading to USB2.0 packet loss.
2014 *
2015 * This quirk is only enabled if a second (on the external PCI bus)
2016 * VT6212L is found -- the CX700 core itself also contains a USB
2017 * host controller with the same PCI ID as the VT6212L.
2018 */
2019
2020 /* Count VT6212L instances */
2021 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2022 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2023 uint8_t b;
2024
2025 /* p should contain the first (internal) VT6212L -- see if we have
2026 an external one by searching again */
2027 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2028 if (!p)
2029 return;
2030 pci_dev_put(p);
2031
2032 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2033 if (b & 0x40) {
2034 /* Turn off PCI Bus Parking */
2035 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2036
2037 dev_info(&dev->dev,
2038 "Disabling VIA CX700 PCI parking\n");
2039 }
2040 }
2041
2042 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2043 if (b != 0) {
2044 /* Turn off PCI Master read caching */
2045 pci_write_config_byte(dev, 0x72, 0x0);
2046
2047 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2048 pci_write_config_byte(dev, 0x75, 0x1);
2049
2050 /* Disable "Read FIFO Timer" */
2051 pci_write_config_byte(dev, 0x77, 0x0);
2052
2053 dev_info(&dev->dev,
2054 "Disabling VIA CX700 PCI caching\n");
2055 }
2056 }
2057}
2058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2059
2060/*
2061 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2062 * VPD end tag will hang the device. This problem was initially
2063 * observed when a vpd entry was created in sysfs
2064 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2065 * will dump 32k of data. Reading a full 32k will cause an access
2066 * beyond the VPD end tag causing the device to hang. Once the device
2067 * is hung, the bnx2 driver will not be able to reset the device.
2068 * We believe that it is legal to read beyond the end tag and
2069 * therefore the solution is to limit the read/write length.
2070 */
2071static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2072{
2073 /*
2074 * Only disable the VPD capability for 5706, 5706S, 5708,
2075 * 5708S and 5709 rev. A
2076 */
2077 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2078 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2079 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2080 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2081 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2082 (dev->revision & 0xf0) == 0x0)) {
2083 if (dev->vpd)
2084 dev->vpd->len = 0x80;
2085 }
2086}
2087
2088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2089 PCI_DEVICE_ID_NX2_5706,
2090 quirk_brcm_570x_limit_vpd);
2091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2092 PCI_DEVICE_ID_NX2_5706S,
2093 quirk_brcm_570x_limit_vpd);
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2095 PCI_DEVICE_ID_NX2_5708,
2096 quirk_brcm_570x_limit_vpd);
2097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2098 PCI_DEVICE_ID_NX2_5708S,
2099 quirk_brcm_570x_limit_vpd);
2100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2101 PCI_DEVICE_ID_NX2_5709,
2102 quirk_brcm_570x_limit_vpd);
2103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2104 PCI_DEVICE_ID_NX2_5709S,
2105 quirk_brcm_570x_limit_vpd);
2106
2107static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2108{
2109 u32 rev;
2110
2111 pci_read_config_dword(dev, 0xf4, &rev);
2112
2113 /* Only CAP the MRRS if the device is a 5719 A0 */
2114 if (rev == 0x05719000) {
2115 int readrq = pcie_get_readrq(dev);
2116 if (readrq > 2048)
2117 pcie_set_readrq(dev, 2048);
2118 }
2119}
2120
2121DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2122 PCI_DEVICE_ID_TIGON3_5719,
2123 quirk_brcm_5719_limit_mrrs);
2124
2125/* Originally in EDAC sources for i82875P:
2126 * Intel tells BIOS developers to hide device 6 which
2127 * configures the overflow device access containing
2128 * the DRBs - this is where we expose device 6.
2129 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2130 */
2131static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2132{
2133 u8 reg;
2134
2135 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2136 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2137 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2138 }
2139}
2140
2141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2142 quirk_unhide_mch_dev6);
2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2144 quirk_unhide_mch_dev6);
2145
2146#ifdef CONFIG_TILE
2147/*
2148 * The Tilera TILEmpower platform needs to set the link speed
2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2151 * capability register of the PEX8624 PCIe switch. The switch
2152 * supports link speed auto negotiation, but falsely sets
2153 * the link speed to 5GT/s.
2154 */
2155static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2156{
2157 if (tile_plx_gen1) {
2158 pci_write_config_dword(dev, 0x98, 0x1);
2159 mdelay(50);
2160 }
2161}
2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2163#endif /* CONFIG_TILE */
2164
2165#ifdef CONFIG_PCI_MSI
2166/* Some chipsets do not support MSI. We cannot easily rely on setting
2167 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2168 * some other busses controlled by the chipset even if Linux is not
2169 * aware of it. Instead of setting the flag on all busses in the
2170 * machine, simply disable MSI globally.
2171 */
2172static void __init quirk_disable_all_msi(struct pci_dev *dev)
2173{
2174 pci_no_msi();
2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2176}
2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2183DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2184
2185/* Disable MSI on chipsets that are known to not support it */
2186static void __devinit quirk_disable_msi(struct pci_dev *dev)
2187{
2188 if (dev->subordinate) {
2189 dev_warn(&dev->dev, "MSI quirk detected; "
2190 "subordinate MSI disabled\n");
2191 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2192 }
2193}
2194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2197
2198/*
2199 * The APC bridge device in AMD 780 family northbridges has some random
2200 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2201 * we use the possible vendor/device IDs of the host bridge for the
2202 * declared quirk, and search for the APC bridge by slot number.
2203 */
2204static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2205{
2206 struct pci_dev *apc_bridge;
2207
2208 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2209 if (apc_bridge) {
2210 if (apc_bridge->device == 0x9602)
2211 quirk_disable_msi(apc_bridge);
2212 pci_dev_put(apc_bridge);
2213 }
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2217
2218/* Go through the list of Hypertransport capabilities and
2219 * return 1 if a HT MSI capability is found and enabled */
2220static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2221{
2222 int pos, ttl = 48;
2223
2224 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2225 while (pos && ttl--) {
2226 u8 flags;
2227
2228 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2229 &flags) == 0)
2230 {
2231 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2232 flags & HT_MSI_FLAGS_ENABLE ?
2233 "enabled" : "disabled");
2234 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2235 }
2236
2237 pos = pci_find_next_ht_capability(dev, pos,
2238 HT_CAPTYPE_MSI_MAPPING);
2239 }
2240 return 0;
2241}
2242
2243/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2244static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2245{
2246 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2247 dev_warn(&dev->dev, "MSI quirk detected; "
2248 "subordinate MSI disabled\n");
2249 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2250 }
2251}
2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2253 quirk_msi_ht_cap);
2254
2255/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2256 * MSI are supported if the MSI capability set in any of these mappings.
2257 */
2258static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2259{
2260 struct pci_dev *pdev;
2261
2262 if (!dev->subordinate)
2263 return;
2264
2265 /* check HT MSI cap on this chipset and the root one.
2266 * a single one having MSI is enough to be sure that MSI are supported.
2267 */
2268 pdev = pci_get_slot(dev->bus, 0);
2269 if (!pdev)
2270 return;
2271 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2272 dev_warn(&dev->dev, "MSI quirk detected; "
2273 "subordinate MSI disabled\n");
2274 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2275 }
2276 pci_dev_put(pdev);
2277}
2278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2279 quirk_nvidia_ck804_msi_ht_cap);
2280
2281/* Force enable MSI mapping capability on HT bridges */
2282static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2283{
2284 int pos, ttl = 48;
2285
2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2287 while (pos && ttl--) {
2288 u8 flags;
2289
2290 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2291 &flags) == 0) {
2292 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2293
2294 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2295 flags | HT_MSI_FLAGS_ENABLE);
2296 }
2297 pos = pci_find_next_ht_capability(dev, pos,
2298 HT_CAPTYPE_MSI_MAPPING);
2299 }
2300}
2301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2302 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2303 ht_enable_msi_mapping);
2304
2305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2306 ht_enable_msi_mapping);
2307
2308/* The P5N32-SLI motherboards from Asus have a problem with msi
2309 * for the MCP55 NIC. It is not yet determined whether the msi problem
2310 * also affects other devices. As for now, turn off msi for this device.
2311 */
2312static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2313{
2314 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2315
2316 if (board_name &&
2317 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2318 strstr(board_name, "P5N32-E SLI"))) {
2319 dev_info(&dev->dev,
2320 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2321 dev->no_msi = 1;
2322 }
2323}
2324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2325 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2326 nvenet_msi_disable);
2327
2328/*
2329 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2330 * config register. This register controls the routing of legacy interrupts
2331 * from devices that route through the MCP55. If this register is misprogramed
2332 * interrupts are only sent to the bsp, unlike conventional systems where the
2333 * irq is broadxast to all online cpus. Not having this register set
2334 * properly prevents kdump from booting up properly, so lets make sure that
2335 * we have it set correctly.
2336 * Note this is an undocumented register.
2337 */
2338static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2339{
2340 u32 cfg;
2341
2342 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2343 return;
2344
2345 pci_read_config_dword(dev, 0x74, &cfg);
2346
2347 if (cfg & ((1 << 2) | (1 << 15))) {
2348 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2349 cfg &= ~((1 << 2) | (1 << 15));
2350 pci_write_config_dword(dev, 0x74, cfg);
2351 }
2352}
2353
2354DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2355 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2356 nvbridge_check_legacy_irq_routing);
2357
2358DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2359 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2360 nvbridge_check_legacy_irq_routing);
2361
2362static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2363{
2364 int pos, ttl = 48;
2365 int found = 0;
2366
2367 /* check if there is HT MSI cap or enabled on this device */
2368 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2369 while (pos && ttl--) {
2370 u8 flags;
2371
2372 if (found < 1)
2373 found = 1;
2374 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2375 &flags) == 0) {
2376 if (flags & HT_MSI_FLAGS_ENABLE) {
2377 if (found < 2) {
2378 found = 2;
2379 break;
2380 }
2381 }
2382 }
2383 pos = pci_find_next_ht_capability(dev, pos,
2384 HT_CAPTYPE_MSI_MAPPING);
2385 }
2386
2387 return found;
2388}
2389
2390static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2391{
2392 struct pci_dev *dev;
2393 int pos;
2394 int i, dev_no;
2395 int found = 0;
2396
2397 dev_no = host_bridge->devfn >> 3;
2398 for (i = dev_no + 1; i < 0x20; i++) {
2399 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2400 if (!dev)
2401 continue;
2402
2403 /* found next host bridge ?*/
2404 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2405 if (pos != 0) {
2406 pci_dev_put(dev);
2407 break;
2408 }
2409
2410 if (ht_check_msi_mapping(dev)) {
2411 found = 1;
2412 pci_dev_put(dev);
2413 break;
2414 }
2415 pci_dev_put(dev);
2416 }
2417
2418 return found;
2419}
2420
2421#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2422#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2423
2424static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2425{
2426 int pos, ctrl_off;
2427 int end = 0;
2428 u16 flags, ctrl;
2429
2430 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2431
2432 if (!pos)
2433 goto out;
2434
2435 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2436
2437 ctrl_off = ((flags >> 10) & 1) ?
2438 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2439 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2440
2441 if (ctrl & (1 << 6))
2442 end = 1;
2443
2444out:
2445 return end;
2446}
2447
2448static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2449{
2450 struct pci_dev *host_bridge;
2451 int pos;
2452 int i, dev_no;
2453 int found = 0;
2454
2455 dev_no = dev->devfn >> 3;
2456 for (i = dev_no; i >= 0; i--) {
2457 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2458 if (!host_bridge)
2459 continue;
2460
2461 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2462 if (pos != 0) {
2463 found = 1;
2464 break;
2465 }
2466 pci_dev_put(host_bridge);
2467 }
2468
2469 if (!found)
2470 return;
2471
2472 /* don't enable end_device/host_bridge with leaf directly here */
2473 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2474 host_bridge_with_leaf(host_bridge))
2475 goto out;
2476
2477 /* root did that ! */
2478 if (msi_ht_cap_enabled(host_bridge))
2479 goto out;
2480
2481 ht_enable_msi_mapping(dev);
2482
2483out:
2484 pci_dev_put(host_bridge);
2485}
2486
2487static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2488{
2489 int pos, ttl = 48;
2490
2491 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2492 while (pos && ttl--) {
2493 u8 flags;
2494
2495 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2496 &flags) == 0) {
2497 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2498
2499 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2500 flags & ~HT_MSI_FLAGS_ENABLE);
2501 }
2502 pos = pci_find_next_ht_capability(dev, pos,
2503 HT_CAPTYPE_MSI_MAPPING);
2504 }
2505}
2506
2507static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2508{
2509 struct pci_dev *host_bridge;
2510 int pos;
2511 int found;
2512
2513 if (!pci_msi_enabled())
2514 return;
2515
2516 /* check if there is HT MSI cap or enabled on this device */
2517 found = ht_check_msi_mapping(dev);
2518
2519 /* no HT MSI CAP */
2520 if (found == 0)
2521 return;
2522
2523 /*
2524 * HT MSI mapping should be disabled on devices that are below
2525 * a non-Hypertransport host bridge. Locate the host bridge...
2526 */
2527 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2528 if (host_bridge == NULL) {
2529 dev_warn(&dev->dev,
2530 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2531 return;
2532 }
2533
2534 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2535 if (pos != 0) {
2536 /* Host bridge is to HT */
2537 if (found == 1) {
2538 /* it is not enabled, try to enable it */
2539 if (all)
2540 ht_enable_msi_mapping(dev);
2541 else
2542 nv_ht_enable_msi_mapping(dev);
2543 }
2544 return;
2545 }
2546
2547 /* HT MSI is not enabled */
2548 if (found == 1)
2549 return;
2550
2551 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2552 ht_disable_msi_mapping(dev);
2553}
2554
2555static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2556{
2557 return __nv_msi_ht_cap_quirk(dev, 1);
2558}
2559
2560static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2561{
2562 return __nv_msi_ht_cap_quirk(dev, 0);
2563}
2564
2565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2566DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2567
2568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2570
2571static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2572{
2573 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2574}
2575static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2576{
2577 struct pci_dev *p;
2578
2579 /* SB700 MSI issue will be fixed at HW level from revision A21,
2580 * we need check PCI REVISION ID of SMBus controller to get SB700
2581 * revision.
2582 */
2583 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2584 NULL);
2585 if (!p)
2586 return;
2587
2588 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2589 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2590 pci_dev_put(p);
2591}
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2593 PCI_DEVICE_ID_TIGON3_5780,
2594 quirk_msi_intx_disable_bug);
2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2596 PCI_DEVICE_ID_TIGON3_5780S,
2597 quirk_msi_intx_disable_bug);
2598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2599 PCI_DEVICE_ID_TIGON3_5714,
2600 quirk_msi_intx_disable_bug);
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2602 PCI_DEVICE_ID_TIGON3_5714S,
2603 quirk_msi_intx_disable_bug);
2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2605 PCI_DEVICE_ID_TIGON3_5715,
2606 quirk_msi_intx_disable_bug);
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2608 PCI_DEVICE_ID_TIGON3_5715S,
2609 quirk_msi_intx_disable_bug);
2610
2611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2612 quirk_msi_intx_disable_ati_bug);
2613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2614 quirk_msi_intx_disable_ati_bug);
2615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2616 quirk_msi_intx_disable_ati_bug);
2617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2618 quirk_msi_intx_disable_ati_bug);
2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2620 quirk_msi_intx_disable_ati_bug);
2621
2622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2623 quirk_msi_intx_disable_bug);
2624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2625 quirk_msi_intx_disable_bug);
2626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2627 quirk_msi_intx_disable_bug);
2628
2629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2630 quirk_msi_intx_disable_bug);
2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2632 quirk_msi_intx_disable_bug);
2633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2634 quirk_msi_intx_disable_bug);
2635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2636 quirk_msi_intx_disable_bug);
2637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2640 quirk_msi_intx_disable_bug);
2641#endif /* CONFIG_PCI_MSI */
2642
2643/* Allow manual resource allocation for PCI hotplug bridges
2644 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2645 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2646 * kernel fails to allocate resources when hotplug device is
2647 * inserted and PCI bus is rescanned.
2648 */
2649static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2650{
2651 dev->is_hotplug_bridge = 1;
2652}
2653
2654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2655
2656/*
2657 * This is a quirk for the Ricoh MMC controller found as a part of
2658 * some mulifunction chips.
2659
2660 * This is very similar and based on the ricoh_mmc driver written by
2661 * Philip Langdale. Thank you for these magic sequences.
2662 *
2663 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2664 * and one or both of cardbus or firewire.
2665 *
2666 * It happens that they implement SD and MMC
2667 * support as separate controllers (and PCI functions). The linux SDHCI
2668 * driver supports MMC cards but the chip detects MMC cards in hardware
2669 * and directs them to the MMC controller - so the SDHCI driver never sees
2670 * them.
2671 *
2672 * To get around this, we must disable the useless MMC controller.
2673 * At that point, the SDHCI controller will start seeing them
2674 * It seems to be the case that the relevant PCI registers to deactivate the
2675 * MMC controller live on PCI function 0, which might be the cardbus controller
2676 * or the firewire controller, depending on the particular chip in question
2677 *
2678 * This has to be done early, because as soon as we disable the MMC controller
2679 * other pci functions shift up one level, e.g. function #2 becomes function
2680 * #1, and this will confuse the pci core.
2681 */
2682
2683#ifdef CONFIG_MMC_RICOH_MMC
2684static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2685{
2686 /* disable via cardbus interface */
2687 u8 write_enable;
2688 u8 write_target;
2689 u8 disable;
2690
2691 /* disable must be done via function #0 */
2692 if (PCI_FUNC(dev->devfn))
2693 return;
2694
2695 pci_read_config_byte(dev, 0xB7, &disable);
2696 if (disable & 0x02)
2697 return;
2698
2699 pci_read_config_byte(dev, 0x8E, &write_enable);
2700 pci_write_config_byte(dev, 0x8E, 0xAA);
2701 pci_read_config_byte(dev, 0x8D, &write_target);
2702 pci_write_config_byte(dev, 0x8D, 0xB7);
2703 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2704 pci_write_config_byte(dev, 0x8E, write_enable);
2705 pci_write_config_byte(dev, 0x8D, write_target);
2706
2707 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2708 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2709}
2710DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2711DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2712
2713static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2714{
2715 /* disable via firewire interface */
2716 u8 write_enable;
2717 u8 disable;
2718
2719 /* disable must be done via function #0 */
2720 if (PCI_FUNC(dev->devfn))
2721 return;
2722 /*
2723 * RICOH 0xe823 SD/MMC card reader fails to recognize
2724 * certain types of SD/MMC cards. Lowering the SD base
2725 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2726 *
2727 * 0x150 - SD2.0 mode enable for changing base clock
2728 * frequency to 50Mhz
2729 * 0xe1 - Base clock frequency
2730 * 0x32 - 50Mhz new clock frequency
2731 * 0xf9 - Key register for 0x150
2732 * 0xfc - key register for 0xe1
2733 */
2734 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2735 pci_write_config_byte(dev, 0xf9, 0xfc);
2736 pci_write_config_byte(dev, 0x150, 0x10);
2737 pci_write_config_byte(dev, 0xf9, 0x00);
2738 pci_write_config_byte(dev, 0xfc, 0x01);
2739 pci_write_config_byte(dev, 0xe1, 0x32);
2740 pci_write_config_byte(dev, 0xfc, 0x00);
2741
2742 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2743 }
2744
2745 pci_read_config_byte(dev, 0xCB, &disable);
2746
2747 if (disable & 0x02)
2748 return;
2749
2750 pci_read_config_byte(dev, 0xCA, &write_enable);
2751 pci_write_config_byte(dev, 0xCA, 0x57);
2752 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2753 pci_write_config_byte(dev, 0xCA, write_enable);
2754
2755 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2756 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2757
2758}
2759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2762DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2763#endif /*CONFIG_MMC_RICOH_MMC*/
2764
2765#ifdef CONFIG_DMAR_TABLE
2766#define VTUNCERRMSK_REG 0x1ac
2767#define VTD_MSK_SPEC_ERRORS (1 << 31)
2768/*
2769 * This is a quirk for masking vt-d spec defined errors to platform error
2770 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2771 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2772 * on the RAS config settings of the platform) when a vt-d fault happens.
2773 * The resulting SMI caused the system to hang.
2774 *
2775 * VT-d spec related errors are already handled by the VT-d OS code, so no
2776 * need to report the same error through other channels.
2777 */
2778static void vtd_mask_spec_errors(struct pci_dev *dev)
2779{
2780 u32 word;
2781
2782 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2783 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2784}
2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2786DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2787#endif
2788
2789static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2790{
2791 /* TI 816x devices do not have class code set when in PCIe boot mode */
2792 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2793 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2794}
2795DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2796 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2797
2798/* Some PCIe devices do not work reliably with the claimed maximum
2799 * payload size supported.
2800 */
2801static void __devinit fixup_mpss_256(struct pci_dev *dev)
2802{
2803 dev->pcie_mpss = 1; /* 256 bytes */
2804}
2805DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2806 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2807DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2808 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2809DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2810 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2811
2812/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2813 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2814 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2815 * until all of the devices are discovered and buses walked, read completion
2816 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2817 * it is possible to hotplug a device with MPS of 256B.
2818 */
2819static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2820{
2821 int err;
2822 u16 rcc;
2823
2824 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2825 return;
2826
2827 /* Intel errata specifies bits to change but does not say what they are.
2828 * Keeping them magical until such time as the registers and values can
2829 * be explained.
2830 */
2831 err = pci_read_config_word(dev, 0x48, &rcc);
2832 if (err) {
2833 dev_err(&dev->dev, "Error attempting to read the read "
2834 "completion coalescing register.\n");
2835 return;
2836 }
2837
2838 if (!(rcc & (1 << 10)))
2839 return;
2840
2841 rcc &= ~(1 << 10);
2842
2843 err = pci_write_config_word(dev, 0x48, rcc);
2844 if (err) {
2845 dev_err(&dev->dev, "Error attempting to write the read "
2846 "completion coalescing register.\n");
2847 return;
2848 }
2849
2850 pr_info_once("Read completion coalescing disabled due to hardware "
2851 "errata relating to 256B MPS.\n");
2852}
2853/* Intel 5000 series memory controllers and ports 2-7 */
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2868/* Intel 5100 series memory controllers and ports 2-7 */
2869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2877DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2880
2881
2882static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev)
2883{
2884 ktime_t calltime, delta, rettime;
2885 unsigned long long duration;
2886
2887 printk(KERN_DEBUG "calling %pF @ %i for %s\n",
2888 fn, task_pid_nr(current), dev_name(&dev->dev));
2889 calltime = ktime_get();
2890 fn(dev);
2891 rettime = ktime_get();
2892 delta = ktime_sub(rettime, calltime);
2893 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2894 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n",
2895 fn, duration, dev_name(&dev->dev));
2896}
2897
2898/*
2899 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2900 * even though no one is handling them (f.e. i915 driver is never loaded).
2901 * Additionally the interrupt destination is not set up properly
2902 * and the interrupt ends up -somewhere-.
2903 *
2904 * These spurious interrupts are "sticky" and the kernel disables
2905 * the (shared) interrupt line after 100.000+ generated interrupts.
2906 *
2907 * Fix it by disabling the still enabled interrupts.
2908 * This resolves crashes often seen on monitor unplug.
2909 */
2910#define I915_DEIER_REG 0x4400c
2911static void __devinit disable_igfx_irq(struct pci_dev *dev)
2912{
2913 void __iomem *regs = pci_iomap(dev, 0, 0);
2914 if (regs == NULL) {
2915 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2916 return;
2917 }
2918
2919 /* Check if any interrupt line is still enabled */
2920 if (readl(regs + I915_DEIER_REG) != 0) {
2921 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2922 "disabling\n");
2923
2924 writel(0, regs + I915_DEIER_REG);
2925 }
2926
2927 pci_iounmap(dev, regs);
2928}
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931
2932static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2933 struct pci_fixup *end)
2934{
2935 for (; f < end; f++)
2936 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2937 f->class == (u32) PCI_ANY_ID) &&
2938 (f->vendor == dev->vendor ||
2939 f->vendor == (u16) PCI_ANY_ID) &&
2940 (f->device == dev->device ||
2941 f->device == (u16) PCI_ANY_ID)) {
2942 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2943 if (initcall_debug)
2944 do_one_fixup_debug(f->hook, dev);
2945 else
2946 f->hook(dev);
2947 }
2948}
2949
2950extern struct pci_fixup __start_pci_fixups_early[];
2951extern struct pci_fixup __end_pci_fixups_early[];
2952extern struct pci_fixup __start_pci_fixups_header[];
2953extern struct pci_fixup __end_pci_fixups_header[];
2954extern struct pci_fixup __start_pci_fixups_final[];
2955extern struct pci_fixup __end_pci_fixups_final[];
2956extern struct pci_fixup __start_pci_fixups_enable[];
2957extern struct pci_fixup __end_pci_fixups_enable[];
2958extern struct pci_fixup __start_pci_fixups_resume[];
2959extern struct pci_fixup __end_pci_fixups_resume[];
2960extern struct pci_fixup __start_pci_fixups_resume_early[];
2961extern struct pci_fixup __end_pci_fixups_resume_early[];
2962extern struct pci_fixup __start_pci_fixups_suspend[];
2963extern struct pci_fixup __end_pci_fixups_suspend[];
2964
2965
2966void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2967{
2968 struct pci_fixup *start, *end;
2969
2970 switch(pass) {
2971 case pci_fixup_early:
2972 start = __start_pci_fixups_early;
2973 end = __end_pci_fixups_early;
2974 break;
2975
2976 case pci_fixup_header:
2977 start = __start_pci_fixups_header;
2978 end = __end_pci_fixups_header;
2979 break;
2980
2981 case pci_fixup_final:
2982 start = __start_pci_fixups_final;
2983 end = __end_pci_fixups_final;
2984 break;
2985
2986 case pci_fixup_enable:
2987 start = __start_pci_fixups_enable;
2988 end = __end_pci_fixups_enable;
2989 break;
2990
2991 case pci_fixup_resume:
2992 start = __start_pci_fixups_resume;
2993 end = __end_pci_fixups_resume;
2994 break;
2995
2996 case pci_fixup_resume_early:
2997 start = __start_pci_fixups_resume_early;
2998 end = __end_pci_fixups_resume_early;
2999 break;
3000
3001 case pci_fixup_suspend:
3002 start = __start_pci_fixups_suspend;
3003 end = __end_pci_fixups_suspend;
3004 break;
3005
3006 default:
3007 /* stupid compiler warning, you would think with an enum... */
3008 return;
3009 }
3010 pci_do_fixups(dev, start, end);
3011}
3012EXPORT_SYMBOL(pci_fixup_device);
3013
3014static int __init pci_apply_final_quirks(void)
3015{
3016 struct pci_dev *dev = NULL;
3017 u8 cls = 0;
3018 u8 tmp;
3019
3020 if (pci_cache_line_size)
3021 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3022 pci_cache_line_size << 2);
3023
3024 for_each_pci_dev(dev) {
3025 pci_fixup_device(pci_fixup_final, dev);
3026 /*
3027 * If arch hasn't set it explicitly yet, use the CLS
3028 * value shared by all PCI devices. If there's a
3029 * mismatch, fall back to the default value.
3030 */
3031 if (!pci_cache_line_size) {
3032 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3033 if (!cls)
3034 cls = tmp;
3035 if (!tmp || cls == tmp)
3036 continue;
3037
3038 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3039 "using %u bytes\n", cls << 2, tmp << 2,
3040 pci_dfl_cache_line_size << 2);
3041 pci_cache_line_size = pci_dfl_cache_line_size;
3042 }
3043 }
3044 if (!pci_cache_line_size) {
3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046 cls << 2, pci_dfl_cache_line_size << 2);
3047 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3048 }
3049
3050 return 0;
3051}
3052
3053fs_initcall_sync(pci_apply_final_quirks);
3054
3055/*
3056 * Followings are device-specific reset methods which can be used to
3057 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3058 * not available.
3059 */
3060static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3061{
3062 int pos;
3063
3064 /* only implement PCI_CLASS_SERIAL_USB at present */
3065 if (dev->class == PCI_CLASS_SERIAL_USB) {
3066 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3067 if (!pos)
3068 return -ENOTTY;
3069
3070 if (probe)
3071 return 0;
3072
3073 pci_write_config_byte(dev, pos + 0x4, 1);
3074 msleep(100);
3075
3076 return 0;
3077 } else {
3078 return -ENOTTY;
3079 }
3080}
3081
3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3083{
3084 int pos;
3085
3086 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3087 if (!pos)
3088 return -ENOTTY;
3089
3090 if (probe)
3091 return 0;
3092
3093 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3094 PCI_EXP_DEVCTL_BCR_FLR);
3095 msleep(100);
3096
3097 return 0;
3098}
3099
3100#include "../gpu/drm/i915/i915_reg.h"
3101#define MSG_CTL 0x45010
3102#define NSDE_PWR_STATE 0xd0100
3103#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3104
3105static int reset_ivb_igd(struct pci_dev *dev, int probe)
3106{
3107 void __iomem *mmio_base;
3108 unsigned long timeout;
3109 u32 val;
3110
3111 if (probe)
3112 return 0;
3113
3114 mmio_base = pci_iomap(dev, 0, 0);
3115 if (!mmio_base)
3116 return -ENOMEM;
3117
3118 iowrite32(0x00000002, mmio_base + MSG_CTL);
3119
3120 /*
3121 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3122 * driver loaded sets the right bits. However, this's a reset and
3123 * the bits have been set by i915 previously, so we clobber
3124 * SOUTH_CHICKEN2 register directly here.
3125 */
3126 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3127
3128 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3129 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3130
3131 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3132 do {
3133 val = ioread32(mmio_base + PCH_PP_STATUS);
3134 if ((val & 0xb0000000) == 0)
3135 goto reset_complete;
3136 msleep(10);
3137 } while (time_before(jiffies, timeout));
3138 dev_warn(&dev->dev, "timeout during reset\n");
3139
3140reset_complete:
3141 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3142
3143 pci_iounmap(dev, mmio_base);
3144 return 0;
3145}
3146
3147#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3148#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3149#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3150
3151static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3152 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3153 reset_intel_82599_sfp_virtfn },
3154 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3155 reset_ivb_igd },
3156 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3157 reset_ivb_igd },
3158 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3159 reset_intel_generic_dev },
3160 { 0 }
3161};
3162
3163/*
3164 * These device-specific reset methods are here rather than in a driver
3165 * because when a host assigns a device to a guest VM, the host may need
3166 * to reset the device but probably doesn't have a driver for it.
3167 */
3168int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3169{
3170 const struct pci_dev_reset_methods *i;
3171
3172 for (i = pci_dev_reset_methods; i->reset; i++) {
3173 if ((i->vendor == dev->vendor ||
3174 i->vendor == (u16)PCI_ANY_ID) &&
3175 (i->device == dev->device ||
3176 i->device == (u16)PCI_ANY_ID))
3177 return i->reset(dev, probe);
3178 }
3179
3180 return -ENOTTY;
3181}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/bitfield.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/pci.h>
20#include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/dmi.h>
25#include <linux/ioport.h>
26#include <linux/sched.h>
27#include <linux/ktime.h>
28#include <linux/mm.h>
29#include <linux/nvme.h>
30#include <linux/platform_data/x86/apple.h>
31#include <linux/pm_runtime.h>
32#include <linux/suspend.h>
33#include <linux/switchtec.h>
34#include "pci.h"
35
36static ktime_t fixup_debug_start(struct pci_dev *dev,
37 void (*fn)(struct pci_dev *dev))
38{
39 if (initcall_debug)
40 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
41
42 return ktime_get();
43}
44
45static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
46 void (*fn)(struct pci_dev *dev))
47{
48 ktime_t delta, rettime;
49 unsigned long long duration;
50
51 rettime = ktime_get();
52 delta = ktime_sub(rettime, calltime);
53 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
54 if (initcall_debug || duration > 10000)
55 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
56}
57
58static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
59 struct pci_fixup *end)
60{
61 ktime_t calltime;
62
63 for (; f < end; f++)
64 if ((f->class == (u32) (dev->class >> f->class_shift) ||
65 f->class == (u32) PCI_ANY_ID) &&
66 (f->vendor == dev->vendor ||
67 f->vendor == (u16) PCI_ANY_ID) &&
68 (f->device == dev->device ||
69 f->device == (u16) PCI_ANY_ID)) {
70 void (*hook)(struct pci_dev *dev);
71#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
72 hook = offset_to_ptr(&f->hook_offset);
73#else
74 hook = f->hook;
75#endif
76 calltime = fixup_debug_start(dev, hook);
77 hook(dev);
78 fixup_debug_report(dev, calltime, hook);
79 }
80}
81
82extern struct pci_fixup __start_pci_fixups_early[];
83extern struct pci_fixup __end_pci_fixups_early[];
84extern struct pci_fixup __start_pci_fixups_header[];
85extern struct pci_fixup __end_pci_fixups_header[];
86extern struct pci_fixup __start_pci_fixups_final[];
87extern struct pci_fixup __end_pci_fixups_final[];
88extern struct pci_fixup __start_pci_fixups_enable[];
89extern struct pci_fixup __end_pci_fixups_enable[];
90extern struct pci_fixup __start_pci_fixups_resume[];
91extern struct pci_fixup __end_pci_fixups_resume[];
92extern struct pci_fixup __start_pci_fixups_resume_early[];
93extern struct pci_fixup __end_pci_fixups_resume_early[];
94extern struct pci_fixup __start_pci_fixups_suspend[];
95extern struct pci_fixup __end_pci_fixups_suspend[];
96extern struct pci_fixup __start_pci_fixups_suspend_late[];
97extern struct pci_fixup __end_pci_fixups_suspend_late[];
98
99static bool pci_apply_fixup_final_quirks;
100
101void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
102{
103 struct pci_fixup *start, *end;
104
105 switch (pass) {
106 case pci_fixup_early:
107 start = __start_pci_fixups_early;
108 end = __end_pci_fixups_early;
109 break;
110
111 case pci_fixup_header:
112 start = __start_pci_fixups_header;
113 end = __end_pci_fixups_header;
114 break;
115
116 case pci_fixup_final:
117 if (!pci_apply_fixup_final_quirks)
118 return;
119 start = __start_pci_fixups_final;
120 end = __end_pci_fixups_final;
121 break;
122
123 case pci_fixup_enable:
124 start = __start_pci_fixups_enable;
125 end = __end_pci_fixups_enable;
126 break;
127
128 case pci_fixup_resume:
129 start = __start_pci_fixups_resume;
130 end = __end_pci_fixups_resume;
131 break;
132
133 case pci_fixup_resume_early:
134 start = __start_pci_fixups_resume_early;
135 end = __end_pci_fixups_resume_early;
136 break;
137
138 case pci_fixup_suspend:
139 start = __start_pci_fixups_suspend;
140 end = __end_pci_fixups_suspend;
141 break;
142
143 case pci_fixup_suspend_late:
144 start = __start_pci_fixups_suspend_late;
145 end = __end_pci_fixups_suspend_late;
146 break;
147
148 default:
149 /* stupid compiler warning, you would think with an enum... */
150 return;
151 }
152 pci_do_fixups(dev, start, end);
153}
154EXPORT_SYMBOL(pci_fixup_device);
155
156static int __init pci_apply_final_quirks(void)
157{
158 struct pci_dev *dev = NULL;
159 u8 cls = 0;
160 u8 tmp;
161
162 if (pci_cache_line_size)
163 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
164
165 pci_apply_fixup_final_quirks = true;
166 for_each_pci_dev(dev) {
167 pci_fixup_device(pci_fixup_final, dev);
168 /*
169 * If arch hasn't set it explicitly yet, use the CLS
170 * value shared by all PCI devices. If there's a
171 * mismatch, fall back to the default value.
172 */
173 if (!pci_cache_line_size) {
174 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
175 if (!cls)
176 cls = tmp;
177 if (!tmp || cls == tmp)
178 continue;
179
180 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
181 cls << 2, tmp << 2,
182 pci_dfl_cache_line_size << 2);
183 pci_cache_line_size = pci_dfl_cache_line_size;
184 }
185 }
186
187 if (!pci_cache_line_size) {
188 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
189 pci_dfl_cache_line_size << 2);
190 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
191 }
192
193 return 0;
194}
195fs_initcall_sync(pci_apply_final_quirks);
196
197/*
198 * Decoding should be disabled for a PCI device during BAR sizing to avoid
199 * conflict. But doing so may cause problems on host bridge and perhaps other
200 * key system devices. For devices that need to have mmio decoding always-on,
201 * we need to set the dev->mmio_always_on bit.
202 */
203static void quirk_mmio_always_on(struct pci_dev *dev)
204{
205 dev->mmio_always_on = 1;
206}
207DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
208 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
209
210/*
211 * The Mellanox Tavor device gives false positive parity errors. Disable
212 * parity error reporting.
213 */
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
216
217/*
218 * Deal with broken BIOSes that neglect to enable passive release,
219 * which can cause problems in combination with the 82441FX/PPro MTRRs
220 */
221static void quirk_passive_release(struct pci_dev *dev)
222{
223 struct pci_dev *d = NULL;
224 unsigned char dlc;
225
226 /*
227 * We have to make sure a particular bit is set in the PIIX3
228 * ISA bridge, so we have to go out and find it.
229 */
230 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
231 pci_read_config_byte(d, 0x82, &dlc);
232 if (!(dlc & 1<<1)) {
233 pci_info(d, "PIIX3: Enabling Passive Release\n");
234 dlc |= 1<<1;
235 pci_write_config_byte(d, 0x82, dlc);
236 }
237 }
238}
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
240DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
241
242#ifdef CONFIG_X86_32
243/*
244 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
245 * workaround but VIA don't answer queries. If you happen to have good
246 * contacts at VIA ask them for me please -- Alan
247 *
248 * This appears to be BIOS not version dependent. So presumably there is a
249 * chipset level fix.
250 */
251static void quirk_isa_dma_hangs(struct pci_dev *dev)
252{
253 if (!isa_dma_bridge_buggy) {
254 isa_dma_bridge_buggy = 1;
255 pci_info(dev, "Activating ISA DMA hang workarounds\n");
256 }
257}
258/*
259 * It's not totally clear which chipsets are the problematic ones. We know
260 * 82C586 and 82C596 variants are affected.
261 */
262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
269#endif
270
271/*
272 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
273 * for some HT machines to use C4 w/o hanging.
274 */
275static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
276{
277 u32 pmbase;
278 u16 pm1a;
279
280 pci_read_config_dword(dev, 0x40, &pmbase);
281 pmbase = pmbase & 0xff80;
282 pm1a = inw(pmbase);
283
284 if (pm1a & 0x10) {
285 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
286 outw(0x10, pmbase);
287 }
288}
289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
290
291/* Chipsets where PCI->PCI transfers vanish or hang */
292static void quirk_nopcipci(struct pci_dev *dev)
293{
294 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
295 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
296 pci_pci_problems |= PCIPCI_FAIL;
297 }
298}
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
301
302static void quirk_nopciamd(struct pci_dev *dev)
303{
304 u8 rev;
305 pci_read_config_byte(dev, 0x08, &rev);
306 if (rev == 0x13) {
307 /* Erratum 24 */
308 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
309 pci_pci_problems |= PCIAGP_FAIL;
310 }
311}
312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
313
314/* Triton requires workarounds to be used by the drivers */
315static void quirk_triton(struct pci_dev *dev)
316{
317 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
318 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
319 pci_pci_problems |= PCIPCI_TRITON;
320 }
321}
322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
326
327/*
328 * VIA Apollo KT133 needs PCI latency patch
329 * Made according to a Windows driver-based patch by George E. Breese;
330 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
331 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
332 * which Mr Breese based his work.
333 *
334 * Updated based on further information from the site and also on
335 * information provided by VIA
336 */
337static void quirk_vialatency(struct pci_dev *dev)
338{
339 struct pci_dev *p;
340 u8 busarb;
341
342 /*
343 * Ok, we have a potential problem chipset here. Now see if we have
344 * a buggy southbridge.
345 */
346 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
347 if (p != NULL) {
348
349 /*
350 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
351 * thanks Dan Hollis.
352 * Check for buggy part revisions
353 */
354 if (p->revision < 0x40 || p->revision > 0x42)
355 goto exit;
356 } else {
357 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
358 if (p == NULL) /* No problem parts */
359 goto exit;
360
361 /* Check for buggy part revisions */
362 if (p->revision < 0x10 || p->revision > 0x12)
363 goto exit;
364 }
365
366 /*
367 * Ok we have the problem. Now set the PCI master grant to occur
368 * every master grant. The apparent bug is that under high PCI load
369 * (quite common in Linux of course) you can get data loss when the
370 * CPU is held off the bus for 3 bus master requests. This happens
371 * to include the IDE controllers....
372 *
373 * VIA only apply this fix when an SB Live! is present but under
374 * both Linux and Windows this isn't enough, and we have seen
375 * corruption without SB Live! but with things like 3 UDMA IDE
376 * controllers. So we ignore that bit of the VIA recommendation..
377 */
378 pci_read_config_byte(dev, 0x76, &busarb);
379
380 /*
381 * Set bit 4 and bit 5 of byte 76 to 0x01
382 * "Master priority rotation on every PCI master grant"
383 */
384 busarb &= ~(1<<5);
385 busarb |= (1<<4);
386 pci_write_config_byte(dev, 0x76, busarb);
387 pci_info(dev, "Applying VIA southbridge workaround\n");
388exit:
389 pci_dev_put(p);
390}
391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
394/* Must restore this on a resume from RAM */
395DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
396DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
397DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
398
399/* VIA Apollo VP3 needs ETBF on BT848/878 */
400static void quirk_viaetbf(struct pci_dev *dev)
401{
402 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
403 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
404 pci_pci_problems |= PCIPCI_VIAETBF;
405 }
406}
407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
408
409static void quirk_vsfx(struct pci_dev *dev)
410{
411 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
412 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
413 pci_pci_problems |= PCIPCI_VSFX;
414 }
415}
416DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
417
418/*
419 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
420 * space. Latency must be set to 0xA and Triton workaround applied too.
421 * [Info kindly provided by ALi]
422 */
423static void quirk_alimagik(struct pci_dev *dev)
424{
425 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
426 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
427 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
428 }
429}
430DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
432
433/* Natoma has some interesting boundary conditions with Zoran stuff at least */
434static void quirk_natoma(struct pci_dev *dev)
435{
436 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
437 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
438 pci_pci_problems |= PCIPCI_NATOMA;
439 }
440}
441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
447
448/*
449 * This chip can cause PCI parity errors if config register 0xA0 is read
450 * while DMAs are occurring.
451 */
452static void quirk_citrine(struct pci_dev *dev)
453{
454 dev->cfg_size = 0xA0;
455}
456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
457
458/*
459 * This chip can cause bus lockups if config addresses above 0x600
460 * are read or written.
461 */
462static void quirk_nfp6000(struct pci_dev *dev)
463{
464 dev->cfg_size = 0x600;
465}
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
470
471/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
472static void quirk_extend_bar_to_page(struct pci_dev *dev)
473{
474 int i;
475
476 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
477 struct resource *r = &dev->resource[i];
478
479 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
480 r->end = PAGE_SIZE - 1;
481 r->start = 0;
482 r->flags |= IORESOURCE_UNSET;
483 pci_info(dev, "expanded BAR %d to page size: %pR\n",
484 i, r);
485 }
486 }
487}
488DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
489
490/*
491 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
492 * If it's needed, re-allocate the region.
493 */
494static void quirk_s3_64M(struct pci_dev *dev)
495{
496 struct resource *r = &dev->resource[0];
497
498 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
499 r->flags |= IORESOURCE_UNSET;
500 r->start = 0;
501 r->end = 0x3ffffff;
502 }
503}
504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
506
507static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
508 const char *name)
509{
510 u32 region;
511 struct pci_bus_region bus_region;
512 struct resource *res = dev->resource + pos;
513
514 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
515
516 if (!region)
517 return;
518
519 res->name = pci_name(dev);
520 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
521 res->flags |=
522 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
523 region &= ~(size - 1);
524
525 /* Convert from PCI bus to resource space */
526 bus_region.start = region;
527 bus_region.end = region + size - 1;
528 pcibios_bus_to_resource(dev->bus, res, &bus_region);
529
530 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
531 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
532}
533
534/*
535 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
536 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
537 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
538 * (which conflicts w/ BAR1's memory range).
539 *
540 * CS553x's ISA PCI BARs may also be read-only (ref:
541 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
542 */
543static void quirk_cs5536_vsa(struct pci_dev *dev)
544{
545 static char *name = "CS5536 ISA bridge";
546
547 if (pci_resource_len(dev, 0) != 8) {
548 quirk_io(dev, 0, 8, name); /* SMB */
549 quirk_io(dev, 1, 256, name); /* GPIO */
550 quirk_io(dev, 2, 64, name); /* MFGPT */
551 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
552 name);
553 }
554}
555DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
556
557static void quirk_io_region(struct pci_dev *dev, int port,
558 unsigned int size, int nr, const char *name)
559{
560 u16 region;
561 struct pci_bus_region bus_region;
562 struct resource *res = dev->resource + nr;
563
564 pci_read_config_word(dev, port, ®ion);
565 region &= ~(size - 1);
566
567 if (!region)
568 return;
569
570 res->name = pci_name(dev);
571 res->flags = IORESOURCE_IO;
572
573 /* Convert from PCI bus to resource space */
574 bus_region.start = region;
575 bus_region.end = region + size - 1;
576 pcibios_bus_to_resource(dev->bus, res, &bus_region);
577
578 if (!pci_claim_resource(dev, nr))
579 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
580}
581
582/*
583 * ATI Northbridge setups MCE the processor if you even read somewhere
584 * between 0x3b0->0x3bb or read 0x3d3
585 */
586static void quirk_ati_exploding_mce(struct pci_dev *dev)
587{
588 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
589 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
590 request_region(0x3b0, 0x0C, "RadeonIGP");
591 request_region(0x3d3, 0x01, "RadeonIGP");
592}
593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
594
595/*
596 * In the AMD NL platform, this device ([1022:7912]) has a class code of
597 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
598 * claim it.
599 *
600 * But the dwc3 driver is a more specific driver for this device, and we'd
601 * prefer to use it instead of xhci. To prevent xhci from claiming the
602 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
603 * defines as "USB device (not host controller)". The dwc3 driver can then
604 * claim it based on its Vendor and Device ID.
605 */
606static void quirk_amd_nl_class(struct pci_dev *pdev)
607{
608 u32 class = pdev->class;
609
610 /* Use "USB Device (not host controller)" class */
611 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
612 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
613 class, pdev->class);
614}
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
616 quirk_amd_nl_class);
617
618/*
619 * Synopsys USB 3.x host HAPS platform has a class code of
620 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
621 * devices should use dwc3-haps driver. Change these devices' class code to
622 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
623 * them.
624 */
625static void quirk_synopsys_haps(struct pci_dev *pdev)
626{
627 u32 class = pdev->class;
628
629 switch (pdev->device) {
630 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
631 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
633 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
634 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
635 class, pdev->class);
636 break;
637 }
638}
639DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
640 PCI_CLASS_SERIAL_USB_XHCI, 0,
641 quirk_synopsys_haps);
642
643/*
644 * Let's make the southbridge information explicit instead of having to
645 * worry about people probing the ACPI areas, for example.. (Yes, it
646 * happens, and if you read the wrong ACPI register it will put the machine
647 * to sleep with no way of waking it up again. Bummer).
648 *
649 * ALI M7101: Two IO regions pointed to by words at
650 * 0xE0 (64 bytes of ACPI registers)
651 * 0xE2 (32 bytes of SMB registers)
652 */
653static void quirk_ali7101_acpi(struct pci_dev *dev)
654{
655 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
656 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
657}
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
659
660static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
661{
662 u32 devres;
663 u32 mask, size, base;
664
665 pci_read_config_dword(dev, port, &devres);
666 if ((devres & enable) != enable)
667 return;
668 mask = (devres >> 16) & 15;
669 base = devres & 0xffff;
670 size = 16;
671 for (;;) {
672 unsigned int bit = size >> 1;
673 if ((bit & mask) == bit)
674 break;
675 size = bit;
676 }
677 /*
678 * For now we only print it out. Eventually we'll want to
679 * reserve it (at least if it's in the 0x1000+ range), but
680 * let's get enough confirmation reports first.
681 */
682 base &= -size;
683 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
684}
685
686static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
687{
688 u32 devres;
689 u32 mask, size, base;
690
691 pci_read_config_dword(dev, port, &devres);
692 if ((devres & enable) != enable)
693 return;
694 base = devres & 0xffff0000;
695 mask = (devres & 0x3f) << 16;
696 size = 128 << 16;
697 for (;;) {
698 unsigned int bit = size >> 1;
699 if ((bit & mask) == bit)
700 break;
701 size = bit;
702 }
703
704 /*
705 * For now we only print it out. Eventually we'll want to
706 * reserve it, but let's get enough confirmation reports first.
707 */
708 base &= -size;
709 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
710}
711
712/*
713 * PIIX4 ACPI: Two IO regions pointed to by longwords at
714 * 0x40 (64 bytes of ACPI registers)
715 * 0x90 (16 bytes of SMB registers)
716 * and a few strange programmable PIIX4 device resources.
717 */
718static void quirk_piix4_acpi(struct pci_dev *dev)
719{
720 u32 res_a;
721
722 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
723 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
724
725 /* Device resource A has enables for some of the other ones */
726 pci_read_config_dword(dev, 0x5c, &res_a);
727
728 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
729 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
730
731 /* Device resource D is just bitfields for static resources */
732
733 /* Device 12 enabled? */
734 if (res_a & (1 << 29)) {
735 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
736 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
737 }
738 /* Device 13 enabled? */
739 if (res_a & (1 << 30)) {
740 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
741 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
742 }
743 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
744 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
745}
746DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
748
749#define ICH_PMBASE 0x40
750#define ICH_ACPI_CNTL 0x44
751#define ICH4_ACPI_EN 0x10
752#define ICH6_ACPI_EN 0x80
753#define ICH4_GPIOBASE 0x58
754#define ICH4_GPIO_CNTL 0x5c
755#define ICH4_GPIO_EN 0x10
756#define ICH6_GPIOBASE 0x48
757#define ICH6_GPIO_CNTL 0x4c
758#define ICH6_GPIO_EN 0x10
759
760/*
761 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
762 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
763 * 0x58 (64 bytes of GPIO I/O space)
764 */
765static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
766{
767 u8 enable;
768
769 /*
770 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
771 * with low legacy (and fixed) ports. We don't know the decoding
772 * priority and can't tell whether the legacy device or the one created
773 * here is really at that address. This happens on boards with broken
774 * BIOSes.
775 */
776 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
777 if (enable & ICH4_ACPI_EN)
778 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
779 "ICH4 ACPI/GPIO/TCO");
780
781 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
782 if (enable & ICH4_GPIO_EN)
783 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
784 "ICH4 GPIO");
785}
786DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
787DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
788DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
795DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
796
797static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
798{
799 u8 enable;
800
801 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
802 if (enable & ICH6_ACPI_EN)
803 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
804 "ICH6 ACPI/GPIO/TCO");
805
806 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
807 if (enable & ICH6_GPIO_EN)
808 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
809 "ICH6 GPIO");
810}
811
812static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
813 const char *name, int dynsize)
814{
815 u32 val;
816 u32 size, base;
817
818 pci_read_config_dword(dev, reg, &val);
819
820 /* Enabled? */
821 if (!(val & 1))
822 return;
823 base = val & 0xfffc;
824 if (dynsize) {
825 /*
826 * This is not correct. It is 16, 32 or 64 bytes depending on
827 * register D31:F0:ADh bits 5:4.
828 *
829 * But this gets us at least _part_ of it.
830 */
831 size = 16;
832 } else {
833 size = 128;
834 }
835 base &= ~(size-1);
836
837 /*
838 * Just print it out for now. We should reserve it after more
839 * debugging.
840 */
841 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
842}
843
844static void quirk_ich6_lpc(struct pci_dev *dev)
845{
846 /* Shared ACPI/GPIO decode with all ICH6+ */
847 ich6_lpc_acpi_gpio(dev);
848
849 /* ICH6-specific generic IO decode */
850 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
851 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
852}
853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
855
856static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
857 const char *name)
858{
859 u32 val;
860 u32 mask, base;
861
862 pci_read_config_dword(dev, reg, &val);
863
864 /* Enabled? */
865 if (!(val & 1))
866 return;
867
868 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
869 base = val & 0xfffc;
870 mask = (val >> 16) & 0xfc;
871 mask |= 3;
872
873 /*
874 * Just print it out for now. We should reserve it after more
875 * debugging.
876 */
877 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
878}
879
880/* ICH7-10 has the same common LPC generic IO decode registers */
881static void quirk_ich7_lpc(struct pci_dev *dev)
882{
883 /* We share the common ACPI/GPIO decode with ICH6 */
884 ich6_lpc_acpi_gpio(dev);
885
886 /* And have 4 ICH7+ generic decodes */
887 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
888 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
889 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
890 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
891}
892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
905
906/*
907 * VIA ACPI: One IO region pointed to by longword at
908 * 0x48 or 0x20 (256 bytes of ACPI registers)
909 */
910static void quirk_vt82c586_acpi(struct pci_dev *dev)
911{
912 if (dev->revision & 0x10)
913 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
914 "vt82c586 ACPI");
915}
916DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
917
918/*
919 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
920 * 0x48 (256 bytes of ACPI registers)
921 * 0x70 (128 bytes of hardware monitoring register)
922 * 0x90 (16 bytes of SMB registers)
923 */
924static void quirk_vt82c686_acpi(struct pci_dev *dev)
925{
926 quirk_vt82c586_acpi(dev);
927
928 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
929 "vt82c686 HW-mon");
930
931 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
932}
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
934
935/*
936 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
937 * 0x88 (128 bytes of power management registers)
938 * 0xd0 (16 bytes of SMB registers)
939 */
940static void quirk_vt8235_acpi(struct pci_dev *dev)
941{
942 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
943 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
944}
945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
946
947/*
948 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
949 * back-to-back: Disable fast back-to-back on the secondary bus segment
950 */
951static void quirk_xio2000a(struct pci_dev *dev)
952{
953 struct pci_dev *pdev;
954 u16 command;
955
956 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
957 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
958 pci_read_config_word(pdev, PCI_COMMAND, &command);
959 if (command & PCI_COMMAND_FAST_BACK)
960 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
961 }
962}
963DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
964 quirk_xio2000a);
965
966#ifdef CONFIG_X86_IO_APIC
967
968#include <asm/io_apic.h>
969
970/*
971 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
972 * devices to the external APIC.
973 *
974 * TODO: When we have device-specific interrupt routers, this code will go
975 * away from quirks.
976 */
977static void quirk_via_ioapic(struct pci_dev *dev)
978{
979 u8 tmp;
980
981 if (nr_ioapics < 1)
982 tmp = 0; /* nothing routed to external APIC */
983 else
984 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
985
986 pci_info(dev, "%s VIA external APIC routing\n",
987 tmp ? "Enabling" : "Disabling");
988
989 /* Offset 0x58: External APIC IRQ output control */
990 pci_write_config_byte(dev, 0x58, tmp);
991}
992DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
993DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994
995/*
996 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
997 * This leads to doubled level interrupt rates.
998 * Set this bit to get rid of cycle wastage.
999 * Otherwise uncritical.
1000 */
1001static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1002{
1003 u8 misc_control2;
1004#define BYPASS_APIC_DEASSERT 8
1005
1006 pci_read_config_byte(dev, 0x5B, &misc_control2);
1007 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1008 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1009 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1010 }
1011}
1012DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1013DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014
1015/*
1016 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1017 * We check all revs >= B0 (yet not in the pre production!) as the bug
1018 * is currently marked NoFix
1019 *
1020 * We have multiple reports of hangs with this chipset that went away with
1021 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1022 * of course. However the advice is demonstrably good even if so.
1023 */
1024static void quirk_amd_ioapic(struct pci_dev *dev)
1025{
1026 if (dev->revision >= 0x02) {
1027 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1028 pci_warn(dev, " : booting with the \"noapic\" option\n");
1029 }
1030}
1031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1032#endif /* CONFIG_X86_IO_APIC */
1033
1034#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1035
1036static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1037{
1038 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1039 if (dev->subsystem_device == 0xa118)
1040 dev->sriov->link = dev->devfn;
1041}
1042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1043#endif
1044
1045/*
1046 * Some settings of MMRBC can lead to data corruption so block changes.
1047 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1048 */
1049static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1050{
1051 if (dev->subordinate && dev->revision <= 0x12) {
1052 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1053 dev->revision);
1054 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1055 }
1056}
1057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1058
1059/*
1060 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1061 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1062 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1063 * of the ACPI SCI interrupt is only done for convenience.
1064 * -jgarzik
1065 */
1066static void quirk_via_acpi(struct pci_dev *d)
1067{
1068 u8 irq;
1069
1070 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1071 pci_read_config_byte(d, 0x42, &irq);
1072 irq &= 0xf;
1073 if (irq && (irq != 2))
1074 d->irq = irq;
1075}
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1078
1079/* VIA bridges which have VLink */
1080static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1081
1082static void quirk_via_bridge(struct pci_dev *dev)
1083{
1084 /* See what bridge we have and find the device ranges */
1085 switch (dev->device) {
1086 case PCI_DEVICE_ID_VIA_82C686:
1087 /*
1088 * The VT82C686 is special; it attaches to PCI and can have
1089 * any device number. All its subdevices are functions of
1090 * that single device.
1091 */
1092 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1093 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1094 break;
1095 case PCI_DEVICE_ID_VIA_8237:
1096 case PCI_DEVICE_ID_VIA_8237A:
1097 via_vlink_dev_lo = 15;
1098 break;
1099 case PCI_DEVICE_ID_VIA_8235:
1100 via_vlink_dev_lo = 16;
1101 break;
1102 case PCI_DEVICE_ID_VIA_8231:
1103 case PCI_DEVICE_ID_VIA_8233_0:
1104 case PCI_DEVICE_ID_VIA_8233A:
1105 case PCI_DEVICE_ID_VIA_8233C_0:
1106 via_vlink_dev_lo = 17;
1107 break;
1108 }
1109}
1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1118
1119/*
1120 * quirk_via_vlink - VIA VLink IRQ number update
1121 * @dev: PCI device
1122 *
1123 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1124 * the IRQ line register which usually is not relevant for PCI cards, is
1125 * actually written so that interrupts get sent to the right place.
1126 *
1127 * We only do this on systems where a VIA south bridge was detected, and
1128 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1129 */
1130static void quirk_via_vlink(struct pci_dev *dev)
1131{
1132 u8 irq, new_irq;
1133
1134 /* Check if we have VLink at all */
1135 if (via_vlink_dev_lo == -1)
1136 return;
1137
1138 new_irq = dev->irq;
1139
1140 /* Don't quirk interrupts outside the legacy IRQ range */
1141 if (!new_irq || new_irq > 15)
1142 return;
1143
1144 /* Internal device ? */
1145 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1146 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1147 return;
1148
1149 /*
1150 * This is an internal VLink device on a PIC interrupt. The BIOS
1151 * ought to have set this but may not have, so we redo it.
1152 */
1153 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1154 if (new_irq != irq) {
1155 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1156 irq, new_irq);
1157 udelay(15); /* unknown if delay really needed */
1158 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1159 }
1160}
1161DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1162
1163/*
1164 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1165 * of VT82C597 for backward compatibility. We need to switch it off to be
1166 * able to recognize the real type of the chip.
1167 */
1168static void quirk_vt82c598_id(struct pci_dev *dev)
1169{
1170 pci_write_config_byte(dev, 0xfc, 0);
1171 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1172}
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1174
1175/*
1176 * CardBus controllers have a legacy base address that enables them to
1177 * respond as i82365 pcmcia controllers. We don't want them to do this
1178 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1179 * driver does not (and should not) handle CardBus.
1180 */
1181static void quirk_cardbus_legacy(struct pci_dev *dev)
1182{
1183 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1184}
1185DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1186 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1187DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1188 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1189
1190/*
1191 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1192 * what the designers were smoking but let's not inhale...
1193 *
1194 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1195 * turn it off!
1196 */
1197static void quirk_amd_ordering(struct pci_dev *dev)
1198{
1199 u32 pcic;
1200 pci_read_config_dword(dev, 0x4C, &pcic);
1201 if ((pcic & 6) != 6) {
1202 pcic |= 6;
1203 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1204 pci_write_config_dword(dev, 0x4C, pcic);
1205 pci_read_config_dword(dev, 0x84, &pcic);
1206 pcic |= (1 << 23); /* Required in this mode */
1207 pci_write_config_dword(dev, 0x84, pcic);
1208 }
1209}
1210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1211DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212
1213/*
1214 * DreamWorks-provided workaround for Dunord I-3000 problem
1215 *
1216 * This card decodes and responds to addresses not apparently assigned to
1217 * it. We force a larger allocation to ensure that nothing gets put too
1218 * close to it.
1219 */
1220static void quirk_dunord(struct pci_dev *dev)
1221{
1222 struct resource *r = &dev->resource[1];
1223
1224 r->flags |= IORESOURCE_UNSET;
1225 r->start = 0;
1226 r->end = 0xffffff;
1227}
1228DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1229
1230/*
1231 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1232 * decoding (transparent), and does indicate this in the ProgIf.
1233 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1234 */
1235static void quirk_transparent_bridge(struct pci_dev *dev)
1236{
1237 dev->transparent = 1;
1238}
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1241
1242/*
1243 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1244 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1245 * found at http://www.national.com/analog for info on what these bits do.
1246 * <christer@weinigel.se>
1247 */
1248static void quirk_mediagx_master(struct pci_dev *dev)
1249{
1250 u8 reg;
1251
1252 pci_read_config_byte(dev, 0x41, ®);
1253 if (reg & 2) {
1254 reg &= ~2;
1255 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1256 reg);
1257 pci_write_config_byte(dev, 0x41, reg);
1258 }
1259}
1260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1261DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262
1263/*
1264 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1265 * in the odd case it is not the results are corruption hence the presence
1266 * of a Linux check.
1267 */
1268static void quirk_disable_pxb(struct pci_dev *pdev)
1269{
1270 u16 config;
1271
1272 if (pdev->revision != 0x04) /* Only C0 requires this */
1273 return;
1274 pci_read_config_word(pdev, 0x40, &config);
1275 if (config & (1<<6)) {
1276 config &= ~(1<<6);
1277 pci_write_config_word(pdev, 0x40, config);
1278 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1279 }
1280}
1281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283
1284static void quirk_amd_ide_mode(struct pci_dev *pdev)
1285{
1286 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1287 u8 tmp;
1288
1289 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1290 if (tmp == 0x01) {
1291 pci_read_config_byte(pdev, 0x40, &tmp);
1292 pci_write_config_byte(pdev, 0x40, tmp|1);
1293 pci_write_config_byte(pdev, 0x9, 1);
1294 pci_write_config_byte(pdev, 0xa, 6);
1295 pci_write_config_byte(pdev, 0x40, tmp);
1296
1297 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1298 pci_info(pdev, "set SATA to AHCI mode\n");
1299 }
1300}
1301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1302DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1304DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1306DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1308DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309
1310/* Serverworks CSB5 IDE does not fully support native mode */
1311static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1312{
1313 u8 prog;
1314 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1315 if (prog & 5) {
1316 prog &= ~5;
1317 pdev->class &= ~5;
1318 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1319 /* PCI layer will sort out resources */
1320 }
1321}
1322DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1323
1324/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1325static void quirk_ide_samemode(struct pci_dev *pdev)
1326{
1327 u8 prog;
1328
1329 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1330
1331 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1332 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1333 prog &= ~5;
1334 pdev->class &= ~5;
1335 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1336 }
1337}
1338DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1339
1340/* Some ATA devices break if put into D3 */
1341static void quirk_no_ata_d3(struct pci_dev *pdev)
1342{
1343 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1344}
1345/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1346DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1347 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1348DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1349 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1350/* ALi loses some register settings that we cannot then restore */
1351DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1352 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1353/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1354 occur when mode detecting */
1355DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1356 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1357
1358/*
1359 * This was originally an Alpha-specific thing, but it really fits here.
1360 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1361 */
1362static void quirk_eisa_bridge(struct pci_dev *dev)
1363{
1364 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1365}
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1367
1368/*
1369 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1370 * is not activated. The myth is that Asus said that they do not want the
1371 * users to be irritated by just another PCI Device in the Win98 device
1372 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1373 * package 2.7.0 for details)
1374 *
1375 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1376 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1377 * becomes necessary to do this tweak in two steps -- the chosen trigger
1378 * is either the Host bridge (preferred) or on-board VGA controller.
1379 *
1380 * Note that we used to unhide the SMBus that way on Toshiba laptops
1381 * (Satellite A40 and Tecra M2) but then found that the thermal management
1382 * was done by SMM code, which could cause unsynchronized concurrent
1383 * accesses to the SMBus registers, with potentially bad effects. Thus you
1384 * should be very careful when adding new entries: if SMM is accessing the
1385 * Intel SMBus, this is a very good reason to leave it hidden.
1386 *
1387 * Likewise, many recent laptops use ACPI for thermal management. If the
1388 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1389 * natively, and keeping the SMBus hidden is the right thing to do. If you
1390 * are about to add an entry in the table below, please first disassemble
1391 * the DSDT and double-check that there is no code accessing the SMBus.
1392 */
1393static int asus_hides_smbus;
1394
1395static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1396{
1397 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1398 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1399 switch (dev->subsystem_device) {
1400 case 0x8025: /* P4B-LX */
1401 case 0x8070: /* P4B */
1402 case 0x8088: /* P4B533 */
1403 case 0x1626: /* L3C notebook */
1404 asus_hides_smbus = 1;
1405 }
1406 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1407 switch (dev->subsystem_device) {
1408 case 0x80b1: /* P4GE-V */
1409 case 0x80b2: /* P4PE */
1410 case 0x8093: /* P4B533-V */
1411 asus_hides_smbus = 1;
1412 }
1413 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1414 switch (dev->subsystem_device) {
1415 case 0x8030: /* P4T533 */
1416 asus_hides_smbus = 1;
1417 }
1418 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1419 switch (dev->subsystem_device) {
1420 case 0x8070: /* P4G8X Deluxe */
1421 asus_hides_smbus = 1;
1422 }
1423 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1424 switch (dev->subsystem_device) {
1425 case 0x80c9: /* PU-DLS */
1426 asus_hides_smbus = 1;
1427 }
1428 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1429 switch (dev->subsystem_device) {
1430 case 0x1751: /* M2N notebook */
1431 case 0x1821: /* M5N notebook */
1432 case 0x1897: /* A6L notebook */
1433 asus_hides_smbus = 1;
1434 }
1435 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1436 switch (dev->subsystem_device) {
1437 case 0x184b: /* W1N notebook */
1438 case 0x186a: /* M6Ne notebook */
1439 asus_hides_smbus = 1;
1440 }
1441 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1442 switch (dev->subsystem_device) {
1443 case 0x80f2: /* P4P800-X */
1444 asus_hides_smbus = 1;
1445 }
1446 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1447 switch (dev->subsystem_device) {
1448 case 0x1882: /* M6V notebook */
1449 case 0x1977: /* A6VA notebook */
1450 asus_hides_smbus = 1;
1451 }
1452 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1453 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1454 switch (dev->subsystem_device) {
1455 case 0x088C: /* HP Compaq nc8000 */
1456 case 0x0890: /* HP Compaq nc6000 */
1457 asus_hides_smbus = 1;
1458 }
1459 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1460 switch (dev->subsystem_device) {
1461 case 0x12bc: /* HP D330L */
1462 case 0x12bd: /* HP D530 */
1463 case 0x006a: /* HP Compaq nx9500 */
1464 asus_hides_smbus = 1;
1465 }
1466 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1467 switch (dev->subsystem_device) {
1468 case 0x12bf: /* HP xw4100 */
1469 asus_hides_smbus = 1;
1470 }
1471 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1472 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1473 switch (dev->subsystem_device) {
1474 case 0xC00C: /* Samsung P35 notebook */
1475 asus_hides_smbus = 1;
1476 }
1477 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1478 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1479 switch (dev->subsystem_device) {
1480 case 0x0058: /* Compaq Evo N620c */
1481 asus_hides_smbus = 1;
1482 }
1483 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1484 switch (dev->subsystem_device) {
1485 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1486 /* Motherboard doesn't have Host bridge
1487 * subvendor/subdevice IDs, therefore checking
1488 * its on-board VGA controller */
1489 asus_hides_smbus = 1;
1490 }
1491 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1492 switch (dev->subsystem_device) {
1493 case 0x00b8: /* Compaq Evo D510 CMT */
1494 case 0x00b9: /* Compaq Evo D510 SFF */
1495 case 0x00ba: /* Compaq Evo D510 USDT */
1496 /* Motherboard doesn't have Host bridge
1497 * subvendor/subdevice IDs and on-board VGA
1498 * controller is disabled if an AGP card is
1499 * inserted, therefore checking USB UHCI
1500 * Controller #1 */
1501 asus_hides_smbus = 1;
1502 }
1503 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1504 switch (dev->subsystem_device) {
1505 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1506 /* Motherboard doesn't have host bridge
1507 * subvendor/subdevice IDs, therefore checking
1508 * its on-board VGA controller */
1509 asus_hides_smbus = 1;
1510 }
1511 }
1512}
1513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1523
1524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1527
1528static void asus_hides_smbus_lpc(struct pci_dev *dev)
1529{
1530 u16 val;
1531
1532 if (likely(!asus_hides_smbus))
1533 return;
1534
1535 pci_read_config_word(dev, 0xF2, &val);
1536 if (val & 0x8) {
1537 pci_write_config_word(dev, 0xF2, val & (~0x8));
1538 pci_read_config_word(dev, 0xF2, &val);
1539 if (val & 0x8)
1540 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1541 val);
1542 else
1543 pci_info(dev, "Enabled i801 SMBus device\n");
1544 }
1545}
1546DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1548DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1550DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1553DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1554DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1555DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1556DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1557DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1558DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1560
1561/* It appears we just have one such device. If not, we have a warning */
1562static void __iomem *asus_rcba_base;
1563static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1564{
1565 u32 rcba;
1566
1567 if (likely(!asus_hides_smbus))
1568 return;
1569 WARN_ON(asus_rcba_base);
1570
1571 pci_read_config_dword(dev, 0xF0, &rcba);
1572 /* use bits 31:14, 16 kB aligned */
1573 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1574 if (asus_rcba_base == NULL)
1575 return;
1576}
1577
1578static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1579{
1580 u32 val;
1581
1582 if (likely(!asus_hides_smbus || !asus_rcba_base))
1583 return;
1584
1585 /* read the Function Disable register, dword mode only */
1586 val = readl(asus_rcba_base + 0x3418);
1587
1588 /* enable the SMBus device */
1589 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1590}
1591
1592static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1593{
1594 if (likely(!asus_hides_smbus || !asus_rcba_base))
1595 return;
1596
1597 iounmap(asus_rcba_base);
1598 asus_rcba_base = NULL;
1599 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1600}
1601
1602static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1603{
1604 asus_hides_smbus_lpc_ich6_suspend(dev);
1605 asus_hides_smbus_lpc_ich6_resume_early(dev);
1606 asus_hides_smbus_lpc_ich6_resume(dev);
1607}
1608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1609DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1610DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1611DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1612
1613/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1614static void quirk_sis_96x_smbus(struct pci_dev *dev)
1615{
1616 u8 val = 0;
1617 pci_read_config_byte(dev, 0x77, &val);
1618 if (val & 0x10) {
1619 pci_info(dev, "Enabling SiS 96x SMBus\n");
1620 pci_write_config_byte(dev, 0x77, val & ~0x10);
1621 }
1622}
1623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1627DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1628DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1630DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1631
1632/*
1633 * ... This is further complicated by the fact that some SiS96x south
1634 * bridges pretend to be 85C503/5513 instead. In that case see if we
1635 * spotted a compatible north bridge to make sure.
1636 * (pci_find_device() doesn't work yet)
1637 *
1638 * We can also enable the sis96x bit in the discovery register..
1639 */
1640#define SIS_DETECT_REGISTER 0x40
1641
1642static void quirk_sis_503(struct pci_dev *dev)
1643{
1644 u8 reg;
1645 u16 devid;
1646
1647 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1648 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1649 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1650 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1651 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1652 return;
1653 }
1654
1655 /*
1656 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1657 * it has already been processed. (Depends on link order, which is
1658 * apparently not guaranteed)
1659 */
1660 dev->device = devid;
1661 quirk_sis_96x_smbus(dev);
1662}
1663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1664DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665
1666/*
1667 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1668 * and MC97 modem controller are disabled when a second PCI soundcard is
1669 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1670 * -- bjd
1671 */
1672static void asus_hides_ac97_lpc(struct pci_dev *dev)
1673{
1674 u8 val;
1675 int asus_hides_ac97 = 0;
1676
1677 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1678 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1679 asus_hides_ac97 = 1;
1680 }
1681
1682 if (!asus_hides_ac97)
1683 return;
1684
1685 pci_read_config_byte(dev, 0x50, &val);
1686 if (val & 0xc0) {
1687 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1688 pci_read_config_byte(dev, 0x50, &val);
1689 if (val & 0xc0)
1690 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1691 val);
1692 else
1693 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1694 }
1695}
1696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1697DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698
1699#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1700
1701/*
1702 * If we are using libata we can drive this chip properly but must do this
1703 * early on to make the additional device appear during the PCI scanning.
1704 */
1705static void quirk_jmicron_ata(struct pci_dev *pdev)
1706{
1707 u32 conf1, conf5, class;
1708 u8 hdr;
1709
1710 /* Only poke fn 0 */
1711 if (PCI_FUNC(pdev->devfn))
1712 return;
1713
1714 pci_read_config_dword(pdev, 0x40, &conf1);
1715 pci_read_config_dword(pdev, 0x80, &conf5);
1716
1717 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1718 conf5 &= ~(1 << 24); /* Clear bit 24 */
1719
1720 switch (pdev->device) {
1721 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1722 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1723 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1724 /* The controller should be in single function ahci mode */
1725 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1726 break;
1727
1728 case PCI_DEVICE_ID_JMICRON_JMB365:
1729 case PCI_DEVICE_ID_JMICRON_JMB366:
1730 /* Redirect IDE second PATA port to the right spot */
1731 conf5 |= (1 << 24);
1732 fallthrough;
1733 case PCI_DEVICE_ID_JMICRON_JMB361:
1734 case PCI_DEVICE_ID_JMICRON_JMB363:
1735 case PCI_DEVICE_ID_JMICRON_JMB369:
1736 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1737 /* Set the class codes correctly and then direct IDE 0 */
1738 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1739 break;
1740
1741 case PCI_DEVICE_ID_JMICRON_JMB368:
1742 /* The controller should be in single function IDE mode */
1743 conf1 |= 0x00C00000; /* Set 22, 23 */
1744 break;
1745 }
1746
1747 pci_write_config_dword(pdev, 0x40, conf1);
1748 pci_write_config_dword(pdev, 0x80, conf5);
1749
1750 /* Update pdev accordingly */
1751 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1752 pdev->hdr_type = hdr & 0x7f;
1753 pdev->multifunction = !!(hdr & 0x80);
1754
1755 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1756 pdev->class = class >> 8;
1757}
1758DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1760DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1762DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1763DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1764DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1765DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1766DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1767DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1768DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1769DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1770DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1771DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1773DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1775DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1776
1777#endif
1778
1779static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1780{
1781 if (dev->multifunction) {
1782 device_disable_async_suspend(&dev->dev);
1783 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1784 }
1785}
1786DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1787DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1788DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1789DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1790
1791#ifdef CONFIG_X86_IO_APIC
1792static void quirk_alder_ioapic(struct pci_dev *pdev)
1793{
1794 int i;
1795
1796 if ((pdev->class >> 8) != 0xff00)
1797 return;
1798
1799 /*
1800 * The first BAR is the location of the IO-APIC... we must
1801 * not touch this (and it's already covered by the fixmap), so
1802 * forcibly insert it into the resource tree.
1803 */
1804 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1805 insert_resource(&iomem_resource, &pdev->resource[0]);
1806
1807 /*
1808 * The next five BARs all seem to be rubbish, so just clean
1809 * them out.
1810 */
1811 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1812 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1813}
1814DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1815#endif
1816
1817static void quirk_no_msi(struct pci_dev *dev)
1818{
1819 pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1820 dev->no_msi = 1;
1821}
1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1823DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1825DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1828
1829static void quirk_pcie_mch(struct pci_dev *pdev)
1830{
1831 pdev->no_msi = 1;
1832}
1833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1835DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1836
1837DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1838
1839/*
1840 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1841 * actually on the AMBA bus. These fake PCI devices can support SVA via
1842 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1843 *
1844 * Normally stalling must not be enabled for PCI devices, since it would
1845 * break the PCI requirement for free-flowing writes and may lead to
1846 * deadlock. We expect PCI devices to support ATS and PRI if they want to
1847 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1848 * even when a "PCI" device turns out to be a regular old SoC device
1849 * dressed up as a RCiEP and normal rules don't apply.
1850 */
1851static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1852{
1853 struct property_entry properties[] = {
1854 PROPERTY_ENTRY_BOOL("dma-can-stall"),
1855 {},
1856 };
1857
1858 if (pdev->revision != 0x21 && pdev->revision != 0x30)
1859 return;
1860
1861 pdev->pasid_no_tlp = 1;
1862
1863 /*
1864 * Set the dma-can-stall property on ACPI platforms. Device tree
1865 * can set it directly.
1866 */
1867 if (!pdev->dev.of_node &&
1868 device_create_managed_software_node(&pdev->dev, properties, NULL))
1869 pci_warn(pdev, "could not add stall property");
1870}
1871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1874DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1876DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1877
1878/*
1879 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1880 * together on certain PXH-based systems.
1881 */
1882static void quirk_pcie_pxh(struct pci_dev *dev)
1883{
1884 dev->no_msi = 1;
1885 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1886}
1887DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1888DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1889DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1890DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1891DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1892
1893/*
1894 * Some Intel PCI Express chipsets have trouble with downstream device
1895 * power management.
1896 */
1897static void quirk_intel_pcie_pm(struct pci_dev *dev)
1898{
1899 pci_pm_d3hot_delay = 120;
1900 dev->no_d1d2 = 1;
1901}
1902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1903DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1904DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1906DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1907DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1923
1924static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1925{
1926 if (dev->d3hot_delay >= delay)
1927 return;
1928
1929 dev->d3hot_delay = delay;
1930 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1931 dev->d3hot_delay);
1932}
1933
1934static void quirk_radeon_pm(struct pci_dev *dev)
1935{
1936 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1937 dev->subsystem_device == 0x00e2)
1938 quirk_d3hot_delay(dev, 20);
1939}
1940DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1941
1942/*
1943 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1944 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1945 *
1946 * The kernel attempts to transition these devices to D3cold, but that seems
1947 * to be ineffective on the platforms in question; the PCI device appears to
1948 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1949 * extended delay in order to succeed.
1950 */
1951static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1952{
1953 quirk_d3hot_delay(dev, 20);
1954}
1955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1956DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1957DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1958
1959#ifdef CONFIG_X86_IO_APIC
1960static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1961{
1962 noioapicreroute = 1;
1963 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1964
1965 return 0;
1966}
1967
1968static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1969 /*
1970 * Systems to exclude from boot interrupt reroute quirks
1971 */
1972 {
1973 .callback = dmi_disable_ioapicreroute,
1974 .ident = "ASUSTek Computer INC. M2N-LR",
1975 .matches = {
1976 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1977 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1978 },
1979 },
1980 {}
1981};
1982
1983/*
1984 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1985 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1986 * that a PCI device's interrupt handler is installed on the boot interrupt
1987 * line instead.
1988 */
1989static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1990{
1991 dmi_check_system(boot_interrupt_dmi_table);
1992 if (noioapicquirk || noioapicreroute)
1993 return;
1994
1995 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1996 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1997 dev->vendor, dev->device);
1998}
1999DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2000DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2001DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2002DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2004DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2005DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2006DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2007DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
2008DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
2009DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
2010DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
2011DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
2012DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
2013DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
2014DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
2015
2016/*
2017 * On some chipsets we can disable the generation of legacy INTx boot
2018 * interrupts.
2019 */
2020
2021/*
2022 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2023 * 300641-004US, section 5.7.3.
2024 *
2025 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2026 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2027 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2028 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2029 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2030 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2031 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2032 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2033 * Core IO on Xeon Scalable, see Intel order no 610950.
2034 */
2035#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2036#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2037
2038#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2039#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2040
2041static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2042{
2043 u16 pci_config_word;
2044 u32 pci_config_dword;
2045
2046 if (noioapicquirk)
2047 return;
2048
2049 switch (dev->device) {
2050 case PCI_DEVICE_ID_INTEL_ESB_10:
2051 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2052 &pci_config_word);
2053 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2054 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2055 pci_config_word);
2056 break;
2057 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2058 case 0x0e28: /* Xeon E5/E7 V2 */
2059 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2060 case 0x6f28: /* Xeon D-1500 */
2061 case 0x2034: /* Xeon Scalable Family */
2062 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2063 &pci_config_dword);
2064 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2065 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2066 pci_config_dword);
2067 break;
2068 default:
2069 return;
2070 }
2071 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2072 dev->vendor, dev->device);
2073}
2074/*
2075 * Device 29 Func 5 Device IDs of IO-APIC
2076 * containing ABAR—APIC1 Alternate Base Address Register
2077 */
2078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2079 quirk_disable_intel_boot_interrupt);
2080DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2081 quirk_disable_intel_boot_interrupt);
2082
2083/*
2084 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2085 * containing Coherent Interface Protocol Interrupt Control
2086 *
2087 * Device IDs obtained from volume 2 datasheets of commented
2088 * families above.
2089 */
2090DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2091 quirk_disable_intel_boot_interrupt);
2092DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2093 quirk_disable_intel_boot_interrupt);
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2095 quirk_disable_intel_boot_interrupt);
2096DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2097 quirk_disable_intel_boot_interrupt);
2098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2099 quirk_disable_intel_boot_interrupt);
2100DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2101 quirk_disable_intel_boot_interrupt);
2102DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2103 quirk_disable_intel_boot_interrupt);
2104DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2105 quirk_disable_intel_boot_interrupt);
2106DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2107 quirk_disable_intel_boot_interrupt);
2108DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2109 quirk_disable_intel_boot_interrupt);
2110
2111/* Disable boot interrupts on HT-1000 */
2112#define BC_HT1000_FEATURE_REG 0x64
2113#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2114#define BC_HT1000_MAP_IDX 0xC00
2115#define BC_HT1000_MAP_DATA 0xC01
2116
2117static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2118{
2119 u32 pci_config_dword;
2120 u8 irq;
2121
2122 if (noioapicquirk)
2123 return;
2124
2125 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2126 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2127 BC_HT1000_PIC_REGS_ENABLE);
2128
2129 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2130 outb(irq, BC_HT1000_MAP_IDX);
2131 outb(0x00, BC_HT1000_MAP_DATA);
2132 }
2133
2134 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2135
2136 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2137 dev->vendor, dev->device);
2138}
2139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2140DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2141
2142/* Disable boot interrupts on AMD and ATI chipsets */
2143
2144/*
2145 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2146 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2147 * (due to an erratum).
2148 */
2149#define AMD_813X_MISC 0x40
2150#define AMD_813X_NOIOAMODE (1<<0)
2151#define AMD_813X_REV_B1 0x12
2152#define AMD_813X_REV_B2 0x13
2153
2154static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2155{
2156 u32 pci_config_dword;
2157
2158 if (noioapicquirk)
2159 return;
2160 if ((dev->revision == AMD_813X_REV_B1) ||
2161 (dev->revision == AMD_813X_REV_B2))
2162 return;
2163
2164 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2165 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2166 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2167
2168 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2169 dev->vendor, dev->device);
2170}
2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2172DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2174DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2175
2176#define AMD_8111_PCI_IRQ_ROUTING 0x56
2177
2178static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2179{
2180 u16 pci_config_word;
2181
2182 if (noioapicquirk)
2183 return;
2184
2185 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2186 if (!pci_config_word) {
2187 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2188 dev->vendor, dev->device);
2189 return;
2190 }
2191 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2192 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2193 dev->vendor, dev->device);
2194}
2195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2196DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2197#endif /* CONFIG_X86_IO_APIC */
2198
2199/*
2200 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2201 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2202 * Re-allocate the region if needed...
2203 */
2204static void quirk_tc86c001_ide(struct pci_dev *dev)
2205{
2206 struct resource *r = &dev->resource[0];
2207
2208 if (r->start & 0x8) {
2209 r->flags |= IORESOURCE_UNSET;
2210 r->start = 0;
2211 r->end = 0xf;
2212 }
2213}
2214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2215 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2216 quirk_tc86c001_ide);
2217
2218/*
2219 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2220 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2221 * being read correctly if bit 7 of the base address is set.
2222 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2223 * Re-allocate the regions to a 256-byte boundary if necessary.
2224 */
2225static void quirk_plx_pci9050(struct pci_dev *dev)
2226{
2227 unsigned int bar;
2228
2229 /* Fixed in revision 2 (PCI 9052). */
2230 if (dev->revision >= 2)
2231 return;
2232 for (bar = 0; bar <= 1; bar++)
2233 if (pci_resource_len(dev, bar) == 0x80 &&
2234 (pci_resource_start(dev, bar) & 0x80)) {
2235 struct resource *r = &dev->resource[bar];
2236 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2237 bar);
2238 r->flags |= IORESOURCE_UNSET;
2239 r->start = 0;
2240 r->end = 0xff;
2241 }
2242}
2243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2244 quirk_plx_pci9050);
2245/*
2246 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2247 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2248 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2249 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2250 *
2251 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2252 * driver.
2253 */
2254DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2255DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2256
2257static void quirk_netmos(struct pci_dev *dev)
2258{
2259 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2260 unsigned int num_serial = dev->subsystem_device & 0xf;
2261
2262 /*
2263 * These Netmos parts are multiport serial devices with optional
2264 * parallel ports. Even when parallel ports are present, they
2265 * are identified as class SERIAL, which means the serial driver
2266 * will claim them. To prevent this, mark them as class OTHER.
2267 * These combo devices should be claimed by parport_serial.
2268 *
2269 * The subdevice ID is of the form 0x00PS, where <P> is the number
2270 * of parallel ports and <S> is the number of serial ports.
2271 */
2272 switch (dev->device) {
2273 case PCI_DEVICE_ID_NETMOS_9835:
2274 /* Well, this rule doesn't hold for the following 9835 device */
2275 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2276 dev->subsystem_device == 0x0299)
2277 return;
2278 fallthrough;
2279 case PCI_DEVICE_ID_NETMOS_9735:
2280 case PCI_DEVICE_ID_NETMOS_9745:
2281 case PCI_DEVICE_ID_NETMOS_9845:
2282 case PCI_DEVICE_ID_NETMOS_9855:
2283 if (num_parallel) {
2284 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2285 dev->device, num_parallel, num_serial);
2286 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2287 (dev->class & 0xff);
2288 }
2289 }
2290}
2291DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2292 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2293
2294static void quirk_e100_interrupt(struct pci_dev *dev)
2295{
2296 u16 command, pmcsr;
2297 u8 __iomem *csr;
2298 u8 cmd_hi;
2299
2300 switch (dev->device) {
2301 /* PCI IDs taken from drivers/net/e100.c */
2302 case 0x1029:
2303 case 0x1030 ... 0x1034:
2304 case 0x1038 ... 0x103E:
2305 case 0x1050 ... 0x1057:
2306 case 0x1059:
2307 case 0x1064 ... 0x106B:
2308 case 0x1091 ... 0x1095:
2309 case 0x1209:
2310 case 0x1229:
2311 case 0x2449:
2312 case 0x2459:
2313 case 0x245D:
2314 case 0x27DC:
2315 break;
2316 default:
2317 return;
2318 }
2319
2320 /*
2321 * Some firmware hands off the e100 with interrupts enabled,
2322 * which can cause a flood of interrupts if packets are
2323 * received before the driver attaches to the device. So
2324 * disable all e100 interrupts here. The driver will
2325 * re-enable them when it's ready.
2326 */
2327 pci_read_config_word(dev, PCI_COMMAND, &command);
2328
2329 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2330 return;
2331
2332 /*
2333 * Check that the device is in the D0 power state. If it's not,
2334 * there is no point to look any further.
2335 */
2336 if (dev->pm_cap) {
2337 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2338 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2339 return;
2340 }
2341
2342 /* Convert from PCI bus to resource space. */
2343 csr = ioremap(pci_resource_start(dev, 0), 8);
2344 if (!csr) {
2345 pci_warn(dev, "Can't map e100 registers\n");
2346 return;
2347 }
2348
2349 cmd_hi = readb(csr + 3);
2350 if (cmd_hi == 0) {
2351 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2352 writeb(1, csr + 3);
2353 }
2354
2355 iounmap(csr);
2356}
2357DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2358 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2359
2360/*
2361 * The 82575 and 82598 may experience data corruption issues when transitioning
2362 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2363 */
2364static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2365{
2366 pci_info(dev, "Disabling L0s\n");
2367 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2368}
2369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2370DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2383
2384static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2385{
2386 pci_info(dev, "Disabling ASPM L0s/L1\n");
2387 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2388}
2389
2390/*
2391 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2392 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2393 * disable both L0s and L1 for now to be safe.
2394 */
2395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2396
2397/*
2398 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2399 * Link bit cleared after starting the link retrain process to allow this
2400 * process to finish.
2401 *
2402 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2403 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2404 */
2405static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2406{
2407 dev->clear_retrain_link = 1;
2408 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2409}
2410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2411DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2412DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2413
2414static void fixup_rev1_53c810(struct pci_dev *dev)
2415{
2416 u32 class = dev->class;
2417
2418 /*
2419 * rev 1 ncr53c810 chips don't set the class at all which means
2420 * they don't get their resources remapped. Fix that here.
2421 */
2422 if (class)
2423 return;
2424
2425 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2426 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2427 class, dev->class);
2428}
2429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2430
2431/* Enable 1k I/O space granularity on the Intel P64H2 */
2432static void quirk_p64h2_1k_io(struct pci_dev *dev)
2433{
2434 u16 en1k;
2435
2436 pci_read_config_word(dev, 0x40, &en1k);
2437
2438 if (en1k & 0x200) {
2439 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2440 dev->io_window_1k = 1;
2441 }
2442}
2443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2444
2445/*
2446 * Under some circumstances, AER is not linked with extended capabilities.
2447 * Force it to be linked by setting the corresponding control bit in the
2448 * config space.
2449 */
2450static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2451{
2452 uint8_t b;
2453
2454 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2455 if (!(b & 0x20)) {
2456 pci_write_config_byte(dev, 0xf41, b | 0x20);
2457 pci_info(dev, "Linking AER extended capability\n");
2458 }
2459 }
2460}
2461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2462 quirk_nvidia_ck804_pcie_aer_ext_cap);
2463DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2464 quirk_nvidia_ck804_pcie_aer_ext_cap);
2465
2466static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2467{
2468 /*
2469 * Disable PCI Bus Parking and PCI Master read caching on CX700
2470 * which causes unspecified timing errors with a VT6212L on the PCI
2471 * bus leading to USB2.0 packet loss.
2472 *
2473 * This quirk is only enabled if a second (on the external PCI bus)
2474 * VT6212L is found -- the CX700 core itself also contains a USB
2475 * host controller with the same PCI ID as the VT6212L.
2476 */
2477
2478 /* Count VT6212L instances */
2479 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2480 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2481 uint8_t b;
2482
2483 /*
2484 * p should contain the first (internal) VT6212L -- see if we have
2485 * an external one by searching again.
2486 */
2487 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2488 if (!p)
2489 return;
2490 pci_dev_put(p);
2491
2492 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2493 if (b & 0x40) {
2494 /* Turn off PCI Bus Parking */
2495 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2496
2497 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2498 }
2499 }
2500
2501 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2502 if (b != 0) {
2503 /* Turn off PCI Master read caching */
2504 pci_write_config_byte(dev, 0x72, 0x0);
2505
2506 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2507 pci_write_config_byte(dev, 0x75, 0x1);
2508
2509 /* Disable "Read FIFO Timer" */
2510 pci_write_config_byte(dev, 0x77, 0x0);
2511
2512 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2513 }
2514 }
2515}
2516DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2517
2518static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2519{
2520 u32 rev;
2521
2522 pci_read_config_dword(dev, 0xf4, &rev);
2523
2524 /* Only CAP the MRRS if the device is a 5719 A0 */
2525 if (rev == 0x05719000) {
2526 int readrq = pcie_get_readrq(dev);
2527 if (readrq > 2048)
2528 pcie_set_readrq(dev, 2048);
2529 }
2530}
2531DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2532 PCI_DEVICE_ID_TIGON3_5719,
2533 quirk_brcm_5719_limit_mrrs);
2534
2535/*
2536 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2537 * hide device 6 which configures the overflow device access containing the
2538 * DRBs - this is where we expose device 6.
2539 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2540 */
2541static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2542{
2543 u8 reg;
2544
2545 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2546 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2547 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2548 }
2549}
2550DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2551 quirk_unhide_mch_dev6);
2552DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2553 quirk_unhide_mch_dev6);
2554
2555#ifdef CONFIG_PCI_MSI
2556/*
2557 * Some chipsets do not support MSI. We cannot easily rely on setting
2558 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2559 * other buses controlled by the chipset even if Linux is not aware of it.
2560 * Instead of setting the flag on all buses in the machine, simply disable
2561 * MSI globally.
2562 */
2563static void quirk_disable_all_msi(struct pci_dev *dev)
2564{
2565 pci_no_msi();
2566 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2567}
2568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2577
2578/* Disable MSI on chipsets that are known to not support it */
2579static void quirk_disable_msi(struct pci_dev *dev)
2580{
2581 if (dev->subordinate) {
2582 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2583 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2584 }
2585}
2586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2589
2590/*
2591 * The APC bridge device in AMD 780 family northbridges has some random
2592 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2593 * we use the possible vendor/device IDs of the host bridge for the
2594 * declared quirk, and search for the APC bridge by slot number.
2595 */
2596static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2597{
2598 struct pci_dev *apc_bridge;
2599
2600 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2601 if (apc_bridge) {
2602 if (apc_bridge->device == 0x9602)
2603 quirk_disable_msi(apc_bridge);
2604 pci_dev_put(apc_bridge);
2605 }
2606}
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2609
2610/*
2611 * Go through the list of HyperTransport capabilities and return 1 if a HT
2612 * MSI capability is found and enabled.
2613 */
2614static int msi_ht_cap_enabled(struct pci_dev *dev)
2615{
2616 int pos, ttl = PCI_FIND_CAP_TTL;
2617
2618 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2619 while (pos && ttl--) {
2620 u8 flags;
2621
2622 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2623 &flags) == 0) {
2624 pci_info(dev, "Found %s HT MSI Mapping\n",
2625 flags & HT_MSI_FLAGS_ENABLE ?
2626 "enabled" : "disabled");
2627 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2628 }
2629
2630 pos = pci_find_next_ht_capability(dev, pos,
2631 HT_CAPTYPE_MSI_MAPPING);
2632 }
2633 return 0;
2634}
2635
2636/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2637static void quirk_msi_ht_cap(struct pci_dev *dev)
2638{
2639 if (!msi_ht_cap_enabled(dev))
2640 quirk_disable_msi(dev);
2641}
2642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2643 quirk_msi_ht_cap);
2644
2645/*
2646 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2647 * if the MSI capability is set in any of these mappings.
2648 */
2649static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2650{
2651 struct pci_dev *pdev;
2652
2653 /*
2654 * Check HT MSI cap on this chipset and the root one. A single one
2655 * having MSI is enough to be sure that MSI is supported.
2656 */
2657 pdev = pci_get_slot(dev->bus, 0);
2658 if (!pdev)
2659 return;
2660 if (!msi_ht_cap_enabled(pdev))
2661 quirk_msi_ht_cap(dev);
2662 pci_dev_put(pdev);
2663}
2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2665 quirk_nvidia_ck804_msi_ht_cap);
2666
2667/* Force enable MSI mapping capability on HT bridges */
2668static void ht_enable_msi_mapping(struct pci_dev *dev)
2669{
2670 int pos, ttl = PCI_FIND_CAP_TTL;
2671
2672 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2673 while (pos && ttl--) {
2674 u8 flags;
2675
2676 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2677 &flags) == 0) {
2678 pci_info(dev, "Enabling HT MSI Mapping\n");
2679
2680 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2681 flags | HT_MSI_FLAGS_ENABLE);
2682 }
2683 pos = pci_find_next_ht_capability(dev, pos,
2684 HT_CAPTYPE_MSI_MAPPING);
2685 }
2686}
2687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2688 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2689 ht_enable_msi_mapping);
2690DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2691 ht_enable_msi_mapping);
2692
2693/*
2694 * The P5N32-SLI motherboards from Asus have a problem with MSI
2695 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2696 * also affects other devices. As for now, turn off MSI for this device.
2697 */
2698static void nvenet_msi_disable(struct pci_dev *dev)
2699{
2700 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2701
2702 if (board_name &&
2703 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2704 strstr(board_name, "P5N32-E SLI"))) {
2705 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2706 dev->no_msi = 1;
2707 }
2708}
2709DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2710 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2711 nvenet_msi_disable);
2712
2713/*
2714 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2715 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2716 * interrupts for PME and AER events; instead only INTx interrupts are
2717 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2718 * for other events, since PCIe specification doesn't support using a mix of
2719 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2720 * service drivers registering their respective ISRs for MSIs.
2721 */
2722static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2723{
2724 dev->no_msi = 1;
2725}
2726DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2727 PCI_CLASS_BRIDGE_PCI, 8,
2728 pci_quirk_nvidia_tegra_disable_rp_msi);
2729DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2730 PCI_CLASS_BRIDGE_PCI, 8,
2731 pci_quirk_nvidia_tegra_disable_rp_msi);
2732DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2733 PCI_CLASS_BRIDGE_PCI, 8,
2734 pci_quirk_nvidia_tegra_disable_rp_msi);
2735DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2736 PCI_CLASS_BRIDGE_PCI, 8,
2737 pci_quirk_nvidia_tegra_disable_rp_msi);
2738DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2739 PCI_CLASS_BRIDGE_PCI, 8,
2740 pci_quirk_nvidia_tegra_disable_rp_msi);
2741DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2742 PCI_CLASS_BRIDGE_PCI, 8,
2743 pci_quirk_nvidia_tegra_disable_rp_msi);
2744DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2745 PCI_CLASS_BRIDGE_PCI, 8,
2746 pci_quirk_nvidia_tegra_disable_rp_msi);
2747DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2748 PCI_CLASS_BRIDGE_PCI, 8,
2749 pci_quirk_nvidia_tegra_disable_rp_msi);
2750DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2751 PCI_CLASS_BRIDGE_PCI, 8,
2752 pci_quirk_nvidia_tegra_disable_rp_msi);
2753DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2754 PCI_CLASS_BRIDGE_PCI, 8,
2755 pci_quirk_nvidia_tegra_disable_rp_msi);
2756DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2757 PCI_CLASS_BRIDGE_PCI, 8,
2758 pci_quirk_nvidia_tegra_disable_rp_msi);
2759DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2760 PCI_CLASS_BRIDGE_PCI, 8,
2761 pci_quirk_nvidia_tegra_disable_rp_msi);
2762DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2763 PCI_CLASS_BRIDGE_PCI, 8,
2764 pci_quirk_nvidia_tegra_disable_rp_msi);
2765DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2766 PCI_CLASS_BRIDGE_PCI, 8,
2767 pci_quirk_nvidia_tegra_disable_rp_msi);
2768DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2769 PCI_CLASS_BRIDGE_PCI, 8,
2770 pci_quirk_nvidia_tegra_disable_rp_msi);
2771DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2772 PCI_CLASS_BRIDGE_PCI, 8,
2773 pci_quirk_nvidia_tegra_disable_rp_msi);
2774
2775/*
2776 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2777 * config register. This register controls the routing of legacy
2778 * interrupts from devices that route through the MCP55. If this register
2779 * is misprogrammed, interrupts are only sent to the BSP, unlike
2780 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2781 * having this register set properly prevents kdump from booting up
2782 * properly, so let's make sure that we have it set correctly.
2783 * Note that this is an undocumented register.
2784 */
2785static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2786{
2787 u32 cfg;
2788
2789 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2790 return;
2791
2792 pci_read_config_dword(dev, 0x74, &cfg);
2793
2794 if (cfg & ((1 << 2) | (1 << 15))) {
2795 pr_info("Rewriting IRQ routing register on MCP55\n");
2796 cfg &= ~((1 << 2) | (1 << 15));
2797 pci_write_config_dword(dev, 0x74, cfg);
2798 }
2799}
2800DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2801 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2802 nvbridge_check_legacy_irq_routing);
2803DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2804 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2805 nvbridge_check_legacy_irq_routing);
2806
2807static int ht_check_msi_mapping(struct pci_dev *dev)
2808{
2809 int pos, ttl = PCI_FIND_CAP_TTL;
2810 int found = 0;
2811
2812 /* Check if there is HT MSI cap or enabled on this device */
2813 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2814 while (pos && ttl--) {
2815 u8 flags;
2816
2817 if (found < 1)
2818 found = 1;
2819 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2820 &flags) == 0) {
2821 if (flags & HT_MSI_FLAGS_ENABLE) {
2822 if (found < 2) {
2823 found = 2;
2824 break;
2825 }
2826 }
2827 }
2828 pos = pci_find_next_ht_capability(dev, pos,
2829 HT_CAPTYPE_MSI_MAPPING);
2830 }
2831
2832 return found;
2833}
2834
2835static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2836{
2837 struct pci_dev *dev;
2838 int pos;
2839 int i, dev_no;
2840 int found = 0;
2841
2842 dev_no = host_bridge->devfn >> 3;
2843 for (i = dev_no + 1; i < 0x20; i++) {
2844 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2845 if (!dev)
2846 continue;
2847
2848 /* found next host bridge? */
2849 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2850 if (pos != 0) {
2851 pci_dev_put(dev);
2852 break;
2853 }
2854
2855 if (ht_check_msi_mapping(dev)) {
2856 found = 1;
2857 pci_dev_put(dev);
2858 break;
2859 }
2860 pci_dev_put(dev);
2861 }
2862
2863 return found;
2864}
2865
2866#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2867#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2868
2869static int is_end_of_ht_chain(struct pci_dev *dev)
2870{
2871 int pos, ctrl_off;
2872 int end = 0;
2873 u16 flags, ctrl;
2874
2875 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2876
2877 if (!pos)
2878 goto out;
2879
2880 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2881
2882 ctrl_off = ((flags >> 10) & 1) ?
2883 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2884 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2885
2886 if (ctrl & (1 << 6))
2887 end = 1;
2888
2889out:
2890 return end;
2891}
2892
2893static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2894{
2895 struct pci_dev *host_bridge;
2896 int pos;
2897 int i, dev_no;
2898 int found = 0;
2899
2900 dev_no = dev->devfn >> 3;
2901 for (i = dev_no; i >= 0; i--) {
2902 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2903 if (!host_bridge)
2904 continue;
2905
2906 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2907 if (pos != 0) {
2908 found = 1;
2909 break;
2910 }
2911 pci_dev_put(host_bridge);
2912 }
2913
2914 if (!found)
2915 return;
2916
2917 /* don't enable end_device/host_bridge with leaf directly here */
2918 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2919 host_bridge_with_leaf(host_bridge))
2920 goto out;
2921
2922 /* root did that ! */
2923 if (msi_ht_cap_enabled(host_bridge))
2924 goto out;
2925
2926 ht_enable_msi_mapping(dev);
2927
2928out:
2929 pci_dev_put(host_bridge);
2930}
2931
2932static void ht_disable_msi_mapping(struct pci_dev *dev)
2933{
2934 int pos, ttl = PCI_FIND_CAP_TTL;
2935
2936 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2937 while (pos && ttl--) {
2938 u8 flags;
2939
2940 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2941 &flags) == 0) {
2942 pci_info(dev, "Disabling HT MSI Mapping\n");
2943
2944 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2945 flags & ~HT_MSI_FLAGS_ENABLE);
2946 }
2947 pos = pci_find_next_ht_capability(dev, pos,
2948 HT_CAPTYPE_MSI_MAPPING);
2949 }
2950}
2951
2952static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2953{
2954 struct pci_dev *host_bridge;
2955 int pos;
2956 int found;
2957
2958 if (!pci_msi_enabled())
2959 return;
2960
2961 /* check if there is HT MSI cap or enabled on this device */
2962 found = ht_check_msi_mapping(dev);
2963
2964 /* no HT MSI CAP */
2965 if (found == 0)
2966 return;
2967
2968 /*
2969 * HT MSI mapping should be disabled on devices that are below
2970 * a non-Hypertransport host bridge. Locate the host bridge...
2971 */
2972 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2973 PCI_DEVFN(0, 0));
2974 if (host_bridge == NULL) {
2975 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2976 return;
2977 }
2978
2979 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2980 if (pos != 0) {
2981 /* Host bridge is to HT */
2982 if (found == 1) {
2983 /* it is not enabled, try to enable it */
2984 if (all)
2985 ht_enable_msi_mapping(dev);
2986 else
2987 nv_ht_enable_msi_mapping(dev);
2988 }
2989 goto out;
2990 }
2991
2992 /* HT MSI is not enabled */
2993 if (found == 1)
2994 goto out;
2995
2996 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2997 ht_disable_msi_mapping(dev);
2998
2999out:
3000 pci_dev_put(host_bridge);
3001}
3002
3003static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
3004{
3005 return __nv_msi_ht_cap_quirk(dev, 1);
3006}
3007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3008DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3009
3010static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
3011{
3012 return __nv_msi_ht_cap_quirk(dev, 0);
3013}
3014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3015DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3016
3017static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3018{
3019 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3020}
3021
3022static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3023{
3024 struct pci_dev *p;
3025
3026 /*
3027 * SB700 MSI issue will be fixed at HW level from revision A21;
3028 * we need check PCI REVISION ID of SMBus controller to get SB700
3029 * revision.
3030 */
3031 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3032 NULL);
3033 if (!p)
3034 return;
3035
3036 if ((p->revision < 0x3B) && (p->revision >= 0x30))
3037 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3038 pci_dev_put(p);
3039}
3040
3041static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3042{
3043 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3044 if (dev->revision < 0x18) {
3045 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3046 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3047 }
3048}
3049DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3050 PCI_DEVICE_ID_TIGON3_5780,
3051 quirk_msi_intx_disable_bug);
3052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3053 PCI_DEVICE_ID_TIGON3_5780S,
3054 quirk_msi_intx_disable_bug);
3055DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3056 PCI_DEVICE_ID_TIGON3_5714,
3057 quirk_msi_intx_disable_bug);
3058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3059 PCI_DEVICE_ID_TIGON3_5714S,
3060 quirk_msi_intx_disable_bug);
3061DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3062 PCI_DEVICE_ID_TIGON3_5715,
3063 quirk_msi_intx_disable_bug);
3064DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3065 PCI_DEVICE_ID_TIGON3_5715S,
3066 quirk_msi_intx_disable_bug);
3067
3068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3069 quirk_msi_intx_disable_ati_bug);
3070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3071 quirk_msi_intx_disable_ati_bug);
3072DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3073 quirk_msi_intx_disable_ati_bug);
3074DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3075 quirk_msi_intx_disable_ati_bug);
3076DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3077 quirk_msi_intx_disable_ati_bug);
3078
3079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3080 quirk_msi_intx_disable_bug);
3081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3082 quirk_msi_intx_disable_bug);
3083DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3084 quirk_msi_intx_disable_bug);
3085
3086DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3087 quirk_msi_intx_disable_bug);
3088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3089 quirk_msi_intx_disable_bug);
3090DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3091 quirk_msi_intx_disable_bug);
3092DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3093 quirk_msi_intx_disable_bug);
3094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3095 quirk_msi_intx_disable_bug);
3096DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3097 quirk_msi_intx_disable_bug);
3098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3099 quirk_msi_intx_disable_qca_bug);
3100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3101 quirk_msi_intx_disable_qca_bug);
3102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3103 quirk_msi_intx_disable_qca_bug);
3104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3105 quirk_msi_intx_disable_qca_bug);
3106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3107 quirk_msi_intx_disable_qca_bug);
3108
3109/*
3110 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3111 * should be disabled on platforms where the device (mistakenly) advertises it.
3112 *
3113 * Notice that this quirk also disables MSI (which may work, but hasn't been
3114 * tested), since currently there is no standard way to disable only MSI-X.
3115 *
3116 * The 0031 device id is reused for other non Root Port device types,
3117 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3118 */
3119static void quirk_al_msi_disable(struct pci_dev *dev)
3120{
3121 dev->no_msi = 1;
3122 pci_warn(dev, "Disabling MSI/MSI-X\n");
3123}
3124DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3125 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3126#endif /* CONFIG_PCI_MSI */
3127
3128/*
3129 * Allow manual resource allocation for PCI hotplug bridges via
3130 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3131 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3132 * allocate resources when hotplug device is inserted and PCI bus is
3133 * rescanned.
3134 */
3135static void quirk_hotplug_bridge(struct pci_dev *dev)
3136{
3137 dev->is_hotplug_bridge = 1;
3138}
3139DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3140
3141/*
3142 * This is a quirk for the Ricoh MMC controller found as a part of some
3143 * multifunction chips.
3144 *
3145 * This is very similar and based on the ricoh_mmc driver written by
3146 * Philip Langdale. Thank you for these magic sequences.
3147 *
3148 * These chips implement the four main memory card controllers (SD, MMC,
3149 * MS, xD) and one or both of CardBus or FireWire.
3150 *
3151 * It happens that they implement SD and MMC support as separate
3152 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3153 * cards but the chip detects MMC cards in hardware and directs them to the
3154 * MMC controller - so the SDHCI driver never sees them.
3155 *
3156 * To get around this, we must disable the useless MMC controller. At that
3157 * point, the SDHCI controller will start seeing them. It seems to be the
3158 * case that the relevant PCI registers to deactivate the MMC controller
3159 * live on PCI function 0, which might be the CardBus controller or the
3160 * FireWire controller, depending on the particular chip in question
3161 *
3162 * This has to be done early, because as soon as we disable the MMC controller
3163 * other PCI functions shift up one level, e.g. function #2 becomes function
3164 * #1, and this will confuse the PCI core.
3165 */
3166#ifdef CONFIG_MMC_RICOH_MMC
3167static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3168{
3169 u8 write_enable;
3170 u8 write_target;
3171 u8 disable;
3172
3173 /*
3174 * Disable via CardBus interface
3175 *
3176 * This must be done via function #0
3177 */
3178 if (PCI_FUNC(dev->devfn))
3179 return;
3180
3181 pci_read_config_byte(dev, 0xB7, &disable);
3182 if (disable & 0x02)
3183 return;
3184
3185 pci_read_config_byte(dev, 0x8E, &write_enable);
3186 pci_write_config_byte(dev, 0x8E, 0xAA);
3187 pci_read_config_byte(dev, 0x8D, &write_target);
3188 pci_write_config_byte(dev, 0x8D, 0xB7);
3189 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3190 pci_write_config_byte(dev, 0x8E, write_enable);
3191 pci_write_config_byte(dev, 0x8D, write_target);
3192
3193 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3194 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3195}
3196DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3197DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3198
3199static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3200{
3201 u8 write_enable;
3202 u8 disable;
3203
3204 /*
3205 * Disable via FireWire interface
3206 *
3207 * This must be done via function #0
3208 */
3209 if (PCI_FUNC(dev->devfn))
3210 return;
3211 /*
3212 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3213 * certain types of SD/MMC cards. Lowering the SD base clock
3214 * frequency from 200Mhz to 50Mhz fixes this issue.
3215 *
3216 * 0x150 - SD2.0 mode enable for changing base clock
3217 * frequency to 50Mhz
3218 * 0xe1 - Base clock frequency
3219 * 0x32 - 50Mhz new clock frequency
3220 * 0xf9 - Key register for 0x150
3221 * 0xfc - key register for 0xe1
3222 */
3223 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3224 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3225 pci_write_config_byte(dev, 0xf9, 0xfc);
3226 pci_write_config_byte(dev, 0x150, 0x10);
3227 pci_write_config_byte(dev, 0xf9, 0x00);
3228 pci_write_config_byte(dev, 0xfc, 0x01);
3229 pci_write_config_byte(dev, 0xe1, 0x32);
3230 pci_write_config_byte(dev, 0xfc, 0x00);
3231
3232 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3233 }
3234
3235 pci_read_config_byte(dev, 0xCB, &disable);
3236
3237 if (disable & 0x02)
3238 return;
3239
3240 pci_read_config_byte(dev, 0xCA, &write_enable);
3241 pci_write_config_byte(dev, 0xCA, 0x57);
3242 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3243 pci_write_config_byte(dev, 0xCA, write_enable);
3244
3245 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3246 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3247
3248}
3249DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3250DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3251DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3252DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3253DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3254DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3255#endif /*CONFIG_MMC_RICOH_MMC*/
3256
3257#ifdef CONFIG_DMAR_TABLE
3258#define VTUNCERRMSK_REG 0x1ac
3259#define VTD_MSK_SPEC_ERRORS (1 << 31)
3260/*
3261 * This is a quirk for masking VT-d spec-defined errors to platform error
3262 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3263 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3264 * on the RAS config settings of the platform) when a VT-d fault happens.
3265 * The resulting SMI caused the system to hang.
3266 *
3267 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3268 * need to report the same error through other channels.
3269 */
3270static void vtd_mask_spec_errors(struct pci_dev *dev)
3271{
3272 u32 word;
3273
3274 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3275 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3276}
3277DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3278DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3279#endif
3280
3281static void fixup_ti816x_class(struct pci_dev *dev)
3282{
3283 u32 class = dev->class;
3284
3285 /* TI 816x devices do not have class code set when in PCIe boot mode */
3286 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3287 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3288 class, dev->class);
3289}
3290DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3291 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3292
3293/*
3294 * Some PCIe devices do not work reliably with the claimed maximum
3295 * payload size supported.
3296 */
3297static void fixup_mpss_256(struct pci_dev *dev)
3298{
3299 dev->pcie_mpss = 1; /* 256 bytes */
3300}
3301DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3302 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3303DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3304 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3305DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3306 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3307DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3308
3309/*
3310 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3311 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3312 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3313 * until all of the devices are discovered and buses walked, read completion
3314 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3315 * it is possible to hotplug a device with MPS of 256B.
3316 */
3317static void quirk_intel_mc_errata(struct pci_dev *dev)
3318{
3319 int err;
3320 u16 rcc;
3321
3322 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3323 pcie_bus_config == PCIE_BUS_DEFAULT)
3324 return;
3325
3326 /*
3327 * Intel erratum specifies bits to change but does not say what
3328 * they are. Keeping them magical until such time as the registers
3329 * and values can be explained.
3330 */
3331 err = pci_read_config_word(dev, 0x48, &rcc);
3332 if (err) {
3333 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3334 return;
3335 }
3336
3337 if (!(rcc & (1 << 10)))
3338 return;
3339
3340 rcc &= ~(1 << 10);
3341
3342 err = pci_write_config_word(dev, 0x48, rcc);
3343 if (err) {
3344 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3345 return;
3346 }
3347
3348 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3349}
3350/* Intel 5000 series memory controllers and ports 2-7 */
3351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3353DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3356DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3357DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3359DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3360DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3361DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3362DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3365/* Intel 5100 series memory controllers and ports 2-7 */
3366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3373DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3376DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3377
3378/*
3379 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3380 * To work around this, query the size it should be configured to by the
3381 * device and modify the resource end to correspond to this new size.
3382 */
3383static void quirk_intel_ntb(struct pci_dev *dev)
3384{
3385 int rc;
3386 u8 val;
3387
3388 rc = pci_read_config_byte(dev, 0x00D0, &val);
3389 if (rc)
3390 return;
3391
3392 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3393
3394 rc = pci_read_config_byte(dev, 0x00D1, &val);
3395 if (rc)
3396 return;
3397
3398 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3399}
3400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3401DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3402
3403/*
3404 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3405 * though no one is handling them (e.g., if the i915 driver is never
3406 * loaded). Additionally the interrupt destination is not set up properly
3407 * and the interrupt ends up -somewhere-.
3408 *
3409 * These spurious interrupts are "sticky" and the kernel disables the
3410 * (shared) interrupt line after 100,000+ generated interrupts.
3411 *
3412 * Fix it by disabling the still enabled interrupts. This resolves crashes
3413 * often seen on monitor unplug.
3414 */
3415#define I915_DEIER_REG 0x4400c
3416static void disable_igfx_irq(struct pci_dev *dev)
3417{
3418 void __iomem *regs = pci_iomap(dev, 0, 0);
3419 if (regs == NULL) {
3420 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3421 return;
3422 }
3423
3424 /* Check if any interrupt line is still enabled */
3425 if (readl(regs + I915_DEIER_REG) != 0) {
3426 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3427
3428 writel(0, regs + I915_DEIER_REG);
3429 }
3430
3431 pci_iounmap(dev, regs);
3432}
3433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3437DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3440
3441/*
3442 * PCI devices which are on Intel chips can skip the 10ms delay
3443 * before entering D3 mode.
3444 */
3445static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3446{
3447 dev->d3hot_delay = 0;
3448}
3449/* C600 Series devices do not need 10ms d3hot_delay */
3450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3453/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3458DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3465/* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3467DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3469DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3470DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3471DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3472DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3473DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3474DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3475
3476/*
3477 * Some devices may pass our check in pci_intx_mask_supported() if
3478 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3479 * support this feature.
3480 */
3481static void quirk_broken_intx_masking(struct pci_dev *dev)
3482{
3483 dev->broken_intx_masking = 1;
3484}
3485DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3486 quirk_broken_intx_masking);
3487DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3488 quirk_broken_intx_masking);
3489DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3490 quirk_broken_intx_masking);
3491
3492/*
3493 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3494 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3495 *
3496 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3497 */
3498DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3499 quirk_broken_intx_masking);
3500
3501/*
3502 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3503 * DisINTx can be set but the interrupt status bit is non-functional.
3504 */
3505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3506DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3507DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3508DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3509DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3510DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3511DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3512DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3513DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3514DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3515DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3516DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3517DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3520DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3521
3522static u16 mellanox_broken_intx_devs[] = {
3523 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3524 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3525 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3526 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3527 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3528 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3529 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3530 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3531 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3532 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3533 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3534 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3535 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3536 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3537};
3538
3539#define CONNECTX_4_CURR_MAX_MINOR 99
3540#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3541
3542/*
3543 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3544 * If so, don't mark it as broken.
3545 * FW minor > 99 means older FW version format and no INTx masking support.
3546 * FW minor < 14 means new FW version format and no INTx masking support.
3547 */
3548static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3549{
3550 __be32 __iomem *fw_ver;
3551 u16 fw_major;
3552 u16 fw_minor;
3553 u16 fw_subminor;
3554 u32 fw_maj_min;
3555 u32 fw_sub_min;
3556 int i;
3557
3558 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3559 if (pdev->device == mellanox_broken_intx_devs[i]) {
3560 pdev->broken_intx_masking = 1;
3561 return;
3562 }
3563 }
3564
3565 /*
3566 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3567 * support so shouldn't be checked further
3568 */
3569 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3570 return;
3571
3572 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3573 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3574 return;
3575
3576 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3577 if (pci_enable_device_mem(pdev)) {
3578 pci_warn(pdev, "Can't enable device memory\n");
3579 return;
3580 }
3581
3582 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3583 if (!fw_ver) {
3584 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3585 goto out;
3586 }
3587
3588 /* Reading from resource space should be 32b aligned */
3589 fw_maj_min = ioread32be(fw_ver);
3590 fw_sub_min = ioread32be(fw_ver + 1);
3591 fw_major = fw_maj_min & 0xffff;
3592 fw_minor = fw_maj_min >> 16;
3593 fw_subminor = fw_sub_min & 0xffff;
3594 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3595 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3596 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3597 fw_major, fw_minor, fw_subminor, pdev->device ==
3598 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3599 pdev->broken_intx_masking = 1;
3600 }
3601
3602 iounmap(fw_ver);
3603
3604out:
3605 pci_disable_device(pdev);
3606}
3607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3608 mellanox_check_broken_intx_masking);
3609
3610static void quirk_no_bus_reset(struct pci_dev *dev)
3611{
3612 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3613}
3614
3615/*
3616 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3617 * prevented for those affected devices.
3618 */
3619static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3620{
3621 if ((dev->device & 0xffc0) == 0x2340)
3622 quirk_no_bus_reset(dev);
3623}
3624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3625 quirk_nvidia_no_bus_reset);
3626
3627/*
3628 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3629 * The device will throw a Link Down error on AER-capable systems and
3630 * regardless of AER, config space of the device is never accessible again
3631 * and typically causes the system to hang or reset when access is attempted.
3632 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3633 */
3634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3640
3641/*
3642 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3643 * reset when used with certain child devices. After the reset, config
3644 * accesses to the child may fail.
3645 */
3646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3647
3648/*
3649 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3650 * automatically disables LTSSM when Secondary Bus Reset is received and
3651 * the device stops working. Prevent bus reset for these devices. With
3652 * this change, the device can be assigned to VMs with VFIO, but it will
3653 * leak state between VMs. Reference
3654 * https://e2e.ti.com/support/processors/f/791/t/954382
3655 */
3656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3657
3658static void quirk_no_pm_reset(struct pci_dev *dev)
3659{
3660 /*
3661 * We can't do a bus reset on root bus devices, but an ineffective
3662 * PM reset may be better than nothing.
3663 */
3664 if (!pci_is_root_bus(dev->bus))
3665 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3666}
3667
3668/*
3669 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3670 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3671 * to have no effect on the device: it retains the framebuffer contents and
3672 * monitor sync. Advertising this support makes other layers, like VFIO,
3673 * assume pci_reset_function() is viable for this device. Mark it as
3674 * unavailable to skip it when testing reset methods.
3675 */
3676DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3677 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3678
3679/*
3680 * Thunderbolt controllers with broken MSI hotplug signaling:
3681 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3682 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3683 */
3684static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3685{
3686 if (pdev->is_hotplug_bridge &&
3687 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3688 pdev->revision <= 1))
3689 pdev->no_msi = 1;
3690}
3691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3692 quirk_thunderbolt_hotplug_msi);
3693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3694 quirk_thunderbolt_hotplug_msi);
3695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3696 quirk_thunderbolt_hotplug_msi);
3697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3698 quirk_thunderbolt_hotplug_msi);
3699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3700 quirk_thunderbolt_hotplug_msi);
3701
3702#ifdef CONFIG_ACPI
3703/*
3704 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3705 *
3706 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3707 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3708 * be present after resume if a device was plugged in before suspend.
3709 *
3710 * The Thunderbolt controller consists of a PCIe switch with downstream
3711 * bridges leading to the NHI and to the tunnel PCI bridges.
3712 *
3713 * This quirk cuts power to the whole chip. Therefore we have to apply it
3714 * during suspend_noirq of the upstream bridge.
3715 *
3716 * Power is automagically restored before resume. No action is needed.
3717 */
3718static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3719{
3720 acpi_handle bridge, SXIO, SXFP, SXLV;
3721
3722 if (!x86_apple_machine)
3723 return;
3724 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3725 return;
3726
3727 /*
3728 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3729 * We don't know how to turn it back on again, but firmware does,
3730 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3731 * firmware.
3732 */
3733 if (!pm_suspend_via_firmware())
3734 return;
3735
3736 bridge = ACPI_HANDLE(&dev->dev);
3737 if (!bridge)
3738 return;
3739
3740 /*
3741 * SXIO and SXLV are present only on machines requiring this quirk.
3742 * Thunderbolt bridges in external devices might have the same
3743 * device ID as those on the host, but they will not have the
3744 * associated ACPI methods. This implicitly checks that we are at
3745 * the right bridge.
3746 */
3747 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3748 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3749 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3750 return;
3751 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3752
3753 /* magic sequence */
3754 acpi_execute_simple_method(SXIO, NULL, 1);
3755 acpi_execute_simple_method(SXFP, NULL, 0);
3756 msleep(300);
3757 acpi_execute_simple_method(SXLV, NULL, 0);
3758 acpi_execute_simple_method(SXIO, NULL, 0);
3759 acpi_execute_simple_method(SXLV, NULL, 0);
3760}
3761DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3762 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3763 quirk_apple_poweroff_thunderbolt);
3764#endif
3765
3766/*
3767 * Following are device-specific reset methods which can be used to
3768 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3769 * not available.
3770 */
3771static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3772{
3773 /*
3774 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3775 *
3776 * The 82599 supports FLR on VFs, but FLR support is reported only
3777 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3778 * Thus we must call pcie_flr() directly without first checking if it is
3779 * supported.
3780 */
3781 if (!probe)
3782 pcie_flr(dev);
3783 return 0;
3784}
3785
3786#define SOUTH_CHICKEN2 0xc2004
3787#define PCH_PP_STATUS 0xc7200
3788#define PCH_PP_CONTROL 0xc7204
3789#define MSG_CTL 0x45010
3790#define NSDE_PWR_STATE 0xd0100
3791#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3792
3793static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3794{
3795 void __iomem *mmio_base;
3796 unsigned long timeout;
3797 u32 val;
3798
3799 if (probe)
3800 return 0;
3801
3802 mmio_base = pci_iomap(dev, 0, 0);
3803 if (!mmio_base)
3804 return -ENOMEM;
3805
3806 iowrite32(0x00000002, mmio_base + MSG_CTL);
3807
3808 /*
3809 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3810 * driver loaded sets the right bits. However, this's a reset and
3811 * the bits have been set by i915 previously, so we clobber
3812 * SOUTH_CHICKEN2 register directly here.
3813 */
3814 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3815
3816 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3817 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3818
3819 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3820 do {
3821 val = ioread32(mmio_base + PCH_PP_STATUS);
3822 if ((val & 0xb0000000) == 0)
3823 goto reset_complete;
3824 msleep(10);
3825 } while (time_before(jiffies, timeout));
3826 pci_warn(dev, "timeout during reset\n");
3827
3828reset_complete:
3829 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3830
3831 pci_iounmap(dev, mmio_base);
3832 return 0;
3833}
3834
3835/* Device-specific reset method for Chelsio T4-based adapters */
3836static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3837{
3838 u16 old_command;
3839 u16 msix_flags;
3840
3841 /*
3842 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3843 * that we have no device-specific reset method.
3844 */
3845 if ((dev->device & 0xf000) != 0x4000)
3846 return -ENOTTY;
3847
3848 /*
3849 * If this is the "probe" phase, return 0 indicating that we can
3850 * reset this device.
3851 */
3852 if (probe)
3853 return 0;
3854
3855 /*
3856 * T4 can wedge if there are DMAs in flight within the chip and Bus
3857 * Master has been disabled. We need to have it on till the Function
3858 * Level Reset completes. (BUS_MASTER is disabled in
3859 * pci_reset_function()).
3860 */
3861 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3862 pci_write_config_word(dev, PCI_COMMAND,
3863 old_command | PCI_COMMAND_MASTER);
3864
3865 /*
3866 * Perform the actual device function reset, saving and restoring
3867 * configuration information around the reset.
3868 */
3869 pci_save_state(dev);
3870
3871 /*
3872 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3873 * are disabled when an MSI-X interrupt message needs to be delivered.
3874 * So we briefly re-enable MSI-X interrupts for the duration of the
3875 * FLR. The pci_restore_state() below will restore the original
3876 * MSI-X state.
3877 */
3878 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3879 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3880 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3881 msix_flags |
3882 PCI_MSIX_FLAGS_ENABLE |
3883 PCI_MSIX_FLAGS_MASKALL);
3884
3885 pcie_flr(dev);
3886
3887 /*
3888 * Restore the configuration information (BAR values, etc.) including
3889 * the original PCI Configuration Space Command word, and return
3890 * success.
3891 */
3892 pci_restore_state(dev);
3893 pci_write_config_word(dev, PCI_COMMAND, old_command);
3894 return 0;
3895}
3896
3897#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3898#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3899#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3900
3901/*
3902 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3903 * FLR where config space reads from the device return -1. We seem to be
3904 * able to avoid this condition if we disable the NVMe controller prior to
3905 * FLR. This quirk is generic for any NVMe class device requiring similar
3906 * assistance to quiesce the device prior to FLR.
3907 *
3908 * NVMe specification: https://nvmexpress.org/resources/specifications/
3909 * Revision 1.0e:
3910 * Chapter 2: Required and optional PCI config registers
3911 * Chapter 3: NVMe control registers
3912 * Chapter 7.3: Reset behavior
3913 */
3914static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
3915{
3916 void __iomem *bar;
3917 u16 cmd;
3918 u32 cfg;
3919
3920 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3921 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
3922 return -ENOTTY;
3923
3924 if (probe)
3925 return 0;
3926
3927 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3928 if (!bar)
3929 return -ENOTTY;
3930
3931 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3932 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3933
3934 cfg = readl(bar + NVME_REG_CC);
3935
3936 /* Disable controller if enabled */
3937 if (cfg & NVME_CC_ENABLE) {
3938 u32 cap = readl(bar + NVME_REG_CAP);
3939 unsigned long timeout;
3940
3941 /*
3942 * Per nvme_disable_ctrl() skip shutdown notification as it
3943 * could complete commands to the admin queue. We only intend
3944 * to quiesce the device before reset.
3945 */
3946 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3947
3948 writel(cfg, bar + NVME_REG_CC);
3949
3950 /*
3951 * Some controllers require an additional delay here, see
3952 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3953 * supported by this quirk.
3954 */
3955
3956 /* Cap register provides max timeout in 500ms increments */
3957 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3958
3959 for (;;) {
3960 u32 status = readl(bar + NVME_REG_CSTS);
3961
3962 /* Ready status becomes zero on disable complete */
3963 if (!(status & NVME_CSTS_RDY))
3964 break;
3965
3966 msleep(100);
3967
3968 if (time_after(jiffies, timeout)) {
3969 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3970 break;
3971 }
3972 }
3973 }
3974
3975 pci_iounmap(dev, bar);
3976
3977 pcie_flr(dev);
3978
3979 return 0;
3980}
3981
3982/*
3983 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3984 * to change after NVMe enable if the driver starts interacting with the
3985 * device too soon after FLR. A 250ms delay after FLR has heuristically
3986 * proven to produce reliably working results for device assignment cases.
3987 */
3988static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
3989{
3990 if (probe)
3991 return pcie_reset_flr(dev, PCI_RESET_PROBE);
3992
3993 pcie_reset_flr(dev, PCI_RESET_DO_RESET);
3994
3995 msleep(250);
3996
3997 return 0;
3998}
3999
4000#define PCI_DEVICE_ID_HINIC_VF 0x375E
4001#define HINIC_VF_FLR_TYPE 0x1000
4002#define HINIC_VF_FLR_CAP_BIT (1UL << 30)
4003#define HINIC_VF_OP 0xE80
4004#define HINIC_VF_FLR_PROC_BIT (1UL << 18)
4005#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
4006
4007/* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4008static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
4009{
4010 unsigned long timeout;
4011 void __iomem *bar;
4012 u32 val;
4013
4014 if (probe)
4015 return 0;
4016
4017 bar = pci_iomap(pdev, 0, 0);
4018 if (!bar)
4019 return -ENOTTY;
4020
4021 /* Get and check firmware capabilities */
4022 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4023 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4024 pci_iounmap(pdev, bar);
4025 return -ENOTTY;
4026 }
4027
4028 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4029 val = ioread32be(bar + HINIC_VF_OP);
4030 val = val | HINIC_VF_FLR_PROC_BIT;
4031 iowrite32be(val, bar + HINIC_VF_OP);
4032
4033 pcie_flr(pdev);
4034
4035 /*
4036 * The device must recapture its Bus and Device Numbers after FLR
4037 * in order generate Completions. Issue a config write to let the
4038 * device capture this information.
4039 */
4040 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4041
4042 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4043 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4044 do {
4045 val = ioread32be(bar + HINIC_VF_OP);
4046 if (!(val & HINIC_VF_FLR_PROC_BIT))
4047 goto reset_complete;
4048 msleep(20);
4049 } while (time_before(jiffies, timeout));
4050
4051 val = ioread32be(bar + HINIC_VF_OP);
4052 if (!(val & HINIC_VF_FLR_PROC_BIT))
4053 goto reset_complete;
4054
4055 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4056
4057reset_complete:
4058 pci_iounmap(pdev, bar);
4059
4060 return 0;
4061}
4062
4063static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4064 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4065 reset_intel_82599_sfp_virtfn },
4066 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4067 reset_ivb_igd },
4068 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4069 reset_ivb_igd },
4070 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4071 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4072 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4073 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4074 reset_chelsio_generic_dev },
4075 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4076 reset_hinic_vf_dev },
4077 { 0 }
4078};
4079
4080/*
4081 * These device-specific reset methods are here rather than in a driver
4082 * because when a host assigns a device to a guest VM, the host may need
4083 * to reset the device but probably doesn't have a driver for it.
4084 */
4085int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4086{
4087 const struct pci_dev_reset_methods *i;
4088
4089 for (i = pci_dev_reset_methods; i->reset; i++) {
4090 if ((i->vendor == dev->vendor ||
4091 i->vendor == (u16)PCI_ANY_ID) &&
4092 (i->device == dev->device ||
4093 i->device == (u16)PCI_ANY_ID))
4094 return i->reset(dev, probe);
4095 }
4096
4097 return -ENOTTY;
4098}
4099
4100static void quirk_dma_func0_alias(struct pci_dev *dev)
4101{
4102 if (PCI_FUNC(dev->devfn) != 0)
4103 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4104}
4105
4106/*
4107 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4108 *
4109 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4110 */
4111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4113
4114static void quirk_dma_func1_alias(struct pci_dev *dev)
4115{
4116 if (PCI_FUNC(dev->devfn) != 1)
4117 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4118}
4119
4120/*
4121 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4122 * SKUs function 1 is present and is a legacy IDE controller, in other
4123 * SKUs this function is not present, making this a ghost requester.
4124 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4125 */
4126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4127 quirk_dma_func1_alias);
4128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4129 quirk_dma_func1_alias);
4130/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4132 quirk_dma_func1_alias);
4133DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4134 quirk_dma_func1_alias);
4135/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4137 quirk_dma_func1_alias);
4138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4139 quirk_dma_func1_alias);
4140/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4141DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4142 quirk_dma_func1_alias);
4143/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4144DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4145 quirk_dma_func1_alias);
4146/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4148 quirk_dma_func1_alias);
4149/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4151 quirk_dma_func1_alias);
4152/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4154 quirk_dma_func1_alias);
4155/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4156DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4157 quirk_dma_func1_alias);
4158/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4160 quirk_dma_func1_alias);
4161/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4162DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4163 quirk_dma_func1_alias);
4164DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4165 quirk_dma_func1_alias);
4166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4167 quirk_dma_func1_alias);
4168/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4169DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4170 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4171 quirk_dma_func1_alias);
4172/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4173DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4174 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4175 quirk_dma_func1_alias);
4176
4177/*
4178 * Some devices DMA with the wrong devfn, not just the wrong function.
4179 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4180 * the alias is "fixed" and independent of the device devfn.
4181 *
4182 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4183 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4184 * single device on the secondary bus. In reality, the single exposed
4185 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4186 * that provides a bridge to the internal bus of the I/O processor. The
4187 * controller supports private devices, which can be hidden from PCI config
4188 * space. In the case of the Adaptec 3405, a private device at 01.0
4189 * appears to be the DMA engine, which therefore needs to become a DMA
4190 * alias for the device.
4191 */
4192static const struct pci_device_id fixed_dma_alias_tbl[] = {
4193 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4194 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4195 .driver_data = PCI_DEVFN(1, 0) },
4196 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4197 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4198 .driver_data = PCI_DEVFN(1, 0) },
4199 { 0 }
4200};
4201
4202static void quirk_fixed_dma_alias(struct pci_dev *dev)
4203{
4204 const struct pci_device_id *id;
4205
4206 id = pci_match_id(fixed_dma_alias_tbl, dev);
4207 if (id)
4208 pci_add_dma_alias(dev, id->driver_data, 1);
4209}
4210DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4211
4212/*
4213 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4214 * using the wrong DMA alias for the device. Some of these devices can be
4215 * used as either forward or reverse bridges, so we need to test whether the
4216 * device is operating in the correct mode. We could probably apply this
4217 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4218 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4219 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4220 */
4221static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4222{
4223 if (!pci_is_root_bus(pdev->bus) &&
4224 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4225 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4226 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4227 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4228}
4229/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4231 quirk_use_pcie_bridge_dma_alias);
4232/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4233DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4234/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4235DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4236/* ITE 8893 has the same problem as the 8892 */
4237DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4238/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4239DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4240
4241/*
4242 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4243 * be added as aliases to the DMA device in order to allow buffer access
4244 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4245 * programmed in the EEPROM.
4246 */
4247static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4248{
4249 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4250 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4251 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4252}
4253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4255
4256/*
4257 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4258 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4259 *
4260 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4261 * when IOMMU is enabled. These aliases allow computational unit access to
4262 * host memory. These aliases mark the whole VCA device as one IOMMU
4263 * group.
4264 *
4265 * All possible slot numbers (0x20) are used, since we are unable to tell
4266 * what slot is used on other side. This quirk is intended for both host
4267 * and computational unit sides. The VCA devices have up to five functions
4268 * (four for DMA channels and one additional).
4269 */
4270static void quirk_pex_vca_alias(struct pci_dev *pdev)
4271{
4272 const unsigned int num_pci_slots = 0x20;
4273 unsigned int slot;
4274
4275 for (slot = 0; slot < num_pci_slots; slot++)
4276 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4277}
4278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4284
4285/*
4286 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4287 * associated not at the root bus, but at a bridge below. This quirk avoids
4288 * generating invalid DMA aliases.
4289 */
4290static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4291{
4292 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4293}
4294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4295 quirk_bridge_cavm_thrx2_pcie_root);
4296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4297 quirk_bridge_cavm_thrx2_pcie_root);
4298
4299/*
4300 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4301 * class code. Fix it.
4302 */
4303static void quirk_tw686x_class(struct pci_dev *pdev)
4304{
4305 u32 class = pdev->class;
4306
4307 /* Use "Multimedia controller" class */
4308 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4309 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4310 class, pdev->class);
4311}
4312DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4313 quirk_tw686x_class);
4314DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4315 quirk_tw686x_class);
4316DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4317 quirk_tw686x_class);
4318DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4319 quirk_tw686x_class);
4320
4321/*
4322 * Some devices have problems with Transaction Layer Packets with the Relaxed
4323 * Ordering Attribute set. Such devices should mark themselves and other
4324 * device drivers should check before sending TLPs with RO set.
4325 */
4326static void quirk_relaxedordering_disable(struct pci_dev *dev)
4327{
4328 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4329 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4330}
4331
4332/*
4333 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4334 * Complex have a Flow Control Credit issue which can cause performance
4335 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4336 */
4337DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4338 quirk_relaxedordering_disable);
4339DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4340 quirk_relaxedordering_disable);
4341DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4342 quirk_relaxedordering_disable);
4343DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4344 quirk_relaxedordering_disable);
4345DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4346 quirk_relaxedordering_disable);
4347DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4348 quirk_relaxedordering_disable);
4349DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4350 quirk_relaxedordering_disable);
4351DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4352 quirk_relaxedordering_disable);
4353DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4354 quirk_relaxedordering_disable);
4355DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4356 quirk_relaxedordering_disable);
4357DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4358 quirk_relaxedordering_disable);
4359DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4360 quirk_relaxedordering_disable);
4361DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4362 quirk_relaxedordering_disable);
4363DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4364 quirk_relaxedordering_disable);
4365DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4366 quirk_relaxedordering_disable);
4367DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4368 quirk_relaxedordering_disable);
4369DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4370 quirk_relaxedordering_disable);
4371DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4372 quirk_relaxedordering_disable);
4373DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4374 quirk_relaxedordering_disable);
4375DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4376 quirk_relaxedordering_disable);
4377DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4378 quirk_relaxedordering_disable);
4379DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4380 quirk_relaxedordering_disable);
4381DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4382 quirk_relaxedordering_disable);
4383DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4384 quirk_relaxedordering_disable);
4385DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4386 quirk_relaxedordering_disable);
4387DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4388 quirk_relaxedordering_disable);
4389DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4390 quirk_relaxedordering_disable);
4391DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4392 quirk_relaxedordering_disable);
4393
4394/*
4395 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4396 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4397 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4398 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4399 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4400 * November 10, 2010). As a result, on this platform we can't use Relaxed
4401 * Ordering for Upstream TLPs.
4402 */
4403DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4404 quirk_relaxedordering_disable);
4405DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4406 quirk_relaxedordering_disable);
4407DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4408 quirk_relaxedordering_disable);
4409
4410/*
4411 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4412 * values for the Attribute as were supplied in the header of the
4413 * corresponding Request, except as explicitly allowed when IDO is used."
4414 *
4415 * If a non-compliant device generates a completion with a different
4416 * attribute than the request, the receiver may accept it (which itself
4417 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4418 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4419 * device access timeout.
4420 *
4421 * If the non-compliant device generates completions with zero attributes
4422 * (instead of copying the attributes from the request), we can work around
4423 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4424 * upstream devices so they always generate requests with zero attributes.
4425 *
4426 * This affects other devices under the same Root Port, but since these
4427 * attributes are performance hints, there should be no functional problem.
4428 *
4429 * Note that Configuration Space accesses are never supposed to have TLP
4430 * Attributes, so we're safe waiting till after any Configuration Space
4431 * accesses to do the Root Port fixup.
4432 */
4433static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4434{
4435 struct pci_dev *root_port = pcie_find_root_port(pdev);
4436
4437 if (!root_port) {
4438 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4439 return;
4440 }
4441
4442 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4443 dev_name(&pdev->dev));
4444 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4445 PCI_EXP_DEVCTL_RELAX_EN |
4446 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4447}
4448
4449/*
4450 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4451 * Completion it generates.
4452 */
4453static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4454{
4455 /*
4456 * This mask/compare operation selects for Physical Function 4 on a
4457 * T5. We only need to fix up the Root Port once for any of the
4458 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4459 * 0x54xx so we use that one.
4460 */
4461 if ((pdev->device & 0xff00) == 0x5400)
4462 quirk_disable_root_port_attributes(pdev);
4463}
4464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4465 quirk_chelsio_T5_disable_root_port_attributes);
4466
4467/*
4468 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4469 * by a device
4470 * @acs_ctrl_req: Bitmask of desired ACS controls
4471 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4472 * the hardware design
4473 *
4474 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4475 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4476 * caller desires. Return 0 otherwise.
4477 */
4478static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4479{
4480 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4481 return 1;
4482 return 0;
4483}
4484
4485/*
4486 * AMD has indicated that the devices below do not support peer-to-peer
4487 * in any system where they are found in the southbridge with an AMD
4488 * IOMMU in the system. Multifunction devices that do not support
4489 * peer-to-peer between functions can claim to support a subset of ACS.
4490 * Such devices effectively enable request redirect (RR) and completion
4491 * redirect (CR) since all transactions are redirected to the upstream
4492 * root complex.
4493 *
4494 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4495 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4496 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4497 *
4498 * 1002:4385 SBx00 SMBus Controller
4499 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4500 * 1002:4383 SBx00 Azalia (Intel HDA)
4501 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4502 * 1002:4384 SBx00 PCI to PCI Bridge
4503 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4504 *
4505 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4506 *
4507 * 1022:780f [AMD] FCH PCI Bridge
4508 * 1022:7809 [AMD] FCH USB OHCI Controller
4509 */
4510static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4511{
4512#ifdef CONFIG_ACPI
4513 struct acpi_table_header *header = NULL;
4514 acpi_status status;
4515
4516 /* Targeting multifunction devices on the SB (appears on root bus) */
4517 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4518 return -ENODEV;
4519
4520 /* The IVRS table describes the AMD IOMMU */
4521 status = acpi_get_table("IVRS", 0, &header);
4522 if (ACPI_FAILURE(status))
4523 return -ENODEV;
4524
4525 acpi_put_table(header);
4526
4527 /* Filter out flags not applicable to multifunction */
4528 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4529
4530 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4531#else
4532 return -ENODEV;
4533#endif
4534}
4535
4536static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4537{
4538 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4539 return false;
4540
4541 switch (dev->device) {
4542 /*
4543 * Effectively selects all downstream ports for whole ThunderX1
4544 * (which represents 8 SoCs).
4545 */
4546 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4547 case 0xaf84: /* ThunderX2 */
4548 case 0xb884: /* ThunderX3 */
4549 return true;
4550 default:
4551 return false;
4552 }
4553}
4554
4555static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4556{
4557 if (!pci_quirk_cavium_acs_match(dev))
4558 return -ENOTTY;
4559
4560 /*
4561 * Cavium Root Ports don't advertise an ACS capability. However,
4562 * the RTL internally implements similar protection as if ACS had
4563 * Source Validation, Request Redirection, Completion Redirection,
4564 * and Upstream Forwarding features enabled. Assert that the
4565 * hardware implements and enables equivalent ACS functionality for
4566 * these flags.
4567 */
4568 return pci_acs_ctrl_enabled(acs_flags,
4569 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4570}
4571
4572static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4573{
4574 /*
4575 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4576 * transactions with others, allowing masking out these bits as if they
4577 * were unimplemented in the ACS capability.
4578 */
4579 return pci_acs_ctrl_enabled(acs_flags,
4580 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4581}
4582
4583/*
4584 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4585 * But the implementation could block peer-to-peer transactions between them
4586 * and provide ACS-like functionality.
4587 */
4588static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4589{
4590 if (!pci_is_pcie(dev) ||
4591 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4592 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4593 return -ENOTTY;
4594
4595 switch (dev->device) {
4596 case 0x0710 ... 0x071e:
4597 case 0x0721:
4598 case 0x0723 ... 0x0732:
4599 return pci_acs_ctrl_enabled(acs_flags,
4600 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4601 }
4602
4603 return false;
4604}
4605
4606/*
4607 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4608 * transactions and validate bus numbers in requests, but do not provide an
4609 * actual PCIe ACS capability. This is the list of device IDs known to fall
4610 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4611 */
4612static const u16 pci_quirk_intel_pch_acs_ids[] = {
4613 /* Ibexpeak PCH */
4614 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4615 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4616 /* Cougarpoint PCH */
4617 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4618 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4619 /* Pantherpoint PCH */
4620 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4621 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4622 /* Lynxpoint-H PCH */
4623 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4624 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4625 /* Lynxpoint-LP PCH */
4626 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4627 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4628 /* Wildcat PCH */
4629 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4630 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4631 /* Patsburg (X79) PCH */
4632 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4633 /* Wellsburg (X99) PCH */
4634 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4635 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4636 /* Lynx Point (9 series) PCH */
4637 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4638};
4639
4640static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4641{
4642 int i;
4643
4644 /* Filter out a few obvious non-matches first */
4645 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4646 return false;
4647
4648 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4649 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4650 return true;
4651
4652 return false;
4653}
4654
4655static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4656{
4657 if (!pci_quirk_intel_pch_acs_match(dev))
4658 return -ENOTTY;
4659
4660 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4661 return pci_acs_ctrl_enabled(acs_flags,
4662 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4663
4664 return pci_acs_ctrl_enabled(acs_flags, 0);
4665}
4666
4667/*
4668 * These QCOM Root Ports do provide ACS-like features to disable peer
4669 * transactions and validate bus numbers in requests, but do not provide an
4670 * actual PCIe ACS capability. Hardware supports source validation but it
4671 * will report the issue as Completer Abort instead of ACS Violation.
4672 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4673 * Complex with unique segment numbers. It is not possible for one Root
4674 * Port to pass traffic to another Root Port. All PCIe transactions are
4675 * terminated inside the Root Port.
4676 */
4677static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4678{
4679 return pci_acs_ctrl_enabled(acs_flags,
4680 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4681}
4682
4683/*
4684 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4685 * number and does provide isolation features to disable peer transactions
4686 * and validate bus numbers in requests, but does not provide an ACS
4687 * capability.
4688 */
4689static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4690{
4691 return pci_acs_ctrl_enabled(acs_flags,
4692 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4693}
4694
4695static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4696{
4697 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4698 return -ENOTTY;
4699
4700 /*
4701 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4702 * but do include ACS-like functionality. The hardware doesn't support
4703 * peer-to-peer transactions via the root port and each has a unique
4704 * segment number.
4705 *
4706 * Additionally, the root ports cannot send traffic to each other.
4707 */
4708 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4709
4710 return acs_flags ? 0 : 1;
4711}
4712
4713/*
4714 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4715 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4716 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4717 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4718 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4719 * control register is at offset 8 instead of 6 and we should probably use
4720 * dword accesses to them. This applies to the following PCI Device IDs, as
4721 * found in volume 1 of the datasheet[2]:
4722 *
4723 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4724 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4725 *
4726 * N.B. This doesn't fix what lspci shows.
4727 *
4728 * The 100 series chipset specification update includes this as errata #23[3].
4729 *
4730 * The 200 series chipset (Union Point) has the same bug according to the
4731 * specification update (Intel 200 Series Chipset Family Platform Controller
4732 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4733 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4734 * chipset include:
4735 *
4736 * 0xa290-0xa29f PCI Express Root port #{0-16}
4737 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4738 *
4739 * Mobile chipsets are also affected, 7th & 8th Generation
4740 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4741 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4742 * Processor Family I/O for U Quad Core Platforms Specification Update,
4743 * August 2017, Revision 002, Document#: 334660-002)[6]
4744 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4745 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4746 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4747 *
4748 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4749 *
4750 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4751 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4752 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4753 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4754 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4755 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4756 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4757 */
4758static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4759{
4760 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4761 return false;
4762
4763 switch (dev->device) {
4764 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4765 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4766 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4767 return true;
4768 }
4769
4770 return false;
4771}
4772
4773#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4774
4775static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4776{
4777 int pos;
4778 u32 cap, ctrl;
4779
4780 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4781 return -ENOTTY;
4782
4783 pos = dev->acs_cap;
4784 if (!pos)
4785 return -ENOTTY;
4786
4787 /* see pci_acs_flags_enabled() */
4788 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4789 acs_flags &= (cap | PCI_ACS_EC);
4790
4791 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4792
4793 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4794}
4795
4796static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4797{
4798 /*
4799 * SV, TB, and UF are not relevant to multifunction endpoints.
4800 *
4801 * Multifunction devices are only required to implement RR, CR, and DT
4802 * in their ACS capability if they support peer-to-peer transactions.
4803 * Devices matching this quirk have been verified by the vendor to not
4804 * perform peer-to-peer with other functions, allowing us to mask out
4805 * these bits as if they were unimplemented in the ACS capability.
4806 */
4807 return pci_acs_ctrl_enabled(acs_flags,
4808 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4809 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4810}
4811
4812static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4813{
4814 /*
4815 * Intel RCiEP's are required to allow p2p only on translated
4816 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4817 * "Root-Complex Peer to Peer Considerations".
4818 */
4819 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4820 return -ENOTTY;
4821
4822 return pci_acs_ctrl_enabled(acs_flags,
4823 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4824}
4825
4826static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4827{
4828 /*
4829 * iProc PAXB Root Ports don't advertise an ACS capability, but
4830 * they do not allow peer-to-peer transactions between Root Ports.
4831 * Allow each Root Port to be in a separate IOMMU group by masking
4832 * SV/RR/CR/UF bits.
4833 */
4834 return pci_acs_ctrl_enabled(acs_flags,
4835 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4836}
4837
4838static const struct pci_dev_acs_enabled {
4839 u16 vendor;
4840 u16 device;
4841 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4842} pci_dev_acs_enabled[] = {
4843 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4844 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4845 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4846 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4847 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4848 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4849 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4850 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4851 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4852 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4853 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4854 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4855 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4856 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4857 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4858 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4859 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4860 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4861 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4862 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4863 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4864 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4865 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4866 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4867 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4868 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4869 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4870 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4871 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4872 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4873 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4874 /* 82580 */
4875 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4876 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4877 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4878 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4879 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4880 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4881 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4882 /* 82576 */
4883 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4884 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4885 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4886 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4887 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4888 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4889 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4890 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4891 /* 82575 */
4892 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4893 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4894 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4895 /* I350 */
4896 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4897 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4898 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4899 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4900 /* 82571 (Quads omitted due to non-ACS switch) */
4901 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4902 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4903 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4904 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4905 /* I219 */
4906 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4907 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4908 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4909 /* QCOM QDF2xxx root ports */
4910 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4911 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4912 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4913 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4914 /* Intel PCH root ports */
4915 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4916 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4917 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4918 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4919 /* Cavium ThunderX */
4920 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4921 /* Cavium multi-function devices */
4922 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4923 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4924 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4925 /* APM X-Gene */
4926 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4927 /* Ampere Computing */
4928 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4929 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4930 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4931 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4932 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4933 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4934 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4935 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4936 /* Broadcom multi-function device */
4937 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4938 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
4939 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
4940 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
4941 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4942 /* Amazon Annapurna Labs */
4943 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4944 /* Zhaoxin multi-function devices */
4945 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4946 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4947 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4948 /* NXP root ports, xx=16, 12, or 08 cores */
4949 /* LX2xx0A : without security features + CAN-FD */
4950 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4951 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4952 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4953 /* LX2xx0C : security features + CAN-FD */
4954 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4955 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4956 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4957 /* LX2xx0E : security features + CAN */
4958 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4959 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4960 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4961 /* LX2xx0N : without security features + CAN */
4962 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4963 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4964 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4965 /* LX2xx2A : without security features + CAN-FD */
4966 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4967 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4968 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4969 /* LX2xx2C : security features + CAN-FD */
4970 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4971 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4972 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4973 /* LX2xx2E : security features + CAN */
4974 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4975 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4976 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4977 /* LX2xx2N : without security features + CAN */
4978 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4979 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4980 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4981 /* Zhaoxin Root/Downstream Ports */
4982 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4983 { 0 }
4984};
4985
4986/*
4987 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4988 * @dev: PCI device
4989 * @acs_flags: Bitmask of desired ACS controls
4990 *
4991 * Returns:
4992 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4993 * device provides the desired controls
4994 * 0: Device does not provide all the desired controls
4995 * >0: Device provides all the controls in @acs_flags
4996 */
4997int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4998{
4999 const struct pci_dev_acs_enabled *i;
5000 int ret;
5001
5002 /*
5003 * Allow devices that do not expose standard PCIe ACS capabilities
5004 * or control to indicate their support here. Multi-function express
5005 * devices which do not allow internal peer-to-peer between functions,
5006 * but do not implement PCIe ACS may wish to return true here.
5007 */
5008 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5009 if ((i->vendor == dev->vendor ||
5010 i->vendor == (u16)PCI_ANY_ID) &&
5011 (i->device == dev->device ||
5012 i->device == (u16)PCI_ANY_ID)) {
5013 ret = i->acs_enabled(dev, acs_flags);
5014 if (ret >= 0)
5015 return ret;
5016 }
5017 }
5018
5019 return -ENOTTY;
5020}
5021
5022/* Config space offset of Root Complex Base Address register */
5023#define INTEL_LPC_RCBA_REG 0xf0
5024/* 31:14 RCBA address */
5025#define INTEL_LPC_RCBA_MASK 0xffffc000
5026/* RCBA Enable */
5027#define INTEL_LPC_RCBA_ENABLE (1 << 0)
5028
5029/* Backbone Scratch Pad Register */
5030#define INTEL_BSPR_REG 0x1104
5031/* Backbone Peer Non-Posted Disable */
5032#define INTEL_BSPR_REG_BPNPD (1 << 8)
5033/* Backbone Peer Posted Disable */
5034#define INTEL_BSPR_REG_BPPD (1 << 9)
5035
5036/* Upstream Peer Decode Configuration Register */
5037#define INTEL_UPDCR_REG 0x1014
5038/* 5:0 Peer Decode Enable bits */
5039#define INTEL_UPDCR_REG_MASK 0x3f
5040
5041static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5042{
5043 u32 rcba, bspr, updcr;
5044 void __iomem *rcba_mem;
5045
5046 /*
5047 * Read the RCBA register from the LPC (D31:F0). PCH root ports
5048 * are D28:F* and therefore get probed before LPC, thus we can't
5049 * use pci_get_slot()/pci_read_config_dword() here.
5050 */
5051 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5052 INTEL_LPC_RCBA_REG, &rcba);
5053 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5054 return -EINVAL;
5055
5056 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5057 PAGE_ALIGN(INTEL_UPDCR_REG));
5058 if (!rcba_mem)
5059 return -ENOMEM;
5060
5061 /*
5062 * The BSPR can disallow peer cycles, but it's set by soft strap and
5063 * therefore read-only. If both posted and non-posted peer cycles are
5064 * disallowed, we're ok. If either are allowed, then we need to use
5065 * the UPDCR to disable peer decodes for each port. This provides the
5066 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5067 */
5068 bspr = readl(rcba_mem + INTEL_BSPR_REG);
5069 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5070 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5071 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5072 if (updcr & INTEL_UPDCR_REG_MASK) {
5073 pci_info(dev, "Disabling UPDCR peer decodes\n");
5074 updcr &= ~INTEL_UPDCR_REG_MASK;
5075 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5076 }
5077 }
5078
5079 iounmap(rcba_mem);
5080 return 0;
5081}
5082
5083/* Miscellaneous Port Configuration register */
5084#define INTEL_MPC_REG 0xd8
5085/* MPC: Invalid Receive Bus Number Check Enable */
5086#define INTEL_MPC_REG_IRBNCE (1 << 26)
5087
5088static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5089{
5090 u32 mpc;
5091
5092 /*
5093 * When enabled, the IRBNCE bit of the MPC register enables the
5094 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5095 * ensures that requester IDs fall within the bus number range
5096 * of the bridge. Enable if not already.
5097 */
5098 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5099 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5100 pci_info(dev, "Enabling MPC IRBNCE\n");
5101 mpc |= INTEL_MPC_REG_IRBNCE;
5102 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5103 }
5104}
5105
5106/*
5107 * Currently this quirk does the equivalent of
5108 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5109 *
5110 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5111 * if dev->external_facing || dev->untrusted
5112 */
5113static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5114{
5115 if (!pci_quirk_intel_pch_acs_match(dev))
5116 return -ENOTTY;
5117
5118 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5119 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5120 return 0;
5121 }
5122
5123 pci_quirk_enable_intel_rp_mpc_acs(dev);
5124
5125 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5126
5127 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5128
5129 return 0;
5130}
5131
5132static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5133{
5134 int pos;
5135 u32 cap, ctrl;
5136
5137 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5138 return -ENOTTY;
5139
5140 pos = dev->acs_cap;
5141 if (!pos)
5142 return -ENOTTY;
5143
5144 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5145 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5146
5147 ctrl |= (cap & PCI_ACS_SV);
5148 ctrl |= (cap & PCI_ACS_RR);
5149 ctrl |= (cap & PCI_ACS_CR);
5150 ctrl |= (cap & PCI_ACS_UF);
5151
5152 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5153 ctrl |= (cap & PCI_ACS_TB);
5154
5155 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5156
5157 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5158
5159 return 0;
5160}
5161
5162static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5163{
5164 int pos;
5165 u32 cap, ctrl;
5166
5167 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5168 return -ENOTTY;
5169
5170 pos = dev->acs_cap;
5171 if (!pos)
5172 return -ENOTTY;
5173
5174 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5175 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5176
5177 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5178
5179 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5180
5181 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5182
5183 return 0;
5184}
5185
5186static const struct pci_dev_acs_ops {
5187 u16 vendor;
5188 u16 device;
5189 int (*enable_acs)(struct pci_dev *dev);
5190 int (*disable_acs_redir)(struct pci_dev *dev);
5191} pci_dev_acs_ops[] = {
5192 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5193 .enable_acs = pci_quirk_enable_intel_pch_acs,
5194 },
5195 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5196 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5197 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5198 },
5199};
5200
5201int pci_dev_specific_enable_acs(struct pci_dev *dev)
5202{
5203 const struct pci_dev_acs_ops *p;
5204 int i, ret;
5205
5206 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5207 p = &pci_dev_acs_ops[i];
5208 if ((p->vendor == dev->vendor ||
5209 p->vendor == (u16)PCI_ANY_ID) &&
5210 (p->device == dev->device ||
5211 p->device == (u16)PCI_ANY_ID) &&
5212 p->enable_acs) {
5213 ret = p->enable_acs(dev);
5214 if (ret >= 0)
5215 return ret;
5216 }
5217 }
5218
5219 return -ENOTTY;
5220}
5221
5222int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5223{
5224 const struct pci_dev_acs_ops *p;
5225 int i, ret;
5226
5227 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5228 p = &pci_dev_acs_ops[i];
5229 if ((p->vendor == dev->vendor ||
5230 p->vendor == (u16)PCI_ANY_ID) &&
5231 (p->device == dev->device ||
5232 p->device == (u16)PCI_ANY_ID) &&
5233 p->disable_acs_redir) {
5234 ret = p->disable_acs_redir(dev);
5235 if (ret >= 0)
5236 return ret;
5237 }
5238 }
5239
5240 return -ENOTTY;
5241}
5242
5243/*
5244 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5245 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5246 * Next Capability pointer in the MSI Capability Structure should point to
5247 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5248 * the list.
5249 */
5250static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5251{
5252 int pos, i = 0;
5253 u8 next_cap;
5254 u16 reg16, *cap;
5255 struct pci_cap_saved_state *state;
5256
5257 /* Bail if the hardware bug is fixed */
5258 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5259 return;
5260
5261 /* Bail if MSI Capability Structure is not found for some reason */
5262 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5263 if (!pos)
5264 return;
5265
5266 /*
5267 * Bail if Next Capability pointer in the MSI Capability Structure
5268 * is not the expected incorrect 0x00.
5269 */
5270 pci_read_config_byte(pdev, pos + 1, &next_cap);
5271 if (next_cap)
5272 return;
5273
5274 /*
5275 * PCIe Capability Structure is expected to be at 0x50 and should
5276 * terminate the list (Next Capability pointer is 0x00). Verify
5277 * Capability Id and Next Capability pointer is as expected.
5278 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5279 * to correctly set kernel data structures which have already been
5280 * set incorrectly due to the hardware bug.
5281 */
5282 pos = 0x50;
5283 pci_read_config_word(pdev, pos, ®16);
5284 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5285 u32 status;
5286#ifndef PCI_EXP_SAVE_REGS
5287#define PCI_EXP_SAVE_REGS 7
5288#endif
5289 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5290
5291 pdev->pcie_cap = pos;
5292 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5293 pdev->pcie_flags_reg = reg16;
5294 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5295 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5296
5297 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5298 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5299 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5300 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5301
5302 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5303 return;
5304
5305 /* Save PCIe cap */
5306 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5307 if (!state)
5308 return;
5309
5310 state->cap.cap_nr = PCI_CAP_ID_EXP;
5311 state->cap.cap_extended = 0;
5312 state->cap.size = size;
5313 cap = (u16 *)&state->cap.data[0];
5314 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5315 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5316 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5317 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5318 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5319 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5320 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5321 hlist_add_head(&state->next, &pdev->saved_cap_space);
5322 }
5323}
5324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5325
5326/*
5327 * FLR may cause the following to devices to hang:
5328 *
5329 * AMD Starship/Matisse HD Audio Controller 0x1487
5330 * AMD Starship USB 3.0 Host Controller 0x148c
5331 * AMD Matisse USB 3.0 Host Controller 0x149c
5332 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5333 * Intel 82579V Gigabit Ethernet Controller 0x1503
5334 *
5335 */
5336static void quirk_no_flr(struct pci_dev *dev)
5337{
5338 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5339}
5340DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5341DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5342DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5343DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5344DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5345
5346static void quirk_no_ext_tags(struct pci_dev *pdev)
5347{
5348 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5349
5350 if (!bridge)
5351 return;
5352
5353 bridge->no_ext_tags = 1;
5354 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5355
5356 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5357}
5358DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5359DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5360DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5361DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5362DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5363DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5364DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5365
5366#ifdef CONFIG_PCI_ATS
5367/*
5368 * Some devices require additional driver setup to enable ATS. Don't use
5369 * ATS for those devices as ATS will be enabled before the driver has had a
5370 * chance to load and configure the device.
5371 */
5372static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5373{
5374 if (pdev->device == 0x15d8) {
5375 if (pdev->revision == 0xcf &&
5376 pdev->subsystem_vendor == 0xea50 &&
5377 (pdev->subsystem_device == 0xce19 ||
5378 pdev->subsystem_device == 0xcc10 ||
5379 pdev->subsystem_device == 0xcc08))
5380 goto no_ats;
5381 else
5382 return;
5383 }
5384
5385no_ats:
5386 pci_info(pdev, "disabling ATS\n");
5387 pdev->ats_cap = 0;
5388}
5389
5390/* AMD Stoney platform GPU */
5391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5392/* AMD Iceland dGPU */
5393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5394/* AMD Navi10 dGPU */
5395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5403/* AMD Navi14 dGPU */
5404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5408/* AMD Raven platform iGPU */
5409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5410#endif /* CONFIG_PCI_ATS */
5411
5412/* Freescale PCIe doesn't support MSI in RC mode */
5413static void quirk_fsl_no_msi(struct pci_dev *pdev)
5414{
5415 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5416 pdev->no_msi = 1;
5417}
5418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5419
5420/*
5421 * Although not allowed by the spec, some multi-function devices have
5422 * dependencies of one function (consumer) on another (supplier). For the
5423 * consumer to work in D0, the supplier must also be in D0. Create a
5424 * device link from the consumer to the supplier to enforce this
5425 * dependency. Runtime PM is allowed by default on the consumer to prevent
5426 * it from permanently keeping the supplier awake.
5427 */
5428static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5429 unsigned int supplier, unsigned int class,
5430 unsigned int class_shift)
5431{
5432 struct pci_dev *supplier_pdev;
5433
5434 if (PCI_FUNC(pdev->devfn) != consumer)
5435 return;
5436
5437 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5438 pdev->bus->number,
5439 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5440 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5441 pci_dev_put(supplier_pdev);
5442 return;
5443 }
5444
5445 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5446 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5447 pci_info(pdev, "D0 power state depends on %s\n",
5448 pci_name(supplier_pdev));
5449 else
5450 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5451 pci_name(supplier_pdev));
5452
5453 pm_runtime_allow(&pdev->dev);
5454 pci_dev_put(supplier_pdev);
5455}
5456
5457/*
5458 * Create device link for GPUs with integrated HDA controller for streaming
5459 * audio to attached displays.
5460 */
5461static void quirk_gpu_hda(struct pci_dev *hda)
5462{
5463 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5464}
5465DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5466 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5467DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5468 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5469DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5470 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5471
5472/*
5473 * Create device link for GPUs with integrated USB xHCI Host
5474 * controller to VGA.
5475 */
5476static void quirk_gpu_usb(struct pci_dev *usb)
5477{
5478 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5479}
5480DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5481 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5482DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5483 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5484
5485/*
5486 * Create device link for GPUs with integrated Type-C UCSI controller
5487 * to VGA. Currently there is no class code defined for UCSI device over PCI
5488 * so using UNKNOWN class for now and it will be updated when UCSI
5489 * over PCI gets a class code.
5490 */
5491#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5492static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5493{
5494 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5495}
5496DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5497 PCI_CLASS_SERIAL_UNKNOWN, 8,
5498 quirk_gpu_usb_typec_ucsi);
5499DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5500 PCI_CLASS_SERIAL_UNKNOWN, 8,
5501 quirk_gpu_usb_typec_ucsi);
5502
5503/*
5504 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5505 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5506 */
5507static void quirk_nvidia_hda(struct pci_dev *gpu)
5508{
5509 u8 hdr_type;
5510 u32 val;
5511
5512 /* There was no integrated HDA controller before MCP89 */
5513 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5514 return;
5515
5516 /* Bit 25 at offset 0x488 enables the HDA controller */
5517 pci_read_config_dword(gpu, 0x488, &val);
5518 if (val & BIT(25))
5519 return;
5520
5521 pci_info(gpu, "Enabling HDA controller\n");
5522 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5523
5524 /* The GPU becomes a multi-function device when the HDA is enabled */
5525 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5526 gpu->multifunction = !!(hdr_type & 0x80);
5527}
5528DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5529 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5530DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5531 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5532
5533/*
5534 * Some IDT switches incorrectly flag an ACS Source Validation error on
5535 * completions for config read requests even though PCIe r4.0, sec
5536 * 6.12.1.1, says that completions are never affected by ACS Source
5537 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5538 *
5539 * Item #36 - Downstream port applies ACS Source Validation to Completions
5540 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5541 * completions are never affected by ACS Source Validation. However,
5542 * completions received by a downstream port of the PCIe switch from a
5543 * device that has not yet captured a PCIe bus number are incorrectly
5544 * dropped by ACS Source Validation by the switch downstream port.
5545 *
5546 * The workaround suggested by IDT is to issue a config write to the
5547 * downstream device before issuing the first config read. This allows the
5548 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5549 * sec 2.2.9), thus avoiding the ACS error on the completion.
5550 *
5551 * However, we don't know when the device is ready to accept the config
5552 * write, so we do config reads until we receive a non-Config Request Retry
5553 * Status, then do the config write.
5554 *
5555 * To avoid hitting the erratum when doing the config reads, we disable ACS
5556 * SV around this process.
5557 */
5558int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5559{
5560 int pos;
5561 u16 ctrl = 0;
5562 bool found;
5563 struct pci_dev *bridge = bus->self;
5564
5565 pos = bridge->acs_cap;
5566
5567 /* Disable ACS SV before initial config reads */
5568 if (pos) {
5569 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5570 if (ctrl & PCI_ACS_SV)
5571 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5572 ctrl & ~PCI_ACS_SV);
5573 }
5574
5575 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5576
5577 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5578 if (found)
5579 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5580
5581 /* Re-enable ACS_SV if it was previously enabled */
5582 if (ctrl & PCI_ACS_SV)
5583 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5584
5585 return found;
5586}
5587
5588/*
5589 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5590 * NT endpoints via the internal switch fabric. These IDs replace the
5591 * originating requestor ID TLPs which access host memory on peer NTB
5592 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5593 * to permit access when the IOMMU is turned on.
5594 */
5595static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5596{
5597 void __iomem *mmio;
5598 struct ntb_info_regs __iomem *mmio_ntb;
5599 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5600 u64 partition_map;
5601 u8 partition;
5602 int pp;
5603
5604 if (pci_enable_device(pdev)) {
5605 pci_err(pdev, "Cannot enable Switchtec device\n");
5606 return;
5607 }
5608
5609 mmio = pci_iomap(pdev, 0, 0);
5610 if (mmio == NULL) {
5611 pci_disable_device(pdev);
5612 pci_err(pdev, "Cannot iomap Switchtec device\n");
5613 return;
5614 }
5615
5616 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5617
5618 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5619 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5620
5621 partition = ioread8(&mmio_ntb->partition_id);
5622
5623 partition_map = ioread32(&mmio_ntb->ep_map);
5624 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5625 partition_map &= ~(1ULL << partition);
5626
5627 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5628 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5629 u32 table_sz = 0;
5630 int te;
5631
5632 if (!(partition_map & (1ULL << pp)))
5633 continue;
5634
5635 pci_dbg(pdev, "Processing partition %d\n", pp);
5636
5637 mmio_peer_ctrl = &mmio_ctrl[pp];
5638
5639 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5640 if (!table_sz) {
5641 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5642 continue;
5643 }
5644
5645 if (table_sz > 512) {
5646 pci_warn(pdev,
5647 "Invalid Switchtec partition %d table_sz %d\n",
5648 pp, table_sz);
5649 continue;
5650 }
5651
5652 for (te = 0; te < table_sz; te++) {
5653 u32 rid_entry;
5654 u8 devfn;
5655
5656 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5657 devfn = (rid_entry >> 1) & 0xFF;
5658 pci_dbg(pdev,
5659 "Aliasing Partition %d Proxy ID %02x.%d\n",
5660 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5661 pci_add_dma_alias(pdev, devfn, 1);
5662 }
5663 }
5664
5665 pci_iounmap(pdev, mmio);
5666 pci_disable_device(pdev);
5667}
5668#define SWITCHTEC_QUIRK(vid) \
5669 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5670 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5671
5672SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5673SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5674SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5675SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5676SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5677SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5678SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5679SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5680SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5681SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5682SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5683SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5684SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5685SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5686SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5687SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5688SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5689SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5690SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5691SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5692SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5693SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5694SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5695SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5696SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5697SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5698SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5699SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5700SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5701SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5702SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5703SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5704SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5705SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5706SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5707SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5708SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5709SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5710SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5711SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5712SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5713SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5714SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5715SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5716SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5717SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5718SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5719SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5720SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */
5721SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */
5722SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */
5723SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */
5724SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */
5725SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */
5726SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */
5727SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */
5728SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */
5729
5730/*
5731 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5732 * These IDs are used to forward responses to the originator on the other
5733 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5734 * the IOMMU is turned on.
5735 */
5736static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5737{
5738 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5739 /* PLX NTB may use all 256 devfns */
5740 pci_add_dma_alias(pdev, 0, 256);
5741}
5742DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5743DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5744
5745/*
5746 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5747 * not always reset the secondary Nvidia GPU between reboots if the system
5748 * is configured to use Hybrid Graphics mode. This results in the GPU
5749 * being left in whatever state it was in during the *previous* boot, which
5750 * causes spurious interrupts from the GPU, which in turn causes us to
5751 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5752 * this also completely breaks nouveau.
5753 *
5754 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5755 * clean state and fixes all these issues.
5756 *
5757 * When the machine is configured in Dedicated display mode, the issue
5758 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5759 * mode, so we can detect that and avoid resetting it.
5760 */
5761static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5762{
5763 void __iomem *map;
5764 int ret;
5765
5766 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5767 pdev->subsystem_device != 0x222e ||
5768 !pci_reset_supported(pdev))
5769 return;
5770
5771 if (pci_enable_device_mem(pdev))
5772 return;
5773
5774 /*
5775 * Based on nvkm_device_ctor() in
5776 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5777 */
5778 map = pci_iomap(pdev, 0, 0x23000);
5779 if (!map) {
5780 pci_err(pdev, "Can't map MMIO space\n");
5781 goto out_disable;
5782 }
5783
5784 /*
5785 * Make sure the GPU looks like it's been POSTed before resetting
5786 * it.
5787 */
5788 if (ioread32(map + 0x2240c) & 0x2) {
5789 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5790 ret = pci_reset_bus(pdev);
5791 if (ret < 0)
5792 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5793 }
5794
5795 iounmap(map);
5796out_disable:
5797 pci_disable_device(pdev);
5798}
5799DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5800 PCI_CLASS_DISPLAY_VGA, 8,
5801 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5802
5803/*
5804 * Device [1b21:2142]
5805 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5806 */
5807static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5808{
5809 pci_info(dev, "PME# does not work under D0, disabling it\n");
5810 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5811}
5812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5813
5814/*
5815 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5816 *
5817 * These devices advertise PME# support in all power states but don't
5818 * reliably assert it.
5819 *
5820 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5821 * says "The MSI Function is not implemented on this device" in chapters
5822 * 7.3.27, 7.3.29-7.3.31.
5823 */
5824static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5825{
5826#ifdef CONFIG_PCI_MSI
5827 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5828 dev->no_msi = 1;
5829#endif
5830 pci_info(dev, "PME# is unreliable, disabling it\n");
5831 dev->pme_support = 0;
5832}
5833DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5835
5836static void apex_pci_fixup_class(struct pci_dev *pdev)
5837{
5838 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5839}
5840DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5841 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
5842
5843/*
5844 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
5845 * ACS P2P Request Redirect is not functional
5846 *
5847 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
5848 * between upstream and downstream ports, packets are queued in an internal
5849 * buffer until CPLD packet. The workaround is to use the switch in store and
5850 * forward mode.
5851 */
5852#define PI7C9X2Gxxx_MODE_REG 0x74
5853#define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0)
5854static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
5855{
5856 struct pci_dev *upstream;
5857 u16 val;
5858
5859 /* Downstream ports only */
5860 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
5861 return;
5862
5863 /* Check for ACS P2P Request Redirect use */
5864 if (!pdev->acs_cap)
5865 return;
5866 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
5867 if (!(val & PCI_ACS_RR))
5868 return;
5869
5870 upstream = pci_upstream_bridge(pdev);
5871 if (!upstream)
5872 return;
5873
5874 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
5875 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
5876 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
5877 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
5878 PI7C9X2Gxxx_STORE_FORWARD_MODE);
5879 }
5880}
5881/*
5882 * Apply fixup on enable and on resume, in order to apply the fix up whenever
5883 * ACS configuration changes or switch mode is reset
5884 */
5885DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
5886 pci_fixup_pericom_acs_store_forward);
5887DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
5888 pci_fixup_pericom_acs_store_forward);
5889DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
5890 pci_fixup_pericom_acs_store_forward);
5891DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
5892 pci_fixup_pericom_acs_store_forward);
5893DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
5894 pci_fixup_pericom_acs_store_forward);
5895DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
5896 pci_fixup_pericom_acs_store_forward);
5897
5898static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
5899{
5900 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
5901}
5902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
5903
5904static void rom_bar_overlap_defect(struct pci_dev *dev)
5905{
5906 pci_info(dev, "working around ROM BAR overlap defect\n");
5907 dev->rom_bar_overlap = 1;
5908}
5909DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
5910DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
5911DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
5912DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
5913
5914#ifdef CONFIG_PCIEASPM
5915/*
5916 * Several Intel DG2 graphics devices advertise that they can only tolerate
5917 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
5918 * from being enabled. But in fact these devices can tolerate unlimited
5919 * latency. Override their Device Capabilities value to allow ASPM L1 to
5920 * be enabled.
5921 */
5922static void aspm_l1_acceptable_latency(struct pci_dev *dev)
5923{
5924 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
5925
5926 if (l1_lat < 7) {
5927 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
5928 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
5929 l1_lat);
5930 }
5931}
5932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
5933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
5934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
5935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
5936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
5937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
5938DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
5939DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
5940DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
5941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
5942DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
5943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
5944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
5945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
5946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
5947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
5948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
5949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
5950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
5951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
5952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
5953DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
5954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
5955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
5956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
5957DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
5958#endif
5959
5960#ifdef CONFIG_PCIE_DPC
5961/*
5962 * Intel Tiger Lake and Alder Lake BIOS has a bug that clears the DPC
5963 * RP PIO Log Size of the integrated Thunderbolt PCIe Root Ports.
5964 */
5965static void dpc_log_size(struct pci_dev *dev)
5966{
5967 u16 dpc, val;
5968
5969 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
5970 if (!dpc)
5971 return;
5972
5973 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
5974 if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
5975 return;
5976
5977 if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
5978 pci_info(dev, "Overriding RP PIO Log Size to 4\n");
5979 dev->dpc_rp_log_size = 4;
5980 }
5981}
5982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
5983DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
5984DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
5985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
5986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
5987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
5988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
5989DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
5990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
5991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
5992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
5993DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
5994#endif