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1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/acpi.h>
25#include <linux/kallsyms.h>
26#include <linux/dmi.h>
27#include <linux/pci-aspm.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/ktime.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h"
33
34/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
40static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
41{
42 dev->mmio_always_on = 1;
43}
44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
46
47/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
51static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
52{
53 dev->broken_parity_status = 1; /* This device gives false positives */
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
58/* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
60static void quirk_passive_release(struct pci_dev *dev)
61{
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75}
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
78
79/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
85
86static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
87{
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 }
92}
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
104
105/*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
109static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110{
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122}
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
125/*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
128static void __devinit quirk_nopcipci(struct pci_dev *dev)
129{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134}
135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
137
138static void __devinit quirk_nopciamd(struct pci_dev *dev)
139{
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147}
148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
149
150/*
151 * Triton requires workarounds to be used by the drivers
152 */
153static void __devinit quirk_triton(struct pci_dev *dev)
154{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159}
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
164
165/*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
169 * and http://www.georgebreese.com/net/software/#PCI
170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
176static void quirk_vialatency(struct pci_dev *dev)
177{
178 struct pci_dev *p;
179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
187 if (p->revision < 0x40 || p->revision > 0x42)
188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
193 /* Check for buggy part revisions */
194 if (p->revision < 0x10 || p->revision > 0x12)
195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
206 * both Linux and Windows this isn't enough, and we have seen
207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218exit:
219 pci_dev_put(p);
220}
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224/* Must restore this on a resume from RAM */
225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
228
229/*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
232static void __devinit quirk_viaetbf(struct pci_dev *dev)
233{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238}
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240
241static void __devinit quirk_vsfx(struct pci_dev *dev)
242{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247}
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
249
250/*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
256static void __init quirk_alimagik(struct pci_dev *dev)
257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262}
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
265
266/*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
270static void __devinit quirk_natoma(struct pci_dev *dev)
271{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276}
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
283
284/*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
288static void __devinit quirk_citrine(struct pci_dev *dev)
289{
290 dev->cfg_size = 0xA0;
291}
292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
293
294/*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
298static void __devinit quirk_s3_64M(struct pci_dev *dev)
299{
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306}
307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
309
310/*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
316static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
317{
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
327static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name)
329{
330 region &= ~(size-1);
331 if (region) {
332 struct pci_bus_region bus_region;
333 struct resource *res = dev->resource + nr;
334
335 res->name = pci_name(dev);
336 res->start = region;
337 res->end = region + size - 1;
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space. */
341 bus_region.start = res->start;
342 bus_region.end = res->end;
343 pcibios_bus_to_resource(dev, res, &bus_region);
344
345 if (pci_claim_resource(dev, nr) == 0)
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
347 res, name);
348 }
349}
350
351/*
352 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */
355static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
356{
357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
359 request_region(0x3b0, 0x0C, "RadeonIGP");
360 request_region(0x3d3, 0x01, "RadeonIGP");
361}
362DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
363
364/*
365 * Let's make the southbridge information explicit instead
366 * of having to worry about people probing the ACPI areas,
367 * for example.. (Yes, it happens, and if you read the wrong
368 * ACPI register it will put the machine to sleep with no
369 * way of waking it up again. Bummer).
370 *
371 * ALI M7101: Two IO regions pointed to by words at
372 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers)
374 */
375static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
376{
377 u16 region;
378
379 pci_read_config_word(dev, 0xE0, ®ion);
380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
381 pci_read_config_word(dev, 0xE2, ®ion);
382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
383}
384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
385
386static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
387{
388 u32 devres;
389 u32 mask, size, base;
390
391 pci_read_config_dword(dev, port, &devres);
392 if ((devres & enable) != enable)
393 return;
394 mask = (devres >> 16) & 15;
395 base = devres & 0xffff;
396 size = 16;
397 for (;;) {
398 unsigned bit = size >> 1;
399 if ((bit & mask) == bit)
400 break;
401 size = bit;
402 }
403 /*
404 * For now we only print it out. Eventually we'll want to
405 * reserve it (at least if it's in the 0x1000+ range), but
406 * let's get enough confirmation reports first.
407 */
408 base &= -size;
409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
410}
411
412static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413{
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 base = devres & 0xffff0000;
421 mask = (devres & 0x3f) << 16;
422 size = 128 << 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it, but let's get enough confirmation reports first.
432 */
433 base &= -size;
434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
435}
436
437/*
438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
439 * 0x40 (64 bytes of ACPI registers)
440 * 0x90 (16 bytes of SMB registers)
441 * and a few strange programmable PIIX4 device resources.
442 */
443static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
444{
445 u32 region, res_a;
446
447 pci_read_config_dword(dev, 0x40, ®ion);
448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
449 pci_read_config_dword(dev, 0x90, ®ion);
450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
451
452 /* Device resource A has enables for some of the other ones */
453 pci_read_config_dword(dev, 0x5c, &res_a);
454
455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
457
458 /* Device resource D is just bitfields for static resources */
459
460 /* Device 12 enabled? */
461 if (res_a & (1 << 29)) {
462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
464 }
465 /* Device 13 enabled? */
466 if (res_a & (1 << 30)) {
467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
469 }
470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
472}
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
475
476#define ICH_PMBASE 0x40
477#define ICH_ACPI_CNTL 0x44
478#define ICH4_ACPI_EN 0x10
479#define ICH6_ACPI_EN 0x80
480#define ICH4_GPIOBASE 0x58
481#define ICH4_GPIO_CNTL 0x5c
482#define ICH4_GPIO_EN 0x10
483#define ICH6_GPIOBASE 0x48
484#define ICH6_GPIO_CNTL 0x4c
485#define ICH6_GPIO_EN 0x10
486
487/*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{
494 u32 region;
495 u8 enable;
496
497 /*
498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
499 * with low legacy (and fixed) ports. We don't know the decoding
500 * priority and can't tell whether the legacy device or the one created
501 * here is really at that address. This happens on boards with broken
502 * BIOSes.
503 */
504
505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
506 if (enable & ICH4_ACPI_EN) {
507 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 if (region >= PCIBIOS_MIN_IO)
510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
511 "ICH4 ACPI/GPIO/TCO");
512 }
513
514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
515 if (enable & ICH4_GPIO_EN) {
516 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
517 region &= PCI_BASE_ADDRESS_IO_MASK;
518 if (region >= PCIBIOS_MIN_IO)
519 quirk_io_region(dev, region, 64,
520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
521 }
522}
523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
533
534static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
535{
536 u32 region;
537 u8 enable;
538
539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
540 if (enable & ICH6_ACPI_EN) {
541 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
542 region &= PCI_BASE_ADDRESS_IO_MASK;
543 if (region >= PCIBIOS_MIN_IO)
544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
545 "ICH6 ACPI/GPIO/TCO");
546 }
547
548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
549 if (enable & ICH6_GPIO_EN) {
550 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
551 region &= PCI_BASE_ADDRESS_IO_MASK;
552 if (region >= PCIBIOS_MIN_IO)
553 quirk_io_region(dev, region, 64,
554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
555 }
556}
557
558static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559{
560 u32 val;
561 u32 size, base;
562
563 pci_read_config_dword(dev, reg, &val);
564
565 /* Enabled? */
566 if (!(val & 1))
567 return;
568 base = val & 0xfffc;
569 if (dynsize) {
570 /*
571 * This is not correct. It is 16, 32 or 64 bytes depending on
572 * register D31:F0:ADh bits 5:4.
573 *
574 * But this gets us at least _part_ of it.
575 */
576 size = 16;
577 } else {
578 size = 128;
579 }
580 base &= ~(size-1);
581
582 /* Just print it out for now. We should reserve it after more debugging */
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584}
585
586static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
587{
588 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev);
590
591 /* ICH6-specific generic IO decode */
592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
594}
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597
598static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599{
600 u32 val;
601 u32 mask, base;
602
603 pci_read_config_dword(dev, reg, &val);
604
605 /* Enabled? */
606 if (!(val & 1))
607 return;
608
609 /*
610 * IO base in bits 15:2, mask in bits 23:18, both
611 * are dword-based
612 */
613 base = val & 0xfffc;
614 mask = (val >> 16) & 0xfc;
615 mask |= 3;
616
617 /* Just print it out for now. We should reserve it after more debugging */
618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
619}
620
621/* ICH7-10 has the same common LPC generic IO decode registers */
622static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
623{
624 /* We share the common ACPI/GPIO decode with ICH6 */
625 ich6_lpc_acpi_gpio(dev);
626
627 /* And have 4 ICH7+ generic decodes */
628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
632}
633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
646
647/*
648 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */
651static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
652{
653 u32 region;
654
655 if (dev->revision & 0x10) {
656 pci_read_config_dword(dev, 0x48, ®ion);
657 region &= PCI_BASE_ADDRESS_IO_MASK;
658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
659 }
660}
661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
662
663/*
664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
665 * 0x48 (256 bytes of ACPI registers)
666 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers)
668 */
669static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
670{
671 u16 hm;
672 u32 smb;
673
674 quirk_vt82c586_acpi(dev);
675
676 pci_read_config_word(dev, 0x70, &hm);
677 hm &= PCI_BASE_ADDRESS_IO_MASK;
678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
679
680 pci_read_config_dword(dev, 0x90, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
685
686/*
687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
688 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers)
690 */
691static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
692{
693 u16 pm, smb;
694
695 pci_read_config_word(dev, 0x88, &pm);
696 pm &= PCI_BASE_ADDRESS_IO_MASK;
697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
698
699 pci_read_config_word(dev, 0xd0, &smb);
700 smb &= PCI_BASE_ADDRESS_IO_MASK;
701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
702}
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
704
705/*
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment
708 */
709static void __devinit quirk_xio2000a(struct pci_dev *dev)
710{
711 struct pci_dev *pdev;
712 u16 command;
713
714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
715 "secondary bus fast back-to-back transfers disabled\n");
716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
717 pci_read_config_word(pdev, PCI_COMMAND, &command);
718 if (command & PCI_COMMAND_FAST_BACK)
719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
720 }
721}
722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
723 quirk_xio2000a);
724
725#ifdef CONFIG_X86_IO_APIC
726
727#include <asm/io_apic.h>
728
729/*
730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
731 * devices to the external APIC.
732 *
733 * TODO: When we have device-specific interrupt routers,
734 * this code will go away from quirks.
735 */
736static void quirk_via_ioapic(struct pci_dev *dev)
737{
738 u8 tmp;
739
740 if (nr_ioapics < 1)
741 tmp = 0; /* nothing routed to external APIC */
742 else
743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
744
745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
746 tmp == 0 ? "Disa" : "Ena");
747
748 /* Offset 0x58: External APIC IRQ output control */
749 pci_write_config_byte (dev, 0x58, tmp);
750}
751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
753
754/*
755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
756 * This leads to doubled level interrupt rates.
757 * Set this bit to get rid of cycle wastage.
758 * Otherwise uncritical.
759 */
760static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
761{
762 u8 misc_control2;
763#define BYPASS_APIC_DEASSERT 8
764
765 pci_read_config_byte(dev, 0x5B, &misc_control2);
766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
769 }
770}
771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
773
774/*
775 * The AMD io apic can hang the box when an apic irq is masked.
776 * We check all revs >= B0 (yet not in the pre production!) as the bug
777 * is currently marked NoFix
778 *
779 * We have multiple reports of hangs with this chipset that went away with
780 * noapic specified. For the moment we assume it's the erratum. We may be wrong
781 * of course. However the advice is demonstrably good even if so..
782 */
783static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
784{
785 if (dev->revision >= 0x02) {
786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
788 }
789}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791
792static void __init quirk_ioapic_rmw(struct pci_dev *dev)
793{
794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1;
796}
797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
798#endif /* CONFIG_X86_IO_APIC */
799
800/*
801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */
804static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{
806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
808 "disabling PCI-X MMRBC\n", dev->revision);
809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
810 }
811}
812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
813
814/*
815 * FIXME: it is questionable that quirk_via_acpi
816 * is needed. It shows up as an ISA bridge, and does not
817 * support the PCI_INTERRUPT_LINE register at all. Therefore
818 * it seems like setting the pci_dev's 'irq' to the
819 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik
821 */
822static void __devinit quirk_via_acpi(struct pci_dev *d)
823{
824 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
826 */
827 u8 irq;
828 pci_read_config_byte(d, 0x42, &irq);
829 irq &= 0xf;
830 if (irq && (irq != 2))
831 d->irq = irq;
832}
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
835
836
837/*
838 * VIA bridges which have VLink
839 */
840
841static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
842
843static void quirk_via_bridge(struct pci_dev *dev)
844{
845 /* See what bridge we have and find the device ranges */
846 switch (dev->device) {
847 case PCI_DEVICE_ID_VIA_82C686:
848 /* The VT82C686 is special, it attaches to PCI and can have
849 any device number. All its subdevices are functions of
850 that single device. */
851 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
852 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
853 break;
854 case PCI_DEVICE_ID_VIA_8237:
855 case PCI_DEVICE_ID_VIA_8237A:
856 via_vlink_dev_lo = 15;
857 break;
858 case PCI_DEVICE_ID_VIA_8235:
859 via_vlink_dev_lo = 16;
860 break;
861 case PCI_DEVICE_ID_VIA_8231:
862 case PCI_DEVICE_ID_VIA_8233_0:
863 case PCI_DEVICE_ID_VIA_8233A:
864 case PCI_DEVICE_ID_VIA_8233C_0:
865 via_vlink_dev_lo = 17;
866 break;
867 }
868}
869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
877
878/**
879 * quirk_via_vlink - VIA VLink IRQ number update
880 * @dev: PCI device
881 *
882 * If the device we are dealing with is on a PIC IRQ we need to
883 * ensure that the IRQ line register which usually is not relevant
884 * for PCI cards, is actually written so that interrupts get sent
885 * to the right place.
886 * We only do this on systems where a VIA south bridge was detected,
887 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 * above).
889 */
890
891static void quirk_via_vlink(struct pci_dev *dev)
892{
893 u8 irq, new_irq;
894
895 /* Check if we have VLink at all */
896 if (via_vlink_dev_lo == -1)
897 return;
898
899 new_irq = dev->irq;
900
901 /* Don't quirk interrupts outside the legacy IRQ range */
902 if (!new_irq || new_irq > 15)
903 return;
904
905 /* Internal device ? */
906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
908 return;
909
910 /* This is an internal VLink device on a PIC interrupt. The BIOS
911 ought to have set this but may not have, so we redo it */
912
913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
914 if (new_irq != irq) {
915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
916 irq, new_irq);
917 udelay(15); /* unknown if delay really needed */
918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
919 }
920}
921DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
922
923/*
924 * VIA VT82C598 has its device ID settable and many BIOSes
925 * set it to the ID of VT82C597 for backward compatibility.
926 * We need to switch it off to be able to recognize the real
927 * type of the chip.
928 */
929static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
930{
931 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
935
936/*
937 * CardBus controllers have a legacy base address that enables them
938 * to respond as i82365 pcmcia controllers. We don't want them to
939 * do this even if the Linux CardBus driver is not loaded, because
940 * the Linux i82365 driver does not (and should not) handle CardBus.
941 */
942static void quirk_cardbus_legacy(struct pci_dev *dev)
943{
944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945}
946DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
948DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
950
951/*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not
953 * sure what the designers were smoking but let's not inhale...
954 *
955 * To be fair to AMD, it follows the spec by default, its BIOS people
956 * who turn it off!
957 */
958static void quirk_amd_ordering(struct pci_dev *dev)
959{
960 u32 pcic;
961 pci_read_config_dword(dev, 0x4C, &pcic);
962 if ((pcic&6)!=6) {
963 pcic |= 6;
964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
965 pci_write_config_dword(dev, 0x4C, pcic);
966 pci_read_config_dword(dev, 0x84, &pcic);
967 pcic |= (1<<23); /* Required in this mode */
968 pci_write_config_dword(dev, 0x84, pcic);
969 }
970}
971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
973
974/*
975 * DreamWorks provided workaround for Dunord I-3000 problem
976 *
977 * This card decodes and responds to addresses not apparently
978 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it.
980 */
981static void __devinit quirk_dunord ( struct pci_dev * dev )
982{
983 struct resource *r = &dev->resource [1];
984 r->start = 0;
985 r->end = 0xffffff;
986}
987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
988
989/*
990 * i82380FB mobile docking controller: its PCI-to-PCI bridge
991 * is subtractive decoding (transparent), and does indicate this
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01.
994 */
995static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
996{
997 dev->transparent = 1;
998}
999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1001
1002/*
1003 * Common misconfiguration of the MediaGX/Geode PCI master that will
1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1005 * datasheets found at http://www.national.com/analog for info on what
1006 * these bits do. <christer@weinigel.se>
1007 */
1008static void quirk_mediagx_master(struct pci_dev *dev)
1009{
1010 u8 reg;
1011 pci_read_config_byte(dev, 0x41, ®);
1012 if (reg & 2) {
1013 reg &= ~2;
1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1015 pci_write_config_byte(dev, 0x41, reg);
1016 }
1017}
1018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1019DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1020
1021/*
1022 * Ensure C0 rev restreaming is off. This is normally done by
1023 * the BIOS but in the odd case it is not the results are corruption
1024 * hence the presence of a Linux check
1025 */
1026static void quirk_disable_pxb(struct pci_dev *pdev)
1027{
1028 u16 config;
1029
1030 if (pdev->revision != 0x04) /* Only C0 requires this */
1031 return;
1032 pci_read_config_word(pdev, 0x40, &config);
1033 if (config & (1<<6)) {
1034 config &= ~(1<<6);
1035 pci_write_config_word(pdev, 0x40, config);
1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1037 }
1038}
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041
1042static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1043{
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp;
1046
1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1048 if (tmp == 0x01) {
1049 pci_read_config_byte(pdev, 0x40, &tmp);
1050 pci_write_config_byte(pdev, 0x40, tmp|1);
1051 pci_write_config_byte(pdev, 0x9, 1);
1052 pci_write_config_byte(pdev, 0xa, 6);
1053 pci_write_config_byte(pdev, 0x40, tmp);
1054
1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1057 }
1058}
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1060DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1062DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1064DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1065
1066/*
1067 * Serverworks CSB5 IDE does not fully support native mode
1068 */
1069static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1070{
1071 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1073 if (prog & 5) {
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1077 /* PCI layer will sort out resources */
1078 }
1079}
1080DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1081
1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */
1085static void __init quirk_ide_samemode(struct pci_dev *pdev)
1086{
1087 u8 prog;
1088
1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1090
1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1093 prog &= ~5;
1094 pdev->class &= ~5;
1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1096 }
1097}
1098DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1099
1100/*
1101 * Some ATA devices break if put into D3
1102 */
1103
1104static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1105{
1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1107}
1108/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1109DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1113/* ALi loses some register settings that we cannot then restore */
1114DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1116/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */
1118DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1120
1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */
1124static void __init quirk_eisa_bridge(struct pci_dev *dev)
1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127}
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1129
1130
1131/*
1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1133 * is not activated. The myth is that Asus said that they do not want the
1134 * users to be irritated by just another PCI Device in the Win98 device
1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1136 * package 2.7.0 for details)
1137 *
1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1140 * becomes necessary to do this tweak in two steps -- the chosen trigger
1141 * is either the Host bridge (preferred) or on-board VGA controller.
1142 *
1143 * Note that we used to unhide the SMBus that way on Toshiba laptops
1144 * (Satellite A40 and Tecra M2) but then found that the thermal management
1145 * was done by SMM code, which could cause unsynchronized concurrent
1146 * accesses to the SMBus registers, with potentially bad effects. Thus you
1147 * should be very careful when adding new entries: if SMM is accessing the
1148 * Intel SMBus, this is a very good reason to leave it hidden.
1149 *
1150 * Likewise, many recent laptops use ACPI for thermal management. If the
1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1152 * natively, and keeping the SMBus hidden is the right thing to do. If you
1153 * are about to add an entry in the table below, please first disassemble
1154 * the DSDT and double-check that there is no code accessing the SMBus.
1155 */
1156static int asus_hides_smbus;
1157
1158static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1162 switch(dev->subsystem_device) {
1163 case 0x8025: /* P4B-LX */
1164 case 0x8070: /* P4B */
1165 case 0x8088: /* P4B533 */
1166 case 0x1626: /* L3C notebook */
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1170 switch(dev->subsystem_device) {
1171 case 0x80b1: /* P4GE-V */
1172 case 0x80b2: /* P4PE */
1173 case 0x8093: /* P4B533-V */
1174 asus_hides_smbus = 1;
1175 }
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1177 switch(dev->subsystem_device) {
1178 case 0x8030: /* P4T533 */
1179 asus_hides_smbus = 1;
1180 }
1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1182 switch (dev->subsystem_device) {
1183 case 0x8070: /* P4G8X Deluxe */
1184 asus_hides_smbus = 1;
1185 }
1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1187 switch (dev->subsystem_device) {
1188 case 0x80c9: /* PU-DLS */
1189 asus_hides_smbus = 1;
1190 }
1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x1751: /* M2N notebook */
1194 case 0x1821: /* M5N notebook */
1195 case 0x1897: /* A6L notebook */
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1199 switch (dev->subsystem_device) {
1200 case 0x184b: /* W1N notebook */
1201 case 0x186a: /* M6Ne notebook */
1202 asus_hides_smbus = 1;
1203 }
1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x80f2: /* P4P800-X */
1207 asus_hides_smbus = 1;
1208 }
1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1210 switch (dev->subsystem_device) {
1211 case 0x1882: /* M6V notebook */
1212 case 0x1977: /* A6VA notebook */
1213 asus_hides_smbus = 1;
1214 }
1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1217 switch(dev->subsystem_device) {
1218 case 0x088C: /* HP Compaq nc8000 */
1219 case 0x0890: /* HP Compaq nc6000 */
1220 asus_hides_smbus = 1;
1221 }
1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1223 switch (dev->subsystem_device) {
1224 case 0x12bc: /* HP D330L */
1225 case 0x12bd: /* HP D530 */
1226 case 0x006a: /* HP Compaq nx9500 */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x12bf: /* HP xw4100 */
1232 asus_hides_smbus = 1;
1233 }
1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch(dev->subsystem_device) {
1237 case 0xC00C: /* Samsung P35 notebook */
1238 asus_hides_smbus = 1;
1239 }
1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch(dev->subsystem_device) {
1243 case 0x0058: /* Compaq Evo N620c */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1247 switch(dev->subsystem_device) {
1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1249 /* Motherboard doesn't have Host bridge
1250 * subvendor/subdevice IDs, therefore checking
1251 * its on-board VGA controller */
1252 asus_hides_smbus = 1;
1253 }
1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1255 switch(dev->subsystem_device) {
1256 case 0x00b8: /* Compaq Evo D510 CMT */
1257 case 0x00b9: /* Compaq Evo D510 SFF */
1258 case 0x00ba: /* Compaq Evo D510 USDT */
1259 /* Motherboard doesn't have Host bridge
1260 * subvendor/subdevice IDs and on-board VGA
1261 * controller is disabled if an AGP card is
1262 * inserted, therefore checking USB UHCI
1263 * Controller #1 */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1267 switch (dev->subsystem_device) {
1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1269 /* Motherboard doesn't have host bridge
1270 * subvendor/subdevice IDs, therefore checking
1271 * its on-board VGA controller */
1272 asus_hides_smbus = 1;
1273 }
1274 }
1275}
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1286
1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1290
1291static void asus_hides_smbus_lpc(struct pci_dev *dev)
1292{
1293 u16 val;
1294
1295 if (likely(!asus_hides_smbus))
1296 return;
1297
1298 pci_read_config_word(dev, 0xF2, &val);
1299 if (val & 0x8) {
1300 pci_write_config_word(dev, 0xF2, val & (~0x8));
1301 pci_read_config_word(dev, 0xF2, &val);
1302 if (val & 0x8)
1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1304 else
1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1306 }
1307}
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1322
1323/* It appears we just have one such device. If not, we have a warning */
1324static void __iomem *asus_rcba_base;
1325static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1326{
1327 u32 rcba;
1328
1329 if (likely(!asus_hides_smbus))
1330 return;
1331 WARN_ON(asus_rcba_base);
1332
1333 pci_read_config_dword(dev, 0xF0, &rcba);
1334 /* use bits 31:14, 16 kB aligned */
1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1336 if (asus_rcba_base == NULL)
1337 return;
1338}
1339
1340static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1341{
1342 u32 val;
1343
1344 if (likely(!asus_hides_smbus || !asus_rcba_base))
1345 return;
1346 /* read the Function Disable register, dword mode only */
1347 val = readl(asus_rcba_base + 0x3418);
1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1349}
1350
1351static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1352{
1353 if (likely(!asus_hides_smbus || !asus_rcba_base))
1354 return;
1355 iounmap(asus_rcba_base);
1356 asus_rcba_base = NULL;
1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1358}
1359
1360static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1361{
1362 asus_hides_smbus_lpc_ich6_suspend(dev);
1363 asus_hides_smbus_lpc_ich6_resume_early(dev);
1364 asus_hides_smbus_lpc_ich6_resume(dev);
1365}
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1367DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1368DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1369DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1370
1371/*
1372 * SiS 96x south bridge: BIOS typically hides SMBus device...
1373 */
1374static void quirk_sis_96x_smbus(struct pci_dev *dev)
1375{
1376 u8 val = 0;
1377 pci_read_config_byte(dev, 0x77, &val);
1378 if (val & 0x10) {
1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1380 pci_write_config_byte(dev, 0x77, val & ~0x10);
1381 }
1382}
1383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1387DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1388DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1390DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1391
1392/*
1393 * ... This is further complicated by the fact that some SiS96x south
1394 * bridges pretend to be 85C503/5513 instead. In that case see if we
1395 * spotted a compatible north bridge to make sure.
1396 * (pci_find_device doesn't work yet)
1397 *
1398 * We can also enable the sis96x bit in the discovery register..
1399 */
1400#define SIS_DETECT_REGISTER 0x40
1401
1402static void quirk_sis_503(struct pci_dev *dev)
1403{
1404 u8 reg;
1405 u16 devid;
1406
1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1412 return;
1413 }
1414
1415 /*
1416 * Ok, it now shows up as a 96x.. run the 96x quirk by
1417 * hand in case it has already been processed.
1418 * (depends on link order, which is apparently not guaranteed)
1419 */
1420 dev->device = devid;
1421 quirk_sis_96x_smbus(dev);
1422}
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1425
1426
1427/*
1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1429 * and MC97 modem controller are disabled when a second PCI soundcard is
1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1431 * -- bjd
1432 */
1433static void asus_hides_ac97_lpc(struct pci_dev *dev)
1434{
1435 u8 val;
1436 int asus_hides_ac97 = 0;
1437
1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1439 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1440 asus_hides_ac97 = 1;
1441 }
1442
1443 if (!asus_hides_ac97)
1444 return;
1445
1446 pci_read_config_byte(dev, 0x50, &val);
1447 if (val & 0xc0) {
1448 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1449 pci_read_config_byte(dev, 0x50, &val);
1450 if (val & 0xc0)
1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1452 else
1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1454 }
1455}
1456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1457DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1458
1459#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1460
1461/*
1462 * If we are using libata we can drive this chip properly but must
1463 * do this early on to make the additional device appear during
1464 * the PCI scanning.
1465 */
1466static void quirk_jmicron_ata(struct pci_dev *pdev)
1467{
1468 u32 conf1, conf5, class;
1469 u8 hdr;
1470
1471 /* Only poke fn 0 */
1472 if (PCI_FUNC(pdev->devfn))
1473 return;
1474
1475 pci_read_config_dword(pdev, 0x40, &conf1);
1476 pci_read_config_dword(pdev, 0x80, &conf5);
1477
1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1479 conf5 &= ~(1 << 24); /* Clear bit 24 */
1480
1481 switch (pdev->device) {
1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1485 /* The controller should be in single function ahci mode */
1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1487 break;
1488
1489 case PCI_DEVICE_ID_JMICRON_JMB365:
1490 case PCI_DEVICE_ID_JMICRON_JMB366:
1491 /* Redirect IDE second PATA port to the right spot */
1492 conf5 |= (1 << 24);
1493 /* Fall through */
1494 case PCI_DEVICE_ID_JMICRON_JMB361:
1495 case PCI_DEVICE_ID_JMICRON_JMB363:
1496 case PCI_DEVICE_ID_JMICRON_JMB369:
1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1498 /* Set the class codes correctly and then direct IDE 0 */
1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1500 break;
1501
1502 case PCI_DEVICE_ID_JMICRON_JMB368:
1503 /* The controller should be in single function IDE mode */
1504 conf1 |= 0x00C00000; /* Set 22, 23 */
1505 break;
1506 }
1507
1508 pci_write_config_dword(pdev, 0x40, conf1);
1509 pci_write_config_dword(pdev, 0x80, conf5);
1510
1511 /* Update pdev accordingly */
1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1513 pdev->hdr_type = hdr & 0x7f;
1514 pdev->multifunction = !!(hdr & 0x80);
1515
1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1517 pdev->class = class >> 8;
1518}
1519DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1520DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1521DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1522DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1524DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1525DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1526DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1527DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1528DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1529DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1530DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1537
1538#endif
1539
1540#ifdef CONFIG_X86_IO_APIC
1541static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1542{
1543 int i;
1544
1545 if ((pdev->class >> 8) != 0xff00)
1546 return;
1547
1548 /* the first BAR is the location of the IO APIC...we must
1549 * not touch this (and it's already covered by the fixmap), so
1550 * forcibly insert it into the resource tree */
1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1552 insert_resource(&iomem_resource, &pdev->resource[0]);
1553
1554 /* The next five BARs all seem to be rubbish, so just clean
1555 * them out */
1556 for (i=1; i < 6; i++) {
1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1558 }
1559
1560}
1561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1562#endif
1563
1564static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1565{
1566 pci_msi_off(pdev);
1567 pdev->no_msi = 1;
1568}
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1572
1573
1574/*
1575 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems.
1577 */
1578static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1579{
1580 pci_msi_off(dev);
1581 dev->no_msi = 1;
1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1583}
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1589
1590/*
1591 * Some Intel PCI Express chipsets have trouble with downstream
1592 * device power management.
1593 */
1594static void quirk_intel_pcie_pm(struct pci_dev * dev)
1595{
1596 pci_pm_d3_delay = 120;
1597 dev->no_d1d2 = 1;
1598}
1599
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1621
1622#ifdef CONFIG_X86_IO_APIC
1623/*
1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1625 * remap the original interrupt in the linux kernel to the boot interrupt, so
1626 * that a PCI device's interrupt handler is installed on the boot interrupt
1627 * line instead.
1628 */
1629static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1630{
1631 if (noioapicquirk || noioapicreroute)
1632 return;
1633
1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1636 dev->vendor, dev->device);
1637}
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1647DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1648DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1649DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1650DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1654
1655/*
1656 * On some chipsets we can disable the generation of legacy INTx boot
1657 * interrupts.
1658 */
1659
1660/*
1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1662 * 300641-004US, section 5.7.3.
1663 */
1664#define INTEL_6300_IOAPIC_ABAR 0x40
1665#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1666
1667static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1668{
1669 u16 pci_config_word;
1670
1671 if (noioapicquirk)
1672 return;
1673
1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1677
1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1679 dev->vendor, dev->device);
1680}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1682DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1683
1684/*
1685 * disable boot interrupts on HT-1000
1686 */
1687#define BC_HT1000_FEATURE_REG 0x64
1688#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1689#define BC_HT1000_MAP_IDX 0xC00
1690#define BC_HT1000_MAP_DATA 0xC01
1691
1692static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1693{
1694 u32 pci_config_dword;
1695 u8 irq;
1696
1697 if (noioapicquirk)
1698 return;
1699
1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1702 BC_HT1000_PIC_REGS_ENABLE);
1703
1704 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1705 outb(irq, BC_HT1000_MAP_IDX);
1706 outb(0x00, BC_HT1000_MAP_DATA);
1707 }
1708
1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1710
1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1712 dev->vendor, dev->device);
1713}
1714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1716
1717/*
1718 * disable boot interrupts on AMD and ATI chipsets
1719 */
1720/*
1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1723 * (due to an erratum).
1724 */
1725#define AMD_813X_MISC 0x40
1726#define AMD_813X_NOIOAMODE (1<<0)
1727#define AMD_813X_REV_B1 0x12
1728#define AMD_813X_REV_B2 0x13
1729
1730static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1731{
1732 u32 pci_config_dword;
1733
1734 if (noioapicquirk)
1735 return;
1736 if ((dev->revision == AMD_813X_REV_B1) ||
1737 (dev->revision == AMD_813X_REV_B2))
1738 return;
1739
1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1741 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1743
1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745 dev->vendor, dev->device);
1746}
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1750DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1751
1752#define AMD_8111_PCI_IRQ_ROUTING 0x56
1753
1754static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1755{
1756 u16 pci_config_word;
1757
1758 if (noioapicquirk)
1759 return;
1760
1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1762 if (!pci_config_word) {
1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1764 "already disabled\n", dev->vendor, dev->device);
1765 return;
1766 }
1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770}
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1773#endif /* CONFIG_X86_IO_APIC */
1774
1775/*
1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed...
1779 */
1780static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1781{
1782 struct resource *r = &dev->resource[0];
1783
1784 if (r->start & 0x8) {
1785 r->start = 0;
1786 r->end = 0xf;
1787 }
1788}
1789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide);
1792
1793static void __devinit quirk_netmos(struct pci_dev *dev)
1794{
1795 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1796 unsigned int num_serial = dev->subsystem_device & 0xf;
1797
1798 /*
1799 * These Netmos parts are multiport serial devices with optional
1800 * parallel ports. Even when parallel ports are present, they
1801 * are identified as class SERIAL, which means the serial driver
1802 * will claim them. To prevent this, mark them as class OTHER.
1803 * These combo devices should be claimed by parport_serial.
1804 *
1805 * The subdevice ID is of the form 0x00PS, where <P> is the number
1806 * of parallel ports and <S> is the number of serial ports.
1807 */
1808 switch (dev->device) {
1809 case PCI_DEVICE_ID_NETMOS_9835:
1810 /* Well, this rule doesn't hold for the following 9835 device */
1811 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1812 dev->subsystem_device == 0x0299)
1813 return;
1814 case PCI_DEVICE_ID_NETMOS_9735:
1815 case PCI_DEVICE_ID_NETMOS_9745:
1816 case PCI_DEVICE_ID_NETMOS_9845:
1817 case PCI_DEVICE_ID_NETMOS_9855:
1818 if (num_parallel) {
1819 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1820 "%u serial); changing class SERIAL to OTHER "
1821 "(use parport_serial)\n",
1822 dev->device, num_parallel, num_serial);
1823 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1824 (dev->class & 0xff);
1825 }
1826 }
1827}
1828DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1829 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1830
1831static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1832{
1833 u16 command, pmcsr;
1834 u8 __iomem *csr;
1835 u8 cmd_hi;
1836 int pm;
1837
1838 switch (dev->device) {
1839 /* PCI IDs taken from drivers/net/e100.c */
1840 case 0x1029:
1841 case 0x1030 ... 0x1034:
1842 case 0x1038 ... 0x103E:
1843 case 0x1050 ... 0x1057:
1844 case 0x1059:
1845 case 0x1064 ... 0x106B:
1846 case 0x1091 ... 0x1095:
1847 case 0x1209:
1848 case 0x1229:
1849 case 0x2449:
1850 case 0x2459:
1851 case 0x245D:
1852 case 0x27DC:
1853 break;
1854 default:
1855 return;
1856 }
1857
1858 /*
1859 * Some firmware hands off the e100 with interrupts enabled,
1860 * which can cause a flood of interrupts if packets are
1861 * received before the driver attaches to the device. So
1862 * disable all e100 interrupts here. The driver will
1863 * re-enable them when it's ready.
1864 */
1865 pci_read_config_word(dev, PCI_COMMAND, &command);
1866
1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1868 return;
1869
1870 /*
1871 * Check that the device is in the D0 power state. If it's not,
1872 * there is no point to look any further.
1873 */
1874 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1875 if (pm) {
1876 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1878 return;
1879 }
1880
1881 /* Convert from PCI bus to resource space. */
1882 csr = ioremap(pci_resource_start(dev, 0), 8);
1883 if (!csr) {
1884 dev_warn(&dev->dev, "Can't map e100 registers\n");
1885 return;
1886 }
1887
1888 cmd_hi = readb(csr + 3);
1889 if (cmd_hi == 0) {
1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1891 "disabling\n");
1892 writeb(1, csr + 3);
1893 }
1894
1895 iounmap(csr);
1896}
1897DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1899
1900/*
1901 * The 82575 and 82598 may experience data corruption issues when transitioning
1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1903 */
1904static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1905{
1906 dev_info(&dev->dev, "Disabling L0s\n");
1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1923
1924static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1925{
1926 /* rev 1 ncr53c810 chips don't set the class at all which means
1927 * they don't get their resources remapped. Fix that here.
1928 */
1929
1930 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1932 dev->class = PCI_CLASS_STORAGE_SCSI;
1933 }
1934}
1935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1936
1937/* Enable 1k I/O space granularity on the Intel P64H2 */
1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939{
1940 u16 en1k;
1941 u8 io_base_lo, io_limit_lo;
1942 unsigned long base, limit;
1943 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1944
1945 pci_read_config_word(dev, 0x40, &en1k);
1946
1947 if (en1k & 0x200) {
1948 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1949
1950 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1951 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1952 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1953 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1954
1955 if (base <= limit) {
1956 res->start = base;
1957 res->end = limit + 0x3ff;
1958 }
1959 }
1960}
1961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1962
1963/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1964 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1965 * in drivers/pci/setup-bus.c
1966 */
1967static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1968{
1969 u16 en1k, iobl_adr, iobl_adr_1k;
1970 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1971
1972 pci_read_config_word(dev, 0x40, &en1k);
1973
1974 if (en1k & 0x200) {
1975 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1976
1977 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1978
1979 if (iobl_adr != iobl_adr_1k) {
1980 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1981 iobl_adr,iobl_adr_1k);
1982 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1983 }
1984 }
1985}
1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1987
1988/* Under some circumstances, AER is not linked with extended capabilities.
1989 * Force it to be linked by setting the corresponding control bit in the
1990 * config space.
1991 */
1992static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1993{
1994 uint8_t b;
1995 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1996 if (!(b & 0x20)) {
1997 pci_write_config_byte(dev, 0xf41, b | 0x20);
1998 dev_info(&dev->dev,
1999 "Linking AER extended capability\n");
2000 }
2001 }
2002}
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2004 quirk_nvidia_ck804_pcie_aer_ext_cap);
2005DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2006 quirk_nvidia_ck804_pcie_aer_ext_cap);
2007
2008static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2009{
2010 /*
2011 * Disable PCI Bus Parking and PCI Master read caching on CX700
2012 * which causes unspecified timing errors with a VT6212L on the PCI
2013 * bus leading to USB2.0 packet loss.
2014 *
2015 * This quirk is only enabled if a second (on the external PCI bus)
2016 * VT6212L is found -- the CX700 core itself also contains a USB
2017 * host controller with the same PCI ID as the VT6212L.
2018 */
2019
2020 /* Count VT6212L instances */
2021 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2022 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2023 uint8_t b;
2024
2025 /* p should contain the first (internal) VT6212L -- see if we have
2026 an external one by searching again */
2027 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2028 if (!p)
2029 return;
2030 pci_dev_put(p);
2031
2032 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2033 if (b & 0x40) {
2034 /* Turn off PCI Bus Parking */
2035 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2036
2037 dev_info(&dev->dev,
2038 "Disabling VIA CX700 PCI parking\n");
2039 }
2040 }
2041
2042 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2043 if (b != 0) {
2044 /* Turn off PCI Master read caching */
2045 pci_write_config_byte(dev, 0x72, 0x0);
2046
2047 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2048 pci_write_config_byte(dev, 0x75, 0x1);
2049
2050 /* Disable "Read FIFO Timer" */
2051 pci_write_config_byte(dev, 0x77, 0x0);
2052
2053 dev_info(&dev->dev,
2054 "Disabling VIA CX700 PCI caching\n");
2055 }
2056 }
2057}
2058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2059
2060/*
2061 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2062 * VPD end tag will hang the device. This problem was initially
2063 * observed when a vpd entry was created in sysfs
2064 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2065 * will dump 32k of data. Reading a full 32k will cause an access
2066 * beyond the VPD end tag causing the device to hang. Once the device
2067 * is hung, the bnx2 driver will not be able to reset the device.
2068 * We believe that it is legal to read beyond the end tag and
2069 * therefore the solution is to limit the read/write length.
2070 */
2071static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2072{
2073 /*
2074 * Only disable the VPD capability for 5706, 5706S, 5708,
2075 * 5708S and 5709 rev. A
2076 */
2077 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2078 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2079 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2080 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2081 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2082 (dev->revision & 0xf0) == 0x0)) {
2083 if (dev->vpd)
2084 dev->vpd->len = 0x80;
2085 }
2086}
2087
2088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2089 PCI_DEVICE_ID_NX2_5706,
2090 quirk_brcm_570x_limit_vpd);
2091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2092 PCI_DEVICE_ID_NX2_5706S,
2093 quirk_brcm_570x_limit_vpd);
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2095 PCI_DEVICE_ID_NX2_5708,
2096 quirk_brcm_570x_limit_vpd);
2097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2098 PCI_DEVICE_ID_NX2_5708S,
2099 quirk_brcm_570x_limit_vpd);
2100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2101 PCI_DEVICE_ID_NX2_5709,
2102 quirk_brcm_570x_limit_vpd);
2103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2104 PCI_DEVICE_ID_NX2_5709S,
2105 quirk_brcm_570x_limit_vpd);
2106
2107static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2108{
2109 u32 rev;
2110
2111 pci_read_config_dword(dev, 0xf4, &rev);
2112
2113 /* Only CAP the MRRS if the device is a 5719 A0 */
2114 if (rev == 0x05719000) {
2115 int readrq = pcie_get_readrq(dev);
2116 if (readrq > 2048)
2117 pcie_set_readrq(dev, 2048);
2118 }
2119}
2120
2121DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2122 PCI_DEVICE_ID_TIGON3_5719,
2123 quirk_brcm_5719_limit_mrrs);
2124
2125/* Originally in EDAC sources for i82875P:
2126 * Intel tells BIOS developers to hide device 6 which
2127 * configures the overflow device access containing
2128 * the DRBs - this is where we expose device 6.
2129 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2130 */
2131static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2132{
2133 u8 reg;
2134
2135 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2136 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2137 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2138 }
2139}
2140
2141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2142 quirk_unhide_mch_dev6);
2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2144 quirk_unhide_mch_dev6);
2145
2146#ifdef CONFIG_TILE
2147/*
2148 * The Tilera TILEmpower platform needs to set the link speed
2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2151 * capability register of the PEX8624 PCIe switch. The switch
2152 * supports link speed auto negotiation, but falsely sets
2153 * the link speed to 5GT/s.
2154 */
2155static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2156{
2157 if (tile_plx_gen1) {
2158 pci_write_config_dword(dev, 0x98, 0x1);
2159 mdelay(50);
2160 }
2161}
2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2163#endif /* CONFIG_TILE */
2164
2165#ifdef CONFIG_PCI_MSI
2166/* Some chipsets do not support MSI. We cannot easily rely on setting
2167 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2168 * some other busses controlled by the chipset even if Linux is not
2169 * aware of it. Instead of setting the flag on all busses in the
2170 * machine, simply disable MSI globally.
2171 */
2172static void __init quirk_disable_all_msi(struct pci_dev *dev)
2173{
2174 pci_no_msi();
2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2176}
2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2183DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2184
2185/* Disable MSI on chipsets that are known to not support it */
2186static void __devinit quirk_disable_msi(struct pci_dev *dev)
2187{
2188 if (dev->subordinate) {
2189 dev_warn(&dev->dev, "MSI quirk detected; "
2190 "subordinate MSI disabled\n");
2191 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2192 }
2193}
2194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2197
2198/*
2199 * The APC bridge device in AMD 780 family northbridges has some random
2200 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2201 * we use the possible vendor/device IDs of the host bridge for the
2202 * declared quirk, and search for the APC bridge by slot number.
2203 */
2204static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2205{
2206 struct pci_dev *apc_bridge;
2207
2208 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2209 if (apc_bridge) {
2210 if (apc_bridge->device == 0x9602)
2211 quirk_disable_msi(apc_bridge);
2212 pci_dev_put(apc_bridge);
2213 }
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2217
2218/* Go through the list of Hypertransport capabilities and
2219 * return 1 if a HT MSI capability is found and enabled */
2220static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2221{
2222 int pos, ttl = 48;
2223
2224 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2225 while (pos && ttl--) {
2226 u8 flags;
2227
2228 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2229 &flags) == 0)
2230 {
2231 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2232 flags & HT_MSI_FLAGS_ENABLE ?
2233 "enabled" : "disabled");
2234 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2235 }
2236
2237 pos = pci_find_next_ht_capability(dev, pos,
2238 HT_CAPTYPE_MSI_MAPPING);
2239 }
2240 return 0;
2241}
2242
2243/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2244static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2245{
2246 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2247 dev_warn(&dev->dev, "MSI quirk detected; "
2248 "subordinate MSI disabled\n");
2249 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2250 }
2251}
2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2253 quirk_msi_ht_cap);
2254
2255/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2256 * MSI are supported if the MSI capability set in any of these mappings.
2257 */
2258static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2259{
2260 struct pci_dev *pdev;
2261
2262 if (!dev->subordinate)
2263 return;
2264
2265 /* check HT MSI cap on this chipset and the root one.
2266 * a single one having MSI is enough to be sure that MSI are supported.
2267 */
2268 pdev = pci_get_slot(dev->bus, 0);
2269 if (!pdev)
2270 return;
2271 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2272 dev_warn(&dev->dev, "MSI quirk detected; "
2273 "subordinate MSI disabled\n");
2274 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2275 }
2276 pci_dev_put(pdev);
2277}
2278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2279 quirk_nvidia_ck804_msi_ht_cap);
2280
2281/* Force enable MSI mapping capability on HT bridges */
2282static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2283{
2284 int pos, ttl = 48;
2285
2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2287 while (pos && ttl--) {
2288 u8 flags;
2289
2290 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2291 &flags) == 0) {
2292 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2293
2294 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2295 flags | HT_MSI_FLAGS_ENABLE);
2296 }
2297 pos = pci_find_next_ht_capability(dev, pos,
2298 HT_CAPTYPE_MSI_MAPPING);
2299 }
2300}
2301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2302 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2303 ht_enable_msi_mapping);
2304
2305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2306 ht_enable_msi_mapping);
2307
2308/* The P5N32-SLI motherboards from Asus have a problem with msi
2309 * for the MCP55 NIC. It is not yet determined whether the msi problem
2310 * also affects other devices. As for now, turn off msi for this device.
2311 */
2312static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2313{
2314 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2315
2316 if (board_name &&
2317 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2318 strstr(board_name, "P5N32-E SLI"))) {
2319 dev_info(&dev->dev,
2320 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2321 dev->no_msi = 1;
2322 }
2323}
2324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2325 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2326 nvenet_msi_disable);
2327
2328/*
2329 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2330 * config register. This register controls the routing of legacy interrupts
2331 * from devices that route through the MCP55. If this register is misprogramed
2332 * interrupts are only sent to the bsp, unlike conventional systems where the
2333 * irq is broadxast to all online cpus. Not having this register set
2334 * properly prevents kdump from booting up properly, so lets make sure that
2335 * we have it set correctly.
2336 * Note this is an undocumented register.
2337 */
2338static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2339{
2340 u32 cfg;
2341
2342 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2343 return;
2344
2345 pci_read_config_dword(dev, 0x74, &cfg);
2346
2347 if (cfg & ((1 << 2) | (1 << 15))) {
2348 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2349 cfg &= ~((1 << 2) | (1 << 15));
2350 pci_write_config_dword(dev, 0x74, cfg);
2351 }
2352}
2353
2354DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2355 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2356 nvbridge_check_legacy_irq_routing);
2357
2358DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2359 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2360 nvbridge_check_legacy_irq_routing);
2361
2362static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2363{
2364 int pos, ttl = 48;
2365 int found = 0;
2366
2367 /* check if there is HT MSI cap or enabled on this device */
2368 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2369 while (pos && ttl--) {
2370 u8 flags;
2371
2372 if (found < 1)
2373 found = 1;
2374 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2375 &flags) == 0) {
2376 if (flags & HT_MSI_FLAGS_ENABLE) {
2377 if (found < 2) {
2378 found = 2;
2379 break;
2380 }
2381 }
2382 }
2383 pos = pci_find_next_ht_capability(dev, pos,
2384 HT_CAPTYPE_MSI_MAPPING);
2385 }
2386
2387 return found;
2388}
2389
2390static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2391{
2392 struct pci_dev *dev;
2393 int pos;
2394 int i, dev_no;
2395 int found = 0;
2396
2397 dev_no = host_bridge->devfn >> 3;
2398 for (i = dev_no + 1; i < 0x20; i++) {
2399 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2400 if (!dev)
2401 continue;
2402
2403 /* found next host bridge ?*/
2404 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2405 if (pos != 0) {
2406 pci_dev_put(dev);
2407 break;
2408 }
2409
2410 if (ht_check_msi_mapping(dev)) {
2411 found = 1;
2412 pci_dev_put(dev);
2413 break;
2414 }
2415 pci_dev_put(dev);
2416 }
2417
2418 return found;
2419}
2420
2421#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2422#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2423
2424static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2425{
2426 int pos, ctrl_off;
2427 int end = 0;
2428 u16 flags, ctrl;
2429
2430 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2431
2432 if (!pos)
2433 goto out;
2434
2435 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2436
2437 ctrl_off = ((flags >> 10) & 1) ?
2438 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2439 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2440
2441 if (ctrl & (1 << 6))
2442 end = 1;
2443
2444out:
2445 return end;
2446}
2447
2448static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2449{
2450 struct pci_dev *host_bridge;
2451 int pos;
2452 int i, dev_no;
2453 int found = 0;
2454
2455 dev_no = dev->devfn >> 3;
2456 for (i = dev_no; i >= 0; i--) {
2457 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2458 if (!host_bridge)
2459 continue;
2460
2461 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2462 if (pos != 0) {
2463 found = 1;
2464 break;
2465 }
2466 pci_dev_put(host_bridge);
2467 }
2468
2469 if (!found)
2470 return;
2471
2472 /* don't enable end_device/host_bridge with leaf directly here */
2473 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2474 host_bridge_with_leaf(host_bridge))
2475 goto out;
2476
2477 /* root did that ! */
2478 if (msi_ht_cap_enabled(host_bridge))
2479 goto out;
2480
2481 ht_enable_msi_mapping(dev);
2482
2483out:
2484 pci_dev_put(host_bridge);
2485}
2486
2487static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2488{
2489 int pos, ttl = 48;
2490
2491 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2492 while (pos && ttl--) {
2493 u8 flags;
2494
2495 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2496 &flags) == 0) {
2497 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2498
2499 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2500 flags & ~HT_MSI_FLAGS_ENABLE);
2501 }
2502 pos = pci_find_next_ht_capability(dev, pos,
2503 HT_CAPTYPE_MSI_MAPPING);
2504 }
2505}
2506
2507static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2508{
2509 struct pci_dev *host_bridge;
2510 int pos;
2511 int found;
2512
2513 if (!pci_msi_enabled())
2514 return;
2515
2516 /* check if there is HT MSI cap or enabled on this device */
2517 found = ht_check_msi_mapping(dev);
2518
2519 /* no HT MSI CAP */
2520 if (found == 0)
2521 return;
2522
2523 /*
2524 * HT MSI mapping should be disabled on devices that are below
2525 * a non-Hypertransport host bridge. Locate the host bridge...
2526 */
2527 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2528 if (host_bridge == NULL) {
2529 dev_warn(&dev->dev,
2530 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2531 return;
2532 }
2533
2534 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2535 if (pos != 0) {
2536 /* Host bridge is to HT */
2537 if (found == 1) {
2538 /* it is not enabled, try to enable it */
2539 if (all)
2540 ht_enable_msi_mapping(dev);
2541 else
2542 nv_ht_enable_msi_mapping(dev);
2543 }
2544 return;
2545 }
2546
2547 /* HT MSI is not enabled */
2548 if (found == 1)
2549 return;
2550
2551 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2552 ht_disable_msi_mapping(dev);
2553}
2554
2555static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2556{
2557 return __nv_msi_ht_cap_quirk(dev, 1);
2558}
2559
2560static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2561{
2562 return __nv_msi_ht_cap_quirk(dev, 0);
2563}
2564
2565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2566DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2567
2568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2570
2571static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2572{
2573 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2574}
2575static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2576{
2577 struct pci_dev *p;
2578
2579 /* SB700 MSI issue will be fixed at HW level from revision A21,
2580 * we need check PCI REVISION ID of SMBus controller to get SB700
2581 * revision.
2582 */
2583 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2584 NULL);
2585 if (!p)
2586 return;
2587
2588 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2589 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2590 pci_dev_put(p);
2591}
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2593 PCI_DEVICE_ID_TIGON3_5780,
2594 quirk_msi_intx_disable_bug);
2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2596 PCI_DEVICE_ID_TIGON3_5780S,
2597 quirk_msi_intx_disable_bug);
2598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2599 PCI_DEVICE_ID_TIGON3_5714,
2600 quirk_msi_intx_disable_bug);
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2602 PCI_DEVICE_ID_TIGON3_5714S,
2603 quirk_msi_intx_disable_bug);
2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2605 PCI_DEVICE_ID_TIGON3_5715,
2606 quirk_msi_intx_disable_bug);
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2608 PCI_DEVICE_ID_TIGON3_5715S,
2609 quirk_msi_intx_disable_bug);
2610
2611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2612 quirk_msi_intx_disable_ati_bug);
2613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2614 quirk_msi_intx_disable_ati_bug);
2615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2616 quirk_msi_intx_disable_ati_bug);
2617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2618 quirk_msi_intx_disable_ati_bug);
2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2620 quirk_msi_intx_disable_ati_bug);
2621
2622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2623 quirk_msi_intx_disable_bug);
2624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2625 quirk_msi_intx_disable_bug);
2626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2627 quirk_msi_intx_disable_bug);
2628
2629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2630 quirk_msi_intx_disable_bug);
2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2632 quirk_msi_intx_disable_bug);
2633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2634 quirk_msi_intx_disable_bug);
2635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2636 quirk_msi_intx_disable_bug);
2637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2640 quirk_msi_intx_disable_bug);
2641#endif /* CONFIG_PCI_MSI */
2642
2643/* Allow manual resource allocation for PCI hotplug bridges
2644 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2645 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2646 * kernel fails to allocate resources when hotplug device is
2647 * inserted and PCI bus is rescanned.
2648 */
2649static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2650{
2651 dev->is_hotplug_bridge = 1;
2652}
2653
2654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2655
2656/*
2657 * This is a quirk for the Ricoh MMC controller found as a part of
2658 * some mulifunction chips.
2659
2660 * This is very similar and based on the ricoh_mmc driver written by
2661 * Philip Langdale. Thank you for these magic sequences.
2662 *
2663 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2664 * and one or both of cardbus or firewire.
2665 *
2666 * It happens that they implement SD and MMC
2667 * support as separate controllers (and PCI functions). The linux SDHCI
2668 * driver supports MMC cards but the chip detects MMC cards in hardware
2669 * and directs them to the MMC controller - so the SDHCI driver never sees
2670 * them.
2671 *
2672 * To get around this, we must disable the useless MMC controller.
2673 * At that point, the SDHCI controller will start seeing them
2674 * It seems to be the case that the relevant PCI registers to deactivate the
2675 * MMC controller live on PCI function 0, which might be the cardbus controller
2676 * or the firewire controller, depending on the particular chip in question
2677 *
2678 * This has to be done early, because as soon as we disable the MMC controller
2679 * other pci functions shift up one level, e.g. function #2 becomes function
2680 * #1, and this will confuse the pci core.
2681 */
2682
2683#ifdef CONFIG_MMC_RICOH_MMC
2684static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2685{
2686 /* disable via cardbus interface */
2687 u8 write_enable;
2688 u8 write_target;
2689 u8 disable;
2690
2691 /* disable must be done via function #0 */
2692 if (PCI_FUNC(dev->devfn))
2693 return;
2694
2695 pci_read_config_byte(dev, 0xB7, &disable);
2696 if (disable & 0x02)
2697 return;
2698
2699 pci_read_config_byte(dev, 0x8E, &write_enable);
2700 pci_write_config_byte(dev, 0x8E, 0xAA);
2701 pci_read_config_byte(dev, 0x8D, &write_target);
2702 pci_write_config_byte(dev, 0x8D, 0xB7);
2703 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2704 pci_write_config_byte(dev, 0x8E, write_enable);
2705 pci_write_config_byte(dev, 0x8D, write_target);
2706
2707 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2708 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2709}
2710DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2711DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2712
2713static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2714{
2715 /* disable via firewire interface */
2716 u8 write_enable;
2717 u8 disable;
2718
2719 /* disable must be done via function #0 */
2720 if (PCI_FUNC(dev->devfn))
2721 return;
2722 /*
2723 * RICOH 0xe823 SD/MMC card reader fails to recognize
2724 * certain types of SD/MMC cards. Lowering the SD base
2725 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2726 *
2727 * 0x150 - SD2.0 mode enable for changing base clock
2728 * frequency to 50Mhz
2729 * 0xe1 - Base clock frequency
2730 * 0x32 - 50Mhz new clock frequency
2731 * 0xf9 - Key register for 0x150
2732 * 0xfc - key register for 0xe1
2733 */
2734 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2735 pci_write_config_byte(dev, 0xf9, 0xfc);
2736 pci_write_config_byte(dev, 0x150, 0x10);
2737 pci_write_config_byte(dev, 0xf9, 0x00);
2738 pci_write_config_byte(dev, 0xfc, 0x01);
2739 pci_write_config_byte(dev, 0xe1, 0x32);
2740 pci_write_config_byte(dev, 0xfc, 0x00);
2741
2742 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2743 }
2744
2745 pci_read_config_byte(dev, 0xCB, &disable);
2746
2747 if (disable & 0x02)
2748 return;
2749
2750 pci_read_config_byte(dev, 0xCA, &write_enable);
2751 pci_write_config_byte(dev, 0xCA, 0x57);
2752 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2753 pci_write_config_byte(dev, 0xCA, write_enable);
2754
2755 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2756 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2757
2758}
2759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2762DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2763#endif /*CONFIG_MMC_RICOH_MMC*/
2764
2765#ifdef CONFIG_DMAR_TABLE
2766#define VTUNCERRMSK_REG 0x1ac
2767#define VTD_MSK_SPEC_ERRORS (1 << 31)
2768/*
2769 * This is a quirk for masking vt-d spec defined errors to platform error
2770 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2771 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2772 * on the RAS config settings of the platform) when a vt-d fault happens.
2773 * The resulting SMI caused the system to hang.
2774 *
2775 * VT-d spec related errors are already handled by the VT-d OS code, so no
2776 * need to report the same error through other channels.
2777 */
2778static void vtd_mask_spec_errors(struct pci_dev *dev)
2779{
2780 u32 word;
2781
2782 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2783 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2784}
2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2786DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2787#endif
2788
2789static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2790{
2791 /* TI 816x devices do not have class code set when in PCIe boot mode */
2792 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2793 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2794}
2795DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2796 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2797
2798/* Some PCIe devices do not work reliably with the claimed maximum
2799 * payload size supported.
2800 */
2801static void __devinit fixup_mpss_256(struct pci_dev *dev)
2802{
2803 dev->pcie_mpss = 1; /* 256 bytes */
2804}
2805DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2806 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2807DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2808 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2809DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2810 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2811
2812/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2813 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2814 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2815 * until all of the devices are discovered and buses walked, read completion
2816 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2817 * it is possible to hotplug a device with MPS of 256B.
2818 */
2819static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2820{
2821 int err;
2822 u16 rcc;
2823
2824 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2825 return;
2826
2827 /* Intel errata specifies bits to change but does not say what they are.
2828 * Keeping them magical until such time as the registers and values can
2829 * be explained.
2830 */
2831 err = pci_read_config_word(dev, 0x48, &rcc);
2832 if (err) {
2833 dev_err(&dev->dev, "Error attempting to read the read "
2834 "completion coalescing register.\n");
2835 return;
2836 }
2837
2838 if (!(rcc & (1 << 10)))
2839 return;
2840
2841 rcc &= ~(1 << 10);
2842
2843 err = pci_write_config_word(dev, 0x48, rcc);
2844 if (err) {
2845 dev_err(&dev->dev, "Error attempting to write the read "
2846 "completion coalescing register.\n");
2847 return;
2848 }
2849
2850 pr_info_once("Read completion coalescing disabled due to hardware "
2851 "errata relating to 256B MPS.\n");
2852}
2853/* Intel 5000 series memory controllers and ports 2-7 */
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2868/* Intel 5100 series memory controllers and ports 2-7 */
2869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2877DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2880
2881
2882static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev)
2883{
2884 ktime_t calltime, delta, rettime;
2885 unsigned long long duration;
2886
2887 printk(KERN_DEBUG "calling %pF @ %i for %s\n",
2888 fn, task_pid_nr(current), dev_name(&dev->dev));
2889 calltime = ktime_get();
2890 fn(dev);
2891 rettime = ktime_get();
2892 delta = ktime_sub(rettime, calltime);
2893 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2894 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n",
2895 fn, duration, dev_name(&dev->dev));
2896}
2897
2898/*
2899 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2900 * even though no one is handling them (f.e. i915 driver is never loaded).
2901 * Additionally the interrupt destination is not set up properly
2902 * and the interrupt ends up -somewhere-.
2903 *
2904 * These spurious interrupts are "sticky" and the kernel disables
2905 * the (shared) interrupt line after 100.000+ generated interrupts.
2906 *
2907 * Fix it by disabling the still enabled interrupts.
2908 * This resolves crashes often seen on monitor unplug.
2909 */
2910#define I915_DEIER_REG 0x4400c
2911static void __devinit disable_igfx_irq(struct pci_dev *dev)
2912{
2913 void __iomem *regs = pci_iomap(dev, 0, 0);
2914 if (regs == NULL) {
2915 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2916 return;
2917 }
2918
2919 /* Check if any interrupt line is still enabled */
2920 if (readl(regs + I915_DEIER_REG) != 0) {
2921 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2922 "disabling\n");
2923
2924 writel(0, regs + I915_DEIER_REG);
2925 }
2926
2927 pci_iounmap(dev, regs);
2928}
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931
2932static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2933 struct pci_fixup *end)
2934{
2935 for (; f < end; f++)
2936 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2937 f->class == (u32) PCI_ANY_ID) &&
2938 (f->vendor == dev->vendor ||
2939 f->vendor == (u16) PCI_ANY_ID) &&
2940 (f->device == dev->device ||
2941 f->device == (u16) PCI_ANY_ID)) {
2942 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2943 if (initcall_debug)
2944 do_one_fixup_debug(f->hook, dev);
2945 else
2946 f->hook(dev);
2947 }
2948}
2949
2950extern struct pci_fixup __start_pci_fixups_early[];
2951extern struct pci_fixup __end_pci_fixups_early[];
2952extern struct pci_fixup __start_pci_fixups_header[];
2953extern struct pci_fixup __end_pci_fixups_header[];
2954extern struct pci_fixup __start_pci_fixups_final[];
2955extern struct pci_fixup __end_pci_fixups_final[];
2956extern struct pci_fixup __start_pci_fixups_enable[];
2957extern struct pci_fixup __end_pci_fixups_enable[];
2958extern struct pci_fixup __start_pci_fixups_resume[];
2959extern struct pci_fixup __end_pci_fixups_resume[];
2960extern struct pci_fixup __start_pci_fixups_resume_early[];
2961extern struct pci_fixup __end_pci_fixups_resume_early[];
2962extern struct pci_fixup __start_pci_fixups_suspend[];
2963extern struct pci_fixup __end_pci_fixups_suspend[];
2964
2965
2966void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2967{
2968 struct pci_fixup *start, *end;
2969
2970 switch(pass) {
2971 case pci_fixup_early:
2972 start = __start_pci_fixups_early;
2973 end = __end_pci_fixups_early;
2974 break;
2975
2976 case pci_fixup_header:
2977 start = __start_pci_fixups_header;
2978 end = __end_pci_fixups_header;
2979 break;
2980
2981 case pci_fixup_final:
2982 start = __start_pci_fixups_final;
2983 end = __end_pci_fixups_final;
2984 break;
2985
2986 case pci_fixup_enable:
2987 start = __start_pci_fixups_enable;
2988 end = __end_pci_fixups_enable;
2989 break;
2990
2991 case pci_fixup_resume:
2992 start = __start_pci_fixups_resume;
2993 end = __end_pci_fixups_resume;
2994 break;
2995
2996 case pci_fixup_resume_early:
2997 start = __start_pci_fixups_resume_early;
2998 end = __end_pci_fixups_resume_early;
2999 break;
3000
3001 case pci_fixup_suspend:
3002 start = __start_pci_fixups_suspend;
3003 end = __end_pci_fixups_suspend;
3004 break;
3005
3006 default:
3007 /* stupid compiler warning, you would think with an enum... */
3008 return;
3009 }
3010 pci_do_fixups(dev, start, end);
3011}
3012EXPORT_SYMBOL(pci_fixup_device);
3013
3014static int __init pci_apply_final_quirks(void)
3015{
3016 struct pci_dev *dev = NULL;
3017 u8 cls = 0;
3018 u8 tmp;
3019
3020 if (pci_cache_line_size)
3021 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3022 pci_cache_line_size << 2);
3023
3024 for_each_pci_dev(dev) {
3025 pci_fixup_device(pci_fixup_final, dev);
3026 /*
3027 * If arch hasn't set it explicitly yet, use the CLS
3028 * value shared by all PCI devices. If there's a
3029 * mismatch, fall back to the default value.
3030 */
3031 if (!pci_cache_line_size) {
3032 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3033 if (!cls)
3034 cls = tmp;
3035 if (!tmp || cls == tmp)
3036 continue;
3037
3038 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3039 "using %u bytes\n", cls << 2, tmp << 2,
3040 pci_dfl_cache_line_size << 2);
3041 pci_cache_line_size = pci_dfl_cache_line_size;
3042 }
3043 }
3044 if (!pci_cache_line_size) {
3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046 cls << 2, pci_dfl_cache_line_size << 2);
3047 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3048 }
3049
3050 return 0;
3051}
3052
3053fs_initcall_sync(pci_apply_final_quirks);
3054
3055/*
3056 * Followings are device-specific reset methods which can be used to
3057 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3058 * not available.
3059 */
3060static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3061{
3062 int pos;
3063
3064 /* only implement PCI_CLASS_SERIAL_USB at present */
3065 if (dev->class == PCI_CLASS_SERIAL_USB) {
3066 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3067 if (!pos)
3068 return -ENOTTY;
3069
3070 if (probe)
3071 return 0;
3072
3073 pci_write_config_byte(dev, pos + 0x4, 1);
3074 msleep(100);
3075
3076 return 0;
3077 } else {
3078 return -ENOTTY;
3079 }
3080}
3081
3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3083{
3084 int pos;
3085
3086 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3087 if (!pos)
3088 return -ENOTTY;
3089
3090 if (probe)
3091 return 0;
3092
3093 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3094 PCI_EXP_DEVCTL_BCR_FLR);
3095 msleep(100);
3096
3097 return 0;
3098}
3099
3100#include "../gpu/drm/i915/i915_reg.h"
3101#define MSG_CTL 0x45010
3102#define NSDE_PWR_STATE 0xd0100
3103#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3104
3105static int reset_ivb_igd(struct pci_dev *dev, int probe)
3106{
3107 void __iomem *mmio_base;
3108 unsigned long timeout;
3109 u32 val;
3110
3111 if (probe)
3112 return 0;
3113
3114 mmio_base = pci_iomap(dev, 0, 0);
3115 if (!mmio_base)
3116 return -ENOMEM;
3117
3118 iowrite32(0x00000002, mmio_base + MSG_CTL);
3119
3120 /*
3121 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3122 * driver loaded sets the right bits. However, this's a reset and
3123 * the bits have been set by i915 previously, so we clobber
3124 * SOUTH_CHICKEN2 register directly here.
3125 */
3126 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3127
3128 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3129 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3130
3131 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3132 do {
3133 val = ioread32(mmio_base + PCH_PP_STATUS);
3134 if ((val & 0xb0000000) == 0)
3135 goto reset_complete;
3136 msleep(10);
3137 } while (time_before(jiffies, timeout));
3138 dev_warn(&dev->dev, "timeout during reset\n");
3139
3140reset_complete:
3141 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3142
3143 pci_iounmap(dev, mmio_base);
3144 return 0;
3145}
3146
3147#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3148#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3149#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3150
3151static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3152 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3153 reset_intel_82599_sfp_virtfn },
3154 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3155 reset_ivb_igd },
3156 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3157 reset_ivb_igd },
3158 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3159 reset_intel_generic_dev },
3160 { 0 }
3161};
3162
3163/*
3164 * These device-specific reset methods are here rather than in a driver
3165 * because when a host assigns a device to a guest VM, the host may need
3166 * to reset the device but probably doesn't have a driver for it.
3167 */
3168int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3169{
3170 const struct pci_dev_reset_methods *i;
3171
3172 for (i = pci_dev_reset_methods; i->reset; i++) {
3173 if ((i->vendor == dev->vendor ||
3174 i->vendor == (u16)PCI_ANY_ID) &&
3175 (i->device == dev->device ||
3176 i->device == (u16)PCI_ANY_ID))
3177 return i->reset(dev, probe);
3178 }
3179
3180 return -ENOTTY;
3181}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/acpi.h>
22#include <linux/dmi.h>
23#include <linux/ioport.h>
24#include <linux/sched.h>
25#include <linux/ktime.h>
26#include <linux/mm.h>
27#include <linux/nvme.h>
28#include <linux/platform_data/x86/apple.h>
29#include <linux/pm_runtime.h>
30#include <linux/switchtec.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h"
33
34static ktime_t fixup_debug_start(struct pci_dev *dev,
35 void (*fn)(struct pci_dev *dev))
36{
37 if (initcall_debug)
38 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
39
40 return ktime_get();
41}
42
43static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
44 void (*fn)(struct pci_dev *dev))
45{
46 ktime_t delta, rettime;
47 unsigned long long duration;
48
49 rettime = ktime_get();
50 delta = ktime_sub(rettime, calltime);
51 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
52 if (initcall_debug || duration > 10000)
53 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
54}
55
56static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
57 struct pci_fixup *end)
58{
59 ktime_t calltime;
60
61 for (; f < end; f++)
62 if ((f->class == (u32) (dev->class >> f->class_shift) ||
63 f->class == (u32) PCI_ANY_ID) &&
64 (f->vendor == dev->vendor ||
65 f->vendor == (u16) PCI_ANY_ID) &&
66 (f->device == dev->device ||
67 f->device == (u16) PCI_ANY_ID)) {
68 void (*hook)(struct pci_dev *dev);
69#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 hook = offset_to_ptr(&f->hook_offset);
71#else
72 hook = f->hook;
73#endif
74 calltime = fixup_debug_start(dev, hook);
75 hook(dev);
76 fixup_debug_report(dev, calltime, hook);
77 }
78}
79
80extern struct pci_fixup __start_pci_fixups_early[];
81extern struct pci_fixup __end_pci_fixups_early[];
82extern struct pci_fixup __start_pci_fixups_header[];
83extern struct pci_fixup __end_pci_fixups_header[];
84extern struct pci_fixup __start_pci_fixups_final[];
85extern struct pci_fixup __end_pci_fixups_final[];
86extern struct pci_fixup __start_pci_fixups_enable[];
87extern struct pci_fixup __end_pci_fixups_enable[];
88extern struct pci_fixup __start_pci_fixups_resume[];
89extern struct pci_fixup __end_pci_fixups_resume[];
90extern struct pci_fixup __start_pci_fixups_resume_early[];
91extern struct pci_fixup __end_pci_fixups_resume_early[];
92extern struct pci_fixup __start_pci_fixups_suspend[];
93extern struct pci_fixup __end_pci_fixups_suspend[];
94extern struct pci_fixup __start_pci_fixups_suspend_late[];
95extern struct pci_fixup __end_pci_fixups_suspend_late[];
96
97static bool pci_apply_fixup_final_quirks;
98
99void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
100{
101 struct pci_fixup *start, *end;
102
103 switch (pass) {
104 case pci_fixup_early:
105 start = __start_pci_fixups_early;
106 end = __end_pci_fixups_early;
107 break;
108
109 case pci_fixup_header:
110 start = __start_pci_fixups_header;
111 end = __end_pci_fixups_header;
112 break;
113
114 case pci_fixup_final:
115 if (!pci_apply_fixup_final_quirks)
116 return;
117 start = __start_pci_fixups_final;
118 end = __end_pci_fixups_final;
119 break;
120
121 case pci_fixup_enable:
122 start = __start_pci_fixups_enable;
123 end = __end_pci_fixups_enable;
124 break;
125
126 case pci_fixup_resume:
127 start = __start_pci_fixups_resume;
128 end = __end_pci_fixups_resume;
129 break;
130
131 case pci_fixup_resume_early:
132 start = __start_pci_fixups_resume_early;
133 end = __end_pci_fixups_resume_early;
134 break;
135
136 case pci_fixup_suspend:
137 start = __start_pci_fixups_suspend;
138 end = __end_pci_fixups_suspend;
139 break;
140
141 case pci_fixup_suspend_late:
142 start = __start_pci_fixups_suspend_late;
143 end = __end_pci_fixups_suspend_late;
144 break;
145
146 default:
147 /* stupid compiler warning, you would think with an enum... */
148 return;
149 }
150 pci_do_fixups(dev, start, end);
151}
152EXPORT_SYMBOL(pci_fixup_device);
153
154static int __init pci_apply_final_quirks(void)
155{
156 struct pci_dev *dev = NULL;
157 u8 cls = 0;
158 u8 tmp;
159
160 if (pci_cache_line_size)
161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
162
163 pci_apply_fixup_final_quirks = true;
164 for_each_pci_dev(dev) {
165 pci_fixup_device(pci_fixup_final, dev);
166 /*
167 * If arch hasn't set it explicitly yet, use the CLS
168 * value shared by all PCI devices. If there's a
169 * mismatch, fall back to the default value.
170 */
171 if (!pci_cache_line_size) {
172 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
173 if (!cls)
174 cls = tmp;
175 if (!tmp || cls == tmp)
176 continue;
177
178 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
179 cls << 2, tmp << 2,
180 pci_dfl_cache_line_size << 2);
181 pci_cache_line_size = pci_dfl_cache_line_size;
182 }
183 }
184
185 if (!pci_cache_line_size) {
186 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
187 pci_dfl_cache_line_size << 2);
188 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
189 }
190
191 return 0;
192}
193fs_initcall_sync(pci_apply_final_quirks);
194
195/*
196 * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 * conflict. But doing so may cause problems on host bridge and perhaps other
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
200 */
201static void quirk_mmio_always_on(struct pci_dev *dev)
202{
203 dev->mmio_always_on = 1;
204}
205DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
207
208/*
209 * The Mellanox Tavor device gives false positive parity errors. Mark this
210 * device with a broken_parity_status to allow PCI scanning code to "skip"
211 * this now blacklisted device.
212 */
213static void quirk_mellanox_tavor(struct pci_dev *dev)
214{
215 dev->broken_parity_status = 1; /* This device gives false positives */
216}
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
219
220/*
221 * Deal with broken BIOSes that neglect to enable passive release,
222 * which can cause problems in combination with the 82441FX/PPro MTRRs
223 */
224static void quirk_passive_release(struct pci_dev *dev)
225{
226 struct pci_dev *d = NULL;
227 unsigned char dlc;
228
229 /*
230 * We have to make sure a particular bit is set in the PIIX3
231 * ISA bridge, so we have to go out and find it.
232 */
233 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
234 pci_read_config_byte(d, 0x82, &dlc);
235 if (!(dlc & 1<<1)) {
236 pci_info(d, "PIIX3: Enabling Passive Release\n");
237 dlc |= 1<<1;
238 pci_write_config_byte(d, 0x82, dlc);
239 }
240 }
241}
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
243DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
244
245/*
246 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
247 * workaround but VIA don't answer queries. If you happen to have good
248 * contacts at VIA ask them for me please -- Alan
249 *
250 * This appears to be BIOS not version dependent. So presumably there is a
251 * chipset level fix.
252 */
253static void quirk_isa_dma_hangs(struct pci_dev *dev)
254{
255 if (!isa_dma_bridge_buggy) {
256 isa_dma_bridge_buggy = 1;
257 pci_info(dev, "Activating ISA DMA hang workarounds\n");
258 }
259}
260/*
261 * It's not totally clear which chipsets are the problematic ones. We know
262 * 82C586 and 82C596 variants are affected.
263 */
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
267DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
268DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
271
272/*
273 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
274 * for some HT machines to use C4 w/o hanging.
275 */
276static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
277{
278 u32 pmbase;
279 u16 pm1a;
280
281 pci_read_config_dword(dev, 0x40, &pmbase);
282 pmbase = pmbase & 0xff80;
283 pm1a = inw(pmbase);
284
285 if (pm1a & 0x10) {
286 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
287 outw(0x10, pmbase);
288 }
289}
290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
291
292/* Chipsets where PCI->PCI transfers vanish or hang */
293static void quirk_nopcipci(struct pci_dev *dev)
294{
295 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
296 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
297 pci_pci_problems |= PCIPCI_FAIL;
298 }
299}
300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
302
303static void quirk_nopciamd(struct pci_dev *dev)
304{
305 u8 rev;
306 pci_read_config_byte(dev, 0x08, &rev);
307 if (rev == 0x13) {
308 /* Erratum 24 */
309 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
310 pci_pci_problems |= PCIAGP_FAIL;
311 }
312}
313DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
314
315/* Triton requires workarounds to be used by the drivers */
316static void quirk_triton(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
319 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_TRITON;
321 }
322}
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
327
328/*
329 * VIA Apollo KT133 needs PCI latency patch
330 * Made according to a Windows driver-based patch by George E. Breese;
331 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
332 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
333 * which Mr Breese based his work.
334 *
335 * Updated based on further information from the site and also on
336 * information provided by VIA
337 */
338static void quirk_vialatency(struct pci_dev *dev)
339{
340 struct pci_dev *p;
341 u8 busarb;
342
343 /*
344 * Ok, we have a potential problem chipset here. Now see if we have
345 * a buggy southbridge.
346 */
347 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
348 if (p != NULL) {
349
350 /*
351 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
352 * thanks Dan Hollis.
353 * Check for buggy part revisions
354 */
355 if (p->revision < 0x40 || p->revision > 0x42)
356 goto exit;
357 } else {
358 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
359 if (p == NULL) /* No problem parts */
360 goto exit;
361
362 /* Check for buggy part revisions */
363 if (p->revision < 0x10 || p->revision > 0x12)
364 goto exit;
365 }
366
367 /*
368 * Ok we have the problem. Now set the PCI master grant to occur
369 * every master grant. The apparent bug is that under high PCI load
370 * (quite common in Linux of course) you can get data loss when the
371 * CPU is held off the bus for 3 bus master requests. This happens
372 * to include the IDE controllers....
373 *
374 * VIA only apply this fix when an SB Live! is present but under
375 * both Linux and Windows this isn't enough, and we have seen
376 * corruption without SB Live! but with things like 3 UDMA IDE
377 * controllers. So we ignore that bit of the VIA recommendation..
378 */
379 pci_read_config_byte(dev, 0x76, &busarb);
380
381 /*
382 * Set bit 4 and bit 5 of byte 76 to 0x01
383 * "Master priority rotation on every PCI master grant"
384 */
385 busarb &= ~(1<<5);
386 busarb |= (1<<4);
387 pci_write_config_byte(dev, 0x76, busarb);
388 pci_info(dev, "Applying VIA southbridge workaround\n");
389exit:
390 pci_dev_put(p);
391}
392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395/* Must restore this on a resume from RAM */
396DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
397DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
398DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
399
400/* VIA Apollo VP3 needs ETBF on BT848/878 */
401static void quirk_viaetbf(struct pci_dev *dev)
402{
403 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
404 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
405 pci_pci_problems |= PCIPCI_VIAETBF;
406 }
407}
408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
409
410static void quirk_vsfx(struct pci_dev *dev)
411{
412 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
413 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 pci_pci_problems |= PCIPCI_VSFX;
415 }
416}
417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
418
419/*
420 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
421 * space. Latency must be set to 0xA and Triton workaround applied too.
422 * [Info kindly provided by ALi]
423 */
424static void quirk_alimagik(struct pci_dev *dev)
425{
426 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
427 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
428 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
429 }
430}
431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
433
434/* Natoma has some interesting boundary conditions with Zoran stuff at least */
435static void quirk_natoma(struct pci_dev *dev)
436{
437 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
438 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
439 pci_pci_problems |= PCIPCI_NATOMA;
440 }
441}
442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
448
449/*
450 * This chip can cause PCI parity errors if config register 0xA0 is read
451 * while DMAs are occurring.
452 */
453static void quirk_citrine(struct pci_dev *dev)
454{
455 dev->cfg_size = 0xA0;
456}
457DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
458
459/*
460 * This chip can cause bus lockups if config addresses above 0x600
461 * are read or written.
462 */
463static void quirk_nfp6000(struct pci_dev *dev)
464{
465 dev->cfg_size = 0x600;
466}
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
471
472/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
473static void quirk_extend_bar_to_page(struct pci_dev *dev)
474{
475 int i;
476
477 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
478 struct resource *r = &dev->resource[i];
479
480 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
481 r->end = PAGE_SIZE - 1;
482 r->start = 0;
483 r->flags |= IORESOURCE_UNSET;
484 pci_info(dev, "expanded BAR %d to page size: %pR\n",
485 i, r);
486 }
487 }
488}
489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
490
491/*
492 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
493 * If it's needed, re-allocate the region.
494 */
495static void quirk_s3_64M(struct pci_dev *dev)
496{
497 struct resource *r = &dev->resource[0];
498
499 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
500 r->flags |= IORESOURCE_UNSET;
501 r->start = 0;
502 r->end = 0x3ffffff;
503 }
504}
505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
507
508static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
509 const char *name)
510{
511 u32 region;
512 struct pci_bus_region bus_region;
513 struct resource *res = dev->resource + pos;
514
515 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
516
517 if (!region)
518 return;
519
520 res->name = pci_name(dev);
521 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
522 res->flags |=
523 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
524 region &= ~(size - 1);
525
526 /* Convert from PCI bus to resource space */
527 bus_region.start = region;
528 bus_region.end = region + size - 1;
529 pcibios_bus_to_resource(dev->bus, res, &bus_region);
530
531 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
532 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
533}
534
535/*
536 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
537 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
538 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
539 * (which conflicts w/ BAR1's memory range).
540 *
541 * CS553x's ISA PCI BARs may also be read-only (ref:
542 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
543 */
544static void quirk_cs5536_vsa(struct pci_dev *dev)
545{
546 static char *name = "CS5536 ISA bridge";
547
548 if (pci_resource_len(dev, 0) != 8) {
549 quirk_io(dev, 0, 8, name); /* SMB */
550 quirk_io(dev, 1, 256, name); /* GPIO */
551 quirk_io(dev, 2, 64, name); /* MFGPT */
552 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
553 name);
554 }
555}
556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
557
558static void quirk_io_region(struct pci_dev *dev, int port,
559 unsigned size, int nr, const char *name)
560{
561 u16 region;
562 struct pci_bus_region bus_region;
563 struct resource *res = dev->resource + nr;
564
565 pci_read_config_word(dev, port, ®ion);
566 region &= ~(size - 1);
567
568 if (!region)
569 return;
570
571 res->name = pci_name(dev);
572 res->flags = IORESOURCE_IO;
573
574 /* Convert from PCI bus to resource space */
575 bus_region.start = region;
576 bus_region.end = region + size - 1;
577 pcibios_bus_to_resource(dev->bus, res, &bus_region);
578
579 if (!pci_claim_resource(dev, nr))
580 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
581}
582
583/*
584 * ATI Northbridge setups MCE the processor if you even read somewhere
585 * between 0x3b0->0x3bb or read 0x3d3
586 */
587static void quirk_ati_exploding_mce(struct pci_dev *dev)
588{
589 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
590 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
591 request_region(0x3b0, 0x0C, "RadeonIGP");
592 request_region(0x3d3, 0x01, "RadeonIGP");
593}
594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
595
596/*
597 * In the AMD NL platform, this device ([1022:7912]) has a class code of
598 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
599 * claim it.
600 *
601 * But the dwc3 driver is a more specific driver for this device, and we'd
602 * prefer to use it instead of xhci. To prevent xhci from claiming the
603 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
604 * defines as "USB device (not host controller)". The dwc3 driver can then
605 * claim it based on its Vendor and Device ID.
606 */
607static void quirk_amd_nl_class(struct pci_dev *pdev)
608{
609 u32 class = pdev->class;
610
611 /* Use "USB Device (not host controller)" class */
612 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
613 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
614 class, pdev->class);
615}
616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
617 quirk_amd_nl_class);
618
619/*
620 * Synopsys USB 3.x host HAPS platform has a class code of
621 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
622 * devices should use dwc3-haps driver. Change these devices' class code to
623 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
624 * them.
625 */
626static void quirk_synopsys_haps(struct pci_dev *pdev)
627{
628 u32 class = pdev->class;
629
630 switch (pdev->device) {
631 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
632 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
633 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
634 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
635 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
636 class, pdev->class);
637 break;
638 }
639}
640DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
641 PCI_CLASS_SERIAL_USB_XHCI, 0,
642 quirk_synopsys_haps);
643
644/*
645 * Let's make the southbridge information explicit instead of having to
646 * worry about people probing the ACPI areas, for example.. (Yes, it
647 * happens, and if you read the wrong ACPI register it will put the machine
648 * to sleep with no way of waking it up again. Bummer).
649 *
650 * ALI M7101: Two IO regions pointed to by words at
651 * 0xE0 (64 bytes of ACPI registers)
652 * 0xE2 (32 bytes of SMB registers)
653 */
654static void quirk_ali7101_acpi(struct pci_dev *dev)
655{
656 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
657 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
658}
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
660
661static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
662{
663 u32 devres;
664 u32 mask, size, base;
665
666 pci_read_config_dword(dev, port, &devres);
667 if ((devres & enable) != enable)
668 return;
669 mask = (devres >> 16) & 15;
670 base = devres & 0xffff;
671 size = 16;
672 for (;;) {
673 unsigned bit = size >> 1;
674 if ((bit & mask) == bit)
675 break;
676 size = bit;
677 }
678 /*
679 * For now we only print it out. Eventually we'll want to
680 * reserve it (at least if it's in the 0x1000+ range), but
681 * let's get enough confirmation reports first.
682 */
683 base &= -size;
684 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
685}
686
687static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
688{
689 u32 devres;
690 u32 mask, size, base;
691
692 pci_read_config_dword(dev, port, &devres);
693 if ((devres & enable) != enable)
694 return;
695 base = devres & 0xffff0000;
696 mask = (devres & 0x3f) << 16;
697 size = 128 << 16;
698 for (;;) {
699 unsigned bit = size >> 1;
700 if ((bit & mask) == bit)
701 break;
702 size = bit;
703 }
704
705 /*
706 * For now we only print it out. Eventually we'll want to
707 * reserve it, but let's get enough confirmation reports first.
708 */
709 base &= -size;
710 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
711}
712
713/*
714 * PIIX4 ACPI: Two IO regions pointed to by longwords at
715 * 0x40 (64 bytes of ACPI registers)
716 * 0x90 (16 bytes of SMB registers)
717 * and a few strange programmable PIIX4 device resources.
718 */
719static void quirk_piix4_acpi(struct pci_dev *dev)
720{
721 u32 res_a;
722
723 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
724 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
725
726 /* Device resource A has enables for some of the other ones */
727 pci_read_config_dword(dev, 0x5c, &res_a);
728
729 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
730 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
731
732 /* Device resource D is just bitfields for static resources */
733
734 /* Device 12 enabled? */
735 if (res_a & (1 << 29)) {
736 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
737 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
738 }
739 /* Device 13 enabled? */
740 if (res_a & (1 << 30)) {
741 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
742 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
743 }
744 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
745 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
746}
747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
749
750#define ICH_PMBASE 0x40
751#define ICH_ACPI_CNTL 0x44
752#define ICH4_ACPI_EN 0x10
753#define ICH6_ACPI_EN 0x80
754#define ICH4_GPIOBASE 0x58
755#define ICH4_GPIO_CNTL 0x5c
756#define ICH4_GPIO_EN 0x10
757#define ICH6_GPIOBASE 0x48
758#define ICH6_GPIO_CNTL 0x4c
759#define ICH6_GPIO_EN 0x10
760
761/*
762 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
763 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
764 * 0x58 (64 bytes of GPIO I/O space)
765 */
766static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
767{
768 u8 enable;
769
770 /*
771 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
772 * with low legacy (and fixed) ports. We don't know the decoding
773 * priority and can't tell whether the legacy device or the one created
774 * here is really at that address. This happens on boards with broken
775 * BIOSes.
776 */
777 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
778 if (enable & ICH4_ACPI_EN)
779 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
780 "ICH4 ACPI/GPIO/TCO");
781
782 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
783 if (enable & ICH4_GPIO_EN)
784 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
785 "ICH4 GPIO");
786}
787DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
788DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
795DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
796DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
797
798static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
799{
800 u8 enable;
801
802 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
803 if (enable & ICH6_ACPI_EN)
804 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
805 "ICH6 ACPI/GPIO/TCO");
806
807 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
808 if (enable & ICH6_GPIO_EN)
809 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
810 "ICH6 GPIO");
811}
812
813static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
814 const char *name, int dynsize)
815{
816 u32 val;
817 u32 size, base;
818
819 pci_read_config_dword(dev, reg, &val);
820
821 /* Enabled? */
822 if (!(val & 1))
823 return;
824 base = val & 0xfffc;
825 if (dynsize) {
826 /*
827 * This is not correct. It is 16, 32 or 64 bytes depending on
828 * register D31:F0:ADh bits 5:4.
829 *
830 * But this gets us at least _part_ of it.
831 */
832 size = 16;
833 } else {
834 size = 128;
835 }
836 base &= ~(size-1);
837
838 /*
839 * Just print it out for now. We should reserve it after more
840 * debugging.
841 */
842 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
843}
844
845static void quirk_ich6_lpc(struct pci_dev *dev)
846{
847 /* Shared ACPI/GPIO decode with all ICH6+ */
848 ich6_lpc_acpi_gpio(dev);
849
850 /* ICH6-specific generic IO decode */
851 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
852 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
853}
854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
856
857static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
858 const char *name)
859{
860 u32 val;
861 u32 mask, base;
862
863 pci_read_config_dword(dev, reg, &val);
864
865 /* Enabled? */
866 if (!(val & 1))
867 return;
868
869 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
870 base = val & 0xfffc;
871 mask = (val >> 16) & 0xfc;
872 mask |= 3;
873
874 /*
875 * Just print it out for now. We should reserve it after more
876 * debugging.
877 */
878 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
879}
880
881/* ICH7-10 has the same common LPC generic IO decode registers */
882static void quirk_ich7_lpc(struct pci_dev *dev)
883{
884 /* We share the common ACPI/GPIO decode with ICH6 */
885 ich6_lpc_acpi_gpio(dev);
886
887 /* And have 4 ICH7+ generic decodes */
888 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
889 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
890 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
891 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
906
907/*
908 * VIA ACPI: One IO region pointed to by longword at
909 * 0x48 or 0x20 (256 bytes of ACPI registers)
910 */
911static void quirk_vt82c586_acpi(struct pci_dev *dev)
912{
913 if (dev->revision & 0x10)
914 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
915 "vt82c586 ACPI");
916}
917DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
918
919/*
920 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
921 * 0x48 (256 bytes of ACPI registers)
922 * 0x70 (128 bytes of hardware monitoring register)
923 * 0x90 (16 bytes of SMB registers)
924 */
925static void quirk_vt82c686_acpi(struct pci_dev *dev)
926{
927 quirk_vt82c586_acpi(dev);
928
929 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
930 "vt82c686 HW-mon");
931
932 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
935
936/*
937 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
938 * 0x88 (128 bytes of power management registers)
939 * 0xd0 (16 bytes of SMB registers)
940 */
941static void quirk_vt8235_acpi(struct pci_dev *dev)
942{
943 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
944 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
945}
946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
947
948/*
949 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
950 * back-to-back: Disable fast back-to-back on the secondary bus segment
951 */
952static void quirk_xio2000a(struct pci_dev *dev)
953{
954 struct pci_dev *pdev;
955 u16 command;
956
957 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
958 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
959 pci_read_config_word(pdev, PCI_COMMAND, &command);
960 if (command & PCI_COMMAND_FAST_BACK)
961 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
962 }
963}
964DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
965 quirk_xio2000a);
966
967#ifdef CONFIG_X86_IO_APIC
968
969#include <asm/io_apic.h>
970
971/*
972 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
973 * devices to the external APIC.
974 *
975 * TODO: When we have device-specific interrupt routers, this code will go
976 * away from quirks.
977 */
978static void quirk_via_ioapic(struct pci_dev *dev)
979{
980 u8 tmp;
981
982 if (nr_ioapics < 1)
983 tmp = 0; /* nothing routed to external APIC */
984 else
985 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
986
987 pci_info(dev, "%sbling VIA external APIC routing\n",
988 tmp == 0 ? "Disa" : "Ena");
989
990 /* Offset 0x58: External APIC IRQ output control */
991 pci_write_config_byte(dev, 0x58, tmp);
992}
993DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
994DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
995
996/*
997 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
998 * This leads to doubled level interrupt rates.
999 * Set this bit to get rid of cycle wastage.
1000 * Otherwise uncritical.
1001 */
1002static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1003{
1004 u8 misc_control2;
1005#define BYPASS_APIC_DEASSERT 8
1006
1007 pci_read_config_byte(dev, 0x5B, &misc_control2);
1008 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1009 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1010 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1011 }
1012}
1013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1014DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1015
1016/*
1017 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1018 * We check all revs >= B0 (yet not in the pre production!) as the bug
1019 * is currently marked NoFix
1020 *
1021 * We have multiple reports of hangs with this chipset that went away with
1022 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1023 * of course. However the advice is demonstrably good even if so.
1024 */
1025static void quirk_amd_ioapic(struct pci_dev *dev)
1026{
1027 if (dev->revision >= 0x02) {
1028 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1029 pci_warn(dev, " : booting with the \"noapic\" option\n");
1030 }
1031}
1032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1033#endif /* CONFIG_X86_IO_APIC */
1034
1035#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1036
1037static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1038{
1039 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1040 if (dev->subsystem_device == 0xa118)
1041 dev->sriov->link = dev->devfn;
1042}
1043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1044#endif
1045
1046/*
1047 * Some settings of MMRBC can lead to data corruption so block changes.
1048 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1049 */
1050static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1051{
1052 if (dev->subordinate && dev->revision <= 0x12) {
1053 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1054 dev->revision);
1055 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1056 }
1057}
1058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1059
1060/*
1061 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1062 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1063 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1064 * of the ACPI SCI interrupt is only done for convenience.
1065 * -jgarzik
1066 */
1067static void quirk_via_acpi(struct pci_dev *d)
1068{
1069 u8 irq;
1070
1071 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1072 pci_read_config_byte(d, 0x42, &irq);
1073 irq &= 0xf;
1074 if (irq && (irq != 2))
1075 d->irq = irq;
1076}
1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1079
1080/* VIA bridges which have VLink */
1081static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1082
1083static void quirk_via_bridge(struct pci_dev *dev)
1084{
1085 /* See what bridge we have and find the device ranges */
1086 switch (dev->device) {
1087 case PCI_DEVICE_ID_VIA_82C686:
1088 /*
1089 * The VT82C686 is special; it attaches to PCI and can have
1090 * any device number. All its subdevices are functions of
1091 * that single device.
1092 */
1093 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1094 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1095 break;
1096 case PCI_DEVICE_ID_VIA_8237:
1097 case PCI_DEVICE_ID_VIA_8237A:
1098 via_vlink_dev_lo = 15;
1099 break;
1100 case PCI_DEVICE_ID_VIA_8235:
1101 via_vlink_dev_lo = 16;
1102 break;
1103 case PCI_DEVICE_ID_VIA_8231:
1104 case PCI_DEVICE_ID_VIA_8233_0:
1105 case PCI_DEVICE_ID_VIA_8233A:
1106 case PCI_DEVICE_ID_VIA_8233C_0:
1107 via_vlink_dev_lo = 17;
1108 break;
1109 }
1110}
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1119
1120/*
1121 * quirk_via_vlink - VIA VLink IRQ number update
1122 * @dev: PCI device
1123 *
1124 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1125 * the IRQ line register which usually is not relevant for PCI cards, is
1126 * actually written so that interrupts get sent to the right place.
1127 *
1128 * We only do this on systems where a VIA south bridge was detected, and
1129 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1130 */
1131static void quirk_via_vlink(struct pci_dev *dev)
1132{
1133 u8 irq, new_irq;
1134
1135 /* Check if we have VLink at all */
1136 if (via_vlink_dev_lo == -1)
1137 return;
1138
1139 new_irq = dev->irq;
1140
1141 /* Don't quirk interrupts outside the legacy IRQ range */
1142 if (!new_irq || new_irq > 15)
1143 return;
1144
1145 /* Internal device ? */
1146 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1147 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1148 return;
1149
1150 /*
1151 * This is an internal VLink device on a PIC interrupt. The BIOS
1152 * ought to have set this but may not have, so we redo it.
1153 */
1154 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1155 if (new_irq != irq) {
1156 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1157 irq, new_irq);
1158 udelay(15); /* unknown if delay really needed */
1159 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1160 }
1161}
1162DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1163
1164/*
1165 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1166 * of VT82C597 for backward compatibility. We need to switch it off to be
1167 * able to recognize the real type of the chip.
1168 */
1169static void quirk_vt82c598_id(struct pci_dev *dev)
1170{
1171 pci_write_config_byte(dev, 0xfc, 0);
1172 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1173}
1174DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1175
1176/*
1177 * CardBus controllers have a legacy base address that enables them to
1178 * respond as i82365 pcmcia controllers. We don't want them to do this
1179 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1180 * driver does not (and should not) handle CardBus.
1181 */
1182static void quirk_cardbus_legacy(struct pci_dev *dev)
1183{
1184 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1185}
1186DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1187 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1188DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1189 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1190
1191/*
1192 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1193 * what the designers were smoking but let's not inhale...
1194 *
1195 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1196 * turn it off!
1197 */
1198static void quirk_amd_ordering(struct pci_dev *dev)
1199{
1200 u32 pcic;
1201 pci_read_config_dword(dev, 0x4C, &pcic);
1202 if ((pcic & 6) != 6) {
1203 pcic |= 6;
1204 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1205 pci_write_config_dword(dev, 0x4C, pcic);
1206 pci_read_config_dword(dev, 0x84, &pcic);
1207 pcic |= (1 << 23); /* Required in this mode */
1208 pci_write_config_dword(dev, 0x84, pcic);
1209 }
1210}
1211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1212DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1213
1214/*
1215 * DreamWorks-provided workaround for Dunord I-3000 problem
1216 *
1217 * This card decodes and responds to addresses not apparently assigned to
1218 * it. We force a larger allocation to ensure that nothing gets put too
1219 * close to it.
1220 */
1221static void quirk_dunord(struct pci_dev *dev)
1222{
1223 struct resource *r = &dev->resource[1];
1224
1225 r->flags |= IORESOURCE_UNSET;
1226 r->start = 0;
1227 r->end = 0xffffff;
1228}
1229DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1230
1231/*
1232 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1233 * decoding (transparent), and does indicate this in the ProgIf.
1234 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1235 */
1236static void quirk_transparent_bridge(struct pci_dev *dev)
1237{
1238 dev->transparent = 1;
1239}
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1242
1243/*
1244 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1245 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1246 * found at http://www.national.com/analog for info on what these bits do.
1247 * <christer@weinigel.se>
1248 */
1249static void quirk_mediagx_master(struct pci_dev *dev)
1250{
1251 u8 reg;
1252
1253 pci_read_config_byte(dev, 0x41, ®);
1254 if (reg & 2) {
1255 reg &= ~2;
1256 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1257 reg);
1258 pci_write_config_byte(dev, 0x41, reg);
1259 }
1260}
1261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1262DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1263
1264/*
1265 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1266 * in the odd case it is not the results are corruption hence the presence
1267 * of a Linux check.
1268 */
1269static void quirk_disable_pxb(struct pci_dev *pdev)
1270{
1271 u16 config;
1272
1273 if (pdev->revision != 0x04) /* Only C0 requires this */
1274 return;
1275 pci_read_config_word(pdev, 0x40, &config);
1276 if (config & (1<<6)) {
1277 config &= ~(1<<6);
1278 pci_write_config_word(pdev, 0x40, config);
1279 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1280 }
1281}
1282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1283DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1284
1285static void quirk_amd_ide_mode(struct pci_dev *pdev)
1286{
1287 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1288 u8 tmp;
1289
1290 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1291 if (tmp == 0x01) {
1292 pci_read_config_byte(pdev, 0x40, &tmp);
1293 pci_write_config_byte(pdev, 0x40, tmp|1);
1294 pci_write_config_byte(pdev, 0x9, 1);
1295 pci_write_config_byte(pdev, 0xa, 6);
1296 pci_write_config_byte(pdev, 0x40, tmp);
1297
1298 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1299 pci_info(pdev, "set SATA to AHCI mode\n");
1300 }
1301}
1302DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1303DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1305DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1307DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1309DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1310
1311/* Serverworks CSB5 IDE does not fully support native mode */
1312static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1313{
1314 u8 prog;
1315 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1316 if (prog & 5) {
1317 prog &= ~5;
1318 pdev->class &= ~5;
1319 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1320 /* PCI layer will sort out resources */
1321 }
1322}
1323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1324
1325/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1326static void quirk_ide_samemode(struct pci_dev *pdev)
1327{
1328 u8 prog;
1329
1330 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1331
1332 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1333 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1334 prog &= ~5;
1335 pdev->class &= ~5;
1336 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1337 }
1338}
1339DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1340
1341/* Some ATA devices break if put into D3 */
1342static void quirk_no_ata_d3(struct pci_dev *pdev)
1343{
1344 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1345}
1346/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1347DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1348 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1350 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1351/* ALi loses some register settings that we cannot then restore */
1352DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1355 occur when mode detecting */
1356DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1357 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1358
1359/*
1360 * This was originally an Alpha-specific thing, but it really fits here.
1361 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1362 */
1363static void quirk_eisa_bridge(struct pci_dev *dev)
1364{
1365 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1366}
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1368
1369/*
1370 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1371 * is not activated. The myth is that Asus said that they do not want the
1372 * users to be irritated by just another PCI Device in the Win98 device
1373 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1374 * package 2.7.0 for details)
1375 *
1376 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1377 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1378 * becomes necessary to do this tweak in two steps -- the chosen trigger
1379 * is either the Host bridge (preferred) or on-board VGA controller.
1380 *
1381 * Note that we used to unhide the SMBus that way on Toshiba laptops
1382 * (Satellite A40 and Tecra M2) but then found that the thermal management
1383 * was done by SMM code, which could cause unsynchronized concurrent
1384 * accesses to the SMBus registers, with potentially bad effects. Thus you
1385 * should be very careful when adding new entries: if SMM is accessing the
1386 * Intel SMBus, this is a very good reason to leave it hidden.
1387 *
1388 * Likewise, many recent laptops use ACPI for thermal management. If the
1389 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1390 * natively, and keeping the SMBus hidden is the right thing to do. If you
1391 * are about to add an entry in the table below, please first disassemble
1392 * the DSDT and double-check that there is no code accessing the SMBus.
1393 */
1394static int asus_hides_smbus;
1395
1396static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1397{
1398 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1399 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1400 switch (dev->subsystem_device) {
1401 case 0x8025: /* P4B-LX */
1402 case 0x8070: /* P4B */
1403 case 0x8088: /* P4B533 */
1404 case 0x1626: /* L3C notebook */
1405 asus_hides_smbus = 1;
1406 }
1407 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1408 switch (dev->subsystem_device) {
1409 case 0x80b1: /* P4GE-V */
1410 case 0x80b2: /* P4PE */
1411 case 0x8093: /* P4B533-V */
1412 asus_hides_smbus = 1;
1413 }
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1415 switch (dev->subsystem_device) {
1416 case 0x8030: /* P4T533 */
1417 asus_hides_smbus = 1;
1418 }
1419 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1420 switch (dev->subsystem_device) {
1421 case 0x8070: /* P4G8X Deluxe */
1422 asus_hides_smbus = 1;
1423 }
1424 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1425 switch (dev->subsystem_device) {
1426 case 0x80c9: /* PU-DLS */
1427 asus_hides_smbus = 1;
1428 }
1429 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1430 switch (dev->subsystem_device) {
1431 case 0x1751: /* M2N notebook */
1432 case 0x1821: /* M5N notebook */
1433 case 0x1897: /* A6L notebook */
1434 asus_hides_smbus = 1;
1435 }
1436 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1437 switch (dev->subsystem_device) {
1438 case 0x184b: /* W1N notebook */
1439 case 0x186a: /* M6Ne notebook */
1440 asus_hides_smbus = 1;
1441 }
1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1443 switch (dev->subsystem_device) {
1444 case 0x80f2: /* P4P800-X */
1445 asus_hides_smbus = 1;
1446 }
1447 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1448 switch (dev->subsystem_device) {
1449 case 0x1882: /* M6V notebook */
1450 case 0x1977: /* A6VA notebook */
1451 asus_hides_smbus = 1;
1452 }
1453 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1454 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1455 switch (dev->subsystem_device) {
1456 case 0x088C: /* HP Compaq nc8000 */
1457 case 0x0890: /* HP Compaq nc6000 */
1458 asus_hides_smbus = 1;
1459 }
1460 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1461 switch (dev->subsystem_device) {
1462 case 0x12bc: /* HP D330L */
1463 case 0x12bd: /* HP D530 */
1464 case 0x006a: /* HP Compaq nx9500 */
1465 asus_hides_smbus = 1;
1466 }
1467 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1468 switch (dev->subsystem_device) {
1469 case 0x12bf: /* HP xw4100 */
1470 asus_hides_smbus = 1;
1471 }
1472 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1473 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1474 switch (dev->subsystem_device) {
1475 case 0xC00C: /* Samsung P35 notebook */
1476 asus_hides_smbus = 1;
1477 }
1478 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1479 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1480 switch (dev->subsystem_device) {
1481 case 0x0058: /* Compaq Evo N620c */
1482 asus_hides_smbus = 1;
1483 }
1484 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1485 switch (dev->subsystem_device) {
1486 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1487 /* Motherboard doesn't have Host bridge
1488 * subvendor/subdevice IDs, therefore checking
1489 * its on-board VGA controller */
1490 asus_hides_smbus = 1;
1491 }
1492 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1493 switch (dev->subsystem_device) {
1494 case 0x00b8: /* Compaq Evo D510 CMT */
1495 case 0x00b9: /* Compaq Evo D510 SFF */
1496 case 0x00ba: /* Compaq Evo D510 USDT */
1497 /* Motherboard doesn't have Host bridge
1498 * subvendor/subdevice IDs and on-board VGA
1499 * controller is disabled if an AGP card is
1500 * inserted, therefore checking USB UHCI
1501 * Controller #1 */
1502 asus_hides_smbus = 1;
1503 }
1504 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1505 switch (dev->subsystem_device) {
1506 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1507 /* Motherboard doesn't have host bridge
1508 * subvendor/subdevice IDs, therefore checking
1509 * its on-board VGA controller */
1510 asus_hides_smbus = 1;
1511 }
1512 }
1513}
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1524
1525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1528
1529static void asus_hides_smbus_lpc(struct pci_dev *dev)
1530{
1531 u16 val;
1532
1533 if (likely(!asus_hides_smbus))
1534 return;
1535
1536 pci_read_config_word(dev, 0xF2, &val);
1537 if (val & 0x8) {
1538 pci_write_config_word(dev, 0xF2, val & (~0x8));
1539 pci_read_config_word(dev, 0xF2, &val);
1540 if (val & 0x8)
1541 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1542 val);
1543 else
1544 pci_info(dev, "Enabled i801 SMBus device\n");
1545 }
1546}
1547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1548DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1550DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1551DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1554DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1555DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1556DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1557DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1558DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1560DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1561
1562/* It appears we just have one such device. If not, we have a warning */
1563static void __iomem *asus_rcba_base;
1564static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1565{
1566 u32 rcba;
1567
1568 if (likely(!asus_hides_smbus))
1569 return;
1570 WARN_ON(asus_rcba_base);
1571
1572 pci_read_config_dword(dev, 0xF0, &rcba);
1573 /* use bits 31:14, 16 kB aligned */
1574 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1575 if (asus_rcba_base == NULL)
1576 return;
1577}
1578
1579static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1580{
1581 u32 val;
1582
1583 if (likely(!asus_hides_smbus || !asus_rcba_base))
1584 return;
1585
1586 /* read the Function Disable register, dword mode only */
1587 val = readl(asus_rcba_base + 0x3418);
1588
1589 /* enable the SMBus device */
1590 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1591}
1592
1593static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1594{
1595 if (likely(!asus_hides_smbus || !asus_rcba_base))
1596 return;
1597
1598 iounmap(asus_rcba_base);
1599 asus_rcba_base = NULL;
1600 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1601}
1602
1603static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1604{
1605 asus_hides_smbus_lpc_ich6_suspend(dev);
1606 asus_hides_smbus_lpc_ich6_resume_early(dev);
1607 asus_hides_smbus_lpc_ich6_resume(dev);
1608}
1609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1610DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1611DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1612DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1613
1614/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1615static void quirk_sis_96x_smbus(struct pci_dev *dev)
1616{
1617 u8 val = 0;
1618 pci_read_config_byte(dev, 0x77, &val);
1619 if (val & 0x10) {
1620 pci_info(dev, "Enabling SiS 96x SMBus\n");
1621 pci_write_config_byte(dev, 0x77, val & ~0x10);
1622 }
1623}
1624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1629DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1630DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1631DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1632
1633/*
1634 * ... This is further complicated by the fact that some SiS96x south
1635 * bridges pretend to be 85C503/5513 instead. In that case see if we
1636 * spotted a compatible north bridge to make sure.
1637 * (pci_find_device() doesn't work yet)
1638 *
1639 * We can also enable the sis96x bit in the discovery register..
1640 */
1641#define SIS_DETECT_REGISTER 0x40
1642
1643static void quirk_sis_503(struct pci_dev *dev)
1644{
1645 u8 reg;
1646 u16 devid;
1647
1648 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1649 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1650 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1651 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1652 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1653 return;
1654 }
1655
1656 /*
1657 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1658 * it has already been processed. (Depends on link order, which is
1659 * apparently not guaranteed)
1660 */
1661 dev->device = devid;
1662 quirk_sis_96x_smbus(dev);
1663}
1664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1665DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1666
1667/*
1668 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1669 * and MC97 modem controller are disabled when a second PCI soundcard is
1670 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1671 * -- bjd
1672 */
1673static void asus_hides_ac97_lpc(struct pci_dev *dev)
1674{
1675 u8 val;
1676 int asus_hides_ac97 = 0;
1677
1678 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1679 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1680 asus_hides_ac97 = 1;
1681 }
1682
1683 if (!asus_hides_ac97)
1684 return;
1685
1686 pci_read_config_byte(dev, 0x50, &val);
1687 if (val & 0xc0) {
1688 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1689 pci_read_config_byte(dev, 0x50, &val);
1690 if (val & 0xc0)
1691 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1692 val);
1693 else
1694 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1695 }
1696}
1697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1698DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1699
1700#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1701
1702/*
1703 * If we are using libata we can drive this chip properly but must do this
1704 * early on to make the additional device appear during the PCI scanning.
1705 */
1706static void quirk_jmicron_ata(struct pci_dev *pdev)
1707{
1708 u32 conf1, conf5, class;
1709 u8 hdr;
1710
1711 /* Only poke fn 0 */
1712 if (PCI_FUNC(pdev->devfn))
1713 return;
1714
1715 pci_read_config_dword(pdev, 0x40, &conf1);
1716 pci_read_config_dword(pdev, 0x80, &conf5);
1717
1718 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1719 conf5 &= ~(1 << 24); /* Clear bit 24 */
1720
1721 switch (pdev->device) {
1722 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1723 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1724 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1725 /* The controller should be in single function ahci mode */
1726 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1727 break;
1728
1729 case PCI_DEVICE_ID_JMICRON_JMB365:
1730 case PCI_DEVICE_ID_JMICRON_JMB366:
1731 /* Redirect IDE second PATA port to the right spot */
1732 conf5 |= (1 << 24);
1733 fallthrough;
1734 case PCI_DEVICE_ID_JMICRON_JMB361:
1735 case PCI_DEVICE_ID_JMICRON_JMB363:
1736 case PCI_DEVICE_ID_JMICRON_JMB369:
1737 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1738 /* Set the class codes correctly and then direct IDE 0 */
1739 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1740 break;
1741
1742 case PCI_DEVICE_ID_JMICRON_JMB368:
1743 /* The controller should be in single function IDE mode */
1744 conf1 |= 0x00C00000; /* Set 22, 23 */
1745 break;
1746 }
1747
1748 pci_write_config_dword(pdev, 0x40, conf1);
1749 pci_write_config_dword(pdev, 0x80, conf5);
1750
1751 /* Update pdev accordingly */
1752 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1753 pdev->hdr_type = hdr & 0x7f;
1754 pdev->multifunction = !!(hdr & 0x80);
1755
1756 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1757 pdev->class = class >> 8;
1758}
1759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1760DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1762DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1763DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1764DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1765DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1766DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1767DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1768DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1769DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1770DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1771DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1773DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1774DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1775DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1776DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1777
1778#endif
1779
1780static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1781{
1782 if (dev->multifunction) {
1783 device_disable_async_suspend(&dev->dev);
1784 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1785 }
1786}
1787DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1788DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1789DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1791
1792#ifdef CONFIG_X86_IO_APIC
1793static void quirk_alder_ioapic(struct pci_dev *pdev)
1794{
1795 int i;
1796
1797 if ((pdev->class >> 8) != 0xff00)
1798 return;
1799
1800 /*
1801 * The first BAR is the location of the IO-APIC... we must
1802 * not touch this (and it's already covered by the fixmap), so
1803 * forcibly insert it into the resource tree.
1804 */
1805 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1806 insert_resource(&iomem_resource, &pdev->resource[0]);
1807
1808 /*
1809 * The next five BARs all seem to be rubbish, so just clean
1810 * them out.
1811 */
1812 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1813 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1814}
1815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1816#endif
1817
1818static void quirk_pcie_mch(struct pci_dev *pdev)
1819{
1820 pdev->no_msi = 1;
1821}
1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1823DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1825
1826DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1827
1828/*
1829 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1830 * together on certain PXH-based systems.
1831 */
1832static void quirk_pcie_pxh(struct pci_dev *dev)
1833{
1834 dev->no_msi = 1;
1835 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1836}
1837DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1838DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1839DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1840DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1841DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1842
1843/*
1844 * Some Intel PCI Express chipsets have trouble with downstream device
1845 * power management.
1846 */
1847static void quirk_intel_pcie_pm(struct pci_dev *dev)
1848{
1849 pci_pm_d3_delay = 120;
1850 dev->no_d1d2 = 1;
1851}
1852DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1854DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1855DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1856DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1859DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1864DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1866DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1871DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1873
1874static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1875{
1876 if (dev->d3_delay >= delay)
1877 return;
1878
1879 dev->d3_delay = delay;
1880 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1881 dev->d3_delay);
1882}
1883
1884static void quirk_radeon_pm(struct pci_dev *dev)
1885{
1886 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1887 dev->subsystem_device == 0x00e2)
1888 quirk_d3hot_delay(dev, 20);
1889}
1890DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1891
1892/*
1893 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1894 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1895 *
1896 * The kernel attempts to transition these devices to D3cold, but that seems
1897 * to be ineffective on the platforms in question; the PCI device appears to
1898 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1899 * extended delay in order to succeed.
1900 */
1901static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1902{
1903 quirk_d3hot_delay(dev, 20);
1904}
1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1906DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1907
1908#ifdef CONFIG_X86_IO_APIC
1909static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1910{
1911 noioapicreroute = 1;
1912 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1913
1914 return 0;
1915}
1916
1917static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1918 /*
1919 * Systems to exclude from boot interrupt reroute quirks
1920 */
1921 {
1922 .callback = dmi_disable_ioapicreroute,
1923 .ident = "ASUSTek Computer INC. M2N-LR",
1924 .matches = {
1925 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1926 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1927 },
1928 },
1929 {}
1930};
1931
1932/*
1933 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1934 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1935 * that a PCI device's interrupt handler is installed on the boot interrupt
1936 * line instead.
1937 */
1938static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1939{
1940 dmi_check_system(boot_interrupt_dmi_table);
1941 if (noioapicquirk || noioapicreroute)
1942 return;
1943
1944 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1945 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1946 dev->vendor, dev->device);
1947}
1948DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1949DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1950DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1952DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1956DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1957DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1958DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1959DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1960DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1961DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1962DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1963DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1964
1965/*
1966 * On some chipsets we can disable the generation of legacy INTx boot
1967 * interrupts.
1968 */
1969
1970/*
1971 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1972 * 300641-004US, section 5.7.3.
1973 *
1974 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1975 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1976 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1977 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1978 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1979 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1980 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1981 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1982 * Core IO on Xeon Scalable, see Intel order no 610950.
1983 */
1984#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1985#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1986
1987#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1988#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1989
1990static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1991{
1992 u16 pci_config_word;
1993 u32 pci_config_dword;
1994
1995 if (noioapicquirk)
1996 return;
1997
1998 switch (dev->device) {
1999 case PCI_DEVICE_ID_INTEL_ESB_10:
2000 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2001 &pci_config_word);
2002 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2003 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2004 pci_config_word);
2005 break;
2006 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2007 case 0x0e28: /* Xeon E5/E7 V2 */
2008 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2009 case 0x6f28: /* Xeon D-1500 */
2010 case 0x2034: /* Xeon Scalable Family */
2011 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2012 &pci_config_dword);
2013 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2014 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2015 pci_config_dword);
2016 break;
2017 default:
2018 return;
2019 }
2020 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2021 dev->vendor, dev->device);
2022}
2023/*
2024 * Device 29 Func 5 Device IDs of IO-APIC
2025 * containing ABAR—APIC1 Alternate Base Address Register
2026 */
2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2028 quirk_disable_intel_boot_interrupt);
2029DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2030 quirk_disable_intel_boot_interrupt);
2031
2032/*
2033 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2034 * containing Coherent Interface Protocol Interrupt Control
2035 *
2036 * Device IDs obtained from volume 2 datasheets of commented
2037 * families above.
2038 */
2039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2040 quirk_disable_intel_boot_interrupt);
2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2042 quirk_disable_intel_boot_interrupt);
2043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2044 quirk_disable_intel_boot_interrupt);
2045DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2046 quirk_disable_intel_boot_interrupt);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2048 quirk_disable_intel_boot_interrupt);
2049DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2050 quirk_disable_intel_boot_interrupt);
2051DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2052 quirk_disable_intel_boot_interrupt);
2053DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2054 quirk_disable_intel_boot_interrupt);
2055DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2056 quirk_disable_intel_boot_interrupt);
2057DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2058 quirk_disable_intel_boot_interrupt);
2059
2060/* Disable boot interrupts on HT-1000 */
2061#define BC_HT1000_FEATURE_REG 0x64
2062#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2063#define BC_HT1000_MAP_IDX 0xC00
2064#define BC_HT1000_MAP_DATA 0xC01
2065
2066static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2067{
2068 u32 pci_config_dword;
2069 u8 irq;
2070
2071 if (noioapicquirk)
2072 return;
2073
2074 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2075 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2076 BC_HT1000_PIC_REGS_ENABLE);
2077
2078 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2079 outb(irq, BC_HT1000_MAP_IDX);
2080 outb(0x00, BC_HT1000_MAP_DATA);
2081 }
2082
2083 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2084
2085 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2086 dev->vendor, dev->device);
2087}
2088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2089DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2090
2091/* Disable boot interrupts on AMD and ATI chipsets */
2092
2093/*
2094 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2095 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2096 * (due to an erratum).
2097 */
2098#define AMD_813X_MISC 0x40
2099#define AMD_813X_NOIOAMODE (1<<0)
2100#define AMD_813X_REV_B1 0x12
2101#define AMD_813X_REV_B2 0x13
2102
2103static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2104{
2105 u32 pci_config_dword;
2106
2107 if (noioapicquirk)
2108 return;
2109 if ((dev->revision == AMD_813X_REV_B1) ||
2110 (dev->revision == AMD_813X_REV_B2))
2111 return;
2112
2113 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2114 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2115 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2116
2117 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2118 dev->vendor, dev->device);
2119}
2120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2121DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2123DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2124
2125#define AMD_8111_PCI_IRQ_ROUTING 0x56
2126
2127static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2128{
2129 u16 pci_config_word;
2130
2131 if (noioapicquirk)
2132 return;
2133
2134 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2135 if (!pci_config_word) {
2136 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2137 dev->vendor, dev->device);
2138 return;
2139 }
2140 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2141 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2142 dev->vendor, dev->device);
2143}
2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2145DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2146#endif /* CONFIG_X86_IO_APIC */
2147
2148/*
2149 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2150 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2151 * Re-allocate the region if needed...
2152 */
2153static void quirk_tc86c001_ide(struct pci_dev *dev)
2154{
2155 struct resource *r = &dev->resource[0];
2156
2157 if (r->start & 0x8) {
2158 r->flags |= IORESOURCE_UNSET;
2159 r->start = 0;
2160 r->end = 0xf;
2161 }
2162}
2163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2164 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2165 quirk_tc86c001_ide);
2166
2167/*
2168 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2169 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2170 * being read correctly if bit 7 of the base address is set.
2171 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2172 * Re-allocate the regions to a 256-byte boundary if necessary.
2173 */
2174static void quirk_plx_pci9050(struct pci_dev *dev)
2175{
2176 unsigned int bar;
2177
2178 /* Fixed in revision 2 (PCI 9052). */
2179 if (dev->revision >= 2)
2180 return;
2181 for (bar = 0; bar <= 1; bar++)
2182 if (pci_resource_len(dev, bar) == 0x80 &&
2183 (pci_resource_start(dev, bar) & 0x80)) {
2184 struct resource *r = &dev->resource[bar];
2185 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2186 bar);
2187 r->flags |= IORESOURCE_UNSET;
2188 r->start = 0;
2189 r->end = 0xff;
2190 }
2191}
2192DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2193 quirk_plx_pci9050);
2194/*
2195 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2196 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2197 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2198 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2199 *
2200 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2201 * driver.
2202 */
2203DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2204DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2205
2206static void quirk_netmos(struct pci_dev *dev)
2207{
2208 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2209 unsigned int num_serial = dev->subsystem_device & 0xf;
2210
2211 /*
2212 * These Netmos parts are multiport serial devices with optional
2213 * parallel ports. Even when parallel ports are present, they
2214 * are identified as class SERIAL, which means the serial driver
2215 * will claim them. To prevent this, mark them as class OTHER.
2216 * These combo devices should be claimed by parport_serial.
2217 *
2218 * The subdevice ID is of the form 0x00PS, where <P> is the number
2219 * of parallel ports and <S> is the number of serial ports.
2220 */
2221 switch (dev->device) {
2222 case PCI_DEVICE_ID_NETMOS_9835:
2223 /* Well, this rule doesn't hold for the following 9835 device */
2224 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2225 dev->subsystem_device == 0x0299)
2226 return;
2227 fallthrough;
2228 case PCI_DEVICE_ID_NETMOS_9735:
2229 case PCI_DEVICE_ID_NETMOS_9745:
2230 case PCI_DEVICE_ID_NETMOS_9845:
2231 case PCI_DEVICE_ID_NETMOS_9855:
2232 if (num_parallel) {
2233 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2234 dev->device, num_parallel, num_serial);
2235 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2236 (dev->class & 0xff);
2237 }
2238 }
2239}
2240DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2241 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2242
2243static void quirk_e100_interrupt(struct pci_dev *dev)
2244{
2245 u16 command, pmcsr;
2246 u8 __iomem *csr;
2247 u8 cmd_hi;
2248
2249 switch (dev->device) {
2250 /* PCI IDs taken from drivers/net/e100.c */
2251 case 0x1029:
2252 case 0x1030 ... 0x1034:
2253 case 0x1038 ... 0x103E:
2254 case 0x1050 ... 0x1057:
2255 case 0x1059:
2256 case 0x1064 ... 0x106B:
2257 case 0x1091 ... 0x1095:
2258 case 0x1209:
2259 case 0x1229:
2260 case 0x2449:
2261 case 0x2459:
2262 case 0x245D:
2263 case 0x27DC:
2264 break;
2265 default:
2266 return;
2267 }
2268
2269 /*
2270 * Some firmware hands off the e100 with interrupts enabled,
2271 * which can cause a flood of interrupts if packets are
2272 * received before the driver attaches to the device. So
2273 * disable all e100 interrupts here. The driver will
2274 * re-enable them when it's ready.
2275 */
2276 pci_read_config_word(dev, PCI_COMMAND, &command);
2277
2278 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2279 return;
2280
2281 /*
2282 * Check that the device is in the D0 power state. If it's not,
2283 * there is no point to look any further.
2284 */
2285 if (dev->pm_cap) {
2286 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2287 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2288 return;
2289 }
2290
2291 /* Convert from PCI bus to resource space. */
2292 csr = ioremap(pci_resource_start(dev, 0), 8);
2293 if (!csr) {
2294 pci_warn(dev, "Can't map e100 registers\n");
2295 return;
2296 }
2297
2298 cmd_hi = readb(csr + 3);
2299 if (cmd_hi == 0) {
2300 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2301 writeb(1, csr + 3);
2302 }
2303
2304 iounmap(csr);
2305}
2306DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2307 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2308
2309/*
2310 * The 82575 and 82598 may experience data corruption issues when transitioning
2311 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2312 */
2313static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2314{
2315 pci_info(dev, "Disabling L0s\n");
2316 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2317}
2318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2329DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2330DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2332
2333static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2334{
2335 pci_info(dev, "Disabling ASPM L0s/L1\n");
2336 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2337}
2338
2339/*
2340 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2341 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2342 * disable both L0s and L1 for now to be safe.
2343 */
2344DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2345
2346/*
2347 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2348 * Link bit cleared after starting the link retrain process to allow this
2349 * process to finish.
2350 *
2351 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2352 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2353 */
2354static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2355{
2356 dev->clear_retrain_link = 1;
2357 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2358}
2359DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link);
2360DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link);
2361DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link);
2362
2363static void fixup_rev1_53c810(struct pci_dev *dev)
2364{
2365 u32 class = dev->class;
2366
2367 /*
2368 * rev 1 ncr53c810 chips don't set the class at all which means
2369 * they don't get their resources remapped. Fix that here.
2370 */
2371 if (class)
2372 return;
2373
2374 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2375 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2376 class, dev->class);
2377}
2378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2379
2380/* Enable 1k I/O space granularity on the Intel P64H2 */
2381static void quirk_p64h2_1k_io(struct pci_dev *dev)
2382{
2383 u16 en1k;
2384
2385 pci_read_config_word(dev, 0x40, &en1k);
2386
2387 if (en1k & 0x200) {
2388 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2389 dev->io_window_1k = 1;
2390 }
2391}
2392DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2393
2394/*
2395 * Under some circumstances, AER is not linked with extended capabilities.
2396 * Force it to be linked by setting the corresponding control bit in the
2397 * config space.
2398 */
2399static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2400{
2401 uint8_t b;
2402
2403 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2404 if (!(b & 0x20)) {
2405 pci_write_config_byte(dev, 0xf41, b | 0x20);
2406 pci_info(dev, "Linking AER extended capability\n");
2407 }
2408 }
2409}
2410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2411 quirk_nvidia_ck804_pcie_aer_ext_cap);
2412DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2413 quirk_nvidia_ck804_pcie_aer_ext_cap);
2414
2415static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2416{
2417 /*
2418 * Disable PCI Bus Parking and PCI Master read caching on CX700
2419 * which causes unspecified timing errors with a VT6212L on the PCI
2420 * bus leading to USB2.0 packet loss.
2421 *
2422 * This quirk is only enabled if a second (on the external PCI bus)
2423 * VT6212L is found -- the CX700 core itself also contains a USB
2424 * host controller with the same PCI ID as the VT6212L.
2425 */
2426
2427 /* Count VT6212L instances */
2428 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2429 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2430 uint8_t b;
2431
2432 /*
2433 * p should contain the first (internal) VT6212L -- see if we have
2434 * an external one by searching again.
2435 */
2436 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2437 if (!p)
2438 return;
2439 pci_dev_put(p);
2440
2441 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2442 if (b & 0x40) {
2443 /* Turn off PCI Bus Parking */
2444 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2445
2446 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2447 }
2448 }
2449
2450 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2451 if (b != 0) {
2452 /* Turn off PCI Master read caching */
2453 pci_write_config_byte(dev, 0x72, 0x0);
2454
2455 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2456 pci_write_config_byte(dev, 0x75, 0x1);
2457
2458 /* Disable "Read FIFO Timer" */
2459 pci_write_config_byte(dev, 0x77, 0x0);
2460
2461 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2462 }
2463 }
2464}
2465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2466
2467static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2468{
2469 u32 rev;
2470
2471 pci_read_config_dword(dev, 0xf4, &rev);
2472
2473 /* Only CAP the MRRS if the device is a 5719 A0 */
2474 if (rev == 0x05719000) {
2475 int readrq = pcie_get_readrq(dev);
2476 if (readrq > 2048)
2477 pcie_set_readrq(dev, 2048);
2478 }
2479}
2480DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2481 PCI_DEVICE_ID_TIGON3_5719,
2482 quirk_brcm_5719_limit_mrrs);
2483
2484/*
2485 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2486 * hide device 6 which configures the overflow device access containing the
2487 * DRBs - this is where we expose device 6.
2488 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2489 */
2490static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2491{
2492 u8 reg;
2493
2494 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2495 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2496 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2497 }
2498}
2499DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2500 quirk_unhide_mch_dev6);
2501DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2502 quirk_unhide_mch_dev6);
2503
2504#ifdef CONFIG_PCI_MSI
2505/*
2506 * Some chipsets do not support MSI. We cannot easily rely on setting
2507 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2508 * other buses controlled by the chipset even if Linux is not aware of it.
2509 * Instead of setting the flag on all buses in the machine, simply disable
2510 * MSI globally.
2511 */
2512static void quirk_disable_all_msi(struct pci_dev *dev)
2513{
2514 pci_no_msi();
2515 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2516}
2517DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2520DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2522DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2523DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2524DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2525
2526/* Disable MSI on chipsets that are known to not support it */
2527static void quirk_disable_msi(struct pci_dev *dev)
2528{
2529 if (dev->subordinate) {
2530 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2531 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2532 }
2533}
2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2536DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2537
2538/*
2539 * The APC bridge device in AMD 780 family northbridges has some random
2540 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2541 * we use the possible vendor/device IDs of the host bridge for the
2542 * declared quirk, and search for the APC bridge by slot number.
2543 */
2544static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2545{
2546 struct pci_dev *apc_bridge;
2547
2548 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2549 if (apc_bridge) {
2550 if (apc_bridge->device == 0x9602)
2551 quirk_disable_msi(apc_bridge);
2552 pci_dev_put(apc_bridge);
2553 }
2554}
2555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2557
2558/*
2559 * Go through the list of HyperTransport capabilities and return 1 if a HT
2560 * MSI capability is found and enabled.
2561 */
2562static int msi_ht_cap_enabled(struct pci_dev *dev)
2563{
2564 int pos, ttl = PCI_FIND_CAP_TTL;
2565
2566 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2567 while (pos && ttl--) {
2568 u8 flags;
2569
2570 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2571 &flags) == 0) {
2572 pci_info(dev, "Found %s HT MSI Mapping\n",
2573 flags & HT_MSI_FLAGS_ENABLE ?
2574 "enabled" : "disabled");
2575 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2576 }
2577
2578 pos = pci_find_next_ht_capability(dev, pos,
2579 HT_CAPTYPE_MSI_MAPPING);
2580 }
2581 return 0;
2582}
2583
2584/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2585static void quirk_msi_ht_cap(struct pci_dev *dev)
2586{
2587 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2588 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2589 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2590 }
2591}
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2593 quirk_msi_ht_cap);
2594
2595/*
2596 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2597 * if the MSI capability is set in any of these mappings.
2598 */
2599static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2600{
2601 struct pci_dev *pdev;
2602
2603 if (!dev->subordinate)
2604 return;
2605
2606 /*
2607 * Check HT MSI cap on this chipset and the root one. A single one
2608 * having MSI is enough to be sure that MSI is supported.
2609 */
2610 pdev = pci_get_slot(dev->bus, 0);
2611 if (!pdev)
2612 return;
2613 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2614 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2615 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2616 }
2617 pci_dev_put(pdev);
2618}
2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2620 quirk_nvidia_ck804_msi_ht_cap);
2621
2622/* Force enable MSI mapping capability on HT bridges */
2623static void ht_enable_msi_mapping(struct pci_dev *dev)
2624{
2625 int pos, ttl = PCI_FIND_CAP_TTL;
2626
2627 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2628 while (pos && ttl--) {
2629 u8 flags;
2630
2631 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2632 &flags) == 0) {
2633 pci_info(dev, "Enabling HT MSI Mapping\n");
2634
2635 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2636 flags | HT_MSI_FLAGS_ENABLE);
2637 }
2638 pos = pci_find_next_ht_capability(dev, pos,
2639 HT_CAPTYPE_MSI_MAPPING);
2640 }
2641}
2642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2643 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2644 ht_enable_msi_mapping);
2645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2646 ht_enable_msi_mapping);
2647
2648/*
2649 * The P5N32-SLI motherboards from Asus have a problem with MSI
2650 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2651 * also affects other devices. As for now, turn off MSI for this device.
2652 */
2653static void nvenet_msi_disable(struct pci_dev *dev)
2654{
2655 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2656
2657 if (board_name &&
2658 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2659 strstr(board_name, "P5N32-E SLI"))) {
2660 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2661 dev->no_msi = 1;
2662 }
2663}
2664DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2665 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2666 nvenet_msi_disable);
2667
2668/*
2669 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2670 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2671 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2672 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2673 * for other events, since PCIe specificiation doesn't support using a mix of
2674 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2675 * service drivers registering their respective ISRs for MSIs.
2676 */
2677static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2678{
2679 dev->no_msi = 1;
2680}
2681DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2682 PCI_CLASS_BRIDGE_PCI, 8,
2683 pci_quirk_nvidia_tegra_disable_rp_msi);
2684DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2685 PCI_CLASS_BRIDGE_PCI, 8,
2686 pci_quirk_nvidia_tegra_disable_rp_msi);
2687DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2688 PCI_CLASS_BRIDGE_PCI, 8,
2689 pci_quirk_nvidia_tegra_disable_rp_msi);
2690DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2691 PCI_CLASS_BRIDGE_PCI, 8,
2692 pci_quirk_nvidia_tegra_disable_rp_msi);
2693DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2694 PCI_CLASS_BRIDGE_PCI, 8,
2695 pci_quirk_nvidia_tegra_disable_rp_msi);
2696DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2697 PCI_CLASS_BRIDGE_PCI, 8,
2698 pci_quirk_nvidia_tegra_disable_rp_msi);
2699DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2700 PCI_CLASS_BRIDGE_PCI, 8,
2701 pci_quirk_nvidia_tegra_disable_rp_msi);
2702DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2703 PCI_CLASS_BRIDGE_PCI, 8,
2704 pci_quirk_nvidia_tegra_disable_rp_msi);
2705DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2706 PCI_CLASS_BRIDGE_PCI, 8,
2707 pci_quirk_nvidia_tegra_disable_rp_msi);
2708DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2709 PCI_CLASS_BRIDGE_PCI, 8,
2710 pci_quirk_nvidia_tegra_disable_rp_msi);
2711DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2712 PCI_CLASS_BRIDGE_PCI, 8,
2713 pci_quirk_nvidia_tegra_disable_rp_msi);
2714DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2715 PCI_CLASS_BRIDGE_PCI, 8,
2716 pci_quirk_nvidia_tegra_disable_rp_msi);
2717DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2718 PCI_CLASS_BRIDGE_PCI, 8,
2719 pci_quirk_nvidia_tegra_disable_rp_msi);
2720
2721/*
2722 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2723 * config register. This register controls the routing of legacy
2724 * interrupts from devices that route through the MCP55. If this register
2725 * is misprogrammed, interrupts are only sent to the BSP, unlike
2726 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2727 * having this register set properly prevents kdump from booting up
2728 * properly, so let's make sure that we have it set correctly.
2729 * Note that this is an undocumented register.
2730 */
2731static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2732{
2733 u32 cfg;
2734
2735 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2736 return;
2737
2738 pci_read_config_dword(dev, 0x74, &cfg);
2739
2740 if (cfg & ((1 << 2) | (1 << 15))) {
2741 pr_info("Rewriting IRQ routing register on MCP55\n");
2742 cfg &= ~((1 << 2) | (1 << 15));
2743 pci_write_config_dword(dev, 0x74, cfg);
2744 }
2745}
2746DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2747 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2748 nvbridge_check_legacy_irq_routing);
2749DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2750 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2751 nvbridge_check_legacy_irq_routing);
2752
2753static int ht_check_msi_mapping(struct pci_dev *dev)
2754{
2755 int pos, ttl = PCI_FIND_CAP_TTL;
2756 int found = 0;
2757
2758 /* Check if there is HT MSI cap or enabled on this device */
2759 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2760 while (pos && ttl--) {
2761 u8 flags;
2762
2763 if (found < 1)
2764 found = 1;
2765 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2766 &flags) == 0) {
2767 if (flags & HT_MSI_FLAGS_ENABLE) {
2768 if (found < 2) {
2769 found = 2;
2770 break;
2771 }
2772 }
2773 }
2774 pos = pci_find_next_ht_capability(dev, pos,
2775 HT_CAPTYPE_MSI_MAPPING);
2776 }
2777
2778 return found;
2779}
2780
2781static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2782{
2783 struct pci_dev *dev;
2784 int pos;
2785 int i, dev_no;
2786 int found = 0;
2787
2788 dev_no = host_bridge->devfn >> 3;
2789 for (i = dev_no + 1; i < 0x20; i++) {
2790 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2791 if (!dev)
2792 continue;
2793
2794 /* found next host bridge? */
2795 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2796 if (pos != 0) {
2797 pci_dev_put(dev);
2798 break;
2799 }
2800
2801 if (ht_check_msi_mapping(dev)) {
2802 found = 1;
2803 pci_dev_put(dev);
2804 break;
2805 }
2806 pci_dev_put(dev);
2807 }
2808
2809 return found;
2810}
2811
2812#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2813#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2814
2815static int is_end_of_ht_chain(struct pci_dev *dev)
2816{
2817 int pos, ctrl_off;
2818 int end = 0;
2819 u16 flags, ctrl;
2820
2821 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2822
2823 if (!pos)
2824 goto out;
2825
2826 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2827
2828 ctrl_off = ((flags >> 10) & 1) ?
2829 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2830 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2831
2832 if (ctrl & (1 << 6))
2833 end = 1;
2834
2835out:
2836 return end;
2837}
2838
2839static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2840{
2841 struct pci_dev *host_bridge;
2842 int pos;
2843 int i, dev_no;
2844 int found = 0;
2845
2846 dev_no = dev->devfn >> 3;
2847 for (i = dev_no; i >= 0; i--) {
2848 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2849 if (!host_bridge)
2850 continue;
2851
2852 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2853 if (pos != 0) {
2854 found = 1;
2855 break;
2856 }
2857 pci_dev_put(host_bridge);
2858 }
2859
2860 if (!found)
2861 return;
2862
2863 /* don't enable end_device/host_bridge with leaf directly here */
2864 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2865 host_bridge_with_leaf(host_bridge))
2866 goto out;
2867
2868 /* root did that ! */
2869 if (msi_ht_cap_enabled(host_bridge))
2870 goto out;
2871
2872 ht_enable_msi_mapping(dev);
2873
2874out:
2875 pci_dev_put(host_bridge);
2876}
2877
2878static void ht_disable_msi_mapping(struct pci_dev *dev)
2879{
2880 int pos, ttl = PCI_FIND_CAP_TTL;
2881
2882 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2883 while (pos && ttl--) {
2884 u8 flags;
2885
2886 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2887 &flags) == 0) {
2888 pci_info(dev, "Disabling HT MSI Mapping\n");
2889
2890 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2891 flags & ~HT_MSI_FLAGS_ENABLE);
2892 }
2893 pos = pci_find_next_ht_capability(dev, pos,
2894 HT_CAPTYPE_MSI_MAPPING);
2895 }
2896}
2897
2898static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2899{
2900 struct pci_dev *host_bridge;
2901 int pos;
2902 int found;
2903
2904 if (!pci_msi_enabled())
2905 return;
2906
2907 /* check if there is HT MSI cap or enabled on this device */
2908 found = ht_check_msi_mapping(dev);
2909
2910 /* no HT MSI CAP */
2911 if (found == 0)
2912 return;
2913
2914 /*
2915 * HT MSI mapping should be disabled on devices that are below
2916 * a non-Hypertransport host bridge. Locate the host bridge...
2917 */
2918 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2919 PCI_DEVFN(0, 0));
2920 if (host_bridge == NULL) {
2921 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2922 return;
2923 }
2924
2925 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2926 if (pos != 0) {
2927 /* Host bridge is to HT */
2928 if (found == 1) {
2929 /* it is not enabled, try to enable it */
2930 if (all)
2931 ht_enable_msi_mapping(dev);
2932 else
2933 nv_ht_enable_msi_mapping(dev);
2934 }
2935 goto out;
2936 }
2937
2938 /* HT MSI is not enabled */
2939 if (found == 1)
2940 goto out;
2941
2942 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2943 ht_disable_msi_mapping(dev);
2944
2945out:
2946 pci_dev_put(host_bridge);
2947}
2948
2949static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2950{
2951 return __nv_msi_ht_cap_quirk(dev, 1);
2952}
2953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2954DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2955
2956static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2957{
2958 return __nv_msi_ht_cap_quirk(dev, 0);
2959}
2960DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2961DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2962
2963static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2964{
2965 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2966}
2967
2968static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2969{
2970 struct pci_dev *p;
2971
2972 /*
2973 * SB700 MSI issue will be fixed at HW level from revision A21;
2974 * we need check PCI REVISION ID of SMBus controller to get SB700
2975 * revision.
2976 */
2977 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2978 NULL);
2979 if (!p)
2980 return;
2981
2982 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2983 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2984 pci_dev_put(p);
2985}
2986
2987static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2988{
2989 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2990 if (dev->revision < 0x18) {
2991 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2992 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2993 }
2994}
2995DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2996 PCI_DEVICE_ID_TIGON3_5780,
2997 quirk_msi_intx_disable_bug);
2998DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2999 PCI_DEVICE_ID_TIGON3_5780S,
3000 quirk_msi_intx_disable_bug);
3001DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3002 PCI_DEVICE_ID_TIGON3_5714,
3003 quirk_msi_intx_disable_bug);
3004DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3005 PCI_DEVICE_ID_TIGON3_5714S,
3006 quirk_msi_intx_disable_bug);
3007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3008 PCI_DEVICE_ID_TIGON3_5715,
3009 quirk_msi_intx_disable_bug);
3010DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3011 PCI_DEVICE_ID_TIGON3_5715S,
3012 quirk_msi_intx_disable_bug);
3013
3014DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3015 quirk_msi_intx_disable_ati_bug);
3016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3017 quirk_msi_intx_disable_ati_bug);
3018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3019 quirk_msi_intx_disable_ati_bug);
3020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3021 quirk_msi_intx_disable_ati_bug);
3022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3023 quirk_msi_intx_disable_ati_bug);
3024
3025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3026 quirk_msi_intx_disable_bug);
3027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3028 quirk_msi_intx_disable_bug);
3029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3030 quirk_msi_intx_disable_bug);
3031
3032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3033 quirk_msi_intx_disable_bug);
3034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3035 quirk_msi_intx_disable_bug);
3036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3037 quirk_msi_intx_disable_bug);
3038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3039 quirk_msi_intx_disable_bug);
3040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3041 quirk_msi_intx_disable_bug);
3042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3043 quirk_msi_intx_disable_bug);
3044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3045 quirk_msi_intx_disable_qca_bug);
3046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3047 quirk_msi_intx_disable_qca_bug);
3048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3049 quirk_msi_intx_disable_qca_bug);
3050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3051 quirk_msi_intx_disable_qca_bug);
3052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3053 quirk_msi_intx_disable_qca_bug);
3054
3055/*
3056 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3057 * should be disabled on platforms where the device (mistakenly) advertises it.
3058 *
3059 * Notice that this quirk also disables MSI (which may work, but hasn't been
3060 * tested), since currently there is no standard way to disable only MSI-X.
3061 *
3062 * The 0031 device id is reused for other non Root Port device types,
3063 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3064 */
3065static void quirk_al_msi_disable(struct pci_dev *dev)
3066{
3067 dev->no_msi = 1;
3068 pci_warn(dev, "Disabling MSI/MSI-X\n");
3069}
3070DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3071 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3072#endif /* CONFIG_PCI_MSI */
3073
3074/*
3075 * Allow manual resource allocation for PCI hotplug bridges via
3076 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3077 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3078 * allocate resources when hotplug device is inserted and PCI bus is
3079 * rescanned.
3080 */
3081static void quirk_hotplug_bridge(struct pci_dev *dev)
3082{
3083 dev->is_hotplug_bridge = 1;
3084}
3085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3086
3087/*
3088 * This is a quirk for the Ricoh MMC controller found as a part of some
3089 * multifunction chips.
3090 *
3091 * This is very similar and based on the ricoh_mmc driver written by
3092 * Philip Langdale. Thank you for these magic sequences.
3093 *
3094 * These chips implement the four main memory card controllers (SD, MMC,
3095 * MS, xD) and one or both of CardBus or FireWire.
3096 *
3097 * It happens that they implement SD and MMC support as separate
3098 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3099 * cards but the chip detects MMC cards in hardware and directs them to the
3100 * MMC controller - so the SDHCI driver never sees them.
3101 *
3102 * To get around this, we must disable the useless MMC controller. At that
3103 * point, the SDHCI controller will start seeing them. It seems to be the
3104 * case that the relevant PCI registers to deactivate the MMC controller
3105 * live on PCI function 0, which might be the CardBus controller or the
3106 * FireWire controller, depending on the particular chip in question
3107 *
3108 * This has to be done early, because as soon as we disable the MMC controller
3109 * other PCI functions shift up one level, e.g. function #2 becomes function
3110 * #1, and this will confuse the PCI core.
3111 */
3112#ifdef CONFIG_MMC_RICOH_MMC
3113static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3114{
3115 u8 write_enable;
3116 u8 write_target;
3117 u8 disable;
3118
3119 /*
3120 * Disable via CardBus interface
3121 *
3122 * This must be done via function #0
3123 */
3124 if (PCI_FUNC(dev->devfn))
3125 return;
3126
3127 pci_read_config_byte(dev, 0xB7, &disable);
3128 if (disable & 0x02)
3129 return;
3130
3131 pci_read_config_byte(dev, 0x8E, &write_enable);
3132 pci_write_config_byte(dev, 0x8E, 0xAA);
3133 pci_read_config_byte(dev, 0x8D, &write_target);
3134 pci_write_config_byte(dev, 0x8D, 0xB7);
3135 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3136 pci_write_config_byte(dev, 0x8E, write_enable);
3137 pci_write_config_byte(dev, 0x8D, write_target);
3138
3139 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3140 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3141}
3142DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3143DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3144
3145static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3146{
3147 u8 write_enable;
3148 u8 disable;
3149
3150 /*
3151 * Disable via FireWire interface
3152 *
3153 * This must be done via function #0
3154 */
3155 if (PCI_FUNC(dev->devfn))
3156 return;
3157 /*
3158 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3159 * certain types of SD/MMC cards. Lowering the SD base clock
3160 * frequency from 200Mhz to 50Mhz fixes this issue.
3161 *
3162 * 0x150 - SD2.0 mode enable for changing base clock
3163 * frequency to 50Mhz
3164 * 0xe1 - Base clock frequency
3165 * 0x32 - 50Mhz new clock frequency
3166 * 0xf9 - Key register for 0x150
3167 * 0xfc - key register for 0xe1
3168 */
3169 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3170 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3171 pci_write_config_byte(dev, 0xf9, 0xfc);
3172 pci_write_config_byte(dev, 0x150, 0x10);
3173 pci_write_config_byte(dev, 0xf9, 0x00);
3174 pci_write_config_byte(dev, 0xfc, 0x01);
3175 pci_write_config_byte(dev, 0xe1, 0x32);
3176 pci_write_config_byte(dev, 0xfc, 0x00);
3177
3178 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3179 }
3180
3181 pci_read_config_byte(dev, 0xCB, &disable);
3182
3183 if (disable & 0x02)
3184 return;
3185
3186 pci_read_config_byte(dev, 0xCA, &write_enable);
3187 pci_write_config_byte(dev, 0xCA, 0x57);
3188 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3189 pci_write_config_byte(dev, 0xCA, write_enable);
3190
3191 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3192 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3193
3194}
3195DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3196DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3197DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3198DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3199DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3200DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3201#endif /*CONFIG_MMC_RICOH_MMC*/
3202
3203#ifdef CONFIG_DMAR_TABLE
3204#define VTUNCERRMSK_REG 0x1ac
3205#define VTD_MSK_SPEC_ERRORS (1 << 31)
3206/*
3207 * This is a quirk for masking VT-d spec-defined errors to platform error
3208 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3209 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3210 * on the RAS config settings of the platform) when a VT-d fault happens.
3211 * The resulting SMI caused the system to hang.
3212 *
3213 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3214 * need to report the same error through other channels.
3215 */
3216static void vtd_mask_spec_errors(struct pci_dev *dev)
3217{
3218 u32 word;
3219
3220 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3221 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3222}
3223DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3224DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3225#endif
3226
3227static void fixup_ti816x_class(struct pci_dev *dev)
3228{
3229 u32 class = dev->class;
3230
3231 /* TI 816x devices do not have class code set when in PCIe boot mode */
3232 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3233 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3234 class, dev->class);
3235}
3236DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3237 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3238
3239/*
3240 * Some PCIe devices do not work reliably with the claimed maximum
3241 * payload size supported.
3242 */
3243static void fixup_mpss_256(struct pci_dev *dev)
3244{
3245 dev->pcie_mpss = 1; /* 256 bytes */
3246}
3247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3248 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3250 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3251DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3252 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3253
3254/*
3255 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3256 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3257 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3258 * until all of the devices are discovered and buses walked, read completion
3259 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3260 * it is possible to hotplug a device with MPS of 256B.
3261 */
3262static void quirk_intel_mc_errata(struct pci_dev *dev)
3263{
3264 int err;
3265 u16 rcc;
3266
3267 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3268 pcie_bus_config == PCIE_BUS_DEFAULT)
3269 return;
3270
3271 /*
3272 * Intel erratum specifies bits to change but does not say what
3273 * they are. Keeping them magical until such time as the registers
3274 * and values can be explained.
3275 */
3276 err = pci_read_config_word(dev, 0x48, &rcc);
3277 if (err) {
3278 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3279 return;
3280 }
3281
3282 if (!(rcc & (1 << 10)))
3283 return;
3284
3285 rcc &= ~(1 << 10);
3286
3287 err = pci_write_config_word(dev, 0x48, rcc);
3288 if (err) {
3289 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3290 return;
3291 }
3292
3293 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3294}
3295/* Intel 5000 series memory controllers and ports 2-7 */
3296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3302DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3310/* Intel 5100 series memory controllers and ports 2-7 */
3311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3322
3323/*
3324 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3325 * To work around this, query the size it should be configured to by the
3326 * device and modify the resource end to correspond to this new size.
3327 */
3328static void quirk_intel_ntb(struct pci_dev *dev)
3329{
3330 int rc;
3331 u8 val;
3332
3333 rc = pci_read_config_byte(dev, 0x00D0, &val);
3334 if (rc)
3335 return;
3336
3337 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3338
3339 rc = pci_read_config_byte(dev, 0x00D1, &val);
3340 if (rc)
3341 return;
3342
3343 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3344}
3345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3347
3348/*
3349 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3350 * though no one is handling them (e.g., if the i915 driver is never
3351 * loaded). Additionally the interrupt destination is not set up properly
3352 * and the interrupt ends up -somewhere-.
3353 *
3354 * These spurious interrupts are "sticky" and the kernel disables the
3355 * (shared) interrupt line after 100,000+ generated interrupts.
3356 *
3357 * Fix it by disabling the still enabled interrupts. This resolves crashes
3358 * often seen on monitor unplug.
3359 */
3360#define I915_DEIER_REG 0x4400c
3361static void disable_igfx_irq(struct pci_dev *dev)
3362{
3363 void __iomem *regs = pci_iomap(dev, 0, 0);
3364 if (regs == NULL) {
3365 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3366 return;
3367 }
3368
3369 /* Check if any interrupt line is still enabled */
3370 if (readl(regs + I915_DEIER_REG) != 0) {
3371 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3372
3373 writel(0, regs + I915_DEIER_REG);
3374 }
3375
3376 pci_iounmap(dev, regs);
3377}
3378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3385
3386/*
3387 * PCI devices which are on Intel chips can skip the 10ms delay
3388 * before entering D3 mode.
3389 */
3390static void quirk_remove_d3_delay(struct pci_dev *dev)
3391{
3392 dev->d3_delay = 0;
3393}
3394/* C600 Series devices do not need 10ms d3_delay */
3395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3398/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3410/* Intel Cherrytrail devices do not need 10ms d3_delay */
3411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3412DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3414DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3415DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3416DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3417DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3419DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3420
3421/*
3422 * Some devices may pass our check in pci_intx_mask_supported() if
3423 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3424 * support this feature.
3425 */
3426static void quirk_broken_intx_masking(struct pci_dev *dev)
3427{
3428 dev->broken_intx_masking = 1;
3429}
3430DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3431 quirk_broken_intx_masking);
3432DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3433 quirk_broken_intx_masking);
3434DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3435 quirk_broken_intx_masking);
3436
3437/*
3438 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3439 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3440 *
3441 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3442 */
3443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3444 quirk_broken_intx_masking);
3445
3446/*
3447 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3448 * DisINTx can be set but the interrupt status bit is non-functional.
3449 */
3450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3453DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3458DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3466
3467static u16 mellanox_broken_intx_devs[] = {
3468 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3469 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3470 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3471 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3472 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3473 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3474 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3475 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3476 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3477 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3478 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3479 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3480 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3481 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3482};
3483
3484#define CONNECTX_4_CURR_MAX_MINOR 99
3485#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3486
3487/*
3488 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3489 * If so, don't mark it as broken.
3490 * FW minor > 99 means older FW version format and no INTx masking support.
3491 * FW minor < 14 means new FW version format and no INTx masking support.
3492 */
3493static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3494{
3495 __be32 __iomem *fw_ver;
3496 u16 fw_major;
3497 u16 fw_minor;
3498 u16 fw_subminor;
3499 u32 fw_maj_min;
3500 u32 fw_sub_min;
3501 int i;
3502
3503 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3504 if (pdev->device == mellanox_broken_intx_devs[i]) {
3505 pdev->broken_intx_masking = 1;
3506 return;
3507 }
3508 }
3509
3510 /*
3511 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3512 * support so shouldn't be checked further
3513 */
3514 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3515 return;
3516
3517 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3518 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3519 return;
3520
3521 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3522 if (pci_enable_device_mem(pdev)) {
3523 pci_warn(pdev, "Can't enable device memory\n");
3524 return;
3525 }
3526
3527 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3528 if (!fw_ver) {
3529 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3530 goto out;
3531 }
3532
3533 /* Reading from resource space should be 32b aligned */
3534 fw_maj_min = ioread32be(fw_ver);
3535 fw_sub_min = ioread32be(fw_ver + 1);
3536 fw_major = fw_maj_min & 0xffff;
3537 fw_minor = fw_maj_min >> 16;
3538 fw_subminor = fw_sub_min & 0xffff;
3539 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3540 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3541 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3542 fw_major, fw_minor, fw_subminor, pdev->device ==
3543 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3544 pdev->broken_intx_masking = 1;
3545 }
3546
3547 iounmap(fw_ver);
3548
3549out:
3550 pci_disable_device(pdev);
3551}
3552DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3553 mellanox_check_broken_intx_masking);
3554
3555static void quirk_no_bus_reset(struct pci_dev *dev)
3556{
3557 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3558}
3559
3560/*
3561 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3562 * The device will throw a Link Down error on AER-capable systems and
3563 * regardless of AER, config space of the device is never accessible again
3564 * and typically causes the system to hang or reset when access is attempted.
3565 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3566 */
3567DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3568DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3569DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3570DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3571DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3572
3573/*
3574 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3575 * reset when used with certain child devices. After the reset, config
3576 * accesses to the child may fail.
3577 */
3578DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3579
3580static void quirk_no_pm_reset(struct pci_dev *dev)
3581{
3582 /*
3583 * We can't do a bus reset on root bus devices, but an ineffective
3584 * PM reset may be better than nothing.
3585 */
3586 if (!pci_is_root_bus(dev->bus))
3587 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3588}
3589
3590/*
3591 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3592 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3593 * to have no effect on the device: it retains the framebuffer contents and
3594 * monitor sync. Advertising this support makes other layers, like VFIO,
3595 * assume pci_reset_function() is viable for this device. Mark it as
3596 * unavailable to skip it when testing reset methods.
3597 */
3598DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3599 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3600
3601/*
3602 * Thunderbolt controllers with broken MSI hotplug signaling:
3603 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3604 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3605 */
3606static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3607{
3608 if (pdev->is_hotplug_bridge &&
3609 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3610 pdev->revision <= 1))
3611 pdev->no_msi = 1;
3612}
3613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3614 quirk_thunderbolt_hotplug_msi);
3615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3616 quirk_thunderbolt_hotplug_msi);
3617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3618 quirk_thunderbolt_hotplug_msi);
3619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3620 quirk_thunderbolt_hotplug_msi);
3621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3622 quirk_thunderbolt_hotplug_msi);
3623
3624#ifdef CONFIG_ACPI
3625/*
3626 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3627 *
3628 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3629 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3630 * be present after resume if a device was plugged in before suspend.
3631 *
3632 * The Thunderbolt controller consists of a PCIe switch with downstream
3633 * bridges leading to the NHI and to the tunnel PCI bridges.
3634 *
3635 * This quirk cuts power to the whole chip. Therefore we have to apply it
3636 * during suspend_noirq of the upstream bridge.
3637 *
3638 * Power is automagically restored before resume. No action is needed.
3639 */
3640static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3641{
3642 acpi_handle bridge, SXIO, SXFP, SXLV;
3643
3644 if (!x86_apple_machine)
3645 return;
3646 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3647 return;
3648 bridge = ACPI_HANDLE(&dev->dev);
3649 if (!bridge)
3650 return;
3651
3652 /*
3653 * SXIO and SXLV are present only on machines requiring this quirk.
3654 * Thunderbolt bridges in external devices might have the same
3655 * device ID as those on the host, but they will not have the
3656 * associated ACPI methods. This implicitly checks that we are at
3657 * the right bridge.
3658 */
3659 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3660 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3661 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3662 return;
3663 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3664
3665 /* magic sequence */
3666 acpi_execute_simple_method(SXIO, NULL, 1);
3667 acpi_execute_simple_method(SXFP, NULL, 0);
3668 msleep(300);
3669 acpi_execute_simple_method(SXLV, NULL, 0);
3670 acpi_execute_simple_method(SXIO, NULL, 0);
3671 acpi_execute_simple_method(SXLV, NULL, 0);
3672}
3673DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3674 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3675 quirk_apple_poweroff_thunderbolt);
3676
3677/*
3678 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3679 *
3680 * During suspend the Thunderbolt controller is reset and all PCI
3681 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3682 * during resume. We have to manually wait for the NHI since there is
3683 * no parent child relationship between the NHI and the tunneled
3684 * bridges.
3685 */
3686static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3687{
3688 struct pci_dev *sibling = NULL;
3689 struct pci_dev *nhi = NULL;
3690
3691 if (!x86_apple_machine)
3692 return;
3693 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3694 return;
3695
3696 /*
3697 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3698 * host controller and not on a Thunderbolt endpoint.
3699 */
3700 sibling = pci_get_slot(dev->bus, 0x0);
3701 if (sibling == dev)
3702 goto out; /* we are the downstream bridge to the NHI */
3703 if (!sibling || !sibling->subordinate)
3704 goto out;
3705 nhi = pci_get_slot(sibling->subordinate, 0x0);
3706 if (!nhi)
3707 goto out;
3708 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3709 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3710 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3711 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3712 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3713 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3714 goto out;
3715 pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3716 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3717out:
3718 pci_dev_put(nhi);
3719 pci_dev_put(sibling);
3720}
3721DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3722 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3723 quirk_apple_wait_for_thunderbolt);
3724DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3725 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3726 quirk_apple_wait_for_thunderbolt);
3727DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3728 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3729 quirk_apple_wait_for_thunderbolt);
3730DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3731 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3732 quirk_apple_wait_for_thunderbolt);
3733#endif
3734
3735/*
3736 * Following are device-specific reset methods which can be used to
3737 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3738 * not available.
3739 */
3740static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3741{
3742 /*
3743 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3744 *
3745 * The 82599 supports FLR on VFs, but FLR support is reported only
3746 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3747 * Thus we must call pcie_flr() directly without first checking if it is
3748 * supported.
3749 */
3750 if (!probe)
3751 pcie_flr(dev);
3752 return 0;
3753}
3754
3755#define SOUTH_CHICKEN2 0xc2004
3756#define PCH_PP_STATUS 0xc7200
3757#define PCH_PP_CONTROL 0xc7204
3758#define MSG_CTL 0x45010
3759#define NSDE_PWR_STATE 0xd0100
3760#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3761
3762static int reset_ivb_igd(struct pci_dev *dev, int probe)
3763{
3764 void __iomem *mmio_base;
3765 unsigned long timeout;
3766 u32 val;
3767
3768 if (probe)
3769 return 0;
3770
3771 mmio_base = pci_iomap(dev, 0, 0);
3772 if (!mmio_base)
3773 return -ENOMEM;
3774
3775 iowrite32(0x00000002, mmio_base + MSG_CTL);
3776
3777 /*
3778 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3779 * driver loaded sets the right bits. However, this's a reset and
3780 * the bits have been set by i915 previously, so we clobber
3781 * SOUTH_CHICKEN2 register directly here.
3782 */
3783 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3784
3785 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3786 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3787
3788 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3789 do {
3790 val = ioread32(mmio_base + PCH_PP_STATUS);
3791 if ((val & 0xb0000000) == 0)
3792 goto reset_complete;
3793 msleep(10);
3794 } while (time_before(jiffies, timeout));
3795 pci_warn(dev, "timeout during reset\n");
3796
3797reset_complete:
3798 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3799
3800 pci_iounmap(dev, mmio_base);
3801 return 0;
3802}
3803
3804/* Device-specific reset method for Chelsio T4-based adapters */
3805static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3806{
3807 u16 old_command;
3808 u16 msix_flags;
3809
3810 /*
3811 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3812 * that we have no device-specific reset method.
3813 */
3814 if ((dev->device & 0xf000) != 0x4000)
3815 return -ENOTTY;
3816
3817 /*
3818 * If this is the "probe" phase, return 0 indicating that we can
3819 * reset this device.
3820 */
3821 if (probe)
3822 return 0;
3823
3824 /*
3825 * T4 can wedge if there are DMAs in flight within the chip and Bus
3826 * Master has been disabled. We need to have it on till the Function
3827 * Level Reset completes. (BUS_MASTER is disabled in
3828 * pci_reset_function()).
3829 */
3830 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3831 pci_write_config_word(dev, PCI_COMMAND,
3832 old_command | PCI_COMMAND_MASTER);
3833
3834 /*
3835 * Perform the actual device function reset, saving and restoring
3836 * configuration information around the reset.
3837 */
3838 pci_save_state(dev);
3839
3840 /*
3841 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3842 * are disabled when an MSI-X interrupt message needs to be delivered.
3843 * So we briefly re-enable MSI-X interrupts for the duration of the
3844 * FLR. The pci_restore_state() below will restore the original
3845 * MSI-X state.
3846 */
3847 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3848 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3849 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3850 msix_flags |
3851 PCI_MSIX_FLAGS_ENABLE |
3852 PCI_MSIX_FLAGS_MASKALL);
3853
3854 pcie_flr(dev);
3855
3856 /*
3857 * Restore the configuration information (BAR values, etc.) including
3858 * the original PCI Configuration Space Command word, and return
3859 * success.
3860 */
3861 pci_restore_state(dev);
3862 pci_write_config_word(dev, PCI_COMMAND, old_command);
3863 return 0;
3864}
3865
3866#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3867#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3868#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3869
3870/*
3871 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3872 * FLR where config space reads from the device return -1. We seem to be
3873 * able to avoid this condition if we disable the NVMe controller prior to
3874 * FLR. This quirk is generic for any NVMe class device requiring similar
3875 * assistance to quiesce the device prior to FLR.
3876 *
3877 * NVMe specification: https://nvmexpress.org/resources/specifications/
3878 * Revision 1.0e:
3879 * Chapter 2: Required and optional PCI config registers
3880 * Chapter 3: NVMe control registers
3881 * Chapter 7.3: Reset behavior
3882 */
3883static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3884{
3885 void __iomem *bar;
3886 u16 cmd;
3887 u32 cfg;
3888
3889 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3890 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3891 return -ENOTTY;
3892
3893 if (probe)
3894 return 0;
3895
3896 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3897 if (!bar)
3898 return -ENOTTY;
3899
3900 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3901 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3902
3903 cfg = readl(bar + NVME_REG_CC);
3904
3905 /* Disable controller if enabled */
3906 if (cfg & NVME_CC_ENABLE) {
3907 u32 cap = readl(bar + NVME_REG_CAP);
3908 unsigned long timeout;
3909
3910 /*
3911 * Per nvme_disable_ctrl() skip shutdown notification as it
3912 * could complete commands to the admin queue. We only intend
3913 * to quiesce the device before reset.
3914 */
3915 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3916
3917 writel(cfg, bar + NVME_REG_CC);
3918
3919 /*
3920 * Some controllers require an additional delay here, see
3921 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3922 * supported by this quirk.
3923 */
3924
3925 /* Cap register provides max timeout in 500ms increments */
3926 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3927
3928 for (;;) {
3929 u32 status = readl(bar + NVME_REG_CSTS);
3930
3931 /* Ready status becomes zero on disable complete */
3932 if (!(status & NVME_CSTS_RDY))
3933 break;
3934
3935 msleep(100);
3936
3937 if (time_after(jiffies, timeout)) {
3938 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3939 break;
3940 }
3941 }
3942 }
3943
3944 pci_iounmap(dev, bar);
3945
3946 pcie_flr(dev);
3947
3948 return 0;
3949}
3950
3951/*
3952 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3953 * to change after NVMe enable if the driver starts interacting with the
3954 * device too soon after FLR. A 250ms delay after FLR has heuristically
3955 * proven to produce reliably working results for device assignment cases.
3956 */
3957static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3958{
3959 if (!pcie_has_flr(dev))
3960 return -ENOTTY;
3961
3962 if (probe)
3963 return 0;
3964
3965 pcie_flr(dev);
3966
3967 msleep(250);
3968
3969 return 0;
3970}
3971
3972static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3973 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3974 reset_intel_82599_sfp_virtfn },
3975 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3976 reset_ivb_igd },
3977 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3978 reset_ivb_igd },
3979 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3980 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3981 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3982 reset_chelsio_generic_dev },
3983 { 0 }
3984};
3985
3986/*
3987 * These device-specific reset methods are here rather than in a driver
3988 * because when a host assigns a device to a guest VM, the host may need
3989 * to reset the device but probably doesn't have a driver for it.
3990 */
3991int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3992{
3993 const struct pci_dev_reset_methods *i;
3994
3995 for (i = pci_dev_reset_methods; i->reset; i++) {
3996 if ((i->vendor == dev->vendor ||
3997 i->vendor == (u16)PCI_ANY_ID) &&
3998 (i->device == dev->device ||
3999 i->device == (u16)PCI_ANY_ID))
4000 return i->reset(dev, probe);
4001 }
4002
4003 return -ENOTTY;
4004}
4005
4006static void quirk_dma_func0_alias(struct pci_dev *dev)
4007{
4008 if (PCI_FUNC(dev->devfn) != 0)
4009 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4010}
4011
4012/*
4013 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4014 *
4015 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4016 */
4017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4019
4020static void quirk_dma_func1_alias(struct pci_dev *dev)
4021{
4022 if (PCI_FUNC(dev->devfn) != 1)
4023 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4024}
4025
4026/*
4027 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4028 * SKUs function 1 is present and is a legacy IDE controller, in other
4029 * SKUs this function is not present, making this a ghost requester.
4030 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4031 */
4032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4033 quirk_dma_func1_alias);
4034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4035 quirk_dma_func1_alias);
4036DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4037 quirk_dma_func1_alias);
4038/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4039DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4040 quirk_dma_func1_alias);
4041DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4042 quirk_dma_func1_alias);
4043/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4044DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4045 quirk_dma_func1_alias);
4046/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4047DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4048 quirk_dma_func1_alias);
4049/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4051 quirk_dma_func1_alias);
4052/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4054 quirk_dma_func1_alias);
4055/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4057 quirk_dma_func1_alias);
4058/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4060 quirk_dma_func1_alias);
4061/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4063 quirk_dma_func1_alias);
4064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4065 quirk_dma_func1_alias);
4066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4067 quirk_dma_func1_alias);
4068/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4070 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4071 quirk_dma_func1_alias);
4072/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4073DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4074 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4075 quirk_dma_func1_alias);
4076
4077/*
4078 * Some devices DMA with the wrong devfn, not just the wrong function.
4079 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4080 * the alias is "fixed" and independent of the device devfn.
4081 *
4082 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4083 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4084 * single device on the secondary bus. In reality, the single exposed
4085 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4086 * that provides a bridge to the internal bus of the I/O processor. The
4087 * controller supports private devices, which can be hidden from PCI config
4088 * space. In the case of the Adaptec 3405, a private device at 01.0
4089 * appears to be the DMA engine, which therefore needs to become a DMA
4090 * alias for the device.
4091 */
4092static const struct pci_device_id fixed_dma_alias_tbl[] = {
4093 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4094 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4095 .driver_data = PCI_DEVFN(1, 0) },
4096 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4097 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4098 .driver_data = PCI_DEVFN(1, 0) },
4099 { 0 }
4100};
4101
4102static void quirk_fixed_dma_alias(struct pci_dev *dev)
4103{
4104 const struct pci_device_id *id;
4105
4106 id = pci_match_id(fixed_dma_alias_tbl, dev);
4107 if (id)
4108 pci_add_dma_alias(dev, id->driver_data, 1);
4109}
4110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4111
4112/*
4113 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4114 * using the wrong DMA alias for the device. Some of these devices can be
4115 * used as either forward or reverse bridges, so we need to test whether the
4116 * device is operating in the correct mode. We could probably apply this
4117 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4118 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4119 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4120 */
4121static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4122{
4123 if (!pci_is_root_bus(pdev->bus) &&
4124 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4125 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4126 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4127 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4128}
4129/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4131 quirk_use_pcie_bridge_dma_alias);
4132/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4133DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4134/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4135DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4136/* ITE 8893 has the same problem as the 8892 */
4137DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4138/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4139DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4140
4141/*
4142 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4143 * be added as aliases to the DMA device in order to allow buffer access
4144 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4145 * programmed in the EEPROM.
4146 */
4147static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4148{
4149 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4150 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4151 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4152}
4153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4154DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4155
4156/*
4157 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4158 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4159 *
4160 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4161 * when IOMMU is enabled. These aliases allow computational unit access to
4162 * host memory. These aliases mark the whole VCA device as one IOMMU
4163 * group.
4164 *
4165 * All possible slot numbers (0x20) are used, since we are unable to tell
4166 * what slot is used on other side. This quirk is intended for both host
4167 * and computational unit sides. The VCA devices have up to five functions
4168 * (four for DMA channels and one additional).
4169 */
4170static void quirk_pex_vca_alias(struct pci_dev *pdev)
4171{
4172 const unsigned int num_pci_slots = 0x20;
4173 unsigned int slot;
4174
4175 for (slot = 0; slot < num_pci_slots; slot++)
4176 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4177}
4178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4181DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4184
4185/*
4186 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4187 * associated not at the root bus, but at a bridge below. This quirk avoids
4188 * generating invalid DMA aliases.
4189 */
4190static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4191{
4192 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4193}
4194DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4195 quirk_bridge_cavm_thrx2_pcie_root);
4196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4197 quirk_bridge_cavm_thrx2_pcie_root);
4198
4199/*
4200 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4201 * class code. Fix it.
4202 */
4203static void quirk_tw686x_class(struct pci_dev *pdev)
4204{
4205 u32 class = pdev->class;
4206
4207 /* Use "Multimedia controller" class */
4208 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4209 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4210 class, pdev->class);
4211}
4212DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4213 quirk_tw686x_class);
4214DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4215 quirk_tw686x_class);
4216DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4217 quirk_tw686x_class);
4218DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4219 quirk_tw686x_class);
4220
4221/*
4222 * Some devices have problems with Transaction Layer Packets with the Relaxed
4223 * Ordering Attribute set. Such devices should mark themselves and other
4224 * device drivers should check before sending TLPs with RO set.
4225 */
4226static void quirk_relaxedordering_disable(struct pci_dev *dev)
4227{
4228 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4229 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4230}
4231
4232/*
4233 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4234 * Complex have a Flow Control Credit issue which can cause performance
4235 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4236 */
4237DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4238 quirk_relaxedordering_disable);
4239DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4240 quirk_relaxedordering_disable);
4241DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4242 quirk_relaxedordering_disable);
4243DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4244 quirk_relaxedordering_disable);
4245DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4246 quirk_relaxedordering_disable);
4247DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4248 quirk_relaxedordering_disable);
4249DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4250 quirk_relaxedordering_disable);
4251DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4252 quirk_relaxedordering_disable);
4253DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4254 quirk_relaxedordering_disable);
4255DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4256 quirk_relaxedordering_disable);
4257DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4258 quirk_relaxedordering_disable);
4259DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4260 quirk_relaxedordering_disable);
4261DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4262 quirk_relaxedordering_disable);
4263DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4264 quirk_relaxedordering_disable);
4265DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4266 quirk_relaxedordering_disable);
4267DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4268 quirk_relaxedordering_disable);
4269DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4270 quirk_relaxedordering_disable);
4271DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4272 quirk_relaxedordering_disable);
4273DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4274 quirk_relaxedordering_disable);
4275DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4276 quirk_relaxedordering_disable);
4277DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4278 quirk_relaxedordering_disable);
4279DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4280 quirk_relaxedordering_disable);
4281DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4282 quirk_relaxedordering_disable);
4283DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4284 quirk_relaxedordering_disable);
4285DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4286 quirk_relaxedordering_disable);
4287DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4288 quirk_relaxedordering_disable);
4289DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4290 quirk_relaxedordering_disable);
4291DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4292 quirk_relaxedordering_disable);
4293
4294/*
4295 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4296 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4297 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4298 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4299 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4300 * November 10, 2010). As a result, on this platform we can't use Relaxed
4301 * Ordering for Upstream TLPs.
4302 */
4303DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4304 quirk_relaxedordering_disable);
4305DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4306 quirk_relaxedordering_disable);
4307DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4308 quirk_relaxedordering_disable);
4309
4310/*
4311 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4312 * values for the Attribute as were supplied in the header of the
4313 * corresponding Request, except as explicitly allowed when IDO is used."
4314 *
4315 * If a non-compliant device generates a completion with a different
4316 * attribute than the request, the receiver may accept it (which itself
4317 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4318 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4319 * device access timeout.
4320 *
4321 * If the non-compliant device generates completions with zero attributes
4322 * (instead of copying the attributes from the request), we can work around
4323 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4324 * upstream devices so they always generate requests with zero attributes.
4325 *
4326 * This affects other devices under the same Root Port, but since these
4327 * attributes are performance hints, there should be no functional problem.
4328 *
4329 * Note that Configuration Space accesses are never supposed to have TLP
4330 * Attributes, so we're safe waiting till after any Configuration Space
4331 * accesses to do the Root Port fixup.
4332 */
4333static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4334{
4335 struct pci_dev *root_port = pcie_find_root_port(pdev);
4336
4337 if (!root_port) {
4338 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4339 return;
4340 }
4341
4342 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4343 dev_name(&pdev->dev));
4344 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4345 PCI_EXP_DEVCTL_RELAX_EN |
4346 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4347}
4348
4349/*
4350 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4351 * Completion it generates.
4352 */
4353static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4354{
4355 /*
4356 * This mask/compare operation selects for Physical Function 4 on a
4357 * T5. We only need to fix up the Root Port once for any of the
4358 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4359 * 0x54xx so we use that one.
4360 */
4361 if ((pdev->device & 0xff00) == 0x5400)
4362 quirk_disable_root_port_attributes(pdev);
4363}
4364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4365 quirk_chelsio_T5_disable_root_port_attributes);
4366
4367/*
4368 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4369 * by a device
4370 * @acs_ctrl_req: Bitmask of desired ACS controls
4371 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4372 * the hardware design
4373 *
4374 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4375 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4376 * caller desires. Return 0 otherwise.
4377 */
4378static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4379{
4380 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4381 return 1;
4382 return 0;
4383}
4384
4385/*
4386 * AMD has indicated that the devices below do not support peer-to-peer
4387 * in any system where they are found in the southbridge with an AMD
4388 * IOMMU in the system. Multifunction devices that do not support
4389 * peer-to-peer between functions can claim to support a subset of ACS.
4390 * Such devices effectively enable request redirect (RR) and completion
4391 * redirect (CR) since all transactions are redirected to the upstream
4392 * root complex.
4393 *
4394 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4395 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4396 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4397 *
4398 * 1002:4385 SBx00 SMBus Controller
4399 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4400 * 1002:4383 SBx00 Azalia (Intel HDA)
4401 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4402 * 1002:4384 SBx00 PCI to PCI Bridge
4403 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4404 *
4405 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4406 *
4407 * 1022:780f [AMD] FCH PCI Bridge
4408 * 1022:7809 [AMD] FCH USB OHCI Controller
4409 */
4410static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4411{
4412#ifdef CONFIG_ACPI
4413 struct acpi_table_header *header = NULL;
4414 acpi_status status;
4415
4416 /* Targeting multifunction devices on the SB (appears on root bus) */
4417 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4418 return -ENODEV;
4419
4420 /* The IVRS table describes the AMD IOMMU */
4421 status = acpi_get_table("IVRS", 0, &header);
4422 if (ACPI_FAILURE(status))
4423 return -ENODEV;
4424
4425 acpi_put_table(header);
4426
4427 /* Filter out flags not applicable to multifunction */
4428 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4429
4430 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4431#else
4432 return -ENODEV;
4433#endif
4434}
4435
4436static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4437{
4438 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4439 return false;
4440
4441 switch (dev->device) {
4442 /*
4443 * Effectively selects all downstream ports for whole ThunderX1
4444 * (which represents 8 SoCs).
4445 */
4446 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4447 case 0xaf84: /* ThunderX2 */
4448 case 0xb884: /* ThunderX3 */
4449 return true;
4450 default:
4451 return false;
4452 }
4453}
4454
4455static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4456{
4457 if (!pci_quirk_cavium_acs_match(dev))
4458 return -ENOTTY;
4459
4460 /*
4461 * Cavium Root Ports don't advertise an ACS capability. However,
4462 * the RTL internally implements similar protection as if ACS had
4463 * Source Validation, Request Redirection, Completion Redirection,
4464 * and Upstream Forwarding features enabled. Assert that the
4465 * hardware implements and enables equivalent ACS functionality for
4466 * these flags.
4467 */
4468 return pci_acs_ctrl_enabled(acs_flags,
4469 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4470}
4471
4472static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4473{
4474 /*
4475 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4476 * transactions with others, allowing masking out these bits as if they
4477 * were unimplemented in the ACS capability.
4478 */
4479 return pci_acs_ctrl_enabled(acs_flags,
4480 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4481}
4482
4483/*
4484 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4485 * But the implementation could block peer-to-peer transactions between them
4486 * and provide ACS-like functionality.
4487 */
4488static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4489{
4490 if (!pci_is_pcie(dev) ||
4491 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4492 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4493 return -ENOTTY;
4494
4495 switch (dev->device) {
4496 case 0x0710 ... 0x071e:
4497 case 0x0721:
4498 case 0x0723 ... 0x0732:
4499 return pci_acs_ctrl_enabled(acs_flags,
4500 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4501 }
4502
4503 return false;
4504}
4505
4506/*
4507 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4508 * transactions and validate bus numbers in requests, but do not provide an
4509 * actual PCIe ACS capability. This is the list of device IDs known to fall
4510 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4511 */
4512static const u16 pci_quirk_intel_pch_acs_ids[] = {
4513 /* Ibexpeak PCH */
4514 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4515 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4516 /* Cougarpoint PCH */
4517 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4518 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4519 /* Pantherpoint PCH */
4520 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4521 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4522 /* Lynxpoint-H PCH */
4523 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4524 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4525 /* Lynxpoint-LP PCH */
4526 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4527 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4528 /* Wildcat PCH */
4529 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4530 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4531 /* Patsburg (X79) PCH */
4532 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4533 /* Wellsburg (X99) PCH */
4534 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4535 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4536 /* Lynx Point (9 series) PCH */
4537 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4538};
4539
4540static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4541{
4542 int i;
4543
4544 /* Filter out a few obvious non-matches first */
4545 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4546 return false;
4547
4548 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4549 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4550 return true;
4551
4552 return false;
4553}
4554
4555static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4556{
4557 if (!pci_quirk_intel_pch_acs_match(dev))
4558 return -ENOTTY;
4559
4560 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4561 return pci_acs_ctrl_enabled(acs_flags,
4562 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4563
4564 return pci_acs_ctrl_enabled(acs_flags, 0);
4565}
4566
4567/*
4568 * These QCOM Root Ports do provide ACS-like features to disable peer
4569 * transactions and validate bus numbers in requests, but do not provide an
4570 * actual PCIe ACS capability. Hardware supports source validation but it
4571 * will report the issue as Completer Abort instead of ACS Violation.
4572 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4573 * Complex with unique segment numbers. It is not possible for one Root
4574 * Port to pass traffic to another Root Port. All PCIe transactions are
4575 * terminated inside the Root Port.
4576 */
4577static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4578{
4579 return pci_acs_ctrl_enabled(acs_flags,
4580 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4581}
4582
4583static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4584{
4585 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4586 return -ENOTTY;
4587
4588 /*
4589 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4590 * but do include ACS-like functionality. The hardware doesn't support
4591 * peer-to-peer transactions via the root port and each has a unique
4592 * segment number.
4593 *
4594 * Additionally, the root ports cannot send traffic to each other.
4595 */
4596 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4597
4598 return acs_flags ? 0 : 1;
4599}
4600
4601/*
4602 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4603 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4604 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4605 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4606 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4607 * control register is at offset 8 instead of 6 and we should probably use
4608 * dword accesses to them. This applies to the following PCI Device IDs, as
4609 * found in volume 1 of the datasheet[2]:
4610 *
4611 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4612 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4613 *
4614 * N.B. This doesn't fix what lspci shows.
4615 *
4616 * The 100 series chipset specification update includes this as errata #23[3].
4617 *
4618 * The 200 series chipset (Union Point) has the same bug according to the
4619 * specification update (Intel 200 Series Chipset Family Platform Controller
4620 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4621 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4622 * chipset include:
4623 *
4624 * 0xa290-0xa29f PCI Express Root port #{0-16}
4625 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4626 *
4627 * Mobile chipsets are also affected, 7th & 8th Generation
4628 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4629 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4630 * Processor Family I/O for U Quad Core Platforms Specification Update,
4631 * August 2017, Revision 002, Document#: 334660-002)[6]
4632 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4633 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4634 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4635 *
4636 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4637 *
4638 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4639 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4640 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4641 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4642 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4643 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4644 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4645 */
4646static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4647{
4648 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4649 return false;
4650
4651 switch (dev->device) {
4652 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4653 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4654 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4655 return true;
4656 }
4657
4658 return false;
4659}
4660
4661#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4662
4663static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4664{
4665 int pos;
4666 u32 cap, ctrl;
4667
4668 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4669 return -ENOTTY;
4670
4671 pos = dev->acs_cap;
4672 if (!pos)
4673 return -ENOTTY;
4674
4675 /* see pci_acs_flags_enabled() */
4676 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4677 acs_flags &= (cap | PCI_ACS_EC);
4678
4679 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4680
4681 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4682}
4683
4684static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4685{
4686 /*
4687 * SV, TB, and UF are not relevant to multifunction endpoints.
4688 *
4689 * Multifunction devices are only required to implement RR, CR, and DT
4690 * in their ACS capability if they support peer-to-peer transactions.
4691 * Devices matching this quirk have been verified by the vendor to not
4692 * perform peer-to-peer with other functions, allowing us to mask out
4693 * these bits as if they were unimplemented in the ACS capability.
4694 */
4695 return pci_acs_ctrl_enabled(acs_flags,
4696 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4697 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4698}
4699
4700static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4701{
4702 /*
4703 * Intel RCiEP's are required to allow p2p only on translated
4704 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4705 * "Root-Complex Peer to Peer Considerations".
4706 */
4707 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4708 return -ENOTTY;
4709
4710 return pci_acs_ctrl_enabled(acs_flags,
4711 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4712}
4713
4714static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4715{
4716 /*
4717 * iProc PAXB Root Ports don't advertise an ACS capability, but
4718 * they do not allow peer-to-peer transactions between Root Ports.
4719 * Allow each Root Port to be in a separate IOMMU group by masking
4720 * SV/RR/CR/UF bits.
4721 */
4722 return pci_acs_ctrl_enabled(acs_flags,
4723 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4724}
4725
4726static const struct pci_dev_acs_enabled {
4727 u16 vendor;
4728 u16 device;
4729 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4730} pci_dev_acs_enabled[] = {
4731 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4732 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4733 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4734 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4735 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4736 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4737 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4738 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4739 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4740 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4741 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4742 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4743 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4744 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4745 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4746 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4747 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4748 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4749 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4750 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4751 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4752 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4753 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4754 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4755 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4756 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4757 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4758 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4759 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4760 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4761 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4762 /* 82580 */
4763 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4764 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4765 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4766 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4767 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4768 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4769 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4770 /* 82576 */
4771 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4772 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4773 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4774 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4775 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4776 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4777 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4778 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4779 /* 82575 */
4780 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4781 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4782 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4783 /* I350 */
4784 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4785 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4786 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4787 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4788 /* 82571 (Quads omitted due to non-ACS switch) */
4789 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4790 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4791 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4792 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4793 /* I219 */
4794 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4795 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4796 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4797 /* QCOM QDF2xxx root ports */
4798 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4799 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4800 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4801 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4802 /* Intel PCH root ports */
4803 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4804 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4805 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4806 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4807 /* Cavium ThunderX */
4808 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4809 /* APM X-Gene */
4810 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4811 /* Ampere Computing */
4812 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4813 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4814 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4815 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4816 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4817 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4818 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4819 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4820 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4821 /* Amazon Annapurna Labs */
4822 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4823 /* Zhaoxin multi-function devices */
4824 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4825 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4826 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4827 /* Zhaoxin Root/Downstream Ports */
4828 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4829 { 0 }
4830};
4831
4832/*
4833 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4834 * @dev: PCI device
4835 * @acs_flags: Bitmask of desired ACS controls
4836 *
4837 * Returns:
4838 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4839 * device provides the desired controls
4840 * 0: Device does not provide all the desired controls
4841 * >0: Device provides all the controls in @acs_flags
4842 */
4843int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4844{
4845 const struct pci_dev_acs_enabled *i;
4846 int ret;
4847
4848 /*
4849 * Allow devices that do not expose standard PCIe ACS capabilities
4850 * or control to indicate their support here. Multi-function express
4851 * devices which do not allow internal peer-to-peer between functions,
4852 * but do not implement PCIe ACS may wish to return true here.
4853 */
4854 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4855 if ((i->vendor == dev->vendor ||
4856 i->vendor == (u16)PCI_ANY_ID) &&
4857 (i->device == dev->device ||
4858 i->device == (u16)PCI_ANY_ID)) {
4859 ret = i->acs_enabled(dev, acs_flags);
4860 if (ret >= 0)
4861 return ret;
4862 }
4863 }
4864
4865 return -ENOTTY;
4866}
4867
4868/* Config space offset of Root Complex Base Address register */
4869#define INTEL_LPC_RCBA_REG 0xf0
4870/* 31:14 RCBA address */
4871#define INTEL_LPC_RCBA_MASK 0xffffc000
4872/* RCBA Enable */
4873#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4874
4875/* Backbone Scratch Pad Register */
4876#define INTEL_BSPR_REG 0x1104
4877/* Backbone Peer Non-Posted Disable */
4878#define INTEL_BSPR_REG_BPNPD (1 << 8)
4879/* Backbone Peer Posted Disable */
4880#define INTEL_BSPR_REG_BPPD (1 << 9)
4881
4882/* Upstream Peer Decode Configuration Register */
4883#define INTEL_UPDCR_REG 0x1014
4884/* 5:0 Peer Decode Enable bits */
4885#define INTEL_UPDCR_REG_MASK 0x3f
4886
4887static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4888{
4889 u32 rcba, bspr, updcr;
4890 void __iomem *rcba_mem;
4891
4892 /*
4893 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4894 * are D28:F* and therefore get probed before LPC, thus we can't
4895 * use pci_get_slot()/pci_read_config_dword() here.
4896 */
4897 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4898 INTEL_LPC_RCBA_REG, &rcba);
4899 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4900 return -EINVAL;
4901
4902 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
4903 PAGE_ALIGN(INTEL_UPDCR_REG));
4904 if (!rcba_mem)
4905 return -ENOMEM;
4906
4907 /*
4908 * The BSPR can disallow peer cycles, but it's set by soft strap and
4909 * therefore read-only. If both posted and non-posted peer cycles are
4910 * disallowed, we're ok. If either are allowed, then we need to use
4911 * the UPDCR to disable peer decodes for each port. This provides the
4912 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4913 */
4914 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4915 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4916 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4917 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4918 if (updcr & INTEL_UPDCR_REG_MASK) {
4919 pci_info(dev, "Disabling UPDCR peer decodes\n");
4920 updcr &= ~INTEL_UPDCR_REG_MASK;
4921 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4922 }
4923 }
4924
4925 iounmap(rcba_mem);
4926 return 0;
4927}
4928
4929/* Miscellaneous Port Configuration register */
4930#define INTEL_MPC_REG 0xd8
4931/* MPC: Invalid Receive Bus Number Check Enable */
4932#define INTEL_MPC_REG_IRBNCE (1 << 26)
4933
4934static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4935{
4936 u32 mpc;
4937
4938 /*
4939 * When enabled, the IRBNCE bit of the MPC register enables the
4940 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4941 * ensures that requester IDs fall within the bus number range
4942 * of the bridge. Enable if not already.
4943 */
4944 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4945 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4946 pci_info(dev, "Enabling MPC IRBNCE\n");
4947 mpc |= INTEL_MPC_REG_IRBNCE;
4948 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4949 }
4950}
4951
4952static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4953{
4954 if (!pci_quirk_intel_pch_acs_match(dev))
4955 return -ENOTTY;
4956
4957 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4958 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4959 return 0;
4960 }
4961
4962 pci_quirk_enable_intel_rp_mpc_acs(dev);
4963
4964 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4965
4966 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4967
4968 return 0;
4969}
4970
4971static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4972{
4973 int pos;
4974 u32 cap, ctrl;
4975
4976 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4977 return -ENOTTY;
4978
4979 pos = dev->acs_cap;
4980 if (!pos)
4981 return -ENOTTY;
4982
4983 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4984 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4985
4986 ctrl |= (cap & PCI_ACS_SV);
4987 ctrl |= (cap & PCI_ACS_RR);
4988 ctrl |= (cap & PCI_ACS_CR);
4989 ctrl |= (cap & PCI_ACS_UF);
4990
4991 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4992
4993 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4994
4995 return 0;
4996}
4997
4998static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
4999{
5000 int pos;
5001 u32 cap, ctrl;
5002
5003 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5004 return -ENOTTY;
5005
5006 pos = dev->acs_cap;
5007 if (!pos)
5008 return -ENOTTY;
5009
5010 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5011 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5012
5013 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5014
5015 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5016
5017 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5018
5019 return 0;
5020}
5021
5022static const struct pci_dev_acs_ops {
5023 u16 vendor;
5024 u16 device;
5025 int (*enable_acs)(struct pci_dev *dev);
5026 int (*disable_acs_redir)(struct pci_dev *dev);
5027} pci_dev_acs_ops[] = {
5028 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5029 .enable_acs = pci_quirk_enable_intel_pch_acs,
5030 },
5031 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5032 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5033 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5034 },
5035};
5036
5037int pci_dev_specific_enable_acs(struct pci_dev *dev)
5038{
5039 const struct pci_dev_acs_ops *p;
5040 int i, ret;
5041
5042 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5043 p = &pci_dev_acs_ops[i];
5044 if ((p->vendor == dev->vendor ||
5045 p->vendor == (u16)PCI_ANY_ID) &&
5046 (p->device == dev->device ||
5047 p->device == (u16)PCI_ANY_ID) &&
5048 p->enable_acs) {
5049 ret = p->enable_acs(dev);
5050 if (ret >= 0)
5051 return ret;
5052 }
5053 }
5054
5055 return -ENOTTY;
5056}
5057
5058int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5059{
5060 const struct pci_dev_acs_ops *p;
5061 int i, ret;
5062
5063 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5064 p = &pci_dev_acs_ops[i];
5065 if ((p->vendor == dev->vendor ||
5066 p->vendor == (u16)PCI_ANY_ID) &&
5067 (p->device == dev->device ||
5068 p->device == (u16)PCI_ANY_ID) &&
5069 p->disable_acs_redir) {
5070 ret = p->disable_acs_redir(dev);
5071 if (ret >= 0)
5072 return ret;
5073 }
5074 }
5075
5076 return -ENOTTY;
5077}
5078
5079/*
5080 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5081 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5082 * Next Capability pointer in the MSI Capability Structure should point to
5083 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5084 * the list.
5085 */
5086static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5087{
5088 int pos, i = 0;
5089 u8 next_cap;
5090 u16 reg16, *cap;
5091 struct pci_cap_saved_state *state;
5092
5093 /* Bail if the hardware bug is fixed */
5094 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5095 return;
5096
5097 /* Bail if MSI Capability Structure is not found for some reason */
5098 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5099 if (!pos)
5100 return;
5101
5102 /*
5103 * Bail if Next Capability pointer in the MSI Capability Structure
5104 * is not the expected incorrect 0x00.
5105 */
5106 pci_read_config_byte(pdev, pos + 1, &next_cap);
5107 if (next_cap)
5108 return;
5109
5110 /*
5111 * PCIe Capability Structure is expected to be at 0x50 and should
5112 * terminate the list (Next Capability pointer is 0x00). Verify
5113 * Capability Id and Next Capability pointer is as expected.
5114 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5115 * to correctly set kernel data structures which have already been
5116 * set incorrectly due to the hardware bug.
5117 */
5118 pos = 0x50;
5119 pci_read_config_word(pdev, pos, ®16);
5120 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5121 u32 status;
5122#ifndef PCI_EXP_SAVE_REGS
5123#define PCI_EXP_SAVE_REGS 7
5124#endif
5125 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5126
5127 pdev->pcie_cap = pos;
5128 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5129 pdev->pcie_flags_reg = reg16;
5130 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5131 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5132
5133 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5134 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5135 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5136 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5137
5138 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5139 return;
5140
5141 /* Save PCIe cap */
5142 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5143 if (!state)
5144 return;
5145
5146 state->cap.cap_nr = PCI_CAP_ID_EXP;
5147 state->cap.cap_extended = 0;
5148 state->cap.size = size;
5149 cap = (u16 *)&state->cap.data[0];
5150 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5151 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5152 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5153 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5154 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5155 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5156 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5157 hlist_add_head(&state->next, &pdev->saved_cap_space);
5158 }
5159}
5160DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5161
5162/*
5163 * FLR may cause the following to devices to hang:
5164 *
5165 * AMD Starship/Matisse HD Audio Controller 0x1487
5166 * AMD Starship USB 3.0 Host Controller 0x148c
5167 * AMD Matisse USB 3.0 Host Controller 0x149c
5168 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5169 * Intel 82579V Gigabit Ethernet Controller 0x1503
5170 *
5171 */
5172static void quirk_no_flr(struct pci_dev *dev)
5173{
5174 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5175}
5176DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5177DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5178DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5179DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5180DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5181
5182static void quirk_no_ext_tags(struct pci_dev *pdev)
5183{
5184 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5185
5186 if (!bridge)
5187 return;
5188
5189 bridge->no_ext_tags = 1;
5190 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5191
5192 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5193}
5194DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5195DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5196DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5197DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5198DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5199DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5200DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5201
5202#ifdef CONFIG_PCI_ATS
5203/*
5204 * Some devices require additional driver setup to enable ATS. Don't use
5205 * ATS for those devices as ATS will be enabled before the driver has had a
5206 * chance to load and configure the device.
5207 */
5208static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5209{
5210 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5211 (pdev->device == 0x7340 && pdev->revision != 0xc5))
5212 return;
5213
5214 pci_info(pdev, "disabling ATS\n");
5215 pdev->ats_cap = 0;
5216}
5217
5218/* AMD Stoney platform GPU */
5219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5220/* AMD Iceland dGPU */
5221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5222/* AMD Navi10 dGPU */
5223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5224/* AMD Navi14 dGPU */
5225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5226#endif /* CONFIG_PCI_ATS */
5227
5228/* Freescale PCIe doesn't support MSI in RC mode */
5229static void quirk_fsl_no_msi(struct pci_dev *pdev)
5230{
5231 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5232 pdev->no_msi = 1;
5233}
5234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5235
5236/*
5237 * Although not allowed by the spec, some multi-function devices have
5238 * dependencies of one function (consumer) on another (supplier). For the
5239 * consumer to work in D0, the supplier must also be in D0. Create a
5240 * device link from the consumer to the supplier to enforce this
5241 * dependency. Runtime PM is allowed by default on the consumer to prevent
5242 * it from permanently keeping the supplier awake.
5243 */
5244static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5245 unsigned int supplier, unsigned int class,
5246 unsigned int class_shift)
5247{
5248 struct pci_dev *supplier_pdev;
5249
5250 if (PCI_FUNC(pdev->devfn) != consumer)
5251 return;
5252
5253 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5254 pdev->bus->number,
5255 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5256 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5257 pci_dev_put(supplier_pdev);
5258 return;
5259 }
5260
5261 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5262 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5263 pci_info(pdev, "D0 power state depends on %s\n",
5264 pci_name(supplier_pdev));
5265 else
5266 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5267 pci_name(supplier_pdev));
5268
5269 pm_runtime_allow(&pdev->dev);
5270 pci_dev_put(supplier_pdev);
5271}
5272
5273/*
5274 * Create device link for GPUs with integrated HDA controller for streaming
5275 * audio to attached displays.
5276 */
5277static void quirk_gpu_hda(struct pci_dev *hda)
5278{
5279 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5280}
5281DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5282 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5283DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5284 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5285DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5286 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5287
5288/*
5289 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5290 * controller to VGA.
5291 */
5292static void quirk_gpu_usb(struct pci_dev *usb)
5293{
5294 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5295}
5296DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5297 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5298
5299/*
5300 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5301 * to VGA. Currently there is no class code defined for UCSI device over PCI
5302 * so using UNKNOWN class for now and it will be updated when UCSI
5303 * over PCI gets a class code.
5304 */
5305#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5306static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5307{
5308 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5309}
5310DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5311 PCI_CLASS_SERIAL_UNKNOWN, 8,
5312 quirk_gpu_usb_typec_ucsi);
5313
5314/*
5315 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5316 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5317 */
5318static void quirk_nvidia_hda(struct pci_dev *gpu)
5319{
5320 u8 hdr_type;
5321 u32 val;
5322
5323 /* There was no integrated HDA controller before MCP89 */
5324 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5325 return;
5326
5327 /* Bit 25 at offset 0x488 enables the HDA controller */
5328 pci_read_config_dword(gpu, 0x488, &val);
5329 if (val & BIT(25))
5330 return;
5331
5332 pci_info(gpu, "Enabling HDA controller\n");
5333 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5334
5335 /* The GPU becomes a multi-function device when the HDA is enabled */
5336 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5337 gpu->multifunction = !!(hdr_type & 0x80);
5338}
5339DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5340 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5341DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5342 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5343
5344/*
5345 * Some IDT switches incorrectly flag an ACS Source Validation error on
5346 * completions for config read requests even though PCIe r4.0, sec
5347 * 6.12.1.1, says that completions are never affected by ACS Source
5348 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5349 *
5350 * Item #36 - Downstream port applies ACS Source Validation to Completions
5351 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5352 * completions are never affected by ACS Source Validation. However,
5353 * completions received by a downstream port of the PCIe switch from a
5354 * device that has not yet captured a PCIe bus number are incorrectly
5355 * dropped by ACS Source Validation by the switch downstream port.
5356 *
5357 * The workaround suggested by IDT is to issue a config write to the
5358 * downstream device before issuing the first config read. This allows the
5359 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5360 * sec 2.2.9), thus avoiding the ACS error on the completion.
5361 *
5362 * However, we don't know when the device is ready to accept the config
5363 * write, so we do config reads until we receive a non-Config Request Retry
5364 * Status, then do the config write.
5365 *
5366 * To avoid hitting the erratum when doing the config reads, we disable ACS
5367 * SV around this process.
5368 */
5369int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5370{
5371 int pos;
5372 u16 ctrl = 0;
5373 bool found;
5374 struct pci_dev *bridge = bus->self;
5375
5376 pos = bridge->acs_cap;
5377
5378 /* Disable ACS SV before initial config reads */
5379 if (pos) {
5380 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5381 if (ctrl & PCI_ACS_SV)
5382 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5383 ctrl & ~PCI_ACS_SV);
5384 }
5385
5386 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5387
5388 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5389 if (found)
5390 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5391
5392 /* Re-enable ACS_SV if it was previously enabled */
5393 if (ctrl & PCI_ACS_SV)
5394 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5395
5396 return found;
5397}
5398
5399/*
5400 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5401 * NT endpoints via the internal switch fabric. These IDs replace the
5402 * originating requestor ID TLPs which access host memory on peer NTB
5403 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5404 * to permit access when the IOMMU is turned on.
5405 */
5406static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5407{
5408 void __iomem *mmio;
5409 struct ntb_info_regs __iomem *mmio_ntb;
5410 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5411 u64 partition_map;
5412 u8 partition;
5413 int pp;
5414
5415 if (pci_enable_device(pdev)) {
5416 pci_err(pdev, "Cannot enable Switchtec device\n");
5417 return;
5418 }
5419
5420 mmio = pci_iomap(pdev, 0, 0);
5421 if (mmio == NULL) {
5422 pci_disable_device(pdev);
5423 pci_err(pdev, "Cannot iomap Switchtec device\n");
5424 return;
5425 }
5426
5427 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5428
5429 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5430 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5431
5432 partition = ioread8(&mmio_ntb->partition_id);
5433
5434 partition_map = ioread32(&mmio_ntb->ep_map);
5435 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5436 partition_map &= ~(1ULL << partition);
5437
5438 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5439 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5440 u32 table_sz = 0;
5441 int te;
5442
5443 if (!(partition_map & (1ULL << pp)))
5444 continue;
5445
5446 pci_dbg(pdev, "Processing partition %d\n", pp);
5447
5448 mmio_peer_ctrl = &mmio_ctrl[pp];
5449
5450 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5451 if (!table_sz) {
5452 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5453 continue;
5454 }
5455
5456 if (table_sz > 512) {
5457 pci_warn(pdev,
5458 "Invalid Switchtec partition %d table_sz %d\n",
5459 pp, table_sz);
5460 continue;
5461 }
5462
5463 for (te = 0; te < table_sz; te++) {
5464 u32 rid_entry;
5465 u8 devfn;
5466
5467 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5468 devfn = (rid_entry >> 1) & 0xFF;
5469 pci_dbg(pdev,
5470 "Aliasing Partition %d Proxy ID %02x.%d\n",
5471 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5472 pci_add_dma_alias(pdev, devfn, 1);
5473 }
5474 }
5475
5476 pci_iounmap(pdev, mmio);
5477 pci_disable_device(pdev);
5478}
5479#define SWITCHTEC_QUIRK(vid) \
5480 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5481 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5482
5483SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5484SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5485SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5486SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5487SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5488SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5489SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5490SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5491SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5492SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5493SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5494SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5495SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5496SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5497SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5498SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5499SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5500SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5501SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5502SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5503SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5504SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5505SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5506SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5507SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5508SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5509SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5510SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5511SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5512SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5513SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5514SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5515SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5516SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5517SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5518SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5519SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5520SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5521SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5522SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5523SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5524SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5525SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5526SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5527SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5528SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5529SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5530SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5531
5532/*
5533 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5534 * These IDs are used to forward responses to the originator on the other
5535 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5536 * the IOMMU is turned on.
5537 */
5538static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5539{
5540 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5541 /* PLX NTB may use all 256 devfns */
5542 pci_add_dma_alias(pdev, 0, 256);
5543}
5544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5546
5547/*
5548 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5549 * not always reset the secondary Nvidia GPU between reboots if the system
5550 * is configured to use Hybrid Graphics mode. This results in the GPU
5551 * being left in whatever state it was in during the *previous* boot, which
5552 * causes spurious interrupts from the GPU, which in turn causes us to
5553 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5554 * this also completely breaks nouveau.
5555 *
5556 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5557 * clean state and fixes all these issues.
5558 *
5559 * When the machine is configured in Dedicated display mode, the issue
5560 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5561 * mode, so we can detect that and avoid resetting it.
5562 */
5563static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5564{
5565 void __iomem *map;
5566 int ret;
5567
5568 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5569 pdev->subsystem_device != 0x222e ||
5570 !pdev->reset_fn)
5571 return;
5572
5573 if (pci_enable_device_mem(pdev))
5574 return;
5575
5576 /*
5577 * Based on nvkm_device_ctor() in
5578 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5579 */
5580 map = pci_iomap(pdev, 0, 0x23000);
5581 if (!map) {
5582 pci_err(pdev, "Can't map MMIO space\n");
5583 goto out_disable;
5584 }
5585
5586 /*
5587 * Make sure the GPU looks like it's been POSTed before resetting
5588 * it.
5589 */
5590 if (ioread32(map + 0x2240c) & 0x2) {
5591 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5592 ret = pci_reset_bus(pdev);
5593 if (ret < 0)
5594 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5595 }
5596
5597 iounmap(map);
5598out_disable:
5599 pci_disable_device(pdev);
5600}
5601DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5602 PCI_CLASS_DISPLAY_VGA, 8,
5603 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5604
5605/*
5606 * Device [1b21:2142]
5607 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5608 */
5609static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5610{
5611 pci_info(dev, "PME# does not work under D0, disabling it\n");
5612 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5613}
5614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5615
5616/*
5617 * Device [12d8:0x400e] and [12d8:0x400f]
5618 * These devices advertise PME# support in all power states but don't
5619 * reliably assert it.
5620 */
5621static void pci_fixup_no_pme(struct pci_dev *dev)
5622{
5623 pci_info(dev, "PME# is unreliable, disabling it\n");
5624 dev->pme_support = 0;
5625}
5626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_pme);
5627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_pme);
5628
5629static void apex_pci_fixup_class(struct pci_dev *pdev)
5630{
5631 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5632}
5633DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5634 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);