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1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/acpi.h>
25#include <linux/kallsyms.h>
26#include <linux/dmi.h>
27#include <linux/pci-aspm.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/ktime.h>
31#include <asm/dma.h> /* isa_dma_bridge_buggy */
32#include "pci.h"
33
34/*
35 * Decoding should be disabled for a PCI device during BAR sizing to avoid
36 * conflict. But doing so may cause problems on host bridge and perhaps other
37 * key system devices. For devices that need to have mmio decoding always-on,
38 * we need to set the dev->mmio_always_on bit.
39 */
40static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
41{
42 dev->mmio_always_on = 1;
43}
44DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
45 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
46
47/* The Mellanox Tavor device gives false positive parity errors
48 * Mark this device with a broken_parity_status, to allow
49 * PCI scanning code to "skip" this now blacklisted device.
50 */
51static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
52{
53 dev->broken_parity_status = 1; /* This device gives false positives */
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
57
58/* Deal with broken BIOS'es that neglect to enable passive release,
59 which can cause problems in combination with the 82441FX/PPro MTRRs */
60static void quirk_passive_release(struct pci_dev *dev)
61{
62 struct pci_dev *d = NULL;
63 unsigned char dlc;
64
65 /* We have to make sure a particular bit is set in the PIIX3
66 ISA bridge, so we have to go out and find it. */
67 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
68 pci_read_config_byte(d, 0x82, &dlc);
69 if (!(dlc & 1<<1)) {
70 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
71 dlc |= 1<<1;
72 pci_write_config_byte(d, 0x82, dlc);
73 }
74 }
75}
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
78
79/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
80 but VIA don't answer queries. If you happen to have good contacts at VIA
81 ask them for me please -- Alan
82
83 This appears to be BIOS not version dependent. So presumably there is a
84 chipset level fix */
85
86static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
87{
88 if (!isa_dma_bridge_buggy) {
89 isa_dma_bridge_buggy=1;
90 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
91 }
92}
93 /*
94 * Its not totally clear which chipsets are the problematic ones
95 * We know 82C586 and 82C596 variants are affected.
96 */
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
104
105/*
106 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
107 * for some HT machines to use C4 w/o hanging.
108 */
109static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
110{
111 u32 pmbase;
112 u16 pm1a;
113
114 pci_read_config_dword(dev, 0x40, &pmbase);
115 pmbase = pmbase & 0xff80;
116 pm1a = inw(pmbase);
117
118 if (pm1a & 0x10) {
119 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
120 outw(0x10, pmbase);
121 }
122}
123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
124
125/*
126 * Chipsets where PCI->PCI transfers vanish or hang
127 */
128static void __devinit quirk_nopcipci(struct pci_dev *dev)
129{
130 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
131 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
132 pci_pci_problems |= PCIPCI_FAIL;
133 }
134}
135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
137
138static void __devinit quirk_nopciamd(struct pci_dev *dev)
139{
140 u8 rev;
141 pci_read_config_byte(dev, 0x08, &rev);
142 if (rev == 0x13) {
143 /* Erratum 24 */
144 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
145 pci_pci_problems |= PCIAGP_FAIL;
146 }
147}
148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
149
150/*
151 * Triton requires workarounds to be used by the drivers
152 */
153static void __devinit quirk_triton(struct pci_dev *dev)
154{
155 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
156 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
157 pci_pci_problems |= PCIPCI_TRITON;
158 }
159}
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
164
165/*
166 * VIA Apollo KT133 needs PCI latency patch
167 * Made according to a windows driver based patch by George E. Breese
168 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
169 * and http://www.georgebreese.com/net/software/#PCI
170 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
171 * the info on which Mr Breese based his work.
172 *
173 * Updated based on further information from the site and also on
174 * information provided by VIA
175 */
176static void quirk_vialatency(struct pci_dev *dev)
177{
178 struct pci_dev *p;
179 u8 busarb;
180 /* Ok we have a potential problem chipset here. Now see if we have
181 a buggy southbridge */
182
183 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
184 if (p!=NULL) {
185 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
186 /* Check for buggy part revisions */
187 if (p->revision < 0x40 || p->revision > 0x42)
188 goto exit;
189 } else {
190 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
191 if (p==NULL) /* No problem parts */
192 goto exit;
193 /* Check for buggy part revisions */
194 if (p->revision < 0x10 || p->revision > 0x12)
195 goto exit;
196 }
197
198 /*
199 * Ok we have the problem. Now set the PCI master grant to
200 * occur every master grant. The apparent bug is that under high
201 * PCI load (quite common in Linux of course) you can get data
202 * loss when the CPU is held off the bus for 3 bus master requests
203 * This happens to include the IDE controllers....
204 *
205 * VIA only apply this fix when an SB Live! is present but under
206 * both Linux and Windows this isn't enough, and we have seen
207 * corruption without SB Live! but with things like 3 UDMA IDE
208 * controllers. So we ignore that bit of the VIA recommendation..
209 */
210
211 pci_read_config_byte(dev, 0x76, &busarb);
212 /* Set bit 4 and bi 5 of byte 76 to 0x01
213 "Master priority rotation on every PCI master grant */
214 busarb &= ~(1<<5);
215 busarb |= (1<<4);
216 pci_write_config_byte(dev, 0x76, busarb);
217 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
218exit:
219 pci_dev_put(p);
220}
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224/* Must restore this on a resume from RAM */
225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
227DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
228
229/*
230 * VIA Apollo VP3 needs ETBF on BT848/878
231 */
232static void __devinit quirk_viaetbf(struct pci_dev *dev)
233{
234 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
235 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
236 pci_pci_problems |= PCIPCI_VIAETBF;
237 }
238}
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
240
241static void __devinit quirk_vsfx(struct pci_dev *dev)
242{
243 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
244 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
245 pci_pci_problems |= PCIPCI_VSFX;
246 }
247}
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
249
250/*
251 * Ali Magik requires workarounds to be used by the drivers
252 * that DMA to AGP space. Latency must be set to 0xA and triton
253 * workaround applied too
254 * [Info kindly provided by ALi]
255 */
256static void __init quirk_alimagik(struct pci_dev *dev)
257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
260 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
261 }
262}
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
265
266/*
267 * Natoma has some interesting boundary conditions with Zoran stuff
268 * at least
269 */
270static void __devinit quirk_natoma(struct pci_dev *dev)
271{
272 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
273 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
274 pci_pci_problems |= PCIPCI_NATOMA;
275 }
276}
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
283
284/*
285 * This chip can cause PCI parity errors if config register 0xA0 is read
286 * while DMAs are occurring.
287 */
288static void __devinit quirk_citrine(struct pci_dev *dev)
289{
290 dev->cfg_size = 0xA0;
291}
292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
293
294/*
295 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
296 * If it's needed, re-allocate the region.
297 */
298static void __devinit quirk_s3_64M(struct pci_dev *dev)
299{
300 struct resource *r = &dev->resource[0];
301
302 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
303 r->start = 0;
304 r->end = 0x3ffffff;
305 }
306}
307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
309
310/*
311 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
312 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
313 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
314 * (which conflicts w/ BAR1's memory range).
315 */
316static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
317{
318 if (pci_resource_len(dev, 0) != 8) {
319 struct resource *res = &dev->resource[0];
320 res->end = res->start + 8 - 1;
321 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
322 "(incorrect header); workaround applied.\n");
323 }
324}
325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
326
327static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
328 unsigned size, int nr, const char *name)
329{
330 region &= ~(size-1);
331 if (region) {
332 struct pci_bus_region bus_region;
333 struct resource *res = dev->resource + nr;
334
335 res->name = pci_name(dev);
336 res->start = region;
337 res->end = region + size - 1;
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space. */
341 bus_region.start = res->start;
342 bus_region.end = res->end;
343 pcibios_bus_to_resource(dev, res, &bus_region);
344
345 if (pci_claim_resource(dev, nr) == 0)
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
347 res, name);
348 }
349}
350
351/*
352 * ATI Northbridge setups MCE the processor if you even
353 * read somewhere between 0x3b0->0x3bb or read 0x3d3
354 */
355static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
356{
357 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
358 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
359 request_region(0x3b0, 0x0C, "RadeonIGP");
360 request_region(0x3d3, 0x01, "RadeonIGP");
361}
362DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
363
364/*
365 * Let's make the southbridge information explicit instead
366 * of having to worry about people probing the ACPI areas,
367 * for example.. (Yes, it happens, and if you read the wrong
368 * ACPI register it will put the machine to sleep with no
369 * way of waking it up again. Bummer).
370 *
371 * ALI M7101: Two IO regions pointed to by words at
372 * 0xE0 (64 bytes of ACPI registers)
373 * 0xE2 (32 bytes of SMB registers)
374 */
375static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
376{
377 u16 region;
378
379 pci_read_config_word(dev, 0xE0, ®ion);
380 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
381 pci_read_config_word(dev, 0xE2, ®ion);
382 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
383}
384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
385
386static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
387{
388 u32 devres;
389 u32 mask, size, base;
390
391 pci_read_config_dword(dev, port, &devres);
392 if ((devres & enable) != enable)
393 return;
394 mask = (devres >> 16) & 15;
395 base = devres & 0xffff;
396 size = 16;
397 for (;;) {
398 unsigned bit = size >> 1;
399 if ((bit & mask) == bit)
400 break;
401 size = bit;
402 }
403 /*
404 * For now we only print it out. Eventually we'll want to
405 * reserve it (at least if it's in the 0x1000+ range), but
406 * let's get enough confirmation reports first.
407 */
408 base &= -size;
409 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
410}
411
412static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
413{
414 u32 devres;
415 u32 mask, size, base;
416
417 pci_read_config_dword(dev, port, &devres);
418 if ((devres & enable) != enable)
419 return;
420 base = devres & 0xffff0000;
421 mask = (devres & 0x3f) << 16;
422 size = 128 << 16;
423 for (;;) {
424 unsigned bit = size >> 1;
425 if ((bit & mask) == bit)
426 break;
427 size = bit;
428 }
429 /*
430 * For now we only print it out. Eventually we'll want to
431 * reserve it, but let's get enough confirmation reports first.
432 */
433 base &= -size;
434 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
435}
436
437/*
438 * PIIX4 ACPI: Two IO regions pointed to by longwords at
439 * 0x40 (64 bytes of ACPI registers)
440 * 0x90 (16 bytes of SMB registers)
441 * and a few strange programmable PIIX4 device resources.
442 */
443static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
444{
445 u32 region, res_a;
446
447 pci_read_config_dword(dev, 0x40, ®ion);
448 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
449 pci_read_config_dword(dev, 0x90, ®ion);
450 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
451
452 /* Device resource A has enables for some of the other ones */
453 pci_read_config_dword(dev, 0x5c, &res_a);
454
455 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
456 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
457
458 /* Device resource D is just bitfields for static resources */
459
460 /* Device 12 enabled? */
461 if (res_a & (1 << 29)) {
462 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
463 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
464 }
465 /* Device 13 enabled? */
466 if (res_a & (1 << 30)) {
467 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
468 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
469 }
470 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
471 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
472}
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
474DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
475
476#define ICH_PMBASE 0x40
477#define ICH_ACPI_CNTL 0x44
478#define ICH4_ACPI_EN 0x10
479#define ICH6_ACPI_EN 0x80
480#define ICH4_GPIOBASE 0x58
481#define ICH4_GPIO_CNTL 0x5c
482#define ICH4_GPIO_EN 0x10
483#define ICH6_GPIOBASE 0x48
484#define ICH6_GPIO_CNTL 0x4c
485#define ICH6_GPIO_EN 0x10
486
487/*
488 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
489 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
490 * 0x58 (64 bytes of GPIO I/O space)
491 */
492static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
493{
494 u32 region;
495 u8 enable;
496
497 /*
498 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
499 * with low legacy (and fixed) ports. We don't know the decoding
500 * priority and can't tell whether the legacy device or the one created
501 * here is really at that address. This happens on boards with broken
502 * BIOSes.
503 */
504
505 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
506 if (enable & ICH4_ACPI_EN) {
507 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
508 region &= PCI_BASE_ADDRESS_IO_MASK;
509 if (region >= PCIBIOS_MIN_IO)
510 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
511 "ICH4 ACPI/GPIO/TCO");
512 }
513
514 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
515 if (enable & ICH4_GPIO_EN) {
516 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
517 region &= PCI_BASE_ADDRESS_IO_MASK;
518 if (region >= PCIBIOS_MIN_IO)
519 quirk_io_region(dev, region, 64,
520 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
521 }
522}
523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
533
534static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
535{
536 u32 region;
537 u8 enable;
538
539 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
540 if (enable & ICH6_ACPI_EN) {
541 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
542 region &= PCI_BASE_ADDRESS_IO_MASK;
543 if (region >= PCIBIOS_MIN_IO)
544 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
545 "ICH6 ACPI/GPIO/TCO");
546 }
547
548 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
549 if (enable & ICH6_GPIO_EN) {
550 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
551 region &= PCI_BASE_ADDRESS_IO_MASK;
552 if (region >= PCIBIOS_MIN_IO)
553 quirk_io_region(dev, region, 64,
554 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
555 }
556}
557
558static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
559{
560 u32 val;
561 u32 size, base;
562
563 pci_read_config_dword(dev, reg, &val);
564
565 /* Enabled? */
566 if (!(val & 1))
567 return;
568 base = val & 0xfffc;
569 if (dynsize) {
570 /*
571 * This is not correct. It is 16, 32 or 64 bytes depending on
572 * register D31:F0:ADh bits 5:4.
573 *
574 * But this gets us at least _part_ of it.
575 */
576 size = 16;
577 } else {
578 size = 128;
579 }
580 base &= ~(size-1);
581
582 /* Just print it out for now. We should reserve it after more debugging */
583 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
584}
585
586static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
587{
588 /* Shared ACPI/GPIO decode with all ICH6+ */
589 ich6_lpc_acpi_gpio(dev);
590
591 /* ICH6-specific generic IO decode */
592 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
593 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
594}
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
597
598static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
599{
600 u32 val;
601 u32 mask, base;
602
603 pci_read_config_dword(dev, reg, &val);
604
605 /* Enabled? */
606 if (!(val & 1))
607 return;
608
609 /*
610 * IO base in bits 15:2, mask in bits 23:18, both
611 * are dword-based
612 */
613 base = val & 0xfffc;
614 mask = (val >> 16) & 0xfc;
615 mask |= 3;
616
617 /* Just print it out for now. We should reserve it after more debugging */
618 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
619}
620
621/* ICH7-10 has the same common LPC generic IO decode registers */
622static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
623{
624 /* We share the common ACPI/GPIO decode with ICH6 */
625 ich6_lpc_acpi_gpio(dev);
626
627 /* And have 4 ICH7+ generic decodes */
628 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
629 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
630 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
631 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
632}
633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
634DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
635DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
640DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
646
647/*
648 * VIA ACPI: One IO region pointed to by longword at
649 * 0x48 or 0x20 (256 bytes of ACPI registers)
650 */
651static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
652{
653 u32 region;
654
655 if (dev->revision & 0x10) {
656 pci_read_config_dword(dev, 0x48, ®ion);
657 region &= PCI_BASE_ADDRESS_IO_MASK;
658 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
659 }
660}
661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
662
663/*
664 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
665 * 0x48 (256 bytes of ACPI registers)
666 * 0x70 (128 bytes of hardware monitoring register)
667 * 0x90 (16 bytes of SMB registers)
668 */
669static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
670{
671 u16 hm;
672 u32 smb;
673
674 quirk_vt82c586_acpi(dev);
675
676 pci_read_config_word(dev, 0x70, &hm);
677 hm &= PCI_BASE_ADDRESS_IO_MASK;
678 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
679
680 pci_read_config_dword(dev, 0x90, &smb);
681 smb &= PCI_BASE_ADDRESS_IO_MASK;
682 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
685
686/*
687 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
688 * 0x88 (128 bytes of power management registers)
689 * 0xd0 (16 bytes of SMB registers)
690 */
691static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
692{
693 u16 pm, smb;
694
695 pci_read_config_word(dev, 0x88, &pm);
696 pm &= PCI_BASE_ADDRESS_IO_MASK;
697 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
698
699 pci_read_config_word(dev, 0xd0, &smb);
700 smb &= PCI_BASE_ADDRESS_IO_MASK;
701 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
702}
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
704
705/*
706 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
707 * Disable fast back-to-back on the secondary bus segment
708 */
709static void __devinit quirk_xio2000a(struct pci_dev *dev)
710{
711 struct pci_dev *pdev;
712 u16 command;
713
714 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
715 "secondary bus fast back-to-back transfers disabled\n");
716 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
717 pci_read_config_word(pdev, PCI_COMMAND, &command);
718 if (command & PCI_COMMAND_FAST_BACK)
719 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
720 }
721}
722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
723 quirk_xio2000a);
724
725#ifdef CONFIG_X86_IO_APIC
726
727#include <asm/io_apic.h>
728
729/*
730 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
731 * devices to the external APIC.
732 *
733 * TODO: When we have device-specific interrupt routers,
734 * this code will go away from quirks.
735 */
736static void quirk_via_ioapic(struct pci_dev *dev)
737{
738 u8 tmp;
739
740 if (nr_ioapics < 1)
741 tmp = 0; /* nothing routed to external APIC */
742 else
743 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
744
745 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
746 tmp == 0 ? "Disa" : "Ena");
747
748 /* Offset 0x58: External APIC IRQ output control */
749 pci_write_config_byte (dev, 0x58, tmp);
750}
751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
753
754/*
755 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
756 * This leads to doubled level interrupt rates.
757 * Set this bit to get rid of cycle wastage.
758 * Otherwise uncritical.
759 */
760static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
761{
762 u8 misc_control2;
763#define BYPASS_APIC_DEASSERT 8
764
765 pci_read_config_byte(dev, 0x5B, &misc_control2);
766 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
767 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
768 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
769 }
770}
771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
773
774/*
775 * The AMD io apic can hang the box when an apic irq is masked.
776 * We check all revs >= B0 (yet not in the pre production!) as the bug
777 * is currently marked NoFix
778 *
779 * We have multiple reports of hangs with this chipset that went away with
780 * noapic specified. For the moment we assume it's the erratum. We may be wrong
781 * of course. However the advice is demonstrably good even if so..
782 */
783static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
784{
785 if (dev->revision >= 0x02) {
786 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
787 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
788 }
789}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791
792static void __init quirk_ioapic_rmw(struct pci_dev *dev)
793{
794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1;
796}
797DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
798#endif /* CONFIG_X86_IO_APIC */
799
800/*
801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */
804static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{
806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
808 "disabling PCI-X MMRBC\n", dev->revision);
809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
810 }
811}
812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
813
814/*
815 * FIXME: it is questionable that quirk_via_acpi
816 * is needed. It shows up as an ISA bridge, and does not
817 * support the PCI_INTERRUPT_LINE register at all. Therefore
818 * it seems like setting the pci_dev's 'irq' to the
819 * value of the ACPI SCI interrupt is only done for convenience.
820 * -jgarzik
821 */
822static void __devinit quirk_via_acpi(struct pci_dev *d)
823{
824 /*
825 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
826 */
827 u8 irq;
828 pci_read_config_byte(d, 0x42, &irq);
829 irq &= 0xf;
830 if (irq && (irq != 2))
831 d->irq = irq;
832}
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
835
836
837/*
838 * VIA bridges which have VLink
839 */
840
841static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
842
843static void quirk_via_bridge(struct pci_dev *dev)
844{
845 /* See what bridge we have and find the device ranges */
846 switch (dev->device) {
847 case PCI_DEVICE_ID_VIA_82C686:
848 /* The VT82C686 is special, it attaches to PCI and can have
849 any device number. All its subdevices are functions of
850 that single device. */
851 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
852 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
853 break;
854 case PCI_DEVICE_ID_VIA_8237:
855 case PCI_DEVICE_ID_VIA_8237A:
856 via_vlink_dev_lo = 15;
857 break;
858 case PCI_DEVICE_ID_VIA_8235:
859 via_vlink_dev_lo = 16;
860 break;
861 case PCI_DEVICE_ID_VIA_8231:
862 case PCI_DEVICE_ID_VIA_8233_0:
863 case PCI_DEVICE_ID_VIA_8233A:
864 case PCI_DEVICE_ID_VIA_8233C_0:
865 via_vlink_dev_lo = 17;
866 break;
867 }
868}
869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
877
878/**
879 * quirk_via_vlink - VIA VLink IRQ number update
880 * @dev: PCI device
881 *
882 * If the device we are dealing with is on a PIC IRQ we need to
883 * ensure that the IRQ line register which usually is not relevant
884 * for PCI cards, is actually written so that interrupts get sent
885 * to the right place.
886 * We only do this on systems where a VIA south bridge was detected,
887 * and only for VIA devices on the motherboard (see quirk_via_bridge
888 * above).
889 */
890
891static void quirk_via_vlink(struct pci_dev *dev)
892{
893 u8 irq, new_irq;
894
895 /* Check if we have VLink at all */
896 if (via_vlink_dev_lo == -1)
897 return;
898
899 new_irq = dev->irq;
900
901 /* Don't quirk interrupts outside the legacy IRQ range */
902 if (!new_irq || new_irq > 15)
903 return;
904
905 /* Internal device ? */
906 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
907 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
908 return;
909
910 /* This is an internal VLink device on a PIC interrupt. The BIOS
911 ought to have set this but may not have, so we redo it */
912
913 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
914 if (new_irq != irq) {
915 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
916 irq, new_irq);
917 udelay(15); /* unknown if delay really needed */
918 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
919 }
920}
921DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
922
923/*
924 * VIA VT82C598 has its device ID settable and many BIOSes
925 * set it to the ID of VT82C597 for backward compatibility.
926 * We need to switch it off to be able to recognize the real
927 * type of the chip.
928 */
929static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
930{
931 pci_write_config_byte(dev, 0xfc, 0);
932 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
935
936/*
937 * CardBus controllers have a legacy base address that enables them
938 * to respond as i82365 pcmcia controllers. We don't want them to
939 * do this even if the Linux CardBus driver is not loaded, because
940 * the Linux i82365 driver does not (and should not) handle CardBus.
941 */
942static void quirk_cardbus_legacy(struct pci_dev *dev)
943{
944 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
945}
946DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
947 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
948DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
949 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
950
951/*
952 * Following the PCI ordering rules is optional on the AMD762. I'm not
953 * sure what the designers were smoking but let's not inhale...
954 *
955 * To be fair to AMD, it follows the spec by default, its BIOS people
956 * who turn it off!
957 */
958static void quirk_amd_ordering(struct pci_dev *dev)
959{
960 u32 pcic;
961 pci_read_config_dword(dev, 0x4C, &pcic);
962 if ((pcic&6)!=6) {
963 pcic |= 6;
964 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
965 pci_write_config_dword(dev, 0x4C, pcic);
966 pci_read_config_dword(dev, 0x84, &pcic);
967 pcic |= (1<<23); /* Required in this mode */
968 pci_write_config_dword(dev, 0x84, pcic);
969 }
970}
971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
973
974/*
975 * DreamWorks provided workaround for Dunord I-3000 problem
976 *
977 * This card decodes and responds to addresses not apparently
978 * assigned to it. We force a larger allocation to ensure that
979 * nothing gets put too close to it.
980 */
981static void __devinit quirk_dunord ( struct pci_dev * dev )
982{
983 struct resource *r = &dev->resource [1];
984 r->start = 0;
985 r->end = 0xffffff;
986}
987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
988
989/*
990 * i82380FB mobile docking controller: its PCI-to-PCI bridge
991 * is subtractive decoding (transparent), and does indicate this
992 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
993 * instead of 0x01.
994 */
995static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
996{
997 dev->transparent = 1;
998}
999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1001
1002/*
1003 * Common misconfiguration of the MediaGX/Geode PCI master that will
1004 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1005 * datasheets found at http://www.national.com/analog for info on what
1006 * these bits do. <christer@weinigel.se>
1007 */
1008static void quirk_mediagx_master(struct pci_dev *dev)
1009{
1010 u8 reg;
1011 pci_read_config_byte(dev, 0x41, ®);
1012 if (reg & 2) {
1013 reg &= ~2;
1014 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1015 pci_write_config_byte(dev, 0x41, reg);
1016 }
1017}
1018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1019DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1020
1021/*
1022 * Ensure C0 rev restreaming is off. This is normally done by
1023 * the BIOS but in the odd case it is not the results are corruption
1024 * hence the presence of a Linux check
1025 */
1026static void quirk_disable_pxb(struct pci_dev *pdev)
1027{
1028 u16 config;
1029
1030 if (pdev->revision != 0x04) /* Only C0 requires this */
1031 return;
1032 pci_read_config_word(pdev, 0x40, &config);
1033 if (config & (1<<6)) {
1034 config &= ~(1<<6);
1035 pci_write_config_word(pdev, 0x40, config);
1036 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1037 }
1038}
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1041
1042static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1043{
1044 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1045 u8 tmp;
1046
1047 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1048 if (tmp == 0x01) {
1049 pci_read_config_byte(pdev, 0x40, &tmp);
1050 pci_write_config_byte(pdev, 0x40, tmp|1);
1051 pci_write_config_byte(pdev, 0x9, 1);
1052 pci_write_config_byte(pdev, 0xa, 6);
1053 pci_write_config_byte(pdev, 0x40, tmp);
1054
1055 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1056 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1057 }
1058}
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1060DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1062DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1064DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1065
1066/*
1067 * Serverworks CSB5 IDE does not fully support native mode
1068 */
1069static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1070{
1071 u8 prog;
1072 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1073 if (prog & 5) {
1074 prog &= ~5;
1075 pdev->class &= ~5;
1076 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1077 /* PCI layer will sort out resources */
1078 }
1079}
1080DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1081
1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */
1085static void __init quirk_ide_samemode(struct pci_dev *pdev)
1086{
1087 u8 prog;
1088
1089 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1090
1091 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1092 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1093 prog &= ~5;
1094 pdev->class &= ~5;
1095 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1096 }
1097}
1098DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1099
1100/*
1101 * Some ATA devices break if put into D3
1102 */
1103
1104static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1105{
1106 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1107}
1108/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1109DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1110 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1111DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1112 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1113/* ALi loses some register settings that we cannot then restore */
1114DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1115 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1116/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1117 occur when mode detecting */
1118DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1119 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1120
1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */
1124static void __init quirk_eisa_bridge(struct pci_dev *dev)
1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127}
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1129
1130
1131/*
1132 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1133 * is not activated. The myth is that Asus said that they do not want the
1134 * users to be irritated by just another PCI Device in the Win98 device
1135 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1136 * package 2.7.0 for details)
1137 *
1138 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1139 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1140 * becomes necessary to do this tweak in two steps -- the chosen trigger
1141 * is either the Host bridge (preferred) or on-board VGA controller.
1142 *
1143 * Note that we used to unhide the SMBus that way on Toshiba laptops
1144 * (Satellite A40 and Tecra M2) but then found that the thermal management
1145 * was done by SMM code, which could cause unsynchronized concurrent
1146 * accesses to the SMBus registers, with potentially bad effects. Thus you
1147 * should be very careful when adding new entries: if SMM is accessing the
1148 * Intel SMBus, this is a very good reason to leave it hidden.
1149 *
1150 * Likewise, many recent laptops use ACPI for thermal management. If the
1151 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1152 * natively, and keeping the SMBus hidden is the right thing to do. If you
1153 * are about to add an entry in the table below, please first disassemble
1154 * the DSDT and double-check that there is no code accessing the SMBus.
1155 */
1156static int asus_hides_smbus;
1157
1158static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1162 switch(dev->subsystem_device) {
1163 case 0x8025: /* P4B-LX */
1164 case 0x8070: /* P4B */
1165 case 0x8088: /* P4B533 */
1166 case 0x1626: /* L3C notebook */
1167 asus_hides_smbus = 1;
1168 }
1169 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1170 switch(dev->subsystem_device) {
1171 case 0x80b1: /* P4GE-V */
1172 case 0x80b2: /* P4PE */
1173 case 0x8093: /* P4B533-V */
1174 asus_hides_smbus = 1;
1175 }
1176 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1177 switch(dev->subsystem_device) {
1178 case 0x8030: /* P4T533 */
1179 asus_hides_smbus = 1;
1180 }
1181 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1182 switch (dev->subsystem_device) {
1183 case 0x8070: /* P4G8X Deluxe */
1184 asus_hides_smbus = 1;
1185 }
1186 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1187 switch (dev->subsystem_device) {
1188 case 0x80c9: /* PU-DLS */
1189 asus_hides_smbus = 1;
1190 }
1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x1751: /* M2N notebook */
1194 case 0x1821: /* M5N notebook */
1195 case 0x1897: /* A6L notebook */
1196 asus_hides_smbus = 1;
1197 }
1198 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1199 switch (dev->subsystem_device) {
1200 case 0x184b: /* W1N notebook */
1201 case 0x186a: /* M6Ne notebook */
1202 asus_hides_smbus = 1;
1203 }
1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x80f2: /* P4P800-X */
1207 asus_hides_smbus = 1;
1208 }
1209 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1210 switch (dev->subsystem_device) {
1211 case 0x1882: /* M6V notebook */
1212 case 0x1977: /* A6VA notebook */
1213 asus_hides_smbus = 1;
1214 }
1215 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1216 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1217 switch(dev->subsystem_device) {
1218 case 0x088C: /* HP Compaq nc8000 */
1219 case 0x0890: /* HP Compaq nc6000 */
1220 asus_hides_smbus = 1;
1221 }
1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1223 switch (dev->subsystem_device) {
1224 case 0x12bc: /* HP D330L */
1225 case 0x12bd: /* HP D530 */
1226 case 0x006a: /* HP Compaq nx9500 */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x12bf: /* HP xw4100 */
1232 asus_hides_smbus = 1;
1233 }
1234 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1235 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1236 switch(dev->subsystem_device) {
1237 case 0xC00C: /* Samsung P35 notebook */
1238 asus_hides_smbus = 1;
1239 }
1240 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1241 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch(dev->subsystem_device) {
1243 case 0x0058: /* Compaq Evo N620c */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1247 switch(dev->subsystem_device) {
1248 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1249 /* Motherboard doesn't have Host bridge
1250 * subvendor/subdevice IDs, therefore checking
1251 * its on-board VGA controller */
1252 asus_hides_smbus = 1;
1253 }
1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1255 switch(dev->subsystem_device) {
1256 case 0x00b8: /* Compaq Evo D510 CMT */
1257 case 0x00b9: /* Compaq Evo D510 SFF */
1258 case 0x00ba: /* Compaq Evo D510 USDT */
1259 /* Motherboard doesn't have Host bridge
1260 * subvendor/subdevice IDs and on-board VGA
1261 * controller is disabled if an AGP card is
1262 * inserted, therefore checking USB UHCI
1263 * Controller #1 */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1267 switch (dev->subsystem_device) {
1268 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1269 /* Motherboard doesn't have host bridge
1270 * subvendor/subdevice IDs, therefore checking
1271 * its on-board VGA controller */
1272 asus_hides_smbus = 1;
1273 }
1274 }
1275}
1276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1286
1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1290
1291static void asus_hides_smbus_lpc(struct pci_dev *dev)
1292{
1293 u16 val;
1294
1295 if (likely(!asus_hides_smbus))
1296 return;
1297
1298 pci_read_config_word(dev, 0xF2, &val);
1299 if (val & 0x8) {
1300 pci_write_config_word(dev, 0xF2, val & (~0x8));
1301 pci_read_config_word(dev, 0xF2, &val);
1302 if (val & 0x8)
1303 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1304 else
1305 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1306 }
1307}
1308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1316DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1317DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1318DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1321DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1322
1323/* It appears we just have one such device. If not, we have a warning */
1324static void __iomem *asus_rcba_base;
1325static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1326{
1327 u32 rcba;
1328
1329 if (likely(!asus_hides_smbus))
1330 return;
1331 WARN_ON(asus_rcba_base);
1332
1333 pci_read_config_dword(dev, 0xF0, &rcba);
1334 /* use bits 31:14, 16 kB aligned */
1335 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1336 if (asus_rcba_base == NULL)
1337 return;
1338}
1339
1340static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1341{
1342 u32 val;
1343
1344 if (likely(!asus_hides_smbus || !asus_rcba_base))
1345 return;
1346 /* read the Function Disable register, dword mode only */
1347 val = readl(asus_rcba_base + 0x3418);
1348 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1349}
1350
1351static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1352{
1353 if (likely(!asus_hides_smbus || !asus_rcba_base))
1354 return;
1355 iounmap(asus_rcba_base);
1356 asus_rcba_base = NULL;
1357 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1358}
1359
1360static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1361{
1362 asus_hides_smbus_lpc_ich6_suspend(dev);
1363 asus_hides_smbus_lpc_ich6_resume_early(dev);
1364 asus_hides_smbus_lpc_ich6_resume(dev);
1365}
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1367DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1368DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1369DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1370
1371/*
1372 * SiS 96x south bridge: BIOS typically hides SMBus device...
1373 */
1374static void quirk_sis_96x_smbus(struct pci_dev *dev)
1375{
1376 u8 val = 0;
1377 pci_read_config_byte(dev, 0x77, &val);
1378 if (val & 0x10) {
1379 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1380 pci_write_config_byte(dev, 0x77, val & ~0x10);
1381 }
1382}
1383DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1387DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1388DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1390DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1391
1392/*
1393 * ... This is further complicated by the fact that some SiS96x south
1394 * bridges pretend to be 85C503/5513 instead. In that case see if we
1395 * spotted a compatible north bridge to make sure.
1396 * (pci_find_device doesn't work yet)
1397 *
1398 * We can also enable the sis96x bit in the discovery register..
1399 */
1400#define SIS_DETECT_REGISTER 0x40
1401
1402static void quirk_sis_503(struct pci_dev *dev)
1403{
1404 u8 reg;
1405 u16 devid;
1406
1407 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1408 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1409 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1410 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1411 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1412 return;
1413 }
1414
1415 /*
1416 * Ok, it now shows up as a 96x.. run the 96x quirk by
1417 * hand in case it has already been processed.
1418 * (depends on link order, which is apparently not guaranteed)
1419 */
1420 dev->device = devid;
1421 quirk_sis_96x_smbus(dev);
1422}
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1425
1426
1427/*
1428 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1429 * and MC97 modem controller are disabled when a second PCI soundcard is
1430 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1431 * -- bjd
1432 */
1433static void asus_hides_ac97_lpc(struct pci_dev *dev)
1434{
1435 u8 val;
1436 int asus_hides_ac97 = 0;
1437
1438 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1439 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1440 asus_hides_ac97 = 1;
1441 }
1442
1443 if (!asus_hides_ac97)
1444 return;
1445
1446 pci_read_config_byte(dev, 0x50, &val);
1447 if (val & 0xc0) {
1448 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1449 pci_read_config_byte(dev, 0x50, &val);
1450 if (val & 0xc0)
1451 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1452 else
1453 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1454 }
1455}
1456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1457DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1458
1459#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1460
1461/*
1462 * If we are using libata we can drive this chip properly but must
1463 * do this early on to make the additional device appear during
1464 * the PCI scanning.
1465 */
1466static void quirk_jmicron_ata(struct pci_dev *pdev)
1467{
1468 u32 conf1, conf5, class;
1469 u8 hdr;
1470
1471 /* Only poke fn 0 */
1472 if (PCI_FUNC(pdev->devfn))
1473 return;
1474
1475 pci_read_config_dword(pdev, 0x40, &conf1);
1476 pci_read_config_dword(pdev, 0x80, &conf5);
1477
1478 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1479 conf5 &= ~(1 << 24); /* Clear bit 24 */
1480
1481 switch (pdev->device) {
1482 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1483 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1484 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1485 /* The controller should be in single function ahci mode */
1486 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1487 break;
1488
1489 case PCI_DEVICE_ID_JMICRON_JMB365:
1490 case PCI_DEVICE_ID_JMICRON_JMB366:
1491 /* Redirect IDE second PATA port to the right spot */
1492 conf5 |= (1 << 24);
1493 /* Fall through */
1494 case PCI_DEVICE_ID_JMICRON_JMB361:
1495 case PCI_DEVICE_ID_JMICRON_JMB363:
1496 case PCI_DEVICE_ID_JMICRON_JMB369:
1497 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1498 /* Set the class codes correctly and then direct IDE 0 */
1499 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1500 break;
1501
1502 case PCI_DEVICE_ID_JMICRON_JMB368:
1503 /* The controller should be in single function IDE mode */
1504 conf1 |= 0x00C00000; /* Set 22, 23 */
1505 break;
1506 }
1507
1508 pci_write_config_dword(pdev, 0x40, conf1);
1509 pci_write_config_dword(pdev, 0x80, conf5);
1510
1511 /* Update pdev accordingly */
1512 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1513 pdev->hdr_type = hdr & 0x7f;
1514 pdev->multifunction = !!(hdr & 0x80);
1515
1516 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1517 pdev->class = class >> 8;
1518}
1519DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1520DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1521DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1522DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1523DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1524DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1525DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1526DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1527DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1528DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1529DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1530DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1531DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1533DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1534DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1536DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1537
1538#endif
1539
1540#ifdef CONFIG_X86_IO_APIC
1541static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1542{
1543 int i;
1544
1545 if ((pdev->class >> 8) != 0xff00)
1546 return;
1547
1548 /* the first BAR is the location of the IO APIC...we must
1549 * not touch this (and it's already covered by the fixmap), so
1550 * forcibly insert it into the resource tree */
1551 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1552 insert_resource(&iomem_resource, &pdev->resource[0]);
1553
1554 /* The next five BARs all seem to be rubbish, so just clean
1555 * them out */
1556 for (i=1; i < 6; i++) {
1557 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1558 }
1559
1560}
1561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1562#endif
1563
1564static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1565{
1566 pci_msi_off(pdev);
1567 pdev->no_msi = 1;
1568}
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1572
1573
1574/*
1575 * It's possible for the MSI to get corrupted if shpc and acpi
1576 * are used together on certain PXH-based systems.
1577 */
1578static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1579{
1580 pci_msi_off(dev);
1581 dev->no_msi = 1;
1582 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1583}
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1589
1590/*
1591 * Some Intel PCI Express chipsets have trouble with downstream
1592 * device power management.
1593 */
1594static void quirk_intel_pcie_pm(struct pci_dev * dev)
1595{
1596 pci_pm_d3_delay = 120;
1597 dev->no_d1d2 = 1;
1598}
1599
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1621
1622#ifdef CONFIG_X86_IO_APIC
1623/*
1624 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1625 * remap the original interrupt in the linux kernel to the boot interrupt, so
1626 * that a PCI device's interrupt handler is installed on the boot interrupt
1627 * line instead.
1628 */
1629static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1630{
1631 if (noioapicquirk || noioapicreroute)
1632 return;
1633
1634 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1635 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1636 dev->vendor, dev->device);
1637}
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1641DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1646DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1647DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1648DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1649DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1650DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1651DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1652DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1653DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1654
1655/*
1656 * On some chipsets we can disable the generation of legacy INTx boot
1657 * interrupts.
1658 */
1659
1660/*
1661 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1662 * 300641-004US, section 5.7.3.
1663 */
1664#define INTEL_6300_IOAPIC_ABAR 0x40
1665#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1666
1667static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1668{
1669 u16 pci_config_word;
1670
1671 if (noioapicquirk)
1672 return;
1673
1674 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1675 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1676 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1677
1678 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1679 dev->vendor, dev->device);
1680}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1682DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1683
1684/*
1685 * disable boot interrupts on HT-1000
1686 */
1687#define BC_HT1000_FEATURE_REG 0x64
1688#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1689#define BC_HT1000_MAP_IDX 0xC00
1690#define BC_HT1000_MAP_DATA 0xC01
1691
1692static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1693{
1694 u32 pci_config_dword;
1695 u8 irq;
1696
1697 if (noioapicquirk)
1698 return;
1699
1700 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1701 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1702 BC_HT1000_PIC_REGS_ENABLE);
1703
1704 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1705 outb(irq, BC_HT1000_MAP_IDX);
1706 outb(0x00, BC_HT1000_MAP_DATA);
1707 }
1708
1709 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1710
1711 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1712 dev->vendor, dev->device);
1713}
1714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1716
1717/*
1718 * disable boot interrupts on AMD and ATI chipsets
1719 */
1720/*
1721 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1722 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1723 * (due to an erratum).
1724 */
1725#define AMD_813X_MISC 0x40
1726#define AMD_813X_NOIOAMODE (1<<0)
1727#define AMD_813X_REV_B1 0x12
1728#define AMD_813X_REV_B2 0x13
1729
1730static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1731{
1732 u32 pci_config_dword;
1733
1734 if (noioapicquirk)
1735 return;
1736 if ((dev->revision == AMD_813X_REV_B1) ||
1737 (dev->revision == AMD_813X_REV_B2))
1738 return;
1739
1740 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1741 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1742 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1743
1744 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1745 dev->vendor, dev->device);
1746}
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1750DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1751
1752#define AMD_8111_PCI_IRQ_ROUTING 0x56
1753
1754static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1755{
1756 u16 pci_config_word;
1757
1758 if (noioapicquirk)
1759 return;
1760
1761 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1762 if (!pci_config_word) {
1763 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1764 "already disabled\n", dev->vendor, dev->device);
1765 return;
1766 }
1767 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770}
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1773#endif /* CONFIG_X86_IO_APIC */
1774
1775/*
1776 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed...
1779 */
1780static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1781{
1782 struct resource *r = &dev->resource[0];
1783
1784 if (r->start & 0x8) {
1785 r->start = 0;
1786 r->end = 0xf;
1787 }
1788}
1789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1790 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1791 quirk_tc86c001_ide);
1792
1793static void __devinit quirk_netmos(struct pci_dev *dev)
1794{
1795 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1796 unsigned int num_serial = dev->subsystem_device & 0xf;
1797
1798 /*
1799 * These Netmos parts are multiport serial devices with optional
1800 * parallel ports. Even when parallel ports are present, they
1801 * are identified as class SERIAL, which means the serial driver
1802 * will claim them. To prevent this, mark them as class OTHER.
1803 * These combo devices should be claimed by parport_serial.
1804 *
1805 * The subdevice ID is of the form 0x00PS, where <P> is the number
1806 * of parallel ports and <S> is the number of serial ports.
1807 */
1808 switch (dev->device) {
1809 case PCI_DEVICE_ID_NETMOS_9835:
1810 /* Well, this rule doesn't hold for the following 9835 device */
1811 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1812 dev->subsystem_device == 0x0299)
1813 return;
1814 case PCI_DEVICE_ID_NETMOS_9735:
1815 case PCI_DEVICE_ID_NETMOS_9745:
1816 case PCI_DEVICE_ID_NETMOS_9845:
1817 case PCI_DEVICE_ID_NETMOS_9855:
1818 if (num_parallel) {
1819 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1820 "%u serial); changing class SERIAL to OTHER "
1821 "(use parport_serial)\n",
1822 dev->device, num_parallel, num_serial);
1823 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1824 (dev->class & 0xff);
1825 }
1826 }
1827}
1828DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1829 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1830
1831static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1832{
1833 u16 command, pmcsr;
1834 u8 __iomem *csr;
1835 u8 cmd_hi;
1836 int pm;
1837
1838 switch (dev->device) {
1839 /* PCI IDs taken from drivers/net/e100.c */
1840 case 0x1029:
1841 case 0x1030 ... 0x1034:
1842 case 0x1038 ... 0x103E:
1843 case 0x1050 ... 0x1057:
1844 case 0x1059:
1845 case 0x1064 ... 0x106B:
1846 case 0x1091 ... 0x1095:
1847 case 0x1209:
1848 case 0x1229:
1849 case 0x2449:
1850 case 0x2459:
1851 case 0x245D:
1852 case 0x27DC:
1853 break;
1854 default:
1855 return;
1856 }
1857
1858 /*
1859 * Some firmware hands off the e100 with interrupts enabled,
1860 * which can cause a flood of interrupts if packets are
1861 * received before the driver attaches to the device. So
1862 * disable all e100 interrupts here. The driver will
1863 * re-enable them when it's ready.
1864 */
1865 pci_read_config_word(dev, PCI_COMMAND, &command);
1866
1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1868 return;
1869
1870 /*
1871 * Check that the device is in the D0 power state. If it's not,
1872 * there is no point to look any further.
1873 */
1874 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1875 if (pm) {
1876 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1878 return;
1879 }
1880
1881 /* Convert from PCI bus to resource space. */
1882 csr = ioremap(pci_resource_start(dev, 0), 8);
1883 if (!csr) {
1884 dev_warn(&dev->dev, "Can't map e100 registers\n");
1885 return;
1886 }
1887
1888 cmd_hi = readb(csr + 3);
1889 if (cmd_hi == 0) {
1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1891 "disabling\n");
1892 writeb(1, csr + 3);
1893 }
1894
1895 iounmap(csr);
1896}
1897DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1899
1900/*
1901 * The 82575 and 82598 may experience data corruption issues when transitioning
1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1903 */
1904static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1905{
1906 dev_info(&dev->dev, "Disabling L0s\n");
1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1923
1924static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1925{
1926 /* rev 1 ncr53c810 chips don't set the class at all which means
1927 * they don't get their resources remapped. Fix that here.
1928 */
1929
1930 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1932 dev->class = PCI_CLASS_STORAGE_SCSI;
1933 }
1934}
1935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1936
1937/* Enable 1k I/O space granularity on the Intel P64H2 */
1938static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1939{
1940 u16 en1k;
1941 u8 io_base_lo, io_limit_lo;
1942 unsigned long base, limit;
1943 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1944
1945 pci_read_config_word(dev, 0x40, &en1k);
1946
1947 if (en1k & 0x200) {
1948 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1949
1950 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1951 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1952 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1953 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1954
1955 if (base <= limit) {
1956 res->start = base;
1957 res->end = limit + 0x3ff;
1958 }
1959 }
1960}
1961DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1962
1963/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1964 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1965 * in drivers/pci/setup-bus.c
1966 */
1967static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1968{
1969 u16 en1k, iobl_adr, iobl_adr_1k;
1970 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1971
1972 pci_read_config_word(dev, 0x40, &en1k);
1973
1974 if (en1k & 0x200) {
1975 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1976
1977 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1978
1979 if (iobl_adr != iobl_adr_1k) {
1980 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1981 iobl_adr,iobl_adr_1k);
1982 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1983 }
1984 }
1985}
1986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1987
1988/* Under some circumstances, AER is not linked with extended capabilities.
1989 * Force it to be linked by setting the corresponding control bit in the
1990 * config space.
1991 */
1992static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1993{
1994 uint8_t b;
1995 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1996 if (!(b & 0x20)) {
1997 pci_write_config_byte(dev, 0xf41, b | 0x20);
1998 dev_info(&dev->dev,
1999 "Linking AER extended capability\n");
2000 }
2001 }
2002}
2003DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2004 quirk_nvidia_ck804_pcie_aer_ext_cap);
2005DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2006 quirk_nvidia_ck804_pcie_aer_ext_cap);
2007
2008static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2009{
2010 /*
2011 * Disable PCI Bus Parking and PCI Master read caching on CX700
2012 * which causes unspecified timing errors with a VT6212L on the PCI
2013 * bus leading to USB2.0 packet loss.
2014 *
2015 * This quirk is only enabled if a second (on the external PCI bus)
2016 * VT6212L is found -- the CX700 core itself also contains a USB
2017 * host controller with the same PCI ID as the VT6212L.
2018 */
2019
2020 /* Count VT6212L instances */
2021 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2022 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2023 uint8_t b;
2024
2025 /* p should contain the first (internal) VT6212L -- see if we have
2026 an external one by searching again */
2027 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2028 if (!p)
2029 return;
2030 pci_dev_put(p);
2031
2032 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2033 if (b & 0x40) {
2034 /* Turn off PCI Bus Parking */
2035 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2036
2037 dev_info(&dev->dev,
2038 "Disabling VIA CX700 PCI parking\n");
2039 }
2040 }
2041
2042 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2043 if (b != 0) {
2044 /* Turn off PCI Master read caching */
2045 pci_write_config_byte(dev, 0x72, 0x0);
2046
2047 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2048 pci_write_config_byte(dev, 0x75, 0x1);
2049
2050 /* Disable "Read FIFO Timer" */
2051 pci_write_config_byte(dev, 0x77, 0x0);
2052
2053 dev_info(&dev->dev,
2054 "Disabling VIA CX700 PCI caching\n");
2055 }
2056 }
2057}
2058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2059
2060/*
2061 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2062 * VPD end tag will hang the device. This problem was initially
2063 * observed when a vpd entry was created in sysfs
2064 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2065 * will dump 32k of data. Reading a full 32k will cause an access
2066 * beyond the VPD end tag causing the device to hang. Once the device
2067 * is hung, the bnx2 driver will not be able to reset the device.
2068 * We believe that it is legal to read beyond the end tag and
2069 * therefore the solution is to limit the read/write length.
2070 */
2071static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2072{
2073 /*
2074 * Only disable the VPD capability for 5706, 5706S, 5708,
2075 * 5708S and 5709 rev. A
2076 */
2077 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2078 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2079 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2080 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2081 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2082 (dev->revision & 0xf0) == 0x0)) {
2083 if (dev->vpd)
2084 dev->vpd->len = 0x80;
2085 }
2086}
2087
2088DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2089 PCI_DEVICE_ID_NX2_5706,
2090 quirk_brcm_570x_limit_vpd);
2091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2092 PCI_DEVICE_ID_NX2_5706S,
2093 quirk_brcm_570x_limit_vpd);
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2095 PCI_DEVICE_ID_NX2_5708,
2096 quirk_brcm_570x_limit_vpd);
2097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2098 PCI_DEVICE_ID_NX2_5708S,
2099 quirk_brcm_570x_limit_vpd);
2100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2101 PCI_DEVICE_ID_NX2_5709,
2102 quirk_brcm_570x_limit_vpd);
2103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2104 PCI_DEVICE_ID_NX2_5709S,
2105 quirk_brcm_570x_limit_vpd);
2106
2107static void __devinit quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2108{
2109 u32 rev;
2110
2111 pci_read_config_dword(dev, 0xf4, &rev);
2112
2113 /* Only CAP the MRRS if the device is a 5719 A0 */
2114 if (rev == 0x05719000) {
2115 int readrq = pcie_get_readrq(dev);
2116 if (readrq > 2048)
2117 pcie_set_readrq(dev, 2048);
2118 }
2119}
2120
2121DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2122 PCI_DEVICE_ID_TIGON3_5719,
2123 quirk_brcm_5719_limit_mrrs);
2124
2125/* Originally in EDAC sources for i82875P:
2126 * Intel tells BIOS developers to hide device 6 which
2127 * configures the overflow device access containing
2128 * the DRBs - this is where we expose device 6.
2129 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2130 */
2131static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2132{
2133 u8 reg;
2134
2135 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2136 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2137 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2138 }
2139}
2140
2141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2142 quirk_unhide_mch_dev6);
2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2144 quirk_unhide_mch_dev6);
2145
2146#ifdef CONFIG_TILE
2147/*
2148 * The Tilera TILEmpower platform needs to set the link speed
2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2151 * capability register of the PEX8624 PCIe switch. The switch
2152 * supports link speed auto negotiation, but falsely sets
2153 * the link speed to 5GT/s.
2154 */
2155static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2156{
2157 if (tile_plx_gen1) {
2158 pci_write_config_dword(dev, 0x98, 0x1);
2159 mdelay(50);
2160 }
2161}
2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2163#endif /* CONFIG_TILE */
2164
2165#ifdef CONFIG_PCI_MSI
2166/* Some chipsets do not support MSI. We cannot easily rely on setting
2167 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2168 * some other busses controlled by the chipset even if Linux is not
2169 * aware of it. Instead of setting the flag on all busses in the
2170 * machine, simply disable MSI globally.
2171 */
2172static void __init quirk_disable_all_msi(struct pci_dev *dev)
2173{
2174 pci_no_msi();
2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2176}
2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2180DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2181DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2183DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2184
2185/* Disable MSI on chipsets that are known to not support it */
2186static void __devinit quirk_disable_msi(struct pci_dev *dev)
2187{
2188 if (dev->subordinate) {
2189 dev_warn(&dev->dev, "MSI quirk detected; "
2190 "subordinate MSI disabled\n");
2191 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2192 }
2193}
2194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2197
2198/*
2199 * The APC bridge device in AMD 780 family northbridges has some random
2200 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2201 * we use the possible vendor/device IDs of the host bridge for the
2202 * declared quirk, and search for the APC bridge by slot number.
2203 */
2204static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2205{
2206 struct pci_dev *apc_bridge;
2207
2208 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2209 if (apc_bridge) {
2210 if (apc_bridge->device == 0x9602)
2211 quirk_disable_msi(apc_bridge);
2212 pci_dev_put(apc_bridge);
2213 }
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2217
2218/* Go through the list of Hypertransport capabilities and
2219 * return 1 if a HT MSI capability is found and enabled */
2220static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2221{
2222 int pos, ttl = 48;
2223
2224 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2225 while (pos && ttl--) {
2226 u8 flags;
2227
2228 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2229 &flags) == 0)
2230 {
2231 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2232 flags & HT_MSI_FLAGS_ENABLE ?
2233 "enabled" : "disabled");
2234 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2235 }
2236
2237 pos = pci_find_next_ht_capability(dev, pos,
2238 HT_CAPTYPE_MSI_MAPPING);
2239 }
2240 return 0;
2241}
2242
2243/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2244static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2245{
2246 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2247 dev_warn(&dev->dev, "MSI quirk detected; "
2248 "subordinate MSI disabled\n");
2249 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2250 }
2251}
2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2253 quirk_msi_ht_cap);
2254
2255/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2256 * MSI are supported if the MSI capability set in any of these mappings.
2257 */
2258static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2259{
2260 struct pci_dev *pdev;
2261
2262 if (!dev->subordinate)
2263 return;
2264
2265 /* check HT MSI cap on this chipset and the root one.
2266 * a single one having MSI is enough to be sure that MSI are supported.
2267 */
2268 pdev = pci_get_slot(dev->bus, 0);
2269 if (!pdev)
2270 return;
2271 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2272 dev_warn(&dev->dev, "MSI quirk detected; "
2273 "subordinate MSI disabled\n");
2274 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2275 }
2276 pci_dev_put(pdev);
2277}
2278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2279 quirk_nvidia_ck804_msi_ht_cap);
2280
2281/* Force enable MSI mapping capability on HT bridges */
2282static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2283{
2284 int pos, ttl = 48;
2285
2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2287 while (pos && ttl--) {
2288 u8 flags;
2289
2290 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2291 &flags) == 0) {
2292 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2293
2294 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2295 flags | HT_MSI_FLAGS_ENABLE);
2296 }
2297 pos = pci_find_next_ht_capability(dev, pos,
2298 HT_CAPTYPE_MSI_MAPPING);
2299 }
2300}
2301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2302 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2303 ht_enable_msi_mapping);
2304
2305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2306 ht_enable_msi_mapping);
2307
2308/* The P5N32-SLI motherboards from Asus have a problem with msi
2309 * for the MCP55 NIC. It is not yet determined whether the msi problem
2310 * also affects other devices. As for now, turn off msi for this device.
2311 */
2312static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2313{
2314 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2315
2316 if (board_name &&
2317 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2318 strstr(board_name, "P5N32-E SLI"))) {
2319 dev_info(&dev->dev,
2320 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2321 dev->no_msi = 1;
2322 }
2323}
2324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2325 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2326 nvenet_msi_disable);
2327
2328/*
2329 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2330 * config register. This register controls the routing of legacy interrupts
2331 * from devices that route through the MCP55. If this register is misprogramed
2332 * interrupts are only sent to the bsp, unlike conventional systems where the
2333 * irq is broadxast to all online cpus. Not having this register set
2334 * properly prevents kdump from booting up properly, so lets make sure that
2335 * we have it set correctly.
2336 * Note this is an undocumented register.
2337 */
2338static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2339{
2340 u32 cfg;
2341
2342 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2343 return;
2344
2345 pci_read_config_dword(dev, 0x74, &cfg);
2346
2347 if (cfg & ((1 << 2) | (1 << 15))) {
2348 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2349 cfg &= ~((1 << 2) | (1 << 15));
2350 pci_write_config_dword(dev, 0x74, cfg);
2351 }
2352}
2353
2354DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2355 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2356 nvbridge_check_legacy_irq_routing);
2357
2358DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2359 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2360 nvbridge_check_legacy_irq_routing);
2361
2362static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2363{
2364 int pos, ttl = 48;
2365 int found = 0;
2366
2367 /* check if there is HT MSI cap or enabled on this device */
2368 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2369 while (pos && ttl--) {
2370 u8 flags;
2371
2372 if (found < 1)
2373 found = 1;
2374 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2375 &flags) == 0) {
2376 if (flags & HT_MSI_FLAGS_ENABLE) {
2377 if (found < 2) {
2378 found = 2;
2379 break;
2380 }
2381 }
2382 }
2383 pos = pci_find_next_ht_capability(dev, pos,
2384 HT_CAPTYPE_MSI_MAPPING);
2385 }
2386
2387 return found;
2388}
2389
2390static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2391{
2392 struct pci_dev *dev;
2393 int pos;
2394 int i, dev_no;
2395 int found = 0;
2396
2397 dev_no = host_bridge->devfn >> 3;
2398 for (i = dev_no + 1; i < 0x20; i++) {
2399 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2400 if (!dev)
2401 continue;
2402
2403 /* found next host bridge ?*/
2404 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2405 if (pos != 0) {
2406 pci_dev_put(dev);
2407 break;
2408 }
2409
2410 if (ht_check_msi_mapping(dev)) {
2411 found = 1;
2412 pci_dev_put(dev);
2413 break;
2414 }
2415 pci_dev_put(dev);
2416 }
2417
2418 return found;
2419}
2420
2421#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2422#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2423
2424static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2425{
2426 int pos, ctrl_off;
2427 int end = 0;
2428 u16 flags, ctrl;
2429
2430 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2431
2432 if (!pos)
2433 goto out;
2434
2435 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2436
2437 ctrl_off = ((flags >> 10) & 1) ?
2438 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2439 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2440
2441 if (ctrl & (1 << 6))
2442 end = 1;
2443
2444out:
2445 return end;
2446}
2447
2448static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2449{
2450 struct pci_dev *host_bridge;
2451 int pos;
2452 int i, dev_no;
2453 int found = 0;
2454
2455 dev_no = dev->devfn >> 3;
2456 for (i = dev_no; i >= 0; i--) {
2457 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2458 if (!host_bridge)
2459 continue;
2460
2461 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2462 if (pos != 0) {
2463 found = 1;
2464 break;
2465 }
2466 pci_dev_put(host_bridge);
2467 }
2468
2469 if (!found)
2470 return;
2471
2472 /* don't enable end_device/host_bridge with leaf directly here */
2473 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2474 host_bridge_with_leaf(host_bridge))
2475 goto out;
2476
2477 /* root did that ! */
2478 if (msi_ht_cap_enabled(host_bridge))
2479 goto out;
2480
2481 ht_enable_msi_mapping(dev);
2482
2483out:
2484 pci_dev_put(host_bridge);
2485}
2486
2487static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2488{
2489 int pos, ttl = 48;
2490
2491 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2492 while (pos && ttl--) {
2493 u8 flags;
2494
2495 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2496 &flags) == 0) {
2497 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2498
2499 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2500 flags & ~HT_MSI_FLAGS_ENABLE);
2501 }
2502 pos = pci_find_next_ht_capability(dev, pos,
2503 HT_CAPTYPE_MSI_MAPPING);
2504 }
2505}
2506
2507static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2508{
2509 struct pci_dev *host_bridge;
2510 int pos;
2511 int found;
2512
2513 if (!pci_msi_enabled())
2514 return;
2515
2516 /* check if there is HT MSI cap or enabled on this device */
2517 found = ht_check_msi_mapping(dev);
2518
2519 /* no HT MSI CAP */
2520 if (found == 0)
2521 return;
2522
2523 /*
2524 * HT MSI mapping should be disabled on devices that are below
2525 * a non-Hypertransport host bridge. Locate the host bridge...
2526 */
2527 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2528 if (host_bridge == NULL) {
2529 dev_warn(&dev->dev,
2530 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2531 return;
2532 }
2533
2534 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2535 if (pos != 0) {
2536 /* Host bridge is to HT */
2537 if (found == 1) {
2538 /* it is not enabled, try to enable it */
2539 if (all)
2540 ht_enable_msi_mapping(dev);
2541 else
2542 nv_ht_enable_msi_mapping(dev);
2543 }
2544 return;
2545 }
2546
2547 /* HT MSI is not enabled */
2548 if (found == 1)
2549 return;
2550
2551 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2552 ht_disable_msi_mapping(dev);
2553}
2554
2555static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2556{
2557 return __nv_msi_ht_cap_quirk(dev, 1);
2558}
2559
2560static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2561{
2562 return __nv_msi_ht_cap_quirk(dev, 0);
2563}
2564
2565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2566DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2567
2568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2569DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2570
2571static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2572{
2573 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2574}
2575static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2576{
2577 struct pci_dev *p;
2578
2579 /* SB700 MSI issue will be fixed at HW level from revision A21,
2580 * we need check PCI REVISION ID of SMBus controller to get SB700
2581 * revision.
2582 */
2583 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2584 NULL);
2585 if (!p)
2586 return;
2587
2588 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2589 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2590 pci_dev_put(p);
2591}
2592DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2593 PCI_DEVICE_ID_TIGON3_5780,
2594 quirk_msi_intx_disable_bug);
2595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2596 PCI_DEVICE_ID_TIGON3_5780S,
2597 quirk_msi_intx_disable_bug);
2598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2599 PCI_DEVICE_ID_TIGON3_5714,
2600 quirk_msi_intx_disable_bug);
2601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2602 PCI_DEVICE_ID_TIGON3_5714S,
2603 quirk_msi_intx_disable_bug);
2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2605 PCI_DEVICE_ID_TIGON3_5715,
2606 quirk_msi_intx_disable_bug);
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2608 PCI_DEVICE_ID_TIGON3_5715S,
2609 quirk_msi_intx_disable_bug);
2610
2611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2612 quirk_msi_intx_disable_ati_bug);
2613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2614 quirk_msi_intx_disable_ati_bug);
2615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2616 quirk_msi_intx_disable_ati_bug);
2617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2618 quirk_msi_intx_disable_ati_bug);
2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2620 quirk_msi_intx_disable_ati_bug);
2621
2622DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2623 quirk_msi_intx_disable_bug);
2624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2625 quirk_msi_intx_disable_bug);
2626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2627 quirk_msi_intx_disable_bug);
2628
2629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2630 quirk_msi_intx_disable_bug);
2631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2632 quirk_msi_intx_disable_bug);
2633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2634 quirk_msi_intx_disable_bug);
2635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2636 quirk_msi_intx_disable_bug);
2637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2640 quirk_msi_intx_disable_bug);
2641#endif /* CONFIG_PCI_MSI */
2642
2643/* Allow manual resource allocation for PCI hotplug bridges
2644 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2645 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2646 * kernel fails to allocate resources when hotplug device is
2647 * inserted and PCI bus is rescanned.
2648 */
2649static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2650{
2651 dev->is_hotplug_bridge = 1;
2652}
2653
2654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2655
2656/*
2657 * This is a quirk for the Ricoh MMC controller found as a part of
2658 * some mulifunction chips.
2659
2660 * This is very similar and based on the ricoh_mmc driver written by
2661 * Philip Langdale. Thank you for these magic sequences.
2662 *
2663 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2664 * and one or both of cardbus or firewire.
2665 *
2666 * It happens that they implement SD and MMC
2667 * support as separate controllers (and PCI functions). The linux SDHCI
2668 * driver supports MMC cards but the chip detects MMC cards in hardware
2669 * and directs them to the MMC controller - so the SDHCI driver never sees
2670 * them.
2671 *
2672 * To get around this, we must disable the useless MMC controller.
2673 * At that point, the SDHCI controller will start seeing them
2674 * It seems to be the case that the relevant PCI registers to deactivate the
2675 * MMC controller live on PCI function 0, which might be the cardbus controller
2676 * or the firewire controller, depending on the particular chip in question
2677 *
2678 * This has to be done early, because as soon as we disable the MMC controller
2679 * other pci functions shift up one level, e.g. function #2 becomes function
2680 * #1, and this will confuse the pci core.
2681 */
2682
2683#ifdef CONFIG_MMC_RICOH_MMC
2684static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2685{
2686 /* disable via cardbus interface */
2687 u8 write_enable;
2688 u8 write_target;
2689 u8 disable;
2690
2691 /* disable must be done via function #0 */
2692 if (PCI_FUNC(dev->devfn))
2693 return;
2694
2695 pci_read_config_byte(dev, 0xB7, &disable);
2696 if (disable & 0x02)
2697 return;
2698
2699 pci_read_config_byte(dev, 0x8E, &write_enable);
2700 pci_write_config_byte(dev, 0x8E, 0xAA);
2701 pci_read_config_byte(dev, 0x8D, &write_target);
2702 pci_write_config_byte(dev, 0x8D, 0xB7);
2703 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2704 pci_write_config_byte(dev, 0x8E, write_enable);
2705 pci_write_config_byte(dev, 0x8D, write_target);
2706
2707 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2708 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2709}
2710DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2711DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2712
2713static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2714{
2715 /* disable via firewire interface */
2716 u8 write_enable;
2717 u8 disable;
2718
2719 /* disable must be done via function #0 */
2720 if (PCI_FUNC(dev->devfn))
2721 return;
2722 /*
2723 * RICOH 0xe823 SD/MMC card reader fails to recognize
2724 * certain types of SD/MMC cards. Lowering the SD base
2725 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2726 *
2727 * 0x150 - SD2.0 mode enable for changing base clock
2728 * frequency to 50Mhz
2729 * 0xe1 - Base clock frequency
2730 * 0x32 - 50Mhz new clock frequency
2731 * 0xf9 - Key register for 0x150
2732 * 0xfc - key register for 0xe1
2733 */
2734 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2735 pci_write_config_byte(dev, 0xf9, 0xfc);
2736 pci_write_config_byte(dev, 0x150, 0x10);
2737 pci_write_config_byte(dev, 0xf9, 0x00);
2738 pci_write_config_byte(dev, 0xfc, 0x01);
2739 pci_write_config_byte(dev, 0xe1, 0x32);
2740 pci_write_config_byte(dev, 0xfc, 0x00);
2741
2742 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2743 }
2744
2745 pci_read_config_byte(dev, 0xCB, &disable);
2746
2747 if (disable & 0x02)
2748 return;
2749
2750 pci_read_config_byte(dev, 0xCA, &write_enable);
2751 pci_write_config_byte(dev, 0xCA, 0x57);
2752 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2753 pci_write_config_byte(dev, 0xCA, write_enable);
2754
2755 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2756 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2757
2758}
2759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2762DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2763#endif /*CONFIG_MMC_RICOH_MMC*/
2764
2765#ifdef CONFIG_DMAR_TABLE
2766#define VTUNCERRMSK_REG 0x1ac
2767#define VTD_MSK_SPEC_ERRORS (1 << 31)
2768/*
2769 * This is a quirk for masking vt-d spec defined errors to platform error
2770 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2771 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2772 * on the RAS config settings of the platform) when a vt-d fault happens.
2773 * The resulting SMI caused the system to hang.
2774 *
2775 * VT-d spec related errors are already handled by the VT-d OS code, so no
2776 * need to report the same error through other channels.
2777 */
2778static void vtd_mask_spec_errors(struct pci_dev *dev)
2779{
2780 u32 word;
2781
2782 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2783 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2784}
2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2786DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2787#endif
2788
2789static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2790{
2791 /* TI 816x devices do not have class code set when in PCIe boot mode */
2792 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2793 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2794}
2795DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2796 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2797
2798/* Some PCIe devices do not work reliably with the claimed maximum
2799 * payload size supported.
2800 */
2801static void __devinit fixup_mpss_256(struct pci_dev *dev)
2802{
2803 dev->pcie_mpss = 1; /* 256 bytes */
2804}
2805DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2806 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2807DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2808 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2809DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2810 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2811
2812/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2813 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2814 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2815 * until all of the devices are discovered and buses walked, read completion
2816 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2817 * it is possible to hotplug a device with MPS of 256B.
2818 */
2819static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2820{
2821 int err;
2822 u16 rcc;
2823
2824 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2825 return;
2826
2827 /* Intel errata specifies bits to change but does not say what they are.
2828 * Keeping them magical until such time as the registers and values can
2829 * be explained.
2830 */
2831 err = pci_read_config_word(dev, 0x48, &rcc);
2832 if (err) {
2833 dev_err(&dev->dev, "Error attempting to read the read "
2834 "completion coalescing register.\n");
2835 return;
2836 }
2837
2838 if (!(rcc & (1 << 10)))
2839 return;
2840
2841 rcc &= ~(1 << 10);
2842
2843 err = pci_write_config_word(dev, 0x48, rcc);
2844 if (err) {
2845 dev_err(&dev->dev, "Error attempting to write the read "
2846 "completion coalescing register.\n");
2847 return;
2848 }
2849
2850 pr_info_once("Read completion coalescing disabled due to hardware "
2851 "errata relating to 256B MPS.\n");
2852}
2853/* Intel 5000 series memory controllers and ports 2-7 */
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2868/* Intel 5100 series memory controllers and ports 2-7 */
2869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2874DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2877DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2879DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2880
2881
2882static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev)
2883{
2884 ktime_t calltime, delta, rettime;
2885 unsigned long long duration;
2886
2887 printk(KERN_DEBUG "calling %pF @ %i for %s\n",
2888 fn, task_pid_nr(current), dev_name(&dev->dev));
2889 calltime = ktime_get();
2890 fn(dev);
2891 rettime = ktime_get();
2892 delta = ktime_sub(rettime, calltime);
2893 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2894 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs for %s\n",
2895 fn, duration, dev_name(&dev->dev));
2896}
2897
2898/*
2899 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2900 * even though no one is handling them (f.e. i915 driver is never loaded).
2901 * Additionally the interrupt destination is not set up properly
2902 * and the interrupt ends up -somewhere-.
2903 *
2904 * These spurious interrupts are "sticky" and the kernel disables
2905 * the (shared) interrupt line after 100.000+ generated interrupts.
2906 *
2907 * Fix it by disabling the still enabled interrupts.
2908 * This resolves crashes often seen on monitor unplug.
2909 */
2910#define I915_DEIER_REG 0x4400c
2911static void __devinit disable_igfx_irq(struct pci_dev *dev)
2912{
2913 void __iomem *regs = pci_iomap(dev, 0, 0);
2914 if (regs == NULL) {
2915 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2916 return;
2917 }
2918
2919 /* Check if any interrupt line is still enabled */
2920 if (readl(regs + I915_DEIER_REG) != 0) {
2921 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2922 "disabling\n");
2923
2924 writel(0, regs + I915_DEIER_REG);
2925 }
2926
2927 pci_iounmap(dev, regs);
2928}
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931
2932static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2933 struct pci_fixup *end)
2934{
2935 for (; f < end; f++)
2936 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2937 f->class == (u32) PCI_ANY_ID) &&
2938 (f->vendor == dev->vendor ||
2939 f->vendor == (u16) PCI_ANY_ID) &&
2940 (f->device == dev->device ||
2941 f->device == (u16) PCI_ANY_ID)) {
2942 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2943 if (initcall_debug)
2944 do_one_fixup_debug(f->hook, dev);
2945 else
2946 f->hook(dev);
2947 }
2948}
2949
2950extern struct pci_fixup __start_pci_fixups_early[];
2951extern struct pci_fixup __end_pci_fixups_early[];
2952extern struct pci_fixup __start_pci_fixups_header[];
2953extern struct pci_fixup __end_pci_fixups_header[];
2954extern struct pci_fixup __start_pci_fixups_final[];
2955extern struct pci_fixup __end_pci_fixups_final[];
2956extern struct pci_fixup __start_pci_fixups_enable[];
2957extern struct pci_fixup __end_pci_fixups_enable[];
2958extern struct pci_fixup __start_pci_fixups_resume[];
2959extern struct pci_fixup __end_pci_fixups_resume[];
2960extern struct pci_fixup __start_pci_fixups_resume_early[];
2961extern struct pci_fixup __end_pci_fixups_resume_early[];
2962extern struct pci_fixup __start_pci_fixups_suspend[];
2963extern struct pci_fixup __end_pci_fixups_suspend[];
2964
2965
2966void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2967{
2968 struct pci_fixup *start, *end;
2969
2970 switch(pass) {
2971 case pci_fixup_early:
2972 start = __start_pci_fixups_early;
2973 end = __end_pci_fixups_early;
2974 break;
2975
2976 case pci_fixup_header:
2977 start = __start_pci_fixups_header;
2978 end = __end_pci_fixups_header;
2979 break;
2980
2981 case pci_fixup_final:
2982 start = __start_pci_fixups_final;
2983 end = __end_pci_fixups_final;
2984 break;
2985
2986 case pci_fixup_enable:
2987 start = __start_pci_fixups_enable;
2988 end = __end_pci_fixups_enable;
2989 break;
2990
2991 case pci_fixup_resume:
2992 start = __start_pci_fixups_resume;
2993 end = __end_pci_fixups_resume;
2994 break;
2995
2996 case pci_fixup_resume_early:
2997 start = __start_pci_fixups_resume_early;
2998 end = __end_pci_fixups_resume_early;
2999 break;
3000
3001 case pci_fixup_suspend:
3002 start = __start_pci_fixups_suspend;
3003 end = __end_pci_fixups_suspend;
3004 break;
3005
3006 default:
3007 /* stupid compiler warning, you would think with an enum... */
3008 return;
3009 }
3010 pci_do_fixups(dev, start, end);
3011}
3012EXPORT_SYMBOL(pci_fixup_device);
3013
3014static int __init pci_apply_final_quirks(void)
3015{
3016 struct pci_dev *dev = NULL;
3017 u8 cls = 0;
3018 u8 tmp;
3019
3020 if (pci_cache_line_size)
3021 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3022 pci_cache_line_size << 2);
3023
3024 for_each_pci_dev(dev) {
3025 pci_fixup_device(pci_fixup_final, dev);
3026 /*
3027 * If arch hasn't set it explicitly yet, use the CLS
3028 * value shared by all PCI devices. If there's a
3029 * mismatch, fall back to the default value.
3030 */
3031 if (!pci_cache_line_size) {
3032 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3033 if (!cls)
3034 cls = tmp;
3035 if (!tmp || cls == tmp)
3036 continue;
3037
3038 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3039 "using %u bytes\n", cls << 2, tmp << 2,
3040 pci_dfl_cache_line_size << 2);
3041 pci_cache_line_size = pci_dfl_cache_line_size;
3042 }
3043 }
3044 if (!pci_cache_line_size) {
3045 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3046 cls << 2, pci_dfl_cache_line_size << 2);
3047 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3048 }
3049
3050 return 0;
3051}
3052
3053fs_initcall_sync(pci_apply_final_quirks);
3054
3055/*
3056 * Followings are device-specific reset methods which can be used to
3057 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3058 * not available.
3059 */
3060static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3061{
3062 int pos;
3063
3064 /* only implement PCI_CLASS_SERIAL_USB at present */
3065 if (dev->class == PCI_CLASS_SERIAL_USB) {
3066 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3067 if (!pos)
3068 return -ENOTTY;
3069
3070 if (probe)
3071 return 0;
3072
3073 pci_write_config_byte(dev, pos + 0x4, 1);
3074 msleep(100);
3075
3076 return 0;
3077 } else {
3078 return -ENOTTY;
3079 }
3080}
3081
3082static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3083{
3084 int pos;
3085
3086 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3087 if (!pos)
3088 return -ENOTTY;
3089
3090 if (probe)
3091 return 0;
3092
3093 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3094 PCI_EXP_DEVCTL_BCR_FLR);
3095 msleep(100);
3096
3097 return 0;
3098}
3099
3100#include "../gpu/drm/i915/i915_reg.h"
3101#define MSG_CTL 0x45010
3102#define NSDE_PWR_STATE 0xd0100
3103#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3104
3105static int reset_ivb_igd(struct pci_dev *dev, int probe)
3106{
3107 void __iomem *mmio_base;
3108 unsigned long timeout;
3109 u32 val;
3110
3111 if (probe)
3112 return 0;
3113
3114 mmio_base = pci_iomap(dev, 0, 0);
3115 if (!mmio_base)
3116 return -ENOMEM;
3117
3118 iowrite32(0x00000002, mmio_base + MSG_CTL);
3119
3120 /*
3121 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3122 * driver loaded sets the right bits. However, this's a reset and
3123 * the bits have been set by i915 previously, so we clobber
3124 * SOUTH_CHICKEN2 register directly here.
3125 */
3126 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3127
3128 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3129 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3130
3131 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3132 do {
3133 val = ioread32(mmio_base + PCH_PP_STATUS);
3134 if ((val & 0xb0000000) == 0)
3135 goto reset_complete;
3136 msleep(10);
3137 } while (time_before(jiffies, timeout));
3138 dev_warn(&dev->dev, "timeout during reset\n");
3139
3140reset_complete:
3141 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3142
3143 pci_iounmap(dev, mmio_base);
3144 return 0;
3145}
3146
3147#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3148#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3149#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3150
3151static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3152 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3153 reset_intel_82599_sfp_virtfn },
3154 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3155 reset_ivb_igd },
3156 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3157 reset_ivb_igd },
3158 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3159 reset_intel_generic_dev },
3160 { 0 }
3161};
3162
3163/*
3164 * These device-specific reset methods are here rather than in a driver
3165 * because when a host assigns a device to a guest VM, the host may need
3166 * to reset the device but probably doesn't have a driver for it.
3167 */
3168int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3169{
3170 const struct pci_dev_reset_methods *i;
3171
3172 for (i = pci_dev_reset_methods; i->reset; i++) {
3173 if ((i->vendor == dev->vendor ||
3174 i->vendor == (u16)PCI_ANY_ID) &&
3175 (i->device == dev->device ||
3176 i->device == (u16)PCI_ANY_ID))
3177 return i->reset(dev, probe);
3178 }
3179
3180 return -ENOTTY;
3181}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/acpi.h>
22#include <linux/dmi.h>
23#include <linux/ioport.h>
24#include <linux/sched.h>
25#include <linux/ktime.h>
26#include <linux/mm.h>
27#include <linux/nvme.h>
28#include <linux/platform_data/x86/apple.h>
29#include <linux/pm_runtime.h>
30#include <linux/suspend.h>
31#include <linux/switchtec.h>
32#include <asm/dma.h> /* isa_dma_bridge_buggy */
33#include "pci.h"
34
35static ktime_t fixup_debug_start(struct pci_dev *dev,
36 void (*fn)(struct pci_dev *dev))
37{
38 if (initcall_debug)
39 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
40
41 return ktime_get();
42}
43
44static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
45 void (*fn)(struct pci_dev *dev))
46{
47 ktime_t delta, rettime;
48 unsigned long long duration;
49
50 rettime = ktime_get();
51 delta = ktime_sub(rettime, calltime);
52 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
53 if (initcall_debug || duration > 10000)
54 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
55}
56
57static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
58 struct pci_fixup *end)
59{
60 ktime_t calltime;
61
62 for (; f < end; f++)
63 if ((f->class == (u32) (dev->class >> f->class_shift) ||
64 f->class == (u32) PCI_ANY_ID) &&
65 (f->vendor == dev->vendor ||
66 f->vendor == (u16) PCI_ANY_ID) &&
67 (f->device == dev->device ||
68 f->device == (u16) PCI_ANY_ID)) {
69 void (*hook)(struct pci_dev *dev);
70#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 hook = offset_to_ptr(&f->hook_offset);
72#else
73 hook = f->hook;
74#endif
75 calltime = fixup_debug_start(dev, hook);
76 hook(dev);
77 fixup_debug_report(dev, calltime, hook);
78 }
79}
80
81extern struct pci_fixup __start_pci_fixups_early[];
82extern struct pci_fixup __end_pci_fixups_early[];
83extern struct pci_fixup __start_pci_fixups_header[];
84extern struct pci_fixup __end_pci_fixups_header[];
85extern struct pci_fixup __start_pci_fixups_final[];
86extern struct pci_fixup __end_pci_fixups_final[];
87extern struct pci_fixup __start_pci_fixups_enable[];
88extern struct pci_fixup __end_pci_fixups_enable[];
89extern struct pci_fixup __start_pci_fixups_resume[];
90extern struct pci_fixup __end_pci_fixups_resume[];
91extern struct pci_fixup __start_pci_fixups_resume_early[];
92extern struct pci_fixup __end_pci_fixups_resume_early[];
93extern struct pci_fixup __start_pci_fixups_suspend[];
94extern struct pci_fixup __end_pci_fixups_suspend[];
95extern struct pci_fixup __start_pci_fixups_suspend_late[];
96extern struct pci_fixup __end_pci_fixups_suspend_late[];
97
98static bool pci_apply_fixup_final_quirks;
99
100void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
101{
102 struct pci_fixup *start, *end;
103
104 switch (pass) {
105 case pci_fixup_early:
106 start = __start_pci_fixups_early;
107 end = __end_pci_fixups_early;
108 break;
109
110 case pci_fixup_header:
111 start = __start_pci_fixups_header;
112 end = __end_pci_fixups_header;
113 break;
114
115 case pci_fixup_final:
116 if (!pci_apply_fixup_final_quirks)
117 return;
118 start = __start_pci_fixups_final;
119 end = __end_pci_fixups_final;
120 break;
121
122 case pci_fixup_enable:
123 start = __start_pci_fixups_enable;
124 end = __end_pci_fixups_enable;
125 break;
126
127 case pci_fixup_resume:
128 start = __start_pci_fixups_resume;
129 end = __end_pci_fixups_resume;
130 break;
131
132 case pci_fixup_resume_early:
133 start = __start_pci_fixups_resume_early;
134 end = __end_pci_fixups_resume_early;
135 break;
136
137 case pci_fixup_suspend:
138 start = __start_pci_fixups_suspend;
139 end = __end_pci_fixups_suspend;
140 break;
141
142 case pci_fixup_suspend_late:
143 start = __start_pci_fixups_suspend_late;
144 end = __end_pci_fixups_suspend_late;
145 break;
146
147 default:
148 /* stupid compiler warning, you would think with an enum... */
149 return;
150 }
151 pci_do_fixups(dev, start, end);
152}
153EXPORT_SYMBOL(pci_fixup_device);
154
155static int __init pci_apply_final_quirks(void)
156{
157 struct pci_dev *dev = NULL;
158 u8 cls = 0;
159 u8 tmp;
160
161 if (pci_cache_line_size)
162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
163
164 pci_apply_fixup_final_quirks = true;
165 for_each_pci_dev(dev) {
166 pci_fixup_device(pci_fixup_final, dev);
167 /*
168 * If arch hasn't set it explicitly yet, use the CLS
169 * value shared by all PCI devices. If there's a
170 * mismatch, fall back to the default value.
171 */
172 if (!pci_cache_line_size) {
173 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
174 if (!cls)
175 cls = tmp;
176 if (!tmp || cls == tmp)
177 continue;
178
179 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
180 cls << 2, tmp << 2,
181 pci_dfl_cache_line_size << 2);
182 pci_cache_line_size = pci_dfl_cache_line_size;
183 }
184 }
185
186 if (!pci_cache_line_size) {
187 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
188 pci_dfl_cache_line_size << 2);
189 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
190 }
191
192 return 0;
193}
194fs_initcall_sync(pci_apply_final_quirks);
195
196/*
197 * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 * conflict. But doing so may cause problems on host bridge and perhaps other
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
201 */
202static void quirk_mmio_always_on(struct pci_dev *dev)
203{
204 dev->mmio_always_on = 1;
205}
206DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
207 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
208
209/*
210 * The Mellanox Tavor device gives false positive parity errors. Disable
211 * parity error reporting.
212 */
213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
215
216/*
217 * Deal with broken BIOSes that neglect to enable passive release,
218 * which can cause problems in combination with the 82441FX/PPro MTRRs
219 */
220static void quirk_passive_release(struct pci_dev *dev)
221{
222 struct pci_dev *d = NULL;
223 unsigned char dlc;
224
225 /*
226 * We have to make sure a particular bit is set in the PIIX3
227 * ISA bridge, so we have to go out and find it.
228 */
229 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
230 pci_read_config_byte(d, 0x82, &dlc);
231 if (!(dlc & 1<<1)) {
232 pci_info(d, "PIIX3: Enabling Passive Release\n");
233 dlc |= 1<<1;
234 pci_write_config_byte(d, 0x82, dlc);
235 }
236 }
237}
238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
239DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
240
241/*
242 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
243 * workaround but VIA don't answer queries. If you happen to have good
244 * contacts at VIA ask them for me please -- Alan
245 *
246 * This appears to be BIOS not version dependent. So presumably there is a
247 * chipset level fix.
248 */
249static void quirk_isa_dma_hangs(struct pci_dev *dev)
250{
251 if (!isa_dma_bridge_buggy) {
252 isa_dma_bridge_buggy = 1;
253 pci_info(dev, "Activating ISA DMA hang workarounds\n");
254 }
255}
256/*
257 * It's not totally clear which chipsets are the problematic ones. We know
258 * 82C586 and 82C596 variants are affected.
259 */
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
264DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
266DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
267
268/*
269 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
270 * for some HT machines to use C4 w/o hanging.
271 */
272static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
273{
274 u32 pmbase;
275 u16 pm1a;
276
277 pci_read_config_dword(dev, 0x40, &pmbase);
278 pmbase = pmbase & 0xff80;
279 pm1a = inw(pmbase);
280
281 if (pm1a & 0x10) {
282 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
283 outw(0x10, pmbase);
284 }
285}
286DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
287
288/* Chipsets where PCI->PCI transfers vanish or hang */
289static void quirk_nopcipci(struct pci_dev *dev)
290{
291 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
292 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
293 pci_pci_problems |= PCIPCI_FAIL;
294 }
295}
296DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
298
299static void quirk_nopciamd(struct pci_dev *dev)
300{
301 u8 rev;
302 pci_read_config_byte(dev, 0x08, &rev);
303 if (rev == 0x13) {
304 /* Erratum 24 */
305 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
306 pci_pci_problems |= PCIAGP_FAIL;
307 }
308}
309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
310
311/* Triton requires workarounds to be used by the drivers */
312static void quirk_triton(struct pci_dev *dev)
313{
314 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
315 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
316 pci_pci_problems |= PCIPCI_TRITON;
317 }
318}
319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
323
324/*
325 * VIA Apollo KT133 needs PCI latency patch
326 * Made according to a Windows driver-based patch by George E. Breese;
327 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
328 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
329 * which Mr Breese based his work.
330 *
331 * Updated based on further information from the site and also on
332 * information provided by VIA
333 */
334static void quirk_vialatency(struct pci_dev *dev)
335{
336 struct pci_dev *p;
337 u8 busarb;
338
339 /*
340 * Ok, we have a potential problem chipset here. Now see if we have
341 * a buggy southbridge.
342 */
343 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
344 if (p != NULL) {
345
346 /*
347 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
348 * thanks Dan Hollis.
349 * Check for buggy part revisions
350 */
351 if (p->revision < 0x40 || p->revision > 0x42)
352 goto exit;
353 } else {
354 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
355 if (p == NULL) /* No problem parts */
356 goto exit;
357
358 /* Check for buggy part revisions */
359 if (p->revision < 0x10 || p->revision > 0x12)
360 goto exit;
361 }
362
363 /*
364 * Ok we have the problem. Now set the PCI master grant to occur
365 * every master grant. The apparent bug is that under high PCI load
366 * (quite common in Linux of course) you can get data loss when the
367 * CPU is held off the bus for 3 bus master requests. This happens
368 * to include the IDE controllers....
369 *
370 * VIA only apply this fix when an SB Live! is present but under
371 * both Linux and Windows this isn't enough, and we have seen
372 * corruption without SB Live! but with things like 3 UDMA IDE
373 * controllers. So we ignore that bit of the VIA recommendation..
374 */
375 pci_read_config_byte(dev, 0x76, &busarb);
376
377 /*
378 * Set bit 4 and bit 5 of byte 76 to 0x01
379 * "Master priority rotation on every PCI master grant"
380 */
381 busarb &= ~(1<<5);
382 busarb |= (1<<4);
383 pci_write_config_byte(dev, 0x76, busarb);
384 pci_info(dev, "Applying VIA southbridge workaround\n");
385exit:
386 pci_dev_put(p);
387}
388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
391/* Must restore this on a resume from RAM */
392DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
393DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
394DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395
396/* VIA Apollo VP3 needs ETBF on BT848/878 */
397static void quirk_viaetbf(struct pci_dev *dev)
398{
399 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
400 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
401 pci_pci_problems |= PCIPCI_VIAETBF;
402 }
403}
404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
405
406static void quirk_vsfx(struct pci_dev *dev)
407{
408 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
409 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
410 pci_pci_problems |= PCIPCI_VSFX;
411 }
412}
413DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
414
415/*
416 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
417 * space. Latency must be set to 0xA and Triton workaround applied too.
418 * [Info kindly provided by ALi]
419 */
420static void quirk_alimagik(struct pci_dev *dev)
421{
422 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
423 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
424 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
425 }
426}
427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
429
430/* Natoma has some interesting boundary conditions with Zoran stuff at least */
431static void quirk_natoma(struct pci_dev *dev)
432{
433 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
434 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
435 pci_pci_problems |= PCIPCI_NATOMA;
436 }
437}
438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
444
445/*
446 * This chip can cause PCI parity errors if config register 0xA0 is read
447 * while DMAs are occurring.
448 */
449static void quirk_citrine(struct pci_dev *dev)
450{
451 dev->cfg_size = 0xA0;
452}
453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
454
455/*
456 * This chip can cause bus lockups if config addresses above 0x600
457 * are read or written.
458 */
459static void quirk_nfp6000(struct pci_dev *dev)
460{
461 dev->cfg_size = 0x600;
462}
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
467
468/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
469static void quirk_extend_bar_to_page(struct pci_dev *dev)
470{
471 int i;
472
473 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
474 struct resource *r = &dev->resource[i];
475
476 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
477 r->end = PAGE_SIZE - 1;
478 r->start = 0;
479 r->flags |= IORESOURCE_UNSET;
480 pci_info(dev, "expanded BAR %d to page size: %pR\n",
481 i, r);
482 }
483 }
484}
485DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
486
487/*
488 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
489 * If it's needed, re-allocate the region.
490 */
491static void quirk_s3_64M(struct pci_dev *dev)
492{
493 struct resource *r = &dev->resource[0];
494
495 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
496 r->flags |= IORESOURCE_UNSET;
497 r->start = 0;
498 r->end = 0x3ffffff;
499 }
500}
501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
503
504static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
505 const char *name)
506{
507 u32 region;
508 struct pci_bus_region bus_region;
509 struct resource *res = dev->resource + pos;
510
511 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
512
513 if (!region)
514 return;
515
516 res->name = pci_name(dev);
517 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
518 res->flags |=
519 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
520 region &= ~(size - 1);
521
522 /* Convert from PCI bus to resource space */
523 bus_region.start = region;
524 bus_region.end = region + size - 1;
525 pcibios_bus_to_resource(dev->bus, res, &bus_region);
526
527 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
528 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
529}
530
531/*
532 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
533 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
534 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
535 * (which conflicts w/ BAR1's memory range).
536 *
537 * CS553x's ISA PCI BARs may also be read-only (ref:
538 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
539 */
540static void quirk_cs5536_vsa(struct pci_dev *dev)
541{
542 static char *name = "CS5536 ISA bridge";
543
544 if (pci_resource_len(dev, 0) != 8) {
545 quirk_io(dev, 0, 8, name); /* SMB */
546 quirk_io(dev, 1, 256, name); /* GPIO */
547 quirk_io(dev, 2, 64, name); /* MFGPT */
548 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
549 name);
550 }
551}
552DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
553
554static void quirk_io_region(struct pci_dev *dev, int port,
555 unsigned size, int nr, const char *name)
556{
557 u16 region;
558 struct pci_bus_region bus_region;
559 struct resource *res = dev->resource + nr;
560
561 pci_read_config_word(dev, port, ®ion);
562 region &= ~(size - 1);
563
564 if (!region)
565 return;
566
567 res->name = pci_name(dev);
568 res->flags = IORESOURCE_IO;
569
570 /* Convert from PCI bus to resource space */
571 bus_region.start = region;
572 bus_region.end = region + size - 1;
573 pcibios_bus_to_resource(dev->bus, res, &bus_region);
574
575 if (!pci_claim_resource(dev, nr))
576 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
577}
578
579/*
580 * ATI Northbridge setups MCE the processor if you even read somewhere
581 * between 0x3b0->0x3bb or read 0x3d3
582 */
583static void quirk_ati_exploding_mce(struct pci_dev *dev)
584{
585 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
586 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
587 request_region(0x3b0, 0x0C, "RadeonIGP");
588 request_region(0x3d3, 0x01, "RadeonIGP");
589}
590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
591
592/*
593 * In the AMD NL platform, this device ([1022:7912]) has a class code of
594 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
595 * claim it.
596 *
597 * But the dwc3 driver is a more specific driver for this device, and we'd
598 * prefer to use it instead of xhci. To prevent xhci from claiming the
599 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
600 * defines as "USB device (not host controller)". The dwc3 driver can then
601 * claim it based on its Vendor and Device ID.
602 */
603static void quirk_amd_nl_class(struct pci_dev *pdev)
604{
605 u32 class = pdev->class;
606
607 /* Use "USB Device (not host controller)" class */
608 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
609 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
610 class, pdev->class);
611}
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
613 quirk_amd_nl_class);
614
615/*
616 * Synopsys USB 3.x host HAPS platform has a class code of
617 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
618 * devices should use dwc3-haps driver. Change these devices' class code to
619 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
620 * them.
621 */
622static void quirk_synopsys_haps(struct pci_dev *pdev)
623{
624 u32 class = pdev->class;
625
626 switch (pdev->device) {
627 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
628 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
629 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
630 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
631 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
632 class, pdev->class);
633 break;
634 }
635}
636DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
637 PCI_CLASS_SERIAL_USB_XHCI, 0,
638 quirk_synopsys_haps);
639
640/*
641 * Let's make the southbridge information explicit instead of having to
642 * worry about people probing the ACPI areas, for example.. (Yes, it
643 * happens, and if you read the wrong ACPI register it will put the machine
644 * to sleep with no way of waking it up again. Bummer).
645 *
646 * ALI M7101: Two IO regions pointed to by words at
647 * 0xE0 (64 bytes of ACPI registers)
648 * 0xE2 (32 bytes of SMB registers)
649 */
650static void quirk_ali7101_acpi(struct pci_dev *dev)
651{
652 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
653 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
654}
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
656
657static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
658{
659 u32 devres;
660 u32 mask, size, base;
661
662 pci_read_config_dword(dev, port, &devres);
663 if ((devres & enable) != enable)
664 return;
665 mask = (devres >> 16) & 15;
666 base = devres & 0xffff;
667 size = 16;
668 for (;;) {
669 unsigned bit = size >> 1;
670 if ((bit & mask) == bit)
671 break;
672 size = bit;
673 }
674 /*
675 * For now we only print it out. Eventually we'll want to
676 * reserve it (at least if it's in the 0x1000+ range), but
677 * let's get enough confirmation reports first.
678 */
679 base &= -size;
680 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
681}
682
683static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
684{
685 u32 devres;
686 u32 mask, size, base;
687
688 pci_read_config_dword(dev, port, &devres);
689 if ((devres & enable) != enable)
690 return;
691 base = devres & 0xffff0000;
692 mask = (devres & 0x3f) << 16;
693 size = 128 << 16;
694 for (;;) {
695 unsigned bit = size >> 1;
696 if ((bit & mask) == bit)
697 break;
698 size = bit;
699 }
700
701 /*
702 * For now we only print it out. Eventually we'll want to
703 * reserve it, but let's get enough confirmation reports first.
704 */
705 base &= -size;
706 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
707}
708
709/*
710 * PIIX4 ACPI: Two IO regions pointed to by longwords at
711 * 0x40 (64 bytes of ACPI registers)
712 * 0x90 (16 bytes of SMB registers)
713 * and a few strange programmable PIIX4 device resources.
714 */
715static void quirk_piix4_acpi(struct pci_dev *dev)
716{
717 u32 res_a;
718
719 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
720 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
721
722 /* Device resource A has enables for some of the other ones */
723 pci_read_config_dword(dev, 0x5c, &res_a);
724
725 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
726 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
727
728 /* Device resource D is just bitfields for static resources */
729
730 /* Device 12 enabled? */
731 if (res_a & (1 << 29)) {
732 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
733 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
734 }
735 /* Device 13 enabled? */
736 if (res_a & (1 << 30)) {
737 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
738 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
739 }
740 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
741 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
742}
743DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
745
746#define ICH_PMBASE 0x40
747#define ICH_ACPI_CNTL 0x44
748#define ICH4_ACPI_EN 0x10
749#define ICH6_ACPI_EN 0x80
750#define ICH4_GPIOBASE 0x58
751#define ICH4_GPIO_CNTL 0x5c
752#define ICH4_GPIO_EN 0x10
753#define ICH6_GPIOBASE 0x48
754#define ICH6_GPIO_CNTL 0x4c
755#define ICH6_GPIO_EN 0x10
756
757/*
758 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
759 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
760 * 0x58 (64 bytes of GPIO I/O space)
761 */
762static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
763{
764 u8 enable;
765
766 /*
767 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
768 * with low legacy (and fixed) ports. We don't know the decoding
769 * priority and can't tell whether the legacy device or the one created
770 * here is really at that address. This happens on boards with broken
771 * BIOSes.
772 */
773 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
774 if (enable & ICH4_ACPI_EN)
775 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
776 "ICH4 ACPI/GPIO/TCO");
777
778 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
779 if (enable & ICH4_GPIO_EN)
780 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
781 "ICH4 GPIO");
782}
783DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
784DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
785DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
786DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
787DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
788DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
793
794static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
795{
796 u8 enable;
797
798 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
799 if (enable & ICH6_ACPI_EN)
800 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
801 "ICH6 ACPI/GPIO/TCO");
802
803 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
804 if (enable & ICH6_GPIO_EN)
805 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
806 "ICH6 GPIO");
807}
808
809static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
810 const char *name, int dynsize)
811{
812 u32 val;
813 u32 size, base;
814
815 pci_read_config_dword(dev, reg, &val);
816
817 /* Enabled? */
818 if (!(val & 1))
819 return;
820 base = val & 0xfffc;
821 if (dynsize) {
822 /*
823 * This is not correct. It is 16, 32 or 64 bytes depending on
824 * register D31:F0:ADh bits 5:4.
825 *
826 * But this gets us at least _part_ of it.
827 */
828 size = 16;
829 } else {
830 size = 128;
831 }
832 base &= ~(size-1);
833
834 /*
835 * Just print it out for now. We should reserve it after more
836 * debugging.
837 */
838 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
839}
840
841static void quirk_ich6_lpc(struct pci_dev *dev)
842{
843 /* Shared ACPI/GPIO decode with all ICH6+ */
844 ich6_lpc_acpi_gpio(dev);
845
846 /* ICH6-specific generic IO decode */
847 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
848 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
849}
850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
852
853static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
854 const char *name)
855{
856 u32 val;
857 u32 mask, base;
858
859 pci_read_config_dword(dev, reg, &val);
860
861 /* Enabled? */
862 if (!(val & 1))
863 return;
864
865 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
866 base = val & 0xfffc;
867 mask = (val >> 16) & 0xfc;
868 mask |= 3;
869
870 /*
871 * Just print it out for now. We should reserve it after more
872 * debugging.
873 */
874 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
875}
876
877/* ICH7-10 has the same common LPC generic IO decode registers */
878static void quirk_ich7_lpc(struct pci_dev *dev)
879{
880 /* We share the common ACPI/GPIO decode with ICH6 */
881 ich6_lpc_acpi_gpio(dev);
882
883 /* And have 4 ICH7+ generic decodes */
884 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
885 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
886 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
887 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
888}
889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
902
903/*
904 * VIA ACPI: One IO region pointed to by longword at
905 * 0x48 or 0x20 (256 bytes of ACPI registers)
906 */
907static void quirk_vt82c586_acpi(struct pci_dev *dev)
908{
909 if (dev->revision & 0x10)
910 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
911 "vt82c586 ACPI");
912}
913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
914
915/*
916 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
917 * 0x48 (256 bytes of ACPI registers)
918 * 0x70 (128 bytes of hardware monitoring register)
919 * 0x90 (16 bytes of SMB registers)
920 */
921static void quirk_vt82c686_acpi(struct pci_dev *dev)
922{
923 quirk_vt82c586_acpi(dev);
924
925 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
926 "vt82c686 HW-mon");
927
928 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
929}
930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
931
932/*
933 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
934 * 0x88 (128 bytes of power management registers)
935 * 0xd0 (16 bytes of SMB registers)
936 */
937static void quirk_vt8235_acpi(struct pci_dev *dev)
938{
939 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
940 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
941}
942DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
943
944/*
945 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
946 * back-to-back: Disable fast back-to-back on the secondary bus segment
947 */
948static void quirk_xio2000a(struct pci_dev *dev)
949{
950 struct pci_dev *pdev;
951 u16 command;
952
953 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
954 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
955 pci_read_config_word(pdev, PCI_COMMAND, &command);
956 if (command & PCI_COMMAND_FAST_BACK)
957 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
958 }
959}
960DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
961 quirk_xio2000a);
962
963#ifdef CONFIG_X86_IO_APIC
964
965#include <asm/io_apic.h>
966
967/*
968 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
969 * devices to the external APIC.
970 *
971 * TODO: When we have device-specific interrupt routers, this code will go
972 * away from quirks.
973 */
974static void quirk_via_ioapic(struct pci_dev *dev)
975{
976 u8 tmp;
977
978 if (nr_ioapics < 1)
979 tmp = 0; /* nothing routed to external APIC */
980 else
981 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
982
983 pci_info(dev, "%sbling VIA external APIC routing\n",
984 tmp == 0 ? "Disa" : "Ena");
985
986 /* Offset 0x58: External APIC IRQ output control */
987 pci_write_config_byte(dev, 0x58, tmp);
988}
989DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
990DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
991
992/*
993 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
994 * This leads to doubled level interrupt rates.
995 * Set this bit to get rid of cycle wastage.
996 * Otherwise uncritical.
997 */
998static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
999{
1000 u8 misc_control2;
1001#define BYPASS_APIC_DEASSERT 8
1002
1003 pci_read_config_byte(dev, 0x5B, &misc_control2);
1004 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1005 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1006 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1007 }
1008}
1009DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1010DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1011
1012/*
1013 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1014 * We check all revs >= B0 (yet not in the pre production!) as the bug
1015 * is currently marked NoFix
1016 *
1017 * We have multiple reports of hangs with this chipset that went away with
1018 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1019 * of course. However the advice is demonstrably good even if so.
1020 */
1021static void quirk_amd_ioapic(struct pci_dev *dev)
1022{
1023 if (dev->revision >= 0x02) {
1024 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1025 pci_warn(dev, " : booting with the \"noapic\" option\n");
1026 }
1027}
1028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1029#endif /* CONFIG_X86_IO_APIC */
1030
1031#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1032
1033static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1034{
1035 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1036 if (dev->subsystem_device == 0xa118)
1037 dev->sriov->link = dev->devfn;
1038}
1039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1040#endif
1041
1042/*
1043 * Some settings of MMRBC can lead to data corruption so block changes.
1044 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1045 */
1046static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1047{
1048 if (dev->subordinate && dev->revision <= 0x12) {
1049 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1050 dev->revision);
1051 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1052 }
1053}
1054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1055
1056/*
1057 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1058 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1059 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1060 * of the ACPI SCI interrupt is only done for convenience.
1061 * -jgarzik
1062 */
1063static void quirk_via_acpi(struct pci_dev *d)
1064{
1065 u8 irq;
1066
1067 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1068 pci_read_config_byte(d, 0x42, &irq);
1069 irq &= 0xf;
1070 if (irq && (irq != 2))
1071 d->irq = irq;
1072}
1073DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1075
1076/* VIA bridges which have VLink */
1077static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1078
1079static void quirk_via_bridge(struct pci_dev *dev)
1080{
1081 /* See what bridge we have and find the device ranges */
1082 switch (dev->device) {
1083 case PCI_DEVICE_ID_VIA_82C686:
1084 /*
1085 * The VT82C686 is special; it attaches to PCI and can have
1086 * any device number. All its subdevices are functions of
1087 * that single device.
1088 */
1089 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1090 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1091 break;
1092 case PCI_DEVICE_ID_VIA_8237:
1093 case PCI_DEVICE_ID_VIA_8237A:
1094 via_vlink_dev_lo = 15;
1095 break;
1096 case PCI_DEVICE_ID_VIA_8235:
1097 via_vlink_dev_lo = 16;
1098 break;
1099 case PCI_DEVICE_ID_VIA_8231:
1100 case PCI_DEVICE_ID_VIA_8233_0:
1101 case PCI_DEVICE_ID_VIA_8233A:
1102 case PCI_DEVICE_ID_VIA_8233C_0:
1103 via_vlink_dev_lo = 17;
1104 break;
1105 }
1106}
1107DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1108DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1114DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1115
1116/*
1117 * quirk_via_vlink - VIA VLink IRQ number update
1118 * @dev: PCI device
1119 *
1120 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1121 * the IRQ line register which usually is not relevant for PCI cards, is
1122 * actually written so that interrupts get sent to the right place.
1123 *
1124 * We only do this on systems where a VIA south bridge was detected, and
1125 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1126 */
1127static void quirk_via_vlink(struct pci_dev *dev)
1128{
1129 u8 irq, new_irq;
1130
1131 /* Check if we have VLink at all */
1132 if (via_vlink_dev_lo == -1)
1133 return;
1134
1135 new_irq = dev->irq;
1136
1137 /* Don't quirk interrupts outside the legacy IRQ range */
1138 if (!new_irq || new_irq > 15)
1139 return;
1140
1141 /* Internal device ? */
1142 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1143 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1144 return;
1145
1146 /*
1147 * This is an internal VLink device on a PIC interrupt. The BIOS
1148 * ought to have set this but may not have, so we redo it.
1149 */
1150 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1151 if (new_irq != irq) {
1152 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1153 irq, new_irq);
1154 udelay(15); /* unknown if delay really needed */
1155 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1156 }
1157}
1158DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1159
1160/*
1161 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1162 * of VT82C597 for backward compatibility. We need to switch it off to be
1163 * able to recognize the real type of the chip.
1164 */
1165static void quirk_vt82c598_id(struct pci_dev *dev)
1166{
1167 pci_write_config_byte(dev, 0xfc, 0);
1168 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1169}
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1171
1172/*
1173 * CardBus controllers have a legacy base address that enables them to
1174 * respond as i82365 pcmcia controllers. We don't want them to do this
1175 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1176 * driver does not (and should not) handle CardBus.
1177 */
1178static void quirk_cardbus_legacy(struct pci_dev *dev)
1179{
1180 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1181}
1182DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1183 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1184DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1185 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1186
1187/*
1188 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1189 * what the designers were smoking but let's not inhale...
1190 *
1191 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1192 * turn it off!
1193 */
1194static void quirk_amd_ordering(struct pci_dev *dev)
1195{
1196 u32 pcic;
1197 pci_read_config_dword(dev, 0x4C, &pcic);
1198 if ((pcic & 6) != 6) {
1199 pcic |= 6;
1200 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1201 pci_write_config_dword(dev, 0x4C, pcic);
1202 pci_read_config_dword(dev, 0x84, &pcic);
1203 pcic |= (1 << 23); /* Required in this mode */
1204 pci_write_config_dword(dev, 0x84, pcic);
1205 }
1206}
1207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1208DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1209
1210/*
1211 * DreamWorks-provided workaround for Dunord I-3000 problem
1212 *
1213 * This card decodes and responds to addresses not apparently assigned to
1214 * it. We force a larger allocation to ensure that nothing gets put too
1215 * close to it.
1216 */
1217static void quirk_dunord(struct pci_dev *dev)
1218{
1219 struct resource *r = &dev->resource[1];
1220
1221 r->flags |= IORESOURCE_UNSET;
1222 r->start = 0;
1223 r->end = 0xffffff;
1224}
1225DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1226
1227/*
1228 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1229 * decoding (transparent), and does indicate this in the ProgIf.
1230 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1231 */
1232static void quirk_transparent_bridge(struct pci_dev *dev)
1233{
1234 dev->transparent = 1;
1235}
1236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1238
1239/*
1240 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1241 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1242 * found at http://www.national.com/analog for info on what these bits do.
1243 * <christer@weinigel.se>
1244 */
1245static void quirk_mediagx_master(struct pci_dev *dev)
1246{
1247 u8 reg;
1248
1249 pci_read_config_byte(dev, 0x41, ®);
1250 if (reg & 2) {
1251 reg &= ~2;
1252 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1253 reg);
1254 pci_write_config_byte(dev, 0x41, reg);
1255 }
1256}
1257DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1258DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1259
1260/*
1261 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1262 * in the odd case it is not the results are corruption hence the presence
1263 * of a Linux check.
1264 */
1265static void quirk_disable_pxb(struct pci_dev *pdev)
1266{
1267 u16 config;
1268
1269 if (pdev->revision != 0x04) /* Only C0 requires this */
1270 return;
1271 pci_read_config_word(pdev, 0x40, &config);
1272 if (config & (1<<6)) {
1273 config &= ~(1<<6);
1274 pci_write_config_word(pdev, 0x40, config);
1275 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1276 }
1277}
1278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1279DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1280
1281static void quirk_amd_ide_mode(struct pci_dev *pdev)
1282{
1283 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1284 u8 tmp;
1285
1286 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1287 if (tmp == 0x01) {
1288 pci_read_config_byte(pdev, 0x40, &tmp);
1289 pci_write_config_byte(pdev, 0x40, tmp|1);
1290 pci_write_config_byte(pdev, 0x9, 1);
1291 pci_write_config_byte(pdev, 0xa, 6);
1292 pci_write_config_byte(pdev, 0x40, tmp);
1293
1294 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1295 pci_info(pdev, "set SATA to AHCI mode\n");
1296 }
1297}
1298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1299DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1301DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1302DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1303DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1305DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1306
1307/* Serverworks CSB5 IDE does not fully support native mode */
1308static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1309{
1310 u8 prog;
1311 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1312 if (prog & 5) {
1313 prog &= ~5;
1314 pdev->class &= ~5;
1315 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1316 /* PCI layer will sort out resources */
1317 }
1318}
1319DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1320
1321/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1322static void quirk_ide_samemode(struct pci_dev *pdev)
1323{
1324 u8 prog;
1325
1326 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1327
1328 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1329 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1330 prog &= ~5;
1331 pdev->class &= ~5;
1332 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1333 }
1334}
1335DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1336
1337/* Some ATA devices break if put into D3 */
1338static void quirk_no_ata_d3(struct pci_dev *pdev)
1339{
1340 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1341}
1342/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1343DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1344 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1345DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1346 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1347/* ALi loses some register settings that we cannot then restore */
1348DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1349 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1350/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1351 occur when mode detecting */
1352DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1353 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1354
1355/*
1356 * This was originally an Alpha-specific thing, but it really fits here.
1357 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1358 */
1359static void quirk_eisa_bridge(struct pci_dev *dev)
1360{
1361 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1362}
1363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1364
1365/*
1366 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1367 * is not activated. The myth is that Asus said that they do not want the
1368 * users to be irritated by just another PCI Device in the Win98 device
1369 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1370 * package 2.7.0 for details)
1371 *
1372 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1373 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1374 * becomes necessary to do this tweak in two steps -- the chosen trigger
1375 * is either the Host bridge (preferred) or on-board VGA controller.
1376 *
1377 * Note that we used to unhide the SMBus that way on Toshiba laptops
1378 * (Satellite A40 and Tecra M2) but then found that the thermal management
1379 * was done by SMM code, which could cause unsynchronized concurrent
1380 * accesses to the SMBus registers, with potentially bad effects. Thus you
1381 * should be very careful when adding new entries: if SMM is accessing the
1382 * Intel SMBus, this is a very good reason to leave it hidden.
1383 *
1384 * Likewise, many recent laptops use ACPI for thermal management. If the
1385 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1386 * natively, and keeping the SMBus hidden is the right thing to do. If you
1387 * are about to add an entry in the table below, please first disassemble
1388 * the DSDT and double-check that there is no code accessing the SMBus.
1389 */
1390static int asus_hides_smbus;
1391
1392static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1393{
1394 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1395 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1396 switch (dev->subsystem_device) {
1397 case 0x8025: /* P4B-LX */
1398 case 0x8070: /* P4B */
1399 case 0x8088: /* P4B533 */
1400 case 0x1626: /* L3C notebook */
1401 asus_hides_smbus = 1;
1402 }
1403 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1404 switch (dev->subsystem_device) {
1405 case 0x80b1: /* P4GE-V */
1406 case 0x80b2: /* P4PE */
1407 case 0x8093: /* P4B533-V */
1408 asus_hides_smbus = 1;
1409 }
1410 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1411 switch (dev->subsystem_device) {
1412 case 0x8030: /* P4T533 */
1413 asus_hides_smbus = 1;
1414 }
1415 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1416 switch (dev->subsystem_device) {
1417 case 0x8070: /* P4G8X Deluxe */
1418 asus_hides_smbus = 1;
1419 }
1420 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1421 switch (dev->subsystem_device) {
1422 case 0x80c9: /* PU-DLS */
1423 asus_hides_smbus = 1;
1424 }
1425 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1426 switch (dev->subsystem_device) {
1427 case 0x1751: /* M2N notebook */
1428 case 0x1821: /* M5N notebook */
1429 case 0x1897: /* A6L notebook */
1430 asus_hides_smbus = 1;
1431 }
1432 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1433 switch (dev->subsystem_device) {
1434 case 0x184b: /* W1N notebook */
1435 case 0x186a: /* M6Ne notebook */
1436 asus_hides_smbus = 1;
1437 }
1438 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1439 switch (dev->subsystem_device) {
1440 case 0x80f2: /* P4P800-X */
1441 asus_hides_smbus = 1;
1442 }
1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1444 switch (dev->subsystem_device) {
1445 case 0x1882: /* M6V notebook */
1446 case 0x1977: /* A6VA notebook */
1447 asus_hides_smbus = 1;
1448 }
1449 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1450 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1451 switch (dev->subsystem_device) {
1452 case 0x088C: /* HP Compaq nc8000 */
1453 case 0x0890: /* HP Compaq nc6000 */
1454 asus_hides_smbus = 1;
1455 }
1456 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1457 switch (dev->subsystem_device) {
1458 case 0x12bc: /* HP D330L */
1459 case 0x12bd: /* HP D530 */
1460 case 0x006a: /* HP Compaq nx9500 */
1461 asus_hides_smbus = 1;
1462 }
1463 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1464 switch (dev->subsystem_device) {
1465 case 0x12bf: /* HP xw4100 */
1466 asus_hides_smbus = 1;
1467 }
1468 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1469 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1470 switch (dev->subsystem_device) {
1471 case 0xC00C: /* Samsung P35 notebook */
1472 asus_hides_smbus = 1;
1473 }
1474 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1475 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1476 switch (dev->subsystem_device) {
1477 case 0x0058: /* Compaq Evo N620c */
1478 asus_hides_smbus = 1;
1479 }
1480 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1481 switch (dev->subsystem_device) {
1482 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1483 /* Motherboard doesn't have Host bridge
1484 * subvendor/subdevice IDs, therefore checking
1485 * its on-board VGA controller */
1486 asus_hides_smbus = 1;
1487 }
1488 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1489 switch (dev->subsystem_device) {
1490 case 0x00b8: /* Compaq Evo D510 CMT */
1491 case 0x00b9: /* Compaq Evo D510 SFF */
1492 case 0x00ba: /* Compaq Evo D510 USDT */
1493 /* Motherboard doesn't have Host bridge
1494 * subvendor/subdevice IDs and on-board VGA
1495 * controller is disabled if an AGP card is
1496 * inserted, therefore checking USB UHCI
1497 * Controller #1 */
1498 asus_hides_smbus = 1;
1499 }
1500 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1501 switch (dev->subsystem_device) {
1502 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1503 /* Motherboard doesn't have host bridge
1504 * subvendor/subdevice IDs, therefore checking
1505 * its on-board VGA controller */
1506 asus_hides_smbus = 1;
1507 }
1508 }
1509}
1510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1520
1521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1524
1525static void asus_hides_smbus_lpc(struct pci_dev *dev)
1526{
1527 u16 val;
1528
1529 if (likely(!asus_hides_smbus))
1530 return;
1531
1532 pci_read_config_word(dev, 0xF2, &val);
1533 if (val & 0x8) {
1534 pci_write_config_word(dev, 0xF2, val & (~0x8));
1535 pci_read_config_word(dev, 0xF2, &val);
1536 if (val & 0x8)
1537 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1538 val);
1539 else
1540 pci_info(dev, "Enabled i801 SMBus device\n");
1541 }
1542}
1543DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1546DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1548DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1550DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1551DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1552DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1553DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1554DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1555DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1556DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1557
1558/* It appears we just have one such device. If not, we have a warning */
1559static void __iomem *asus_rcba_base;
1560static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1561{
1562 u32 rcba;
1563
1564 if (likely(!asus_hides_smbus))
1565 return;
1566 WARN_ON(asus_rcba_base);
1567
1568 pci_read_config_dword(dev, 0xF0, &rcba);
1569 /* use bits 31:14, 16 kB aligned */
1570 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1571 if (asus_rcba_base == NULL)
1572 return;
1573}
1574
1575static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1576{
1577 u32 val;
1578
1579 if (likely(!asus_hides_smbus || !asus_rcba_base))
1580 return;
1581
1582 /* read the Function Disable register, dword mode only */
1583 val = readl(asus_rcba_base + 0x3418);
1584
1585 /* enable the SMBus device */
1586 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1587}
1588
1589static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1590{
1591 if (likely(!asus_hides_smbus || !asus_rcba_base))
1592 return;
1593
1594 iounmap(asus_rcba_base);
1595 asus_rcba_base = NULL;
1596 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1597}
1598
1599static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1600{
1601 asus_hides_smbus_lpc_ich6_suspend(dev);
1602 asus_hides_smbus_lpc_ich6_resume_early(dev);
1603 asus_hides_smbus_lpc_ich6_resume(dev);
1604}
1605DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1606DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1607DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1608DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1609
1610/* SiS 96x south bridge: BIOS typically hides SMBus device... */
1611static void quirk_sis_96x_smbus(struct pci_dev *dev)
1612{
1613 u8 val = 0;
1614 pci_read_config_byte(dev, 0x77, &val);
1615 if (val & 0x10) {
1616 pci_info(dev, "Enabling SiS 96x SMBus\n");
1617 pci_write_config_byte(dev, 0x77, val & ~0x10);
1618 }
1619}
1620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1624DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1625DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1626DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1627DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1628
1629/*
1630 * ... This is further complicated by the fact that some SiS96x south
1631 * bridges pretend to be 85C503/5513 instead. In that case see if we
1632 * spotted a compatible north bridge to make sure.
1633 * (pci_find_device() doesn't work yet)
1634 *
1635 * We can also enable the sis96x bit in the discovery register..
1636 */
1637#define SIS_DETECT_REGISTER 0x40
1638
1639static void quirk_sis_503(struct pci_dev *dev)
1640{
1641 u8 reg;
1642 u16 devid;
1643
1644 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1645 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1646 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1647 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1648 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1649 return;
1650 }
1651
1652 /*
1653 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1654 * it has already been processed. (Depends on link order, which is
1655 * apparently not guaranteed)
1656 */
1657 dev->device = devid;
1658 quirk_sis_96x_smbus(dev);
1659}
1660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1661DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1662
1663/*
1664 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1665 * and MC97 modem controller are disabled when a second PCI soundcard is
1666 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1667 * -- bjd
1668 */
1669static void asus_hides_ac97_lpc(struct pci_dev *dev)
1670{
1671 u8 val;
1672 int asus_hides_ac97 = 0;
1673
1674 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1675 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1676 asus_hides_ac97 = 1;
1677 }
1678
1679 if (!asus_hides_ac97)
1680 return;
1681
1682 pci_read_config_byte(dev, 0x50, &val);
1683 if (val & 0xc0) {
1684 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1685 pci_read_config_byte(dev, 0x50, &val);
1686 if (val & 0xc0)
1687 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1688 val);
1689 else
1690 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1691 }
1692}
1693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1694DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1695
1696#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1697
1698/*
1699 * If we are using libata we can drive this chip properly but must do this
1700 * early on to make the additional device appear during the PCI scanning.
1701 */
1702static void quirk_jmicron_ata(struct pci_dev *pdev)
1703{
1704 u32 conf1, conf5, class;
1705 u8 hdr;
1706
1707 /* Only poke fn 0 */
1708 if (PCI_FUNC(pdev->devfn))
1709 return;
1710
1711 pci_read_config_dword(pdev, 0x40, &conf1);
1712 pci_read_config_dword(pdev, 0x80, &conf5);
1713
1714 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1715 conf5 &= ~(1 << 24); /* Clear bit 24 */
1716
1717 switch (pdev->device) {
1718 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1719 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1720 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1721 /* The controller should be in single function ahci mode */
1722 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1723 break;
1724
1725 case PCI_DEVICE_ID_JMICRON_JMB365:
1726 case PCI_DEVICE_ID_JMICRON_JMB366:
1727 /* Redirect IDE second PATA port to the right spot */
1728 conf5 |= (1 << 24);
1729 fallthrough;
1730 case PCI_DEVICE_ID_JMICRON_JMB361:
1731 case PCI_DEVICE_ID_JMICRON_JMB363:
1732 case PCI_DEVICE_ID_JMICRON_JMB369:
1733 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1734 /* Set the class codes correctly and then direct IDE 0 */
1735 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1736 break;
1737
1738 case PCI_DEVICE_ID_JMICRON_JMB368:
1739 /* The controller should be in single function IDE mode */
1740 conf1 |= 0x00C00000; /* Set 22, 23 */
1741 break;
1742 }
1743
1744 pci_write_config_dword(pdev, 0x40, conf1);
1745 pci_write_config_dword(pdev, 0x80, conf5);
1746
1747 /* Update pdev accordingly */
1748 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1749 pdev->hdr_type = hdr & 0x7f;
1750 pdev->multifunction = !!(hdr & 0x80);
1751
1752 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1753 pdev->class = class >> 8;
1754}
1755DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1756DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1757DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1758DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1759DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1760DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1761DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1762DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1763DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1764DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1765DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1766DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1767DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1768DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1769DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1770DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1771DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1772DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1773
1774#endif
1775
1776static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1777{
1778 if (dev->multifunction) {
1779 device_disable_async_suspend(&dev->dev);
1780 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1781 }
1782}
1783DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1784DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1787
1788#ifdef CONFIG_X86_IO_APIC
1789static void quirk_alder_ioapic(struct pci_dev *pdev)
1790{
1791 int i;
1792
1793 if ((pdev->class >> 8) != 0xff00)
1794 return;
1795
1796 /*
1797 * The first BAR is the location of the IO-APIC... we must
1798 * not touch this (and it's already covered by the fixmap), so
1799 * forcibly insert it into the resource tree.
1800 */
1801 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1802 insert_resource(&iomem_resource, &pdev->resource[0]);
1803
1804 /*
1805 * The next five BARs all seem to be rubbish, so just clean
1806 * them out.
1807 */
1808 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1809 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1810}
1811DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1812#endif
1813
1814static void quirk_pcie_mch(struct pci_dev *pdev)
1815{
1816 pdev->no_msi = 1;
1817}
1818DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1819DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1821
1822DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1823
1824/*
1825 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1826 * together on certain PXH-based systems.
1827 */
1828static void quirk_pcie_pxh(struct pci_dev *dev)
1829{
1830 dev->no_msi = 1;
1831 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1832}
1833DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1834DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1835DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1836DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1837DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1838
1839/*
1840 * Some Intel PCI Express chipsets have trouble with downstream device
1841 * power management.
1842 */
1843static void quirk_intel_pcie_pm(struct pci_dev *dev)
1844{
1845 pci_pm_d3hot_delay = 120;
1846 dev->no_d1d2 = 1;
1847}
1848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1852DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1854DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1855DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1856DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1859DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1861DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1862DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1863DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1864DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1866DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1869
1870static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1871{
1872 if (dev->d3hot_delay >= delay)
1873 return;
1874
1875 dev->d3hot_delay = delay;
1876 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1877 dev->d3hot_delay);
1878}
1879
1880static void quirk_radeon_pm(struct pci_dev *dev)
1881{
1882 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1883 dev->subsystem_device == 0x00e2)
1884 quirk_d3hot_delay(dev, 20);
1885}
1886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1887
1888/*
1889 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1890 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1891 *
1892 * The kernel attempts to transition these devices to D3cold, but that seems
1893 * to be ineffective on the platforms in question; the PCI device appears to
1894 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1895 * extended delay in order to succeed.
1896 */
1897static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1898{
1899 quirk_d3hot_delay(dev, 20);
1900}
1901DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1903DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
1904
1905#ifdef CONFIG_X86_IO_APIC
1906static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1907{
1908 noioapicreroute = 1;
1909 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1910
1911 return 0;
1912}
1913
1914static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1915 /*
1916 * Systems to exclude from boot interrupt reroute quirks
1917 */
1918 {
1919 .callback = dmi_disable_ioapicreroute,
1920 .ident = "ASUSTek Computer INC. M2N-LR",
1921 .matches = {
1922 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1923 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1924 },
1925 },
1926 {}
1927};
1928
1929/*
1930 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1931 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1932 * that a PCI device's interrupt handler is installed on the boot interrupt
1933 * line instead.
1934 */
1935static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1936{
1937 dmi_check_system(boot_interrupt_dmi_table);
1938 if (noioapicquirk || noioapicreroute)
1939 return;
1940
1941 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1942 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1943 dev->vendor, dev->device);
1944}
1945DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1946DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1947DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1948DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1949DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1950DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1952DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1953DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1954DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1955DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1956DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1957DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1958DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1959DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1960DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1961
1962/*
1963 * On some chipsets we can disable the generation of legacy INTx boot
1964 * interrupts.
1965 */
1966
1967/*
1968 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1969 * 300641-004US, section 5.7.3.
1970 *
1971 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1972 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1973 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1974 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1975 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1976 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1977 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1978 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1979 * Core IO on Xeon Scalable, see Intel order no 610950.
1980 */
1981#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1982#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1983
1984#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1985#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1986
1987static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1988{
1989 u16 pci_config_word;
1990 u32 pci_config_dword;
1991
1992 if (noioapicquirk)
1993 return;
1994
1995 switch (dev->device) {
1996 case PCI_DEVICE_ID_INTEL_ESB_10:
1997 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
1998 &pci_config_word);
1999 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2000 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2001 pci_config_word);
2002 break;
2003 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2004 case 0x0e28: /* Xeon E5/E7 V2 */
2005 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2006 case 0x6f28: /* Xeon D-1500 */
2007 case 0x2034: /* Xeon Scalable Family */
2008 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2009 &pci_config_dword);
2010 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2011 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2012 pci_config_dword);
2013 break;
2014 default:
2015 return;
2016 }
2017 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2018 dev->vendor, dev->device);
2019}
2020/*
2021 * Device 29 Func 5 Device IDs of IO-APIC
2022 * containing ABAR—APIC1 Alternate Base Address Register
2023 */
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2025 quirk_disable_intel_boot_interrupt);
2026DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2027 quirk_disable_intel_boot_interrupt);
2028
2029/*
2030 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2031 * containing Coherent Interface Protocol Interrupt Control
2032 *
2033 * Device IDs obtained from volume 2 datasheets of commented
2034 * families above.
2035 */
2036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2037 quirk_disable_intel_boot_interrupt);
2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2039 quirk_disable_intel_boot_interrupt);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2041 quirk_disable_intel_boot_interrupt);
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2043 quirk_disable_intel_boot_interrupt);
2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2045 quirk_disable_intel_boot_interrupt);
2046DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2047 quirk_disable_intel_boot_interrupt);
2048DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2049 quirk_disable_intel_boot_interrupt);
2050DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2051 quirk_disable_intel_boot_interrupt);
2052DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2053 quirk_disable_intel_boot_interrupt);
2054DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2055 quirk_disable_intel_boot_interrupt);
2056
2057/* Disable boot interrupts on HT-1000 */
2058#define BC_HT1000_FEATURE_REG 0x64
2059#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2060#define BC_HT1000_MAP_IDX 0xC00
2061#define BC_HT1000_MAP_DATA 0xC01
2062
2063static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2064{
2065 u32 pci_config_dword;
2066 u8 irq;
2067
2068 if (noioapicquirk)
2069 return;
2070
2071 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2072 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2073 BC_HT1000_PIC_REGS_ENABLE);
2074
2075 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2076 outb(irq, BC_HT1000_MAP_IDX);
2077 outb(0x00, BC_HT1000_MAP_DATA);
2078 }
2079
2080 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2081
2082 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2083 dev->vendor, dev->device);
2084}
2085DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2086DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2087
2088/* Disable boot interrupts on AMD and ATI chipsets */
2089
2090/*
2091 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2092 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2093 * (due to an erratum).
2094 */
2095#define AMD_813X_MISC 0x40
2096#define AMD_813X_NOIOAMODE (1<<0)
2097#define AMD_813X_REV_B1 0x12
2098#define AMD_813X_REV_B2 0x13
2099
2100static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2101{
2102 u32 pci_config_dword;
2103
2104 if (noioapicquirk)
2105 return;
2106 if ((dev->revision == AMD_813X_REV_B1) ||
2107 (dev->revision == AMD_813X_REV_B2))
2108 return;
2109
2110 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2111 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2112 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2113
2114 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2115 dev->vendor, dev->device);
2116}
2117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2118DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2120DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2121
2122#define AMD_8111_PCI_IRQ_ROUTING 0x56
2123
2124static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2125{
2126 u16 pci_config_word;
2127
2128 if (noioapicquirk)
2129 return;
2130
2131 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2132 if (!pci_config_word) {
2133 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2134 dev->vendor, dev->device);
2135 return;
2136 }
2137 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2138 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2139 dev->vendor, dev->device);
2140}
2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2142DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2143#endif /* CONFIG_X86_IO_APIC */
2144
2145/*
2146 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2147 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2148 * Re-allocate the region if needed...
2149 */
2150static void quirk_tc86c001_ide(struct pci_dev *dev)
2151{
2152 struct resource *r = &dev->resource[0];
2153
2154 if (r->start & 0x8) {
2155 r->flags |= IORESOURCE_UNSET;
2156 r->start = 0;
2157 r->end = 0xf;
2158 }
2159}
2160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2161 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2162 quirk_tc86c001_ide);
2163
2164/*
2165 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2166 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2167 * being read correctly if bit 7 of the base address is set.
2168 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2169 * Re-allocate the regions to a 256-byte boundary if necessary.
2170 */
2171static void quirk_plx_pci9050(struct pci_dev *dev)
2172{
2173 unsigned int bar;
2174
2175 /* Fixed in revision 2 (PCI 9052). */
2176 if (dev->revision >= 2)
2177 return;
2178 for (bar = 0; bar <= 1; bar++)
2179 if (pci_resource_len(dev, bar) == 0x80 &&
2180 (pci_resource_start(dev, bar) & 0x80)) {
2181 struct resource *r = &dev->resource[bar];
2182 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2183 bar);
2184 r->flags |= IORESOURCE_UNSET;
2185 r->start = 0;
2186 r->end = 0xff;
2187 }
2188}
2189DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2190 quirk_plx_pci9050);
2191/*
2192 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2193 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2194 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2195 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2196 *
2197 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2198 * driver.
2199 */
2200DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2201DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2202
2203static void quirk_netmos(struct pci_dev *dev)
2204{
2205 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2206 unsigned int num_serial = dev->subsystem_device & 0xf;
2207
2208 /*
2209 * These Netmos parts are multiport serial devices with optional
2210 * parallel ports. Even when parallel ports are present, they
2211 * are identified as class SERIAL, which means the serial driver
2212 * will claim them. To prevent this, mark them as class OTHER.
2213 * These combo devices should be claimed by parport_serial.
2214 *
2215 * The subdevice ID is of the form 0x00PS, where <P> is the number
2216 * of parallel ports and <S> is the number of serial ports.
2217 */
2218 switch (dev->device) {
2219 case PCI_DEVICE_ID_NETMOS_9835:
2220 /* Well, this rule doesn't hold for the following 9835 device */
2221 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2222 dev->subsystem_device == 0x0299)
2223 return;
2224 fallthrough;
2225 case PCI_DEVICE_ID_NETMOS_9735:
2226 case PCI_DEVICE_ID_NETMOS_9745:
2227 case PCI_DEVICE_ID_NETMOS_9845:
2228 case PCI_DEVICE_ID_NETMOS_9855:
2229 if (num_parallel) {
2230 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2231 dev->device, num_parallel, num_serial);
2232 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2233 (dev->class & 0xff);
2234 }
2235 }
2236}
2237DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2238 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2239
2240static void quirk_e100_interrupt(struct pci_dev *dev)
2241{
2242 u16 command, pmcsr;
2243 u8 __iomem *csr;
2244 u8 cmd_hi;
2245
2246 switch (dev->device) {
2247 /* PCI IDs taken from drivers/net/e100.c */
2248 case 0x1029:
2249 case 0x1030 ... 0x1034:
2250 case 0x1038 ... 0x103E:
2251 case 0x1050 ... 0x1057:
2252 case 0x1059:
2253 case 0x1064 ... 0x106B:
2254 case 0x1091 ... 0x1095:
2255 case 0x1209:
2256 case 0x1229:
2257 case 0x2449:
2258 case 0x2459:
2259 case 0x245D:
2260 case 0x27DC:
2261 break;
2262 default:
2263 return;
2264 }
2265
2266 /*
2267 * Some firmware hands off the e100 with interrupts enabled,
2268 * which can cause a flood of interrupts if packets are
2269 * received before the driver attaches to the device. So
2270 * disable all e100 interrupts here. The driver will
2271 * re-enable them when it's ready.
2272 */
2273 pci_read_config_word(dev, PCI_COMMAND, &command);
2274
2275 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2276 return;
2277
2278 /*
2279 * Check that the device is in the D0 power state. If it's not,
2280 * there is no point to look any further.
2281 */
2282 if (dev->pm_cap) {
2283 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2284 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2285 return;
2286 }
2287
2288 /* Convert from PCI bus to resource space. */
2289 csr = ioremap(pci_resource_start(dev, 0), 8);
2290 if (!csr) {
2291 pci_warn(dev, "Can't map e100 registers\n");
2292 return;
2293 }
2294
2295 cmd_hi = readb(csr + 3);
2296 if (cmd_hi == 0) {
2297 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2298 writeb(1, csr + 3);
2299 }
2300
2301 iounmap(csr);
2302}
2303DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2304 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2305
2306/*
2307 * The 82575 and 82598 may experience data corruption issues when transitioning
2308 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2309 */
2310static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2311{
2312 pci_info(dev, "Disabling L0s\n");
2313 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2314}
2315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2328DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2329
2330static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2331{
2332 pci_info(dev, "Disabling ASPM L0s/L1\n");
2333 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2334}
2335
2336/*
2337 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2338 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2339 * disable both L0s and L1 for now to be safe.
2340 */
2341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2342
2343/*
2344 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2345 * Link bit cleared after starting the link retrain process to allow this
2346 * process to finish.
2347 *
2348 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2349 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2350 */
2351static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2352{
2353 dev->clear_retrain_link = 1;
2354 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2355}
2356DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2357DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2359
2360static void fixup_rev1_53c810(struct pci_dev *dev)
2361{
2362 u32 class = dev->class;
2363
2364 /*
2365 * rev 1 ncr53c810 chips don't set the class at all which means
2366 * they don't get their resources remapped. Fix that here.
2367 */
2368 if (class)
2369 return;
2370
2371 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2372 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2373 class, dev->class);
2374}
2375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2376
2377/* Enable 1k I/O space granularity on the Intel P64H2 */
2378static void quirk_p64h2_1k_io(struct pci_dev *dev)
2379{
2380 u16 en1k;
2381
2382 pci_read_config_word(dev, 0x40, &en1k);
2383
2384 if (en1k & 0x200) {
2385 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2386 dev->io_window_1k = 1;
2387 }
2388}
2389DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2390
2391/*
2392 * Under some circumstances, AER is not linked with extended capabilities.
2393 * Force it to be linked by setting the corresponding control bit in the
2394 * config space.
2395 */
2396static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2397{
2398 uint8_t b;
2399
2400 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2401 if (!(b & 0x20)) {
2402 pci_write_config_byte(dev, 0xf41, b | 0x20);
2403 pci_info(dev, "Linking AER extended capability\n");
2404 }
2405 }
2406}
2407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2408 quirk_nvidia_ck804_pcie_aer_ext_cap);
2409DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2410 quirk_nvidia_ck804_pcie_aer_ext_cap);
2411
2412static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2413{
2414 /*
2415 * Disable PCI Bus Parking and PCI Master read caching on CX700
2416 * which causes unspecified timing errors with a VT6212L on the PCI
2417 * bus leading to USB2.0 packet loss.
2418 *
2419 * This quirk is only enabled if a second (on the external PCI bus)
2420 * VT6212L is found -- the CX700 core itself also contains a USB
2421 * host controller with the same PCI ID as the VT6212L.
2422 */
2423
2424 /* Count VT6212L instances */
2425 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2426 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2427 uint8_t b;
2428
2429 /*
2430 * p should contain the first (internal) VT6212L -- see if we have
2431 * an external one by searching again.
2432 */
2433 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2434 if (!p)
2435 return;
2436 pci_dev_put(p);
2437
2438 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2439 if (b & 0x40) {
2440 /* Turn off PCI Bus Parking */
2441 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2442
2443 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2444 }
2445 }
2446
2447 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2448 if (b != 0) {
2449 /* Turn off PCI Master read caching */
2450 pci_write_config_byte(dev, 0x72, 0x0);
2451
2452 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2453 pci_write_config_byte(dev, 0x75, 0x1);
2454
2455 /* Disable "Read FIFO Timer" */
2456 pci_write_config_byte(dev, 0x77, 0x0);
2457
2458 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2459 }
2460 }
2461}
2462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2463
2464static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2465{
2466 u32 rev;
2467
2468 pci_read_config_dword(dev, 0xf4, &rev);
2469
2470 /* Only CAP the MRRS if the device is a 5719 A0 */
2471 if (rev == 0x05719000) {
2472 int readrq = pcie_get_readrq(dev);
2473 if (readrq > 2048)
2474 pcie_set_readrq(dev, 2048);
2475 }
2476}
2477DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2478 PCI_DEVICE_ID_TIGON3_5719,
2479 quirk_brcm_5719_limit_mrrs);
2480
2481/*
2482 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2483 * hide device 6 which configures the overflow device access containing the
2484 * DRBs - this is where we expose device 6.
2485 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2486 */
2487static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2488{
2489 u8 reg;
2490
2491 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2492 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2493 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2494 }
2495}
2496DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2497 quirk_unhide_mch_dev6);
2498DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2499 quirk_unhide_mch_dev6);
2500
2501#ifdef CONFIG_PCI_MSI
2502/*
2503 * Some chipsets do not support MSI. We cannot easily rely on setting
2504 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2505 * other buses controlled by the chipset even if Linux is not aware of it.
2506 * Instead of setting the flag on all buses in the machine, simply disable
2507 * MSI globally.
2508 */
2509static void quirk_disable_all_msi(struct pci_dev *dev)
2510{
2511 pci_no_msi();
2512 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2513}
2514DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2515DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2516DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2517DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2520DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2522DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2523
2524/* Disable MSI on chipsets that are known to not support it */
2525static void quirk_disable_msi(struct pci_dev *dev)
2526{
2527 if (dev->subordinate) {
2528 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2529 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2530 }
2531}
2532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2533DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2535
2536/*
2537 * The APC bridge device in AMD 780 family northbridges has some random
2538 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2539 * we use the possible vendor/device IDs of the host bridge for the
2540 * declared quirk, and search for the APC bridge by slot number.
2541 */
2542static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2543{
2544 struct pci_dev *apc_bridge;
2545
2546 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2547 if (apc_bridge) {
2548 if (apc_bridge->device == 0x9602)
2549 quirk_disable_msi(apc_bridge);
2550 pci_dev_put(apc_bridge);
2551 }
2552}
2553DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2555
2556/*
2557 * Go through the list of HyperTransport capabilities and return 1 if a HT
2558 * MSI capability is found and enabled.
2559 */
2560static int msi_ht_cap_enabled(struct pci_dev *dev)
2561{
2562 int pos, ttl = PCI_FIND_CAP_TTL;
2563
2564 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2565 while (pos && ttl--) {
2566 u8 flags;
2567
2568 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2569 &flags) == 0) {
2570 pci_info(dev, "Found %s HT MSI Mapping\n",
2571 flags & HT_MSI_FLAGS_ENABLE ?
2572 "enabled" : "disabled");
2573 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2574 }
2575
2576 pos = pci_find_next_ht_capability(dev, pos,
2577 HT_CAPTYPE_MSI_MAPPING);
2578 }
2579 return 0;
2580}
2581
2582/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2583static void quirk_msi_ht_cap(struct pci_dev *dev)
2584{
2585 if (!msi_ht_cap_enabled(dev))
2586 quirk_disable_msi(dev);
2587}
2588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2589 quirk_msi_ht_cap);
2590
2591/*
2592 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2593 * if the MSI capability is set in any of these mappings.
2594 */
2595static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2596{
2597 struct pci_dev *pdev;
2598
2599 /*
2600 * Check HT MSI cap on this chipset and the root one. A single one
2601 * having MSI is enough to be sure that MSI is supported.
2602 */
2603 pdev = pci_get_slot(dev->bus, 0);
2604 if (!pdev)
2605 return;
2606 if (!msi_ht_cap_enabled(pdev))
2607 quirk_msi_ht_cap(dev);
2608 pci_dev_put(pdev);
2609}
2610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2611 quirk_nvidia_ck804_msi_ht_cap);
2612
2613/* Force enable MSI mapping capability on HT bridges */
2614static void ht_enable_msi_mapping(struct pci_dev *dev)
2615{
2616 int pos, ttl = PCI_FIND_CAP_TTL;
2617
2618 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2619 while (pos && ttl--) {
2620 u8 flags;
2621
2622 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2623 &flags) == 0) {
2624 pci_info(dev, "Enabling HT MSI Mapping\n");
2625
2626 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2627 flags | HT_MSI_FLAGS_ENABLE);
2628 }
2629 pos = pci_find_next_ht_capability(dev, pos,
2630 HT_CAPTYPE_MSI_MAPPING);
2631 }
2632}
2633DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2634 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2635 ht_enable_msi_mapping);
2636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2637 ht_enable_msi_mapping);
2638
2639/*
2640 * The P5N32-SLI motherboards from Asus have a problem with MSI
2641 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2642 * also affects other devices. As for now, turn off MSI for this device.
2643 */
2644static void nvenet_msi_disable(struct pci_dev *dev)
2645{
2646 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2647
2648 if (board_name &&
2649 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2650 strstr(board_name, "P5N32-E SLI"))) {
2651 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2652 dev->no_msi = 1;
2653 }
2654}
2655DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2656 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2657 nvenet_msi_disable);
2658
2659/*
2660 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2661 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2662 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2663 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2664 * for other events, since PCIe specificiation doesn't support using a mix of
2665 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2666 * service drivers registering their respective ISRs for MSIs.
2667 */
2668static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2669{
2670 dev->no_msi = 1;
2671}
2672DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2673 PCI_CLASS_BRIDGE_PCI, 8,
2674 pci_quirk_nvidia_tegra_disable_rp_msi);
2675DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2676 PCI_CLASS_BRIDGE_PCI, 8,
2677 pci_quirk_nvidia_tegra_disable_rp_msi);
2678DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2679 PCI_CLASS_BRIDGE_PCI, 8,
2680 pci_quirk_nvidia_tegra_disable_rp_msi);
2681DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2682 PCI_CLASS_BRIDGE_PCI, 8,
2683 pci_quirk_nvidia_tegra_disable_rp_msi);
2684DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2685 PCI_CLASS_BRIDGE_PCI, 8,
2686 pci_quirk_nvidia_tegra_disable_rp_msi);
2687DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2688 PCI_CLASS_BRIDGE_PCI, 8,
2689 pci_quirk_nvidia_tegra_disable_rp_msi);
2690DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2691 PCI_CLASS_BRIDGE_PCI, 8,
2692 pci_quirk_nvidia_tegra_disable_rp_msi);
2693DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2694 PCI_CLASS_BRIDGE_PCI, 8,
2695 pci_quirk_nvidia_tegra_disable_rp_msi);
2696DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2697 PCI_CLASS_BRIDGE_PCI, 8,
2698 pci_quirk_nvidia_tegra_disable_rp_msi);
2699DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2700 PCI_CLASS_BRIDGE_PCI, 8,
2701 pci_quirk_nvidia_tegra_disable_rp_msi);
2702DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2703 PCI_CLASS_BRIDGE_PCI, 8,
2704 pci_quirk_nvidia_tegra_disable_rp_msi);
2705DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2706 PCI_CLASS_BRIDGE_PCI, 8,
2707 pci_quirk_nvidia_tegra_disable_rp_msi);
2708DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2709 PCI_CLASS_BRIDGE_PCI, 8,
2710 pci_quirk_nvidia_tegra_disable_rp_msi);
2711
2712/*
2713 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2714 * config register. This register controls the routing of legacy
2715 * interrupts from devices that route through the MCP55. If this register
2716 * is misprogrammed, interrupts are only sent to the BSP, unlike
2717 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2718 * having this register set properly prevents kdump from booting up
2719 * properly, so let's make sure that we have it set correctly.
2720 * Note that this is an undocumented register.
2721 */
2722static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2723{
2724 u32 cfg;
2725
2726 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2727 return;
2728
2729 pci_read_config_dword(dev, 0x74, &cfg);
2730
2731 if (cfg & ((1 << 2) | (1 << 15))) {
2732 pr_info("Rewriting IRQ routing register on MCP55\n");
2733 cfg &= ~((1 << 2) | (1 << 15));
2734 pci_write_config_dword(dev, 0x74, cfg);
2735 }
2736}
2737DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2738 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2739 nvbridge_check_legacy_irq_routing);
2740DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2741 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2742 nvbridge_check_legacy_irq_routing);
2743
2744static int ht_check_msi_mapping(struct pci_dev *dev)
2745{
2746 int pos, ttl = PCI_FIND_CAP_TTL;
2747 int found = 0;
2748
2749 /* Check if there is HT MSI cap or enabled on this device */
2750 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2751 while (pos && ttl--) {
2752 u8 flags;
2753
2754 if (found < 1)
2755 found = 1;
2756 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2757 &flags) == 0) {
2758 if (flags & HT_MSI_FLAGS_ENABLE) {
2759 if (found < 2) {
2760 found = 2;
2761 break;
2762 }
2763 }
2764 }
2765 pos = pci_find_next_ht_capability(dev, pos,
2766 HT_CAPTYPE_MSI_MAPPING);
2767 }
2768
2769 return found;
2770}
2771
2772static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2773{
2774 struct pci_dev *dev;
2775 int pos;
2776 int i, dev_no;
2777 int found = 0;
2778
2779 dev_no = host_bridge->devfn >> 3;
2780 for (i = dev_no + 1; i < 0x20; i++) {
2781 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2782 if (!dev)
2783 continue;
2784
2785 /* found next host bridge? */
2786 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2787 if (pos != 0) {
2788 pci_dev_put(dev);
2789 break;
2790 }
2791
2792 if (ht_check_msi_mapping(dev)) {
2793 found = 1;
2794 pci_dev_put(dev);
2795 break;
2796 }
2797 pci_dev_put(dev);
2798 }
2799
2800 return found;
2801}
2802
2803#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2804#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2805
2806static int is_end_of_ht_chain(struct pci_dev *dev)
2807{
2808 int pos, ctrl_off;
2809 int end = 0;
2810 u16 flags, ctrl;
2811
2812 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2813
2814 if (!pos)
2815 goto out;
2816
2817 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2818
2819 ctrl_off = ((flags >> 10) & 1) ?
2820 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2821 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2822
2823 if (ctrl & (1 << 6))
2824 end = 1;
2825
2826out:
2827 return end;
2828}
2829
2830static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2831{
2832 struct pci_dev *host_bridge;
2833 int pos;
2834 int i, dev_no;
2835 int found = 0;
2836
2837 dev_no = dev->devfn >> 3;
2838 for (i = dev_no; i >= 0; i--) {
2839 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2840 if (!host_bridge)
2841 continue;
2842
2843 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2844 if (pos != 0) {
2845 found = 1;
2846 break;
2847 }
2848 pci_dev_put(host_bridge);
2849 }
2850
2851 if (!found)
2852 return;
2853
2854 /* don't enable end_device/host_bridge with leaf directly here */
2855 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2856 host_bridge_with_leaf(host_bridge))
2857 goto out;
2858
2859 /* root did that ! */
2860 if (msi_ht_cap_enabled(host_bridge))
2861 goto out;
2862
2863 ht_enable_msi_mapping(dev);
2864
2865out:
2866 pci_dev_put(host_bridge);
2867}
2868
2869static void ht_disable_msi_mapping(struct pci_dev *dev)
2870{
2871 int pos, ttl = PCI_FIND_CAP_TTL;
2872
2873 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2874 while (pos && ttl--) {
2875 u8 flags;
2876
2877 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2878 &flags) == 0) {
2879 pci_info(dev, "Disabling HT MSI Mapping\n");
2880
2881 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2882 flags & ~HT_MSI_FLAGS_ENABLE);
2883 }
2884 pos = pci_find_next_ht_capability(dev, pos,
2885 HT_CAPTYPE_MSI_MAPPING);
2886 }
2887}
2888
2889static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2890{
2891 struct pci_dev *host_bridge;
2892 int pos;
2893 int found;
2894
2895 if (!pci_msi_enabled())
2896 return;
2897
2898 /* check if there is HT MSI cap or enabled on this device */
2899 found = ht_check_msi_mapping(dev);
2900
2901 /* no HT MSI CAP */
2902 if (found == 0)
2903 return;
2904
2905 /*
2906 * HT MSI mapping should be disabled on devices that are below
2907 * a non-Hypertransport host bridge. Locate the host bridge...
2908 */
2909 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2910 PCI_DEVFN(0, 0));
2911 if (host_bridge == NULL) {
2912 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2913 return;
2914 }
2915
2916 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2917 if (pos != 0) {
2918 /* Host bridge is to HT */
2919 if (found == 1) {
2920 /* it is not enabled, try to enable it */
2921 if (all)
2922 ht_enable_msi_mapping(dev);
2923 else
2924 nv_ht_enable_msi_mapping(dev);
2925 }
2926 goto out;
2927 }
2928
2929 /* HT MSI is not enabled */
2930 if (found == 1)
2931 goto out;
2932
2933 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2934 ht_disable_msi_mapping(dev);
2935
2936out:
2937 pci_dev_put(host_bridge);
2938}
2939
2940static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2941{
2942 return __nv_msi_ht_cap_quirk(dev, 1);
2943}
2944DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2945DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2946
2947static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2948{
2949 return __nv_msi_ht_cap_quirk(dev, 0);
2950}
2951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2952DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2953
2954static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2955{
2956 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2957}
2958
2959static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2960{
2961 struct pci_dev *p;
2962
2963 /*
2964 * SB700 MSI issue will be fixed at HW level from revision A21;
2965 * we need check PCI REVISION ID of SMBus controller to get SB700
2966 * revision.
2967 */
2968 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2969 NULL);
2970 if (!p)
2971 return;
2972
2973 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2974 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2975 pci_dev_put(p);
2976}
2977
2978static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2979{
2980 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2981 if (dev->revision < 0x18) {
2982 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2983 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2984 }
2985}
2986DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2987 PCI_DEVICE_ID_TIGON3_5780,
2988 quirk_msi_intx_disable_bug);
2989DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2990 PCI_DEVICE_ID_TIGON3_5780S,
2991 quirk_msi_intx_disable_bug);
2992DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2993 PCI_DEVICE_ID_TIGON3_5714,
2994 quirk_msi_intx_disable_bug);
2995DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2996 PCI_DEVICE_ID_TIGON3_5714S,
2997 quirk_msi_intx_disable_bug);
2998DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2999 PCI_DEVICE_ID_TIGON3_5715,
3000 quirk_msi_intx_disable_bug);
3001DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3002 PCI_DEVICE_ID_TIGON3_5715S,
3003 quirk_msi_intx_disable_bug);
3004
3005DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3006 quirk_msi_intx_disable_ati_bug);
3007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3008 quirk_msi_intx_disable_ati_bug);
3009DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3010 quirk_msi_intx_disable_ati_bug);
3011DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3012 quirk_msi_intx_disable_ati_bug);
3013DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3014 quirk_msi_intx_disable_ati_bug);
3015
3016DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3017 quirk_msi_intx_disable_bug);
3018DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3019 quirk_msi_intx_disable_bug);
3020DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3021 quirk_msi_intx_disable_bug);
3022
3023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3024 quirk_msi_intx_disable_bug);
3025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3026 quirk_msi_intx_disable_bug);
3027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3028 quirk_msi_intx_disable_bug);
3029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3030 quirk_msi_intx_disable_bug);
3031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3032 quirk_msi_intx_disable_bug);
3033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3034 quirk_msi_intx_disable_bug);
3035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3036 quirk_msi_intx_disable_qca_bug);
3037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3038 quirk_msi_intx_disable_qca_bug);
3039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3040 quirk_msi_intx_disable_qca_bug);
3041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3042 quirk_msi_intx_disable_qca_bug);
3043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3044 quirk_msi_intx_disable_qca_bug);
3045
3046/*
3047 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3048 * should be disabled on platforms where the device (mistakenly) advertises it.
3049 *
3050 * Notice that this quirk also disables MSI (which may work, but hasn't been
3051 * tested), since currently there is no standard way to disable only MSI-X.
3052 *
3053 * The 0031 device id is reused for other non Root Port device types,
3054 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3055 */
3056static void quirk_al_msi_disable(struct pci_dev *dev)
3057{
3058 dev->no_msi = 1;
3059 pci_warn(dev, "Disabling MSI/MSI-X\n");
3060}
3061DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3062 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3063#endif /* CONFIG_PCI_MSI */
3064
3065/*
3066 * Allow manual resource allocation for PCI hotplug bridges via
3067 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3068 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3069 * allocate resources when hotplug device is inserted and PCI bus is
3070 * rescanned.
3071 */
3072static void quirk_hotplug_bridge(struct pci_dev *dev)
3073{
3074 dev->is_hotplug_bridge = 1;
3075}
3076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3077
3078/*
3079 * This is a quirk for the Ricoh MMC controller found as a part of some
3080 * multifunction chips.
3081 *
3082 * This is very similar and based on the ricoh_mmc driver written by
3083 * Philip Langdale. Thank you for these magic sequences.
3084 *
3085 * These chips implement the four main memory card controllers (SD, MMC,
3086 * MS, xD) and one or both of CardBus or FireWire.
3087 *
3088 * It happens that they implement SD and MMC support as separate
3089 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3090 * cards but the chip detects MMC cards in hardware and directs them to the
3091 * MMC controller - so the SDHCI driver never sees them.
3092 *
3093 * To get around this, we must disable the useless MMC controller. At that
3094 * point, the SDHCI controller will start seeing them. It seems to be the
3095 * case that the relevant PCI registers to deactivate the MMC controller
3096 * live on PCI function 0, which might be the CardBus controller or the
3097 * FireWire controller, depending on the particular chip in question
3098 *
3099 * This has to be done early, because as soon as we disable the MMC controller
3100 * other PCI functions shift up one level, e.g. function #2 becomes function
3101 * #1, and this will confuse the PCI core.
3102 */
3103#ifdef CONFIG_MMC_RICOH_MMC
3104static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3105{
3106 u8 write_enable;
3107 u8 write_target;
3108 u8 disable;
3109
3110 /*
3111 * Disable via CardBus interface
3112 *
3113 * This must be done via function #0
3114 */
3115 if (PCI_FUNC(dev->devfn))
3116 return;
3117
3118 pci_read_config_byte(dev, 0xB7, &disable);
3119 if (disable & 0x02)
3120 return;
3121
3122 pci_read_config_byte(dev, 0x8E, &write_enable);
3123 pci_write_config_byte(dev, 0x8E, 0xAA);
3124 pci_read_config_byte(dev, 0x8D, &write_target);
3125 pci_write_config_byte(dev, 0x8D, 0xB7);
3126 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3127 pci_write_config_byte(dev, 0x8E, write_enable);
3128 pci_write_config_byte(dev, 0x8D, write_target);
3129
3130 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3131 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3132}
3133DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3134DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3135
3136static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3137{
3138 u8 write_enable;
3139 u8 disable;
3140
3141 /*
3142 * Disable via FireWire interface
3143 *
3144 * This must be done via function #0
3145 */
3146 if (PCI_FUNC(dev->devfn))
3147 return;
3148 /*
3149 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3150 * certain types of SD/MMC cards. Lowering the SD base clock
3151 * frequency from 200Mhz to 50Mhz fixes this issue.
3152 *
3153 * 0x150 - SD2.0 mode enable for changing base clock
3154 * frequency to 50Mhz
3155 * 0xe1 - Base clock frequency
3156 * 0x32 - 50Mhz new clock frequency
3157 * 0xf9 - Key register for 0x150
3158 * 0xfc - key register for 0xe1
3159 */
3160 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3161 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3162 pci_write_config_byte(dev, 0xf9, 0xfc);
3163 pci_write_config_byte(dev, 0x150, 0x10);
3164 pci_write_config_byte(dev, 0xf9, 0x00);
3165 pci_write_config_byte(dev, 0xfc, 0x01);
3166 pci_write_config_byte(dev, 0xe1, 0x32);
3167 pci_write_config_byte(dev, 0xfc, 0x00);
3168
3169 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3170 }
3171
3172 pci_read_config_byte(dev, 0xCB, &disable);
3173
3174 if (disable & 0x02)
3175 return;
3176
3177 pci_read_config_byte(dev, 0xCA, &write_enable);
3178 pci_write_config_byte(dev, 0xCA, 0x57);
3179 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3180 pci_write_config_byte(dev, 0xCA, write_enable);
3181
3182 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3183 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3184
3185}
3186DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3187DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3188DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3189DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3190DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3191DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3192#endif /*CONFIG_MMC_RICOH_MMC*/
3193
3194#ifdef CONFIG_DMAR_TABLE
3195#define VTUNCERRMSK_REG 0x1ac
3196#define VTD_MSK_SPEC_ERRORS (1 << 31)
3197/*
3198 * This is a quirk for masking VT-d spec-defined errors to platform error
3199 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3200 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3201 * on the RAS config settings of the platform) when a VT-d fault happens.
3202 * The resulting SMI caused the system to hang.
3203 *
3204 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3205 * need to report the same error through other channels.
3206 */
3207static void vtd_mask_spec_errors(struct pci_dev *dev)
3208{
3209 u32 word;
3210
3211 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3212 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3213}
3214DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3215DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3216#endif
3217
3218static void fixup_ti816x_class(struct pci_dev *dev)
3219{
3220 u32 class = dev->class;
3221
3222 /* TI 816x devices do not have class code set when in PCIe boot mode */
3223 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3224 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3225 class, dev->class);
3226}
3227DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3228 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3229
3230/*
3231 * Some PCIe devices do not work reliably with the claimed maximum
3232 * payload size supported.
3233 */
3234static void fixup_mpss_256(struct pci_dev *dev)
3235{
3236 dev->pcie_mpss = 1; /* 256 bytes */
3237}
3238DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3239 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3240DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3241 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3242DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3243 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3244DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3245
3246/*
3247 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3248 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3249 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3250 * until all of the devices are discovered and buses walked, read completion
3251 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3252 * it is possible to hotplug a device with MPS of 256B.
3253 */
3254static void quirk_intel_mc_errata(struct pci_dev *dev)
3255{
3256 int err;
3257 u16 rcc;
3258
3259 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3260 pcie_bus_config == PCIE_BUS_DEFAULT)
3261 return;
3262
3263 /*
3264 * Intel erratum specifies bits to change but does not say what
3265 * they are. Keeping them magical until such time as the registers
3266 * and values can be explained.
3267 */
3268 err = pci_read_config_word(dev, 0x48, &rcc);
3269 if (err) {
3270 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3271 return;
3272 }
3273
3274 if (!(rcc & (1 << 10)))
3275 return;
3276
3277 rcc &= ~(1 << 10);
3278
3279 err = pci_write_config_word(dev, 0x48, rcc);
3280 if (err) {
3281 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3282 return;
3283 }
3284
3285 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3286}
3287/* Intel 5000 series memory controllers and ports 2-7 */
3288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3292DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3293DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3302/* Intel 5100 series memory controllers and ports 2-7 */
3303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3306DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3307DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3308DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3314
3315/*
3316 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3317 * To work around this, query the size it should be configured to by the
3318 * device and modify the resource end to correspond to this new size.
3319 */
3320static void quirk_intel_ntb(struct pci_dev *dev)
3321{
3322 int rc;
3323 u8 val;
3324
3325 rc = pci_read_config_byte(dev, 0x00D0, &val);
3326 if (rc)
3327 return;
3328
3329 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3330
3331 rc = pci_read_config_byte(dev, 0x00D1, &val);
3332 if (rc)
3333 return;
3334
3335 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3336}
3337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3339
3340/*
3341 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3342 * though no one is handling them (e.g., if the i915 driver is never
3343 * loaded). Additionally the interrupt destination is not set up properly
3344 * and the interrupt ends up -somewhere-.
3345 *
3346 * These spurious interrupts are "sticky" and the kernel disables the
3347 * (shared) interrupt line after 100,000+ generated interrupts.
3348 *
3349 * Fix it by disabling the still enabled interrupts. This resolves crashes
3350 * often seen on monitor unplug.
3351 */
3352#define I915_DEIER_REG 0x4400c
3353static void disable_igfx_irq(struct pci_dev *dev)
3354{
3355 void __iomem *regs = pci_iomap(dev, 0, 0);
3356 if (regs == NULL) {
3357 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3358 return;
3359 }
3360
3361 /* Check if any interrupt line is still enabled */
3362 if (readl(regs + I915_DEIER_REG) != 0) {
3363 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3364
3365 writel(0, regs + I915_DEIER_REG);
3366 }
3367
3368 pci_iounmap(dev, regs);
3369}
3370DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3377
3378/*
3379 * PCI devices which are on Intel chips can skip the 10ms delay
3380 * before entering D3 mode.
3381 */
3382static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3383{
3384 dev->d3hot_delay = 0;
3385}
3386/* C600 Series devices do not need 10ms d3hot_delay */
3387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3390/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3402/* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3412
3413/*
3414 * Some devices may pass our check in pci_intx_mask_supported() if
3415 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3416 * support this feature.
3417 */
3418static void quirk_broken_intx_masking(struct pci_dev *dev)
3419{
3420 dev->broken_intx_masking = 1;
3421}
3422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3423 quirk_broken_intx_masking);
3424DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3425 quirk_broken_intx_masking);
3426DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3427 quirk_broken_intx_masking);
3428
3429/*
3430 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3431 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3432 *
3433 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3434 */
3435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3436 quirk_broken_intx_masking);
3437
3438/*
3439 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3440 * DisINTx can be set but the interrupt status bit is non-functional.
3441 */
3442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3446DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3447DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3449DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3450DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3452DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3453DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3455DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3456DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3458
3459static u16 mellanox_broken_intx_devs[] = {
3460 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3461 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3462 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3463 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3464 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3465 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3466 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3467 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3468 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3469 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3470 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3471 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3472 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3473 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3474};
3475
3476#define CONNECTX_4_CURR_MAX_MINOR 99
3477#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3478
3479/*
3480 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3481 * If so, don't mark it as broken.
3482 * FW minor > 99 means older FW version format and no INTx masking support.
3483 * FW minor < 14 means new FW version format and no INTx masking support.
3484 */
3485static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3486{
3487 __be32 __iomem *fw_ver;
3488 u16 fw_major;
3489 u16 fw_minor;
3490 u16 fw_subminor;
3491 u32 fw_maj_min;
3492 u32 fw_sub_min;
3493 int i;
3494
3495 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3496 if (pdev->device == mellanox_broken_intx_devs[i]) {
3497 pdev->broken_intx_masking = 1;
3498 return;
3499 }
3500 }
3501
3502 /*
3503 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3504 * support so shouldn't be checked further
3505 */
3506 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3507 return;
3508
3509 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3510 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3511 return;
3512
3513 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3514 if (pci_enable_device_mem(pdev)) {
3515 pci_warn(pdev, "Can't enable device memory\n");
3516 return;
3517 }
3518
3519 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3520 if (!fw_ver) {
3521 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3522 goto out;
3523 }
3524
3525 /* Reading from resource space should be 32b aligned */
3526 fw_maj_min = ioread32be(fw_ver);
3527 fw_sub_min = ioread32be(fw_ver + 1);
3528 fw_major = fw_maj_min & 0xffff;
3529 fw_minor = fw_maj_min >> 16;
3530 fw_subminor = fw_sub_min & 0xffff;
3531 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3532 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3533 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3534 fw_major, fw_minor, fw_subminor, pdev->device ==
3535 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3536 pdev->broken_intx_masking = 1;
3537 }
3538
3539 iounmap(fw_ver);
3540
3541out:
3542 pci_disable_device(pdev);
3543}
3544DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3545 mellanox_check_broken_intx_masking);
3546
3547static void quirk_no_bus_reset(struct pci_dev *dev)
3548{
3549 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3550}
3551
3552/*
3553 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3554 * prevented for those affected devices.
3555 */
3556static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3557{
3558 if ((dev->device & 0xffc0) == 0x2340)
3559 quirk_no_bus_reset(dev);
3560}
3561DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3562 quirk_nvidia_no_bus_reset);
3563
3564/*
3565 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3566 * The device will throw a Link Down error on AER-capable systems and
3567 * regardless of AER, config space of the device is never accessible again
3568 * and typically causes the system to hang or reset when access is attempted.
3569 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3570 */
3571DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3573DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3574DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3575DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3576
3577/*
3578 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3579 * reset when used with certain child devices. After the reset, config
3580 * accesses to the child may fail.
3581 */
3582DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3583
3584/*
3585 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3586 * automatically disables LTSSM when Secondary Bus Reset is received and
3587 * the device stops working. Prevent bus reset for these devices. With
3588 * this change, the device can be assigned to VMs with VFIO, but it will
3589 * leak state between VMs. Reference
3590 * https://e2e.ti.com/support/processors/f/791/t/954382
3591 */
3592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3593
3594static void quirk_no_pm_reset(struct pci_dev *dev)
3595{
3596 /*
3597 * We can't do a bus reset on root bus devices, but an ineffective
3598 * PM reset may be better than nothing.
3599 */
3600 if (!pci_is_root_bus(dev->bus))
3601 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3602}
3603
3604/*
3605 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3606 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3607 * to have no effect on the device: it retains the framebuffer contents and
3608 * monitor sync. Advertising this support makes other layers, like VFIO,
3609 * assume pci_reset_function() is viable for this device. Mark it as
3610 * unavailable to skip it when testing reset methods.
3611 */
3612DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3613 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3614
3615/*
3616 * Thunderbolt controllers with broken MSI hotplug signaling:
3617 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3618 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3619 */
3620static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3621{
3622 if (pdev->is_hotplug_bridge &&
3623 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3624 pdev->revision <= 1))
3625 pdev->no_msi = 1;
3626}
3627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3628 quirk_thunderbolt_hotplug_msi);
3629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3630 quirk_thunderbolt_hotplug_msi);
3631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3632 quirk_thunderbolt_hotplug_msi);
3633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3634 quirk_thunderbolt_hotplug_msi);
3635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3636 quirk_thunderbolt_hotplug_msi);
3637
3638#ifdef CONFIG_ACPI
3639/*
3640 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3641 *
3642 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3643 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3644 * be present after resume if a device was plugged in before suspend.
3645 *
3646 * The Thunderbolt controller consists of a PCIe switch with downstream
3647 * bridges leading to the NHI and to the tunnel PCI bridges.
3648 *
3649 * This quirk cuts power to the whole chip. Therefore we have to apply it
3650 * during suspend_noirq of the upstream bridge.
3651 *
3652 * Power is automagically restored before resume. No action is needed.
3653 */
3654static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3655{
3656 acpi_handle bridge, SXIO, SXFP, SXLV;
3657
3658 if (!x86_apple_machine)
3659 return;
3660 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3661 return;
3662
3663 /*
3664 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3665 * We don't know how to turn it back on again, but firmware does,
3666 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3667 * firmware.
3668 */
3669 if (!pm_suspend_via_firmware())
3670 return;
3671
3672 bridge = ACPI_HANDLE(&dev->dev);
3673 if (!bridge)
3674 return;
3675
3676 /*
3677 * SXIO and SXLV are present only on machines requiring this quirk.
3678 * Thunderbolt bridges in external devices might have the same
3679 * device ID as those on the host, but they will not have the
3680 * associated ACPI methods. This implicitly checks that we are at
3681 * the right bridge.
3682 */
3683 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3684 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3685 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3686 return;
3687 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3688
3689 /* magic sequence */
3690 acpi_execute_simple_method(SXIO, NULL, 1);
3691 acpi_execute_simple_method(SXFP, NULL, 0);
3692 msleep(300);
3693 acpi_execute_simple_method(SXLV, NULL, 0);
3694 acpi_execute_simple_method(SXIO, NULL, 0);
3695 acpi_execute_simple_method(SXLV, NULL, 0);
3696}
3697DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3698 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3699 quirk_apple_poweroff_thunderbolt);
3700#endif
3701
3702/*
3703 * Following are device-specific reset methods which can be used to
3704 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3705 * not available.
3706 */
3707static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3708{
3709 /*
3710 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3711 *
3712 * The 82599 supports FLR on VFs, but FLR support is reported only
3713 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3714 * Thus we must call pcie_flr() directly without first checking if it is
3715 * supported.
3716 */
3717 if (!probe)
3718 pcie_flr(dev);
3719 return 0;
3720}
3721
3722#define SOUTH_CHICKEN2 0xc2004
3723#define PCH_PP_STATUS 0xc7200
3724#define PCH_PP_CONTROL 0xc7204
3725#define MSG_CTL 0x45010
3726#define NSDE_PWR_STATE 0xd0100
3727#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3728
3729static int reset_ivb_igd(struct pci_dev *dev, int probe)
3730{
3731 void __iomem *mmio_base;
3732 unsigned long timeout;
3733 u32 val;
3734
3735 if (probe)
3736 return 0;
3737
3738 mmio_base = pci_iomap(dev, 0, 0);
3739 if (!mmio_base)
3740 return -ENOMEM;
3741
3742 iowrite32(0x00000002, mmio_base + MSG_CTL);
3743
3744 /*
3745 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3746 * driver loaded sets the right bits. However, this's a reset and
3747 * the bits have been set by i915 previously, so we clobber
3748 * SOUTH_CHICKEN2 register directly here.
3749 */
3750 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3751
3752 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3753 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3754
3755 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3756 do {
3757 val = ioread32(mmio_base + PCH_PP_STATUS);
3758 if ((val & 0xb0000000) == 0)
3759 goto reset_complete;
3760 msleep(10);
3761 } while (time_before(jiffies, timeout));
3762 pci_warn(dev, "timeout during reset\n");
3763
3764reset_complete:
3765 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3766
3767 pci_iounmap(dev, mmio_base);
3768 return 0;
3769}
3770
3771/* Device-specific reset method for Chelsio T4-based adapters */
3772static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3773{
3774 u16 old_command;
3775 u16 msix_flags;
3776
3777 /*
3778 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3779 * that we have no device-specific reset method.
3780 */
3781 if ((dev->device & 0xf000) != 0x4000)
3782 return -ENOTTY;
3783
3784 /*
3785 * If this is the "probe" phase, return 0 indicating that we can
3786 * reset this device.
3787 */
3788 if (probe)
3789 return 0;
3790
3791 /*
3792 * T4 can wedge if there are DMAs in flight within the chip and Bus
3793 * Master has been disabled. We need to have it on till the Function
3794 * Level Reset completes. (BUS_MASTER is disabled in
3795 * pci_reset_function()).
3796 */
3797 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3798 pci_write_config_word(dev, PCI_COMMAND,
3799 old_command | PCI_COMMAND_MASTER);
3800
3801 /*
3802 * Perform the actual device function reset, saving and restoring
3803 * configuration information around the reset.
3804 */
3805 pci_save_state(dev);
3806
3807 /*
3808 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3809 * are disabled when an MSI-X interrupt message needs to be delivered.
3810 * So we briefly re-enable MSI-X interrupts for the duration of the
3811 * FLR. The pci_restore_state() below will restore the original
3812 * MSI-X state.
3813 */
3814 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3815 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3816 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3817 msix_flags |
3818 PCI_MSIX_FLAGS_ENABLE |
3819 PCI_MSIX_FLAGS_MASKALL);
3820
3821 pcie_flr(dev);
3822
3823 /*
3824 * Restore the configuration information (BAR values, etc.) including
3825 * the original PCI Configuration Space Command word, and return
3826 * success.
3827 */
3828 pci_restore_state(dev);
3829 pci_write_config_word(dev, PCI_COMMAND, old_command);
3830 return 0;
3831}
3832
3833#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3834#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3835#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3836
3837/*
3838 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3839 * FLR where config space reads from the device return -1. We seem to be
3840 * able to avoid this condition if we disable the NVMe controller prior to
3841 * FLR. This quirk is generic for any NVMe class device requiring similar
3842 * assistance to quiesce the device prior to FLR.
3843 *
3844 * NVMe specification: https://nvmexpress.org/resources/specifications/
3845 * Revision 1.0e:
3846 * Chapter 2: Required and optional PCI config registers
3847 * Chapter 3: NVMe control registers
3848 * Chapter 7.3: Reset behavior
3849 */
3850static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3851{
3852 void __iomem *bar;
3853 u16 cmd;
3854 u32 cfg;
3855
3856 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3857 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3858 return -ENOTTY;
3859
3860 if (probe)
3861 return 0;
3862
3863 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3864 if (!bar)
3865 return -ENOTTY;
3866
3867 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3868 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3869
3870 cfg = readl(bar + NVME_REG_CC);
3871
3872 /* Disable controller if enabled */
3873 if (cfg & NVME_CC_ENABLE) {
3874 u32 cap = readl(bar + NVME_REG_CAP);
3875 unsigned long timeout;
3876
3877 /*
3878 * Per nvme_disable_ctrl() skip shutdown notification as it
3879 * could complete commands to the admin queue. We only intend
3880 * to quiesce the device before reset.
3881 */
3882 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3883
3884 writel(cfg, bar + NVME_REG_CC);
3885
3886 /*
3887 * Some controllers require an additional delay here, see
3888 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3889 * supported by this quirk.
3890 */
3891
3892 /* Cap register provides max timeout in 500ms increments */
3893 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3894
3895 for (;;) {
3896 u32 status = readl(bar + NVME_REG_CSTS);
3897
3898 /* Ready status becomes zero on disable complete */
3899 if (!(status & NVME_CSTS_RDY))
3900 break;
3901
3902 msleep(100);
3903
3904 if (time_after(jiffies, timeout)) {
3905 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3906 break;
3907 }
3908 }
3909 }
3910
3911 pci_iounmap(dev, bar);
3912
3913 pcie_flr(dev);
3914
3915 return 0;
3916}
3917
3918/*
3919 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3920 * to change after NVMe enable if the driver starts interacting with the
3921 * device too soon after FLR. A 250ms delay after FLR has heuristically
3922 * proven to produce reliably working results for device assignment cases.
3923 */
3924static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3925{
3926 if (!pcie_has_flr(dev))
3927 return -ENOTTY;
3928
3929 if (probe)
3930 return 0;
3931
3932 pcie_flr(dev);
3933
3934 msleep(250);
3935
3936 return 0;
3937}
3938
3939#define PCI_DEVICE_ID_HINIC_VF 0x375E
3940#define HINIC_VF_FLR_TYPE 0x1000
3941#define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3942#define HINIC_VF_OP 0xE80
3943#define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3944#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3945
3946/* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3947static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
3948{
3949 unsigned long timeout;
3950 void __iomem *bar;
3951 u32 val;
3952
3953 if (probe)
3954 return 0;
3955
3956 bar = pci_iomap(pdev, 0, 0);
3957 if (!bar)
3958 return -ENOTTY;
3959
3960 /* Get and check firmware capabilities */
3961 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
3962 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
3963 pci_iounmap(pdev, bar);
3964 return -ENOTTY;
3965 }
3966
3967 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
3968 val = ioread32be(bar + HINIC_VF_OP);
3969 val = val | HINIC_VF_FLR_PROC_BIT;
3970 iowrite32be(val, bar + HINIC_VF_OP);
3971
3972 pcie_flr(pdev);
3973
3974 /*
3975 * The device must recapture its Bus and Device Numbers after FLR
3976 * in order generate Completions. Issue a config write to let the
3977 * device capture this information.
3978 */
3979 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
3980
3981 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
3982 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
3983 do {
3984 val = ioread32be(bar + HINIC_VF_OP);
3985 if (!(val & HINIC_VF_FLR_PROC_BIT))
3986 goto reset_complete;
3987 msleep(20);
3988 } while (time_before(jiffies, timeout));
3989
3990 val = ioread32be(bar + HINIC_VF_OP);
3991 if (!(val & HINIC_VF_FLR_PROC_BIT))
3992 goto reset_complete;
3993
3994 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
3995
3996reset_complete:
3997 pci_iounmap(pdev, bar);
3998
3999 return 0;
4000}
4001
4002static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4003 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4004 reset_intel_82599_sfp_virtfn },
4005 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4006 reset_ivb_igd },
4007 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4008 reset_ivb_igd },
4009 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4010 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4011 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4012 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4013 reset_chelsio_generic_dev },
4014 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4015 reset_hinic_vf_dev },
4016 { 0 }
4017};
4018
4019/*
4020 * These device-specific reset methods are here rather than in a driver
4021 * because when a host assigns a device to a guest VM, the host may need
4022 * to reset the device but probably doesn't have a driver for it.
4023 */
4024int pci_dev_specific_reset(struct pci_dev *dev, int probe)
4025{
4026 const struct pci_dev_reset_methods *i;
4027
4028 for (i = pci_dev_reset_methods; i->reset; i++) {
4029 if ((i->vendor == dev->vendor ||
4030 i->vendor == (u16)PCI_ANY_ID) &&
4031 (i->device == dev->device ||
4032 i->device == (u16)PCI_ANY_ID))
4033 return i->reset(dev, probe);
4034 }
4035
4036 return -ENOTTY;
4037}
4038
4039static void quirk_dma_func0_alias(struct pci_dev *dev)
4040{
4041 if (PCI_FUNC(dev->devfn) != 0)
4042 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4043}
4044
4045/*
4046 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4047 *
4048 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4049 */
4050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4051DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4052
4053static void quirk_dma_func1_alias(struct pci_dev *dev)
4054{
4055 if (PCI_FUNC(dev->devfn) != 1)
4056 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4057}
4058
4059/*
4060 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4061 * SKUs function 1 is present and is a legacy IDE controller, in other
4062 * SKUs this function is not present, making this a ghost requester.
4063 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4064 */
4065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4066 quirk_dma_func1_alias);
4067DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4068 quirk_dma_func1_alias);
4069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4070 quirk_dma_func1_alias);
4071/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4072DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4073 quirk_dma_func1_alias);
4074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4075 quirk_dma_func1_alias);
4076/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4078 quirk_dma_func1_alias);
4079/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4081 quirk_dma_func1_alias);
4082/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4084 quirk_dma_func1_alias);
4085/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4087 quirk_dma_func1_alias);
4088/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4090 quirk_dma_func1_alias);
4091/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4093 quirk_dma_func1_alias);
4094/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4096 quirk_dma_func1_alias);
4097/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4099 quirk_dma_func1_alias);
4100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4101 quirk_dma_func1_alias);
4102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4103 quirk_dma_func1_alias);
4104/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4106 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4107 quirk_dma_func1_alias);
4108/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4109DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4110 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4111 quirk_dma_func1_alias);
4112
4113/*
4114 * Some devices DMA with the wrong devfn, not just the wrong function.
4115 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4116 * the alias is "fixed" and independent of the device devfn.
4117 *
4118 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4119 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4120 * single device on the secondary bus. In reality, the single exposed
4121 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4122 * that provides a bridge to the internal bus of the I/O processor. The
4123 * controller supports private devices, which can be hidden from PCI config
4124 * space. In the case of the Adaptec 3405, a private device at 01.0
4125 * appears to be the DMA engine, which therefore needs to become a DMA
4126 * alias for the device.
4127 */
4128static const struct pci_device_id fixed_dma_alias_tbl[] = {
4129 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4130 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4131 .driver_data = PCI_DEVFN(1, 0) },
4132 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4133 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4134 .driver_data = PCI_DEVFN(1, 0) },
4135 { 0 }
4136};
4137
4138static void quirk_fixed_dma_alias(struct pci_dev *dev)
4139{
4140 const struct pci_device_id *id;
4141
4142 id = pci_match_id(fixed_dma_alias_tbl, dev);
4143 if (id)
4144 pci_add_dma_alias(dev, id->driver_data, 1);
4145}
4146DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4147
4148/*
4149 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4150 * using the wrong DMA alias for the device. Some of these devices can be
4151 * used as either forward or reverse bridges, so we need to test whether the
4152 * device is operating in the correct mode. We could probably apply this
4153 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4154 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4155 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4156 */
4157static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4158{
4159 if (!pci_is_root_bus(pdev->bus) &&
4160 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4161 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4162 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4163 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4164}
4165/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4167 quirk_use_pcie_bridge_dma_alias);
4168/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4169DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4170/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4171DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4172/* ITE 8893 has the same problem as the 8892 */
4173DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4174/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4175DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4176
4177/*
4178 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4179 * be added as aliases to the DMA device in order to allow buffer access
4180 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4181 * programmed in the EEPROM.
4182 */
4183static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4184{
4185 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4186 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4187 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4188}
4189DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4190DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4191
4192/*
4193 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4194 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4195 *
4196 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4197 * when IOMMU is enabled. These aliases allow computational unit access to
4198 * host memory. These aliases mark the whole VCA device as one IOMMU
4199 * group.
4200 *
4201 * All possible slot numbers (0x20) are used, since we are unable to tell
4202 * what slot is used on other side. This quirk is intended for both host
4203 * and computational unit sides. The VCA devices have up to five functions
4204 * (four for DMA channels and one additional).
4205 */
4206static void quirk_pex_vca_alias(struct pci_dev *pdev)
4207{
4208 const unsigned int num_pci_slots = 0x20;
4209 unsigned int slot;
4210
4211 for (slot = 0; slot < num_pci_slots; slot++)
4212 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4213}
4214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4215DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4216DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4217DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4218DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4219DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4220
4221/*
4222 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4223 * associated not at the root bus, but at a bridge below. This quirk avoids
4224 * generating invalid DMA aliases.
4225 */
4226static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4227{
4228 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4229}
4230DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4231 quirk_bridge_cavm_thrx2_pcie_root);
4232DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4233 quirk_bridge_cavm_thrx2_pcie_root);
4234
4235/*
4236 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4237 * class code. Fix it.
4238 */
4239static void quirk_tw686x_class(struct pci_dev *pdev)
4240{
4241 u32 class = pdev->class;
4242
4243 /* Use "Multimedia controller" class */
4244 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4245 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4246 class, pdev->class);
4247}
4248DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4249 quirk_tw686x_class);
4250DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4251 quirk_tw686x_class);
4252DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4253 quirk_tw686x_class);
4254DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4255 quirk_tw686x_class);
4256
4257/*
4258 * Some devices have problems with Transaction Layer Packets with the Relaxed
4259 * Ordering Attribute set. Such devices should mark themselves and other
4260 * device drivers should check before sending TLPs with RO set.
4261 */
4262static void quirk_relaxedordering_disable(struct pci_dev *dev)
4263{
4264 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4265 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4266}
4267
4268/*
4269 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4270 * Complex have a Flow Control Credit issue which can cause performance
4271 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4272 */
4273DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4274 quirk_relaxedordering_disable);
4275DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4276 quirk_relaxedordering_disable);
4277DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4278 quirk_relaxedordering_disable);
4279DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4280 quirk_relaxedordering_disable);
4281DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4282 quirk_relaxedordering_disable);
4283DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4284 quirk_relaxedordering_disable);
4285DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4286 quirk_relaxedordering_disable);
4287DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4288 quirk_relaxedordering_disable);
4289DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4290 quirk_relaxedordering_disable);
4291DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4292 quirk_relaxedordering_disable);
4293DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4294 quirk_relaxedordering_disable);
4295DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4296 quirk_relaxedordering_disable);
4297DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4298 quirk_relaxedordering_disable);
4299DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4300 quirk_relaxedordering_disable);
4301DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4302 quirk_relaxedordering_disable);
4303DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4304 quirk_relaxedordering_disable);
4305DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4306 quirk_relaxedordering_disable);
4307DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4308 quirk_relaxedordering_disable);
4309DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4310 quirk_relaxedordering_disable);
4311DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4312 quirk_relaxedordering_disable);
4313DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4314 quirk_relaxedordering_disable);
4315DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4316 quirk_relaxedordering_disable);
4317DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4318 quirk_relaxedordering_disable);
4319DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4320 quirk_relaxedordering_disable);
4321DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4322 quirk_relaxedordering_disable);
4323DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4324 quirk_relaxedordering_disable);
4325DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4326 quirk_relaxedordering_disable);
4327DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4328 quirk_relaxedordering_disable);
4329
4330/*
4331 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4332 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4333 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4334 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4335 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4336 * November 10, 2010). As a result, on this platform we can't use Relaxed
4337 * Ordering for Upstream TLPs.
4338 */
4339DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4340 quirk_relaxedordering_disable);
4341DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4342 quirk_relaxedordering_disable);
4343DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4344 quirk_relaxedordering_disable);
4345
4346/*
4347 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4348 * values for the Attribute as were supplied in the header of the
4349 * corresponding Request, except as explicitly allowed when IDO is used."
4350 *
4351 * If a non-compliant device generates a completion with a different
4352 * attribute than the request, the receiver may accept it (which itself
4353 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4354 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4355 * device access timeout.
4356 *
4357 * If the non-compliant device generates completions with zero attributes
4358 * (instead of copying the attributes from the request), we can work around
4359 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4360 * upstream devices so they always generate requests with zero attributes.
4361 *
4362 * This affects other devices under the same Root Port, but since these
4363 * attributes are performance hints, there should be no functional problem.
4364 *
4365 * Note that Configuration Space accesses are never supposed to have TLP
4366 * Attributes, so we're safe waiting till after any Configuration Space
4367 * accesses to do the Root Port fixup.
4368 */
4369static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4370{
4371 struct pci_dev *root_port = pcie_find_root_port(pdev);
4372
4373 if (!root_port) {
4374 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4375 return;
4376 }
4377
4378 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4379 dev_name(&pdev->dev));
4380 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4381 PCI_EXP_DEVCTL_RELAX_EN |
4382 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4383}
4384
4385/*
4386 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4387 * Completion it generates.
4388 */
4389static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4390{
4391 /*
4392 * This mask/compare operation selects for Physical Function 4 on a
4393 * T5. We only need to fix up the Root Port once for any of the
4394 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4395 * 0x54xx so we use that one.
4396 */
4397 if ((pdev->device & 0xff00) == 0x5400)
4398 quirk_disable_root_port_attributes(pdev);
4399}
4400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4401 quirk_chelsio_T5_disable_root_port_attributes);
4402
4403/*
4404 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4405 * by a device
4406 * @acs_ctrl_req: Bitmask of desired ACS controls
4407 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4408 * the hardware design
4409 *
4410 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4411 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4412 * caller desires. Return 0 otherwise.
4413 */
4414static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4415{
4416 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4417 return 1;
4418 return 0;
4419}
4420
4421/*
4422 * AMD has indicated that the devices below do not support peer-to-peer
4423 * in any system where they are found in the southbridge with an AMD
4424 * IOMMU in the system. Multifunction devices that do not support
4425 * peer-to-peer between functions can claim to support a subset of ACS.
4426 * Such devices effectively enable request redirect (RR) and completion
4427 * redirect (CR) since all transactions are redirected to the upstream
4428 * root complex.
4429 *
4430 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4431 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4432 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4433 *
4434 * 1002:4385 SBx00 SMBus Controller
4435 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4436 * 1002:4383 SBx00 Azalia (Intel HDA)
4437 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4438 * 1002:4384 SBx00 PCI to PCI Bridge
4439 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4440 *
4441 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4442 *
4443 * 1022:780f [AMD] FCH PCI Bridge
4444 * 1022:7809 [AMD] FCH USB OHCI Controller
4445 */
4446static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4447{
4448#ifdef CONFIG_ACPI
4449 struct acpi_table_header *header = NULL;
4450 acpi_status status;
4451
4452 /* Targeting multifunction devices on the SB (appears on root bus) */
4453 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4454 return -ENODEV;
4455
4456 /* The IVRS table describes the AMD IOMMU */
4457 status = acpi_get_table("IVRS", 0, &header);
4458 if (ACPI_FAILURE(status))
4459 return -ENODEV;
4460
4461 acpi_put_table(header);
4462
4463 /* Filter out flags not applicable to multifunction */
4464 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4465
4466 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4467#else
4468 return -ENODEV;
4469#endif
4470}
4471
4472static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4473{
4474 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4475 return false;
4476
4477 switch (dev->device) {
4478 /*
4479 * Effectively selects all downstream ports for whole ThunderX1
4480 * (which represents 8 SoCs).
4481 */
4482 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4483 case 0xaf84: /* ThunderX2 */
4484 case 0xb884: /* ThunderX3 */
4485 return true;
4486 default:
4487 return false;
4488 }
4489}
4490
4491static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4492{
4493 if (!pci_quirk_cavium_acs_match(dev))
4494 return -ENOTTY;
4495
4496 /*
4497 * Cavium Root Ports don't advertise an ACS capability. However,
4498 * the RTL internally implements similar protection as if ACS had
4499 * Source Validation, Request Redirection, Completion Redirection,
4500 * and Upstream Forwarding features enabled. Assert that the
4501 * hardware implements and enables equivalent ACS functionality for
4502 * these flags.
4503 */
4504 return pci_acs_ctrl_enabled(acs_flags,
4505 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4506}
4507
4508static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4509{
4510 /*
4511 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4512 * transactions with others, allowing masking out these bits as if they
4513 * were unimplemented in the ACS capability.
4514 */
4515 return pci_acs_ctrl_enabled(acs_flags,
4516 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4517}
4518
4519/*
4520 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4521 * But the implementation could block peer-to-peer transactions between them
4522 * and provide ACS-like functionality.
4523 */
4524static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4525{
4526 if (!pci_is_pcie(dev) ||
4527 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4528 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4529 return -ENOTTY;
4530
4531 switch (dev->device) {
4532 case 0x0710 ... 0x071e:
4533 case 0x0721:
4534 case 0x0723 ... 0x0732:
4535 return pci_acs_ctrl_enabled(acs_flags,
4536 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4537 }
4538
4539 return false;
4540}
4541
4542/*
4543 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4544 * transactions and validate bus numbers in requests, but do not provide an
4545 * actual PCIe ACS capability. This is the list of device IDs known to fall
4546 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4547 */
4548static const u16 pci_quirk_intel_pch_acs_ids[] = {
4549 /* Ibexpeak PCH */
4550 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4551 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4552 /* Cougarpoint PCH */
4553 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4554 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4555 /* Pantherpoint PCH */
4556 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4557 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4558 /* Lynxpoint-H PCH */
4559 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4560 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4561 /* Lynxpoint-LP PCH */
4562 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4563 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4564 /* Wildcat PCH */
4565 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4566 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4567 /* Patsburg (X79) PCH */
4568 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4569 /* Wellsburg (X99) PCH */
4570 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4571 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4572 /* Lynx Point (9 series) PCH */
4573 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4574};
4575
4576static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4577{
4578 int i;
4579
4580 /* Filter out a few obvious non-matches first */
4581 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4582 return false;
4583
4584 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4585 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4586 return true;
4587
4588 return false;
4589}
4590
4591static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4592{
4593 if (!pci_quirk_intel_pch_acs_match(dev))
4594 return -ENOTTY;
4595
4596 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4597 return pci_acs_ctrl_enabled(acs_flags,
4598 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4599
4600 return pci_acs_ctrl_enabled(acs_flags, 0);
4601}
4602
4603/*
4604 * These QCOM Root Ports do provide ACS-like features to disable peer
4605 * transactions and validate bus numbers in requests, but do not provide an
4606 * actual PCIe ACS capability. Hardware supports source validation but it
4607 * will report the issue as Completer Abort instead of ACS Violation.
4608 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4609 * Complex with unique segment numbers. It is not possible for one Root
4610 * Port to pass traffic to another Root Port. All PCIe transactions are
4611 * terminated inside the Root Port.
4612 */
4613static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4614{
4615 return pci_acs_ctrl_enabled(acs_flags,
4616 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4617}
4618
4619/*
4620 * Each of these NXP Root Ports is in a Root Complex with a unique segment
4621 * number and does provide isolation features to disable peer transactions
4622 * and validate bus numbers in requests, but does not provide an ACS
4623 * capability.
4624 */
4625static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4626{
4627 return pci_acs_ctrl_enabled(acs_flags,
4628 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4629}
4630
4631static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4632{
4633 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4634 return -ENOTTY;
4635
4636 /*
4637 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4638 * but do include ACS-like functionality. The hardware doesn't support
4639 * peer-to-peer transactions via the root port and each has a unique
4640 * segment number.
4641 *
4642 * Additionally, the root ports cannot send traffic to each other.
4643 */
4644 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4645
4646 return acs_flags ? 0 : 1;
4647}
4648
4649/*
4650 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4651 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4652 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4653 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4654 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4655 * control register is at offset 8 instead of 6 and we should probably use
4656 * dword accesses to them. This applies to the following PCI Device IDs, as
4657 * found in volume 1 of the datasheet[2]:
4658 *
4659 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4660 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4661 *
4662 * N.B. This doesn't fix what lspci shows.
4663 *
4664 * The 100 series chipset specification update includes this as errata #23[3].
4665 *
4666 * The 200 series chipset (Union Point) has the same bug according to the
4667 * specification update (Intel 200 Series Chipset Family Platform Controller
4668 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4669 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4670 * chipset include:
4671 *
4672 * 0xa290-0xa29f PCI Express Root port #{0-16}
4673 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4674 *
4675 * Mobile chipsets are also affected, 7th & 8th Generation
4676 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4677 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4678 * Processor Family I/O for U Quad Core Platforms Specification Update,
4679 * August 2017, Revision 002, Document#: 334660-002)[6]
4680 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4681 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4682 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4683 *
4684 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4685 *
4686 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4687 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4688 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4689 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4690 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4691 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4692 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4693 */
4694static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4695{
4696 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4697 return false;
4698
4699 switch (dev->device) {
4700 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4701 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4702 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4703 return true;
4704 }
4705
4706 return false;
4707}
4708
4709#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4710
4711static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4712{
4713 int pos;
4714 u32 cap, ctrl;
4715
4716 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4717 return -ENOTTY;
4718
4719 pos = dev->acs_cap;
4720 if (!pos)
4721 return -ENOTTY;
4722
4723 /* see pci_acs_flags_enabled() */
4724 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4725 acs_flags &= (cap | PCI_ACS_EC);
4726
4727 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4728
4729 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4730}
4731
4732static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4733{
4734 /*
4735 * SV, TB, and UF are not relevant to multifunction endpoints.
4736 *
4737 * Multifunction devices are only required to implement RR, CR, and DT
4738 * in their ACS capability if they support peer-to-peer transactions.
4739 * Devices matching this quirk have been verified by the vendor to not
4740 * perform peer-to-peer with other functions, allowing us to mask out
4741 * these bits as if they were unimplemented in the ACS capability.
4742 */
4743 return pci_acs_ctrl_enabled(acs_flags,
4744 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4745 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4746}
4747
4748static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4749{
4750 /*
4751 * Intel RCiEP's are required to allow p2p only on translated
4752 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4753 * "Root-Complex Peer to Peer Considerations".
4754 */
4755 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4756 return -ENOTTY;
4757
4758 return pci_acs_ctrl_enabled(acs_flags,
4759 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4760}
4761
4762static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4763{
4764 /*
4765 * iProc PAXB Root Ports don't advertise an ACS capability, but
4766 * they do not allow peer-to-peer transactions between Root Ports.
4767 * Allow each Root Port to be in a separate IOMMU group by masking
4768 * SV/RR/CR/UF bits.
4769 */
4770 return pci_acs_ctrl_enabled(acs_flags,
4771 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4772}
4773
4774static const struct pci_dev_acs_enabled {
4775 u16 vendor;
4776 u16 device;
4777 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4778} pci_dev_acs_enabled[] = {
4779 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4780 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4781 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4782 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4783 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4784 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4785 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4786 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4787 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4788 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4789 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4790 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4791 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4792 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4793 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4794 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4795 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4796 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4797 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4798 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4799 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4800 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4801 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4802 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4803 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4804 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4805 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4806 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4807 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4808 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4809 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4810 /* 82580 */
4811 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4812 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4813 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4814 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4815 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4816 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4817 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4818 /* 82576 */
4819 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4820 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4821 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4822 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4823 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4824 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4825 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4826 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4827 /* 82575 */
4828 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4829 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4830 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4831 /* I350 */
4832 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4833 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4834 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4835 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4836 /* 82571 (Quads omitted due to non-ACS switch) */
4837 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4838 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4839 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4840 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4841 /* I219 */
4842 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4843 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4844 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4845 /* QCOM QDF2xxx root ports */
4846 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4847 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4848 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4849 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4850 /* Intel PCH root ports */
4851 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4852 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4853 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4854 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4855 /* Cavium ThunderX */
4856 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4857 /* Cavium multi-function devices */
4858 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
4859 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
4860 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
4861 /* APM X-Gene */
4862 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4863 /* Ampere Computing */
4864 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4865 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4866 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4867 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4868 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4869 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4870 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4871 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4872 /* Broadcom multi-function device */
4873 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4874 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4875 /* Amazon Annapurna Labs */
4876 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4877 /* Zhaoxin multi-function devices */
4878 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4879 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4880 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4881 /* NXP root ports, xx=16, 12, or 08 cores */
4882 /* LX2xx0A : without security features + CAN-FD */
4883 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
4884 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
4885 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
4886 /* LX2xx0C : security features + CAN-FD */
4887 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
4888 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
4889 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
4890 /* LX2xx0E : security features + CAN */
4891 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
4892 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
4893 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
4894 /* LX2xx0N : without security features + CAN */
4895 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
4896 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
4897 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
4898 /* LX2xx2A : without security features + CAN-FD */
4899 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
4900 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
4901 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
4902 /* LX2xx2C : security features + CAN-FD */
4903 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
4904 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
4905 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
4906 /* LX2xx2E : security features + CAN */
4907 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
4908 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
4909 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
4910 /* LX2xx2N : without security features + CAN */
4911 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
4912 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
4913 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
4914 /* Zhaoxin Root/Downstream Ports */
4915 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4916 { 0 }
4917};
4918
4919/*
4920 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4921 * @dev: PCI device
4922 * @acs_flags: Bitmask of desired ACS controls
4923 *
4924 * Returns:
4925 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4926 * device provides the desired controls
4927 * 0: Device does not provide all the desired controls
4928 * >0: Device provides all the controls in @acs_flags
4929 */
4930int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4931{
4932 const struct pci_dev_acs_enabled *i;
4933 int ret;
4934
4935 /*
4936 * Allow devices that do not expose standard PCIe ACS capabilities
4937 * or control to indicate their support here. Multi-function express
4938 * devices which do not allow internal peer-to-peer between functions,
4939 * but do not implement PCIe ACS may wish to return true here.
4940 */
4941 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4942 if ((i->vendor == dev->vendor ||
4943 i->vendor == (u16)PCI_ANY_ID) &&
4944 (i->device == dev->device ||
4945 i->device == (u16)PCI_ANY_ID)) {
4946 ret = i->acs_enabled(dev, acs_flags);
4947 if (ret >= 0)
4948 return ret;
4949 }
4950 }
4951
4952 return -ENOTTY;
4953}
4954
4955/* Config space offset of Root Complex Base Address register */
4956#define INTEL_LPC_RCBA_REG 0xf0
4957/* 31:14 RCBA address */
4958#define INTEL_LPC_RCBA_MASK 0xffffc000
4959/* RCBA Enable */
4960#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4961
4962/* Backbone Scratch Pad Register */
4963#define INTEL_BSPR_REG 0x1104
4964/* Backbone Peer Non-Posted Disable */
4965#define INTEL_BSPR_REG_BPNPD (1 << 8)
4966/* Backbone Peer Posted Disable */
4967#define INTEL_BSPR_REG_BPPD (1 << 9)
4968
4969/* Upstream Peer Decode Configuration Register */
4970#define INTEL_UPDCR_REG 0x1014
4971/* 5:0 Peer Decode Enable bits */
4972#define INTEL_UPDCR_REG_MASK 0x3f
4973
4974static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4975{
4976 u32 rcba, bspr, updcr;
4977 void __iomem *rcba_mem;
4978
4979 /*
4980 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4981 * are D28:F* and therefore get probed before LPC, thus we can't
4982 * use pci_get_slot()/pci_read_config_dword() here.
4983 */
4984 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4985 INTEL_LPC_RCBA_REG, &rcba);
4986 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4987 return -EINVAL;
4988
4989 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
4990 PAGE_ALIGN(INTEL_UPDCR_REG));
4991 if (!rcba_mem)
4992 return -ENOMEM;
4993
4994 /*
4995 * The BSPR can disallow peer cycles, but it's set by soft strap and
4996 * therefore read-only. If both posted and non-posted peer cycles are
4997 * disallowed, we're ok. If either are allowed, then we need to use
4998 * the UPDCR to disable peer decodes for each port. This provides the
4999 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5000 */
5001 bspr = readl(rcba_mem + INTEL_BSPR_REG);
5002 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5003 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5004 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5005 if (updcr & INTEL_UPDCR_REG_MASK) {
5006 pci_info(dev, "Disabling UPDCR peer decodes\n");
5007 updcr &= ~INTEL_UPDCR_REG_MASK;
5008 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5009 }
5010 }
5011
5012 iounmap(rcba_mem);
5013 return 0;
5014}
5015
5016/* Miscellaneous Port Configuration register */
5017#define INTEL_MPC_REG 0xd8
5018/* MPC: Invalid Receive Bus Number Check Enable */
5019#define INTEL_MPC_REG_IRBNCE (1 << 26)
5020
5021static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5022{
5023 u32 mpc;
5024
5025 /*
5026 * When enabled, the IRBNCE bit of the MPC register enables the
5027 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5028 * ensures that requester IDs fall within the bus number range
5029 * of the bridge. Enable if not already.
5030 */
5031 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5032 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5033 pci_info(dev, "Enabling MPC IRBNCE\n");
5034 mpc |= INTEL_MPC_REG_IRBNCE;
5035 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5036 }
5037}
5038
5039/*
5040 * Currently this quirk does the equivalent of
5041 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5042 *
5043 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5044 * if dev->external_facing || dev->untrusted
5045 */
5046static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5047{
5048 if (!pci_quirk_intel_pch_acs_match(dev))
5049 return -ENOTTY;
5050
5051 if (pci_quirk_enable_intel_lpc_acs(dev)) {
5052 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5053 return 0;
5054 }
5055
5056 pci_quirk_enable_intel_rp_mpc_acs(dev);
5057
5058 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5059
5060 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5061
5062 return 0;
5063}
5064
5065static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5066{
5067 int pos;
5068 u32 cap, ctrl;
5069
5070 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5071 return -ENOTTY;
5072
5073 pos = dev->acs_cap;
5074 if (!pos)
5075 return -ENOTTY;
5076
5077 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5078 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5079
5080 ctrl |= (cap & PCI_ACS_SV);
5081 ctrl |= (cap & PCI_ACS_RR);
5082 ctrl |= (cap & PCI_ACS_CR);
5083 ctrl |= (cap & PCI_ACS_UF);
5084
5085 if (dev->external_facing || dev->untrusted)
5086 ctrl |= (cap & PCI_ACS_TB);
5087
5088 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5089
5090 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5091
5092 return 0;
5093}
5094
5095static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5096{
5097 int pos;
5098 u32 cap, ctrl;
5099
5100 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5101 return -ENOTTY;
5102
5103 pos = dev->acs_cap;
5104 if (!pos)
5105 return -ENOTTY;
5106
5107 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5108 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5109
5110 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5111
5112 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5113
5114 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5115
5116 return 0;
5117}
5118
5119static const struct pci_dev_acs_ops {
5120 u16 vendor;
5121 u16 device;
5122 int (*enable_acs)(struct pci_dev *dev);
5123 int (*disable_acs_redir)(struct pci_dev *dev);
5124} pci_dev_acs_ops[] = {
5125 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5126 .enable_acs = pci_quirk_enable_intel_pch_acs,
5127 },
5128 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5129 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5130 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5131 },
5132};
5133
5134int pci_dev_specific_enable_acs(struct pci_dev *dev)
5135{
5136 const struct pci_dev_acs_ops *p;
5137 int i, ret;
5138
5139 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5140 p = &pci_dev_acs_ops[i];
5141 if ((p->vendor == dev->vendor ||
5142 p->vendor == (u16)PCI_ANY_ID) &&
5143 (p->device == dev->device ||
5144 p->device == (u16)PCI_ANY_ID) &&
5145 p->enable_acs) {
5146 ret = p->enable_acs(dev);
5147 if (ret >= 0)
5148 return ret;
5149 }
5150 }
5151
5152 return -ENOTTY;
5153}
5154
5155int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5156{
5157 const struct pci_dev_acs_ops *p;
5158 int i, ret;
5159
5160 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5161 p = &pci_dev_acs_ops[i];
5162 if ((p->vendor == dev->vendor ||
5163 p->vendor == (u16)PCI_ANY_ID) &&
5164 (p->device == dev->device ||
5165 p->device == (u16)PCI_ANY_ID) &&
5166 p->disable_acs_redir) {
5167 ret = p->disable_acs_redir(dev);
5168 if (ret >= 0)
5169 return ret;
5170 }
5171 }
5172
5173 return -ENOTTY;
5174}
5175
5176/*
5177 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5178 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5179 * Next Capability pointer in the MSI Capability Structure should point to
5180 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5181 * the list.
5182 */
5183static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5184{
5185 int pos, i = 0;
5186 u8 next_cap;
5187 u16 reg16, *cap;
5188 struct pci_cap_saved_state *state;
5189
5190 /* Bail if the hardware bug is fixed */
5191 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5192 return;
5193
5194 /* Bail if MSI Capability Structure is not found for some reason */
5195 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5196 if (!pos)
5197 return;
5198
5199 /*
5200 * Bail if Next Capability pointer in the MSI Capability Structure
5201 * is not the expected incorrect 0x00.
5202 */
5203 pci_read_config_byte(pdev, pos + 1, &next_cap);
5204 if (next_cap)
5205 return;
5206
5207 /*
5208 * PCIe Capability Structure is expected to be at 0x50 and should
5209 * terminate the list (Next Capability pointer is 0x00). Verify
5210 * Capability Id and Next Capability pointer is as expected.
5211 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5212 * to correctly set kernel data structures which have already been
5213 * set incorrectly due to the hardware bug.
5214 */
5215 pos = 0x50;
5216 pci_read_config_word(pdev, pos, ®16);
5217 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5218 u32 status;
5219#ifndef PCI_EXP_SAVE_REGS
5220#define PCI_EXP_SAVE_REGS 7
5221#endif
5222 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5223
5224 pdev->pcie_cap = pos;
5225 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5226 pdev->pcie_flags_reg = reg16;
5227 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5228 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5229
5230 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5231 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5232 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5233 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5234
5235 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5236 return;
5237
5238 /* Save PCIe cap */
5239 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5240 if (!state)
5241 return;
5242
5243 state->cap.cap_nr = PCI_CAP_ID_EXP;
5244 state->cap.cap_extended = 0;
5245 state->cap.size = size;
5246 cap = (u16 *)&state->cap.data[0];
5247 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5248 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5249 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5250 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5251 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5252 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5253 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5254 hlist_add_head(&state->next, &pdev->saved_cap_space);
5255 }
5256}
5257DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5258
5259/*
5260 * FLR may cause the following to devices to hang:
5261 *
5262 * AMD Starship/Matisse HD Audio Controller 0x1487
5263 * AMD Starship USB 3.0 Host Controller 0x148c
5264 * AMD Matisse USB 3.0 Host Controller 0x149c
5265 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5266 * Intel 82579V Gigabit Ethernet Controller 0x1503
5267 *
5268 */
5269static void quirk_no_flr(struct pci_dev *dev)
5270{
5271 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5272}
5273DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5274DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5275DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5276DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5277DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5278
5279static void quirk_no_ext_tags(struct pci_dev *pdev)
5280{
5281 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5282
5283 if (!bridge)
5284 return;
5285
5286 bridge->no_ext_tags = 1;
5287 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5288
5289 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5290}
5291DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5292DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5293DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5294DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5295DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5296DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5297DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5298
5299#ifdef CONFIG_PCI_ATS
5300/*
5301 * Some devices require additional driver setup to enable ATS. Don't use
5302 * ATS for those devices as ATS will be enabled before the driver has had a
5303 * chance to load and configure the device.
5304 */
5305static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5306{
5307 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5308 (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
5309 (pdev->device == 0x7341 && pdev->revision != 0x00))
5310 return;
5311
5312 if (pdev->device == 0x15d8) {
5313 if (pdev->revision == 0xcf &&
5314 pdev->subsystem_vendor == 0xea50 &&
5315 (pdev->subsystem_device == 0xce19 ||
5316 pdev->subsystem_device == 0xcc10 ||
5317 pdev->subsystem_device == 0xcc08))
5318 goto no_ats;
5319 else
5320 return;
5321 }
5322
5323no_ats:
5324 pci_info(pdev, "disabling ATS\n");
5325 pdev->ats_cap = 0;
5326}
5327
5328/* AMD Stoney platform GPU */
5329DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5330/* AMD Iceland dGPU */
5331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5332/* AMD Navi10 dGPU */
5333DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5334/* AMD Navi14 dGPU */
5335DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5337/* AMD Raven platform iGPU */
5338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5339#endif /* CONFIG_PCI_ATS */
5340
5341/* Freescale PCIe doesn't support MSI in RC mode */
5342static void quirk_fsl_no_msi(struct pci_dev *pdev)
5343{
5344 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5345 pdev->no_msi = 1;
5346}
5347DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5348
5349/*
5350 * Although not allowed by the spec, some multi-function devices have
5351 * dependencies of one function (consumer) on another (supplier). For the
5352 * consumer to work in D0, the supplier must also be in D0. Create a
5353 * device link from the consumer to the supplier to enforce this
5354 * dependency. Runtime PM is allowed by default on the consumer to prevent
5355 * it from permanently keeping the supplier awake.
5356 */
5357static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5358 unsigned int supplier, unsigned int class,
5359 unsigned int class_shift)
5360{
5361 struct pci_dev *supplier_pdev;
5362
5363 if (PCI_FUNC(pdev->devfn) != consumer)
5364 return;
5365
5366 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5367 pdev->bus->number,
5368 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5369 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5370 pci_dev_put(supplier_pdev);
5371 return;
5372 }
5373
5374 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5375 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5376 pci_info(pdev, "D0 power state depends on %s\n",
5377 pci_name(supplier_pdev));
5378 else
5379 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5380 pci_name(supplier_pdev));
5381
5382 pm_runtime_allow(&pdev->dev);
5383 pci_dev_put(supplier_pdev);
5384}
5385
5386/*
5387 * Create device link for GPUs with integrated HDA controller for streaming
5388 * audio to attached displays.
5389 */
5390static void quirk_gpu_hda(struct pci_dev *hda)
5391{
5392 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5393}
5394DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5395 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5396DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5397 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5398DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5399 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5400
5401/*
5402 * Create device link for GPUs with integrated USB xHCI Host
5403 * controller to VGA.
5404 */
5405static void quirk_gpu_usb(struct pci_dev *usb)
5406{
5407 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5408}
5409DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5410 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5411DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5412 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5413
5414/*
5415 * Create device link for GPUs with integrated Type-C UCSI controller
5416 * to VGA. Currently there is no class code defined for UCSI device over PCI
5417 * so using UNKNOWN class for now and it will be updated when UCSI
5418 * over PCI gets a class code.
5419 */
5420#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5421static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5422{
5423 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5424}
5425DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5426 PCI_CLASS_SERIAL_UNKNOWN, 8,
5427 quirk_gpu_usb_typec_ucsi);
5428DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5429 PCI_CLASS_SERIAL_UNKNOWN, 8,
5430 quirk_gpu_usb_typec_ucsi);
5431
5432/*
5433 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5434 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5435 */
5436static void quirk_nvidia_hda(struct pci_dev *gpu)
5437{
5438 u8 hdr_type;
5439 u32 val;
5440
5441 /* There was no integrated HDA controller before MCP89 */
5442 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5443 return;
5444
5445 /* Bit 25 at offset 0x488 enables the HDA controller */
5446 pci_read_config_dword(gpu, 0x488, &val);
5447 if (val & BIT(25))
5448 return;
5449
5450 pci_info(gpu, "Enabling HDA controller\n");
5451 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5452
5453 /* The GPU becomes a multi-function device when the HDA is enabled */
5454 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5455 gpu->multifunction = !!(hdr_type & 0x80);
5456}
5457DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5458 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5459DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5460 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5461
5462/*
5463 * Some IDT switches incorrectly flag an ACS Source Validation error on
5464 * completions for config read requests even though PCIe r4.0, sec
5465 * 6.12.1.1, says that completions are never affected by ACS Source
5466 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5467 *
5468 * Item #36 - Downstream port applies ACS Source Validation to Completions
5469 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5470 * completions are never affected by ACS Source Validation. However,
5471 * completions received by a downstream port of the PCIe switch from a
5472 * device that has not yet captured a PCIe bus number are incorrectly
5473 * dropped by ACS Source Validation by the switch downstream port.
5474 *
5475 * The workaround suggested by IDT is to issue a config write to the
5476 * downstream device before issuing the first config read. This allows the
5477 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5478 * sec 2.2.9), thus avoiding the ACS error on the completion.
5479 *
5480 * However, we don't know when the device is ready to accept the config
5481 * write, so we do config reads until we receive a non-Config Request Retry
5482 * Status, then do the config write.
5483 *
5484 * To avoid hitting the erratum when doing the config reads, we disable ACS
5485 * SV around this process.
5486 */
5487int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5488{
5489 int pos;
5490 u16 ctrl = 0;
5491 bool found;
5492 struct pci_dev *bridge = bus->self;
5493
5494 pos = bridge->acs_cap;
5495
5496 /* Disable ACS SV before initial config reads */
5497 if (pos) {
5498 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5499 if (ctrl & PCI_ACS_SV)
5500 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5501 ctrl & ~PCI_ACS_SV);
5502 }
5503
5504 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5505
5506 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5507 if (found)
5508 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5509
5510 /* Re-enable ACS_SV if it was previously enabled */
5511 if (ctrl & PCI_ACS_SV)
5512 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5513
5514 return found;
5515}
5516
5517/*
5518 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5519 * NT endpoints via the internal switch fabric. These IDs replace the
5520 * originating requestor ID TLPs which access host memory on peer NTB
5521 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5522 * to permit access when the IOMMU is turned on.
5523 */
5524static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5525{
5526 void __iomem *mmio;
5527 struct ntb_info_regs __iomem *mmio_ntb;
5528 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5529 u64 partition_map;
5530 u8 partition;
5531 int pp;
5532
5533 if (pci_enable_device(pdev)) {
5534 pci_err(pdev, "Cannot enable Switchtec device\n");
5535 return;
5536 }
5537
5538 mmio = pci_iomap(pdev, 0, 0);
5539 if (mmio == NULL) {
5540 pci_disable_device(pdev);
5541 pci_err(pdev, "Cannot iomap Switchtec device\n");
5542 return;
5543 }
5544
5545 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5546
5547 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5548 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5549
5550 partition = ioread8(&mmio_ntb->partition_id);
5551
5552 partition_map = ioread32(&mmio_ntb->ep_map);
5553 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5554 partition_map &= ~(1ULL << partition);
5555
5556 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5557 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5558 u32 table_sz = 0;
5559 int te;
5560
5561 if (!(partition_map & (1ULL << pp)))
5562 continue;
5563
5564 pci_dbg(pdev, "Processing partition %d\n", pp);
5565
5566 mmio_peer_ctrl = &mmio_ctrl[pp];
5567
5568 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5569 if (!table_sz) {
5570 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5571 continue;
5572 }
5573
5574 if (table_sz > 512) {
5575 pci_warn(pdev,
5576 "Invalid Switchtec partition %d table_sz %d\n",
5577 pp, table_sz);
5578 continue;
5579 }
5580
5581 for (te = 0; te < table_sz; te++) {
5582 u32 rid_entry;
5583 u8 devfn;
5584
5585 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5586 devfn = (rid_entry >> 1) & 0xFF;
5587 pci_dbg(pdev,
5588 "Aliasing Partition %d Proxy ID %02x.%d\n",
5589 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5590 pci_add_dma_alias(pdev, devfn, 1);
5591 }
5592 }
5593
5594 pci_iounmap(pdev, mmio);
5595 pci_disable_device(pdev);
5596}
5597#define SWITCHTEC_QUIRK(vid) \
5598 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5599 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5600
5601SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5602SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5603SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5604SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5605SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5606SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5607SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5608SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5609SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5610SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5611SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5612SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5613SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5614SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5615SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5616SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5617SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5618SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5619SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5620SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5621SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5622SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5623SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5624SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5625SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5626SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5627SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5628SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5629SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5630SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5631SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5632SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5633SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5634SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5635SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5636SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5637SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5638SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5639SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5640SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5641SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5642SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5643SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5644SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5645SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5646SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5647SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5648SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5649
5650/*
5651 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5652 * These IDs are used to forward responses to the originator on the other
5653 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5654 * the IOMMU is turned on.
5655 */
5656static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5657{
5658 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5659 /* PLX NTB may use all 256 devfns */
5660 pci_add_dma_alias(pdev, 0, 256);
5661}
5662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5664
5665/*
5666 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5667 * not always reset the secondary Nvidia GPU between reboots if the system
5668 * is configured to use Hybrid Graphics mode. This results in the GPU
5669 * being left in whatever state it was in during the *previous* boot, which
5670 * causes spurious interrupts from the GPU, which in turn causes us to
5671 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5672 * this also completely breaks nouveau.
5673 *
5674 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5675 * clean state and fixes all these issues.
5676 *
5677 * When the machine is configured in Dedicated display mode, the issue
5678 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5679 * mode, so we can detect that and avoid resetting it.
5680 */
5681static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5682{
5683 void __iomem *map;
5684 int ret;
5685
5686 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5687 pdev->subsystem_device != 0x222e ||
5688 !pdev->reset_fn)
5689 return;
5690
5691 if (pci_enable_device_mem(pdev))
5692 return;
5693
5694 /*
5695 * Based on nvkm_device_ctor() in
5696 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5697 */
5698 map = pci_iomap(pdev, 0, 0x23000);
5699 if (!map) {
5700 pci_err(pdev, "Can't map MMIO space\n");
5701 goto out_disable;
5702 }
5703
5704 /*
5705 * Make sure the GPU looks like it's been POSTed before resetting
5706 * it.
5707 */
5708 if (ioread32(map + 0x2240c) & 0x2) {
5709 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5710 ret = pci_reset_bus(pdev);
5711 if (ret < 0)
5712 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5713 }
5714
5715 iounmap(map);
5716out_disable:
5717 pci_disable_device(pdev);
5718}
5719DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5720 PCI_CLASS_DISPLAY_VGA, 8,
5721 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5722
5723/*
5724 * Device [1b21:2142]
5725 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5726 */
5727static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5728{
5729 pci_info(dev, "PME# does not work under D0, disabling it\n");
5730 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5731}
5732DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5733
5734/*
5735 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5736 *
5737 * These devices advertise PME# support in all power states but don't
5738 * reliably assert it.
5739 *
5740 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5741 * says "The MSI Function is not implemented on this device" in chapters
5742 * 7.3.27, 7.3.29-7.3.31.
5743 */
5744static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5745{
5746#ifdef CONFIG_PCI_MSI
5747 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5748 dev->no_msi = 1;
5749#endif
5750 pci_info(dev, "PME# is unreliable, disabling it\n");
5751 dev->pme_support = 0;
5752}
5753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5754DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5755
5756static void apex_pci_fixup_class(struct pci_dev *pdev)
5757{
5758 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5759}
5760DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5761 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);