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1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12#include <linux/export.h>
13
14#include <asm/apic.h>
15#include <asm/io_apic.h>
16#include <asm/irq.h>
17#include <asm/idle.h>
18#include <asm/mce.h>
19#include <asm/hw_irq.h>
20
21atomic_t irq_err_count;
22
23/* Function pointer for generic interrupt vector handling */
24void (*x86_platform_ipi_callback)(void) = NULL;
25
26/*
27 * 'what should we do if we get a hw irq event on an illegal vector'.
28 * each architecture has to answer this themselves.
29 */
30void ack_bad_irq(unsigned int irq)
31{
32 if (printk_ratelimit())
33 pr_err("unexpected IRQ trap at vector %02x\n", irq);
34
35 /*
36 * Currently unexpected vectors happen only on SMP and APIC.
37 * We _must_ ack these because every local APIC has only N
38 * irq slots per priority level, and a 'hanging, unacked' IRQ
39 * holds up an irq slot - in excessive cases (when multiple
40 * unexpected vectors occur) that might lock up the APIC
41 * completely.
42 * But only ack when the APIC is enabled -AK
43 */
44 ack_APIC_irq();
45}
46
47#define irq_stats(x) (&per_cpu(irq_stat, x))
48/*
49 * /proc/interrupts printing for arch specific interrupts
50 */
51int arch_show_interrupts(struct seq_file *p, int prec)
52{
53 int j;
54
55 seq_printf(p, "%*s: ", prec, "NMI");
56 for_each_online_cpu(j)
57 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
58 seq_printf(p, " Non-maskable interrupts\n");
59#ifdef CONFIG_X86_LOCAL_APIC
60 seq_printf(p, "%*s: ", prec, "LOC");
61 for_each_online_cpu(j)
62 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
63 seq_printf(p, " Local timer interrupts\n");
64
65 seq_printf(p, "%*s: ", prec, "SPU");
66 for_each_online_cpu(j)
67 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
68 seq_printf(p, " Spurious interrupts\n");
69 seq_printf(p, "%*s: ", prec, "PMI");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
72 seq_printf(p, " Performance monitoring interrupts\n");
73 seq_printf(p, "%*s: ", prec, "IWI");
74 for_each_online_cpu(j)
75 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
76 seq_printf(p, " IRQ work interrupts\n");
77 seq_printf(p, "%*s: ", prec, "RTR");
78 for_each_online_cpu(j)
79 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
80 seq_printf(p, " APIC ICR read retries\n");
81#endif
82 if (x86_platform_ipi_callback) {
83 seq_printf(p, "%*s: ", prec, "PLT");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
86 seq_printf(p, " Platform interrupts\n");
87 }
88#ifdef CONFIG_SMP
89 seq_printf(p, "%*s: ", prec, "RES");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
92 seq_printf(p, " Rescheduling interrupts\n");
93 seq_printf(p, "%*s: ", prec, "CAL");
94 for_each_online_cpu(j)
95 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
96 seq_printf(p, " Function call interrupts\n");
97 seq_printf(p, "%*s: ", prec, "TLB");
98 for_each_online_cpu(j)
99 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
100 seq_printf(p, " TLB shootdowns\n");
101#endif
102#ifdef CONFIG_X86_THERMAL_VECTOR
103 seq_printf(p, "%*s: ", prec, "TRM");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
106 seq_printf(p, " Thermal event interrupts\n");
107#endif
108#ifdef CONFIG_X86_MCE_THRESHOLD
109 seq_printf(p, "%*s: ", prec, "THR");
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
112 seq_printf(p, " Threshold APIC interrupts\n");
113#endif
114#ifdef CONFIG_X86_MCE
115 seq_printf(p, "%*s: ", prec, "MCE");
116 for_each_online_cpu(j)
117 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
118 seq_printf(p, " Machine check exceptions\n");
119 seq_printf(p, "%*s: ", prec, "MCP");
120 for_each_online_cpu(j)
121 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
122 seq_printf(p, " Machine check polls\n");
123#endif
124 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
125#if defined(CONFIG_X86_IO_APIC)
126 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
127#endif
128 return 0;
129}
130
131/*
132 * /proc/stat helpers
133 */
134u64 arch_irq_stat_cpu(unsigned int cpu)
135{
136 u64 sum = irq_stats(cpu)->__nmi_count;
137
138#ifdef CONFIG_X86_LOCAL_APIC
139 sum += irq_stats(cpu)->apic_timer_irqs;
140 sum += irq_stats(cpu)->irq_spurious_count;
141 sum += irq_stats(cpu)->apic_perf_irqs;
142 sum += irq_stats(cpu)->apic_irq_work_irqs;
143 sum += irq_stats(cpu)->icr_read_retry_count;
144#endif
145 if (x86_platform_ipi_callback)
146 sum += irq_stats(cpu)->x86_platform_ipis;
147#ifdef CONFIG_SMP
148 sum += irq_stats(cpu)->irq_resched_count;
149 sum += irq_stats(cpu)->irq_call_count;
150 sum += irq_stats(cpu)->irq_tlb_count;
151#endif
152#ifdef CONFIG_X86_THERMAL_VECTOR
153 sum += irq_stats(cpu)->irq_thermal_count;
154#endif
155#ifdef CONFIG_X86_MCE_THRESHOLD
156 sum += irq_stats(cpu)->irq_threshold_count;
157#endif
158#ifdef CONFIG_X86_MCE
159 sum += per_cpu(mce_exception_count, cpu);
160 sum += per_cpu(mce_poll_count, cpu);
161#endif
162 return sum;
163}
164
165u64 arch_irq_stat(void)
166{
167 u64 sum = atomic_read(&irq_err_count);
168
169#ifdef CONFIG_X86_IO_APIC
170 sum += atomic_read(&irq_mis_count);
171#endif
172 return sum;
173}
174
175
176/*
177 * do_IRQ handles all normal device IRQ's (the special
178 * SMP cross-CPU interrupts have their own specific
179 * handlers).
180 */
181unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
182{
183 struct pt_regs *old_regs = set_irq_regs(regs);
184
185 /* high bit used in ret_from_ code */
186 unsigned vector = ~regs->orig_ax;
187 unsigned irq;
188
189 irq_enter();
190 exit_idle();
191
192 irq = __this_cpu_read(vector_irq[vector]);
193
194 if (!handle_irq(irq, regs)) {
195 ack_APIC_irq();
196
197 if (printk_ratelimit())
198 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
199 __func__, smp_processor_id(), vector, irq);
200 }
201
202 irq_exit();
203
204 set_irq_regs(old_regs);
205 return 1;
206}
207
208/*
209 * Handler for X86_PLATFORM_IPI_VECTOR.
210 */
211void smp_x86_platform_ipi(struct pt_regs *regs)
212{
213 struct pt_regs *old_regs = set_irq_regs(regs);
214
215 ack_APIC_irq();
216
217 irq_enter();
218
219 exit_idle();
220
221 inc_irq_stat(x86_platform_ipis);
222
223 if (x86_platform_ipi_callback)
224 x86_platform_ipi_callback();
225
226 irq_exit();
227
228 set_irq_regs(old_regs);
229}
230
231EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
232
233#ifdef CONFIG_HOTPLUG_CPU
234/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
235void fixup_irqs(void)
236{
237 unsigned int irq, vector;
238 static int warned;
239 struct irq_desc *desc;
240 struct irq_data *data;
241 struct irq_chip *chip;
242
243 for_each_irq_desc(irq, desc) {
244 int break_affinity = 0;
245 int set_affinity = 1;
246 const struct cpumask *affinity;
247
248 if (!desc)
249 continue;
250 if (irq == 2)
251 continue;
252
253 /* interrupt's are disabled at this point */
254 raw_spin_lock(&desc->lock);
255
256 data = irq_desc_get_irq_data(desc);
257 affinity = data->affinity;
258 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
259 cpumask_subset(affinity, cpu_online_mask)) {
260 raw_spin_unlock(&desc->lock);
261 continue;
262 }
263
264 /*
265 * Complete the irq move. This cpu is going down and for
266 * non intr-remapping case, we can't wait till this interrupt
267 * arrives at this cpu before completing the irq move.
268 */
269 irq_force_complete_move(irq);
270
271 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
272 break_affinity = 1;
273 affinity = cpu_all_mask;
274 }
275
276 chip = irq_data_get_irq_chip(data);
277 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
278 chip->irq_mask(data);
279
280 if (chip->irq_set_affinity)
281 chip->irq_set_affinity(data, affinity, true);
282 else if (!(warned++))
283 set_affinity = 0;
284
285 /*
286 * We unmask if the irq was not marked masked by the
287 * core code. That respects the lazy irq disable
288 * behaviour.
289 */
290 if (!irqd_can_move_in_process_context(data) &&
291 !irqd_irq_masked(data) && chip->irq_unmask)
292 chip->irq_unmask(data);
293
294 raw_spin_unlock(&desc->lock);
295
296 if (break_affinity && set_affinity)
297 printk("Broke affinity for irq %i\n", irq);
298 else if (!set_affinity)
299 printk("Cannot set affinity for irq %i\n", irq);
300 }
301
302 /*
303 * We can remove mdelay() and then send spuriuous interrupts to
304 * new cpu targets for all the irqs that were handled previously by
305 * this cpu. While it works, I have seen spurious interrupt messages
306 * (nothing wrong but still...).
307 *
308 * So for now, retain mdelay(1) and check the IRR and then send those
309 * interrupts to new targets as this cpu is already offlined...
310 */
311 mdelay(1);
312
313 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
314 unsigned int irr;
315
316 if (__this_cpu_read(vector_irq[vector]) < 0)
317 continue;
318
319 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
320 if (irr & (1 << (vector % 32))) {
321 irq = __this_cpu_read(vector_irq[vector]);
322
323 desc = irq_to_desc(irq);
324 data = irq_desc_get_irq_data(desc);
325 chip = irq_data_get_irq_chip(data);
326 raw_spin_lock(&desc->lock);
327 if (chip->irq_retrigger)
328 chip->irq_retrigger(data);
329 raw_spin_unlock(&desc->lock);
330 }
331 }
332}
333#endif
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Common interrupt code for 32 and 64 bit
4 */
5#include <linux/cpu.h>
6#include <linux/interrupt.h>
7#include <linux/kernel_stat.h>
8#include <linux/of.h>
9#include <linux/seq_file.h>
10#include <linux/smp.h>
11#include <linux/ftrace.h>
12#include <linux/delay.h>
13#include <linux/export.h>
14#include <linux/irq.h>
15
16#include <asm/irq_stack.h>
17#include <asm/apic.h>
18#include <asm/io_apic.h>
19#include <asm/irq.h>
20#include <asm/mce.h>
21#include <asm/hw_irq.h>
22#include <asm/desc.h>
23#include <asm/traps.h>
24
25#define CREATE_TRACE_POINTS
26#include <asm/trace/irq_vectors.h>
27
28DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
29EXPORT_PER_CPU_SYMBOL(irq_stat);
30
31atomic_t irq_err_count;
32
33/*
34 * 'what should we do if we get a hw irq event on an illegal vector'.
35 * each architecture has to answer this themselves.
36 */
37void ack_bad_irq(unsigned int irq)
38{
39 if (printk_ratelimit())
40 pr_err("unexpected IRQ trap at vector %02x\n", irq);
41
42 /*
43 * Currently unexpected vectors happen only on SMP and APIC.
44 * We _must_ ack these because every local APIC has only N
45 * irq slots per priority level, and a 'hanging, unacked' IRQ
46 * holds up an irq slot - in excessive cases (when multiple
47 * unexpected vectors occur) that might lock up the APIC
48 * completely.
49 * But only ack when the APIC is enabled -AK
50 */
51 ack_APIC_irq();
52}
53
54#define irq_stats(x) (&per_cpu(irq_stat, x))
55/*
56 * /proc/interrupts printing for arch specific interrupts
57 */
58int arch_show_interrupts(struct seq_file *p, int prec)
59{
60 int j;
61
62 seq_printf(p, "%*s: ", prec, "NMI");
63 for_each_online_cpu(j)
64 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
65 seq_puts(p, " Non-maskable interrupts\n");
66#ifdef CONFIG_X86_LOCAL_APIC
67 seq_printf(p, "%*s: ", prec, "LOC");
68 for_each_online_cpu(j)
69 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
70 seq_puts(p, " Local timer interrupts\n");
71
72 seq_printf(p, "%*s: ", prec, "SPU");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
75 seq_puts(p, " Spurious interrupts\n");
76 seq_printf(p, "%*s: ", prec, "PMI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
79 seq_puts(p, " Performance monitoring interrupts\n");
80 seq_printf(p, "%*s: ", prec, "IWI");
81 for_each_online_cpu(j)
82 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
83 seq_puts(p, " IRQ work interrupts\n");
84 seq_printf(p, "%*s: ", prec, "RTR");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
87 seq_puts(p, " APIC ICR read retries\n");
88 if (x86_platform_ipi_callback) {
89 seq_printf(p, "%*s: ", prec, "PLT");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
92 seq_puts(p, " Platform interrupts\n");
93 }
94#endif
95#ifdef CONFIG_SMP
96 seq_printf(p, "%*s: ", prec, "RES");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
99 seq_puts(p, " Rescheduling interrupts\n");
100 seq_printf(p, "%*s: ", prec, "CAL");
101 for_each_online_cpu(j)
102 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
103 seq_puts(p, " Function call interrupts\n");
104 seq_printf(p, "%*s: ", prec, "TLB");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
107 seq_puts(p, " TLB shootdowns\n");
108#endif
109#ifdef CONFIG_X86_THERMAL_VECTOR
110 seq_printf(p, "%*s: ", prec, "TRM");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
113 seq_puts(p, " Thermal event interrupts\n");
114#endif
115#ifdef CONFIG_X86_MCE_THRESHOLD
116 seq_printf(p, "%*s: ", prec, "THR");
117 for_each_online_cpu(j)
118 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
119 seq_puts(p, " Threshold APIC interrupts\n");
120#endif
121#ifdef CONFIG_X86_MCE_AMD
122 seq_printf(p, "%*s: ", prec, "DFR");
123 for_each_online_cpu(j)
124 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
125 seq_puts(p, " Deferred Error APIC interrupts\n");
126#endif
127#ifdef CONFIG_X86_MCE
128 seq_printf(p, "%*s: ", prec, "MCE");
129 for_each_online_cpu(j)
130 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
131 seq_puts(p, " Machine check exceptions\n");
132 seq_printf(p, "%*s: ", prec, "MCP");
133 for_each_online_cpu(j)
134 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
135 seq_puts(p, " Machine check polls\n");
136#endif
137#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
138 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
139 seq_printf(p, "%*s: ", prec, "HYP");
140 for_each_online_cpu(j)
141 seq_printf(p, "%10u ",
142 irq_stats(j)->irq_hv_callback_count);
143 seq_puts(p, " Hypervisor callback interrupts\n");
144 }
145#endif
146#if IS_ENABLED(CONFIG_HYPERV)
147 if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
148 seq_printf(p, "%*s: ", prec, "HRE");
149 for_each_online_cpu(j)
150 seq_printf(p, "%10u ",
151 irq_stats(j)->irq_hv_reenlightenment_count);
152 seq_puts(p, " Hyper-V reenlightenment interrupts\n");
153 }
154 if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
155 seq_printf(p, "%*s: ", prec, "HVS");
156 for_each_online_cpu(j)
157 seq_printf(p, "%10u ",
158 irq_stats(j)->hyperv_stimer0_count);
159 seq_puts(p, " Hyper-V stimer0 interrupts\n");
160 }
161#endif
162 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
163#if defined(CONFIG_X86_IO_APIC)
164 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
165#endif
166#ifdef CONFIG_HAVE_KVM
167 seq_printf(p, "%*s: ", prec, "PIN");
168 for_each_online_cpu(j)
169 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
170 seq_puts(p, " Posted-interrupt notification event\n");
171
172 seq_printf(p, "%*s: ", prec, "NPI");
173 for_each_online_cpu(j)
174 seq_printf(p, "%10u ",
175 irq_stats(j)->kvm_posted_intr_nested_ipis);
176 seq_puts(p, " Nested posted-interrupt event\n");
177
178 seq_printf(p, "%*s: ", prec, "PIW");
179 for_each_online_cpu(j)
180 seq_printf(p, "%10u ",
181 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
182 seq_puts(p, " Posted-interrupt wakeup event\n");
183#endif
184 return 0;
185}
186
187/*
188 * /proc/stat helpers
189 */
190u64 arch_irq_stat_cpu(unsigned int cpu)
191{
192 u64 sum = irq_stats(cpu)->__nmi_count;
193
194#ifdef CONFIG_X86_LOCAL_APIC
195 sum += irq_stats(cpu)->apic_timer_irqs;
196 sum += irq_stats(cpu)->irq_spurious_count;
197 sum += irq_stats(cpu)->apic_perf_irqs;
198 sum += irq_stats(cpu)->apic_irq_work_irqs;
199 sum += irq_stats(cpu)->icr_read_retry_count;
200 if (x86_platform_ipi_callback)
201 sum += irq_stats(cpu)->x86_platform_ipis;
202#endif
203#ifdef CONFIG_SMP
204 sum += irq_stats(cpu)->irq_resched_count;
205 sum += irq_stats(cpu)->irq_call_count;
206#endif
207#ifdef CONFIG_X86_THERMAL_VECTOR
208 sum += irq_stats(cpu)->irq_thermal_count;
209#endif
210#ifdef CONFIG_X86_MCE_THRESHOLD
211 sum += irq_stats(cpu)->irq_threshold_count;
212#endif
213#ifdef CONFIG_X86_MCE
214 sum += per_cpu(mce_exception_count, cpu);
215 sum += per_cpu(mce_poll_count, cpu);
216#endif
217 return sum;
218}
219
220u64 arch_irq_stat(void)
221{
222 u64 sum = atomic_read(&irq_err_count);
223 return sum;
224}
225
226static __always_inline void handle_irq(struct irq_desc *desc,
227 struct pt_regs *regs)
228{
229 if (IS_ENABLED(CONFIG_X86_64))
230 run_irq_on_irqstack_cond(desc->handle_irq, desc, regs);
231 else
232 __handle_irq(desc, regs);
233}
234
235/*
236 * common_interrupt() handles all normal device IRQ's (the special SMP
237 * cross-CPU interrupts have their own entry points).
238 */
239DEFINE_IDTENTRY_IRQ(common_interrupt)
240{
241 struct pt_regs *old_regs = set_irq_regs(regs);
242 struct irq_desc *desc;
243
244 /* entry code tells RCU that we're not quiescent. Check it. */
245 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
246
247 desc = __this_cpu_read(vector_irq[vector]);
248 if (likely(!IS_ERR_OR_NULL(desc))) {
249 handle_irq(desc, regs);
250 } else {
251 ack_APIC_irq();
252
253 if (desc == VECTOR_UNUSED) {
254 pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n",
255 __func__, smp_processor_id(),
256 vector);
257 } else {
258 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
259 }
260 }
261
262 set_irq_regs(old_regs);
263}
264
265#ifdef CONFIG_X86_LOCAL_APIC
266/* Function pointer for generic interrupt vector handling */
267void (*x86_platform_ipi_callback)(void) = NULL;
268/*
269 * Handler for X86_PLATFORM_IPI_VECTOR.
270 */
271DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
272{
273 struct pt_regs *old_regs = set_irq_regs(regs);
274
275 ack_APIC_irq();
276 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
277 inc_irq_stat(x86_platform_ipis);
278 if (x86_platform_ipi_callback)
279 x86_platform_ipi_callback();
280 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
281 set_irq_regs(old_regs);
282}
283#endif
284
285#ifdef CONFIG_HAVE_KVM
286static void dummy_handler(void) {}
287static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
288
289void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
290{
291 if (handler)
292 kvm_posted_intr_wakeup_handler = handler;
293 else
294 kvm_posted_intr_wakeup_handler = dummy_handler;
295}
296EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
297
298/*
299 * Handler for POSTED_INTERRUPT_VECTOR.
300 */
301DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
302{
303 ack_APIC_irq();
304 inc_irq_stat(kvm_posted_intr_ipis);
305}
306
307/*
308 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
309 */
310DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
311{
312 ack_APIC_irq();
313 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
314 kvm_posted_intr_wakeup_handler();
315}
316
317/*
318 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
319 */
320DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
321{
322 ack_APIC_irq();
323 inc_irq_stat(kvm_posted_intr_nested_ipis);
324}
325#endif
326
327
328#ifdef CONFIG_HOTPLUG_CPU
329/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
330void fixup_irqs(void)
331{
332 unsigned int irr, vector;
333 struct irq_desc *desc;
334 struct irq_data *data;
335 struct irq_chip *chip;
336
337 irq_migrate_all_off_this_cpu();
338
339 /*
340 * We can remove mdelay() and then send spuriuous interrupts to
341 * new cpu targets for all the irqs that were handled previously by
342 * this cpu. While it works, I have seen spurious interrupt messages
343 * (nothing wrong but still...).
344 *
345 * So for now, retain mdelay(1) and check the IRR and then send those
346 * interrupts to new targets as this cpu is already offlined...
347 */
348 mdelay(1);
349
350 /*
351 * We can walk the vector array of this cpu without holding
352 * vector_lock because the cpu is already marked !online, so
353 * nothing else will touch it.
354 */
355 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
356 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
357 continue;
358
359 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
360 if (irr & (1 << (vector % 32))) {
361 desc = __this_cpu_read(vector_irq[vector]);
362
363 raw_spin_lock(&desc->lock);
364 data = irq_desc_get_irq_data(desc);
365 chip = irq_data_get_irq_chip(data);
366 if (chip->irq_retrigger) {
367 chip->irq_retrigger(data);
368 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
369 }
370 raw_spin_unlock(&desc->lock);
371 }
372 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
373 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
374 }
375}
376#endif