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1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12#include <linux/export.h>
13
14#include <asm/apic.h>
15#include <asm/io_apic.h>
16#include <asm/irq.h>
17#include <asm/idle.h>
18#include <asm/mce.h>
19#include <asm/hw_irq.h>
20
21atomic_t irq_err_count;
22
23/* Function pointer for generic interrupt vector handling */
24void (*x86_platform_ipi_callback)(void) = NULL;
25
26/*
27 * 'what should we do if we get a hw irq event on an illegal vector'.
28 * each architecture has to answer this themselves.
29 */
30void ack_bad_irq(unsigned int irq)
31{
32 if (printk_ratelimit())
33 pr_err("unexpected IRQ trap at vector %02x\n", irq);
34
35 /*
36 * Currently unexpected vectors happen only on SMP and APIC.
37 * We _must_ ack these because every local APIC has only N
38 * irq slots per priority level, and a 'hanging, unacked' IRQ
39 * holds up an irq slot - in excessive cases (when multiple
40 * unexpected vectors occur) that might lock up the APIC
41 * completely.
42 * But only ack when the APIC is enabled -AK
43 */
44 ack_APIC_irq();
45}
46
47#define irq_stats(x) (&per_cpu(irq_stat, x))
48/*
49 * /proc/interrupts printing for arch specific interrupts
50 */
51int arch_show_interrupts(struct seq_file *p, int prec)
52{
53 int j;
54
55 seq_printf(p, "%*s: ", prec, "NMI");
56 for_each_online_cpu(j)
57 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
58 seq_printf(p, " Non-maskable interrupts\n");
59#ifdef CONFIG_X86_LOCAL_APIC
60 seq_printf(p, "%*s: ", prec, "LOC");
61 for_each_online_cpu(j)
62 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
63 seq_printf(p, " Local timer interrupts\n");
64
65 seq_printf(p, "%*s: ", prec, "SPU");
66 for_each_online_cpu(j)
67 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
68 seq_printf(p, " Spurious interrupts\n");
69 seq_printf(p, "%*s: ", prec, "PMI");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
72 seq_printf(p, " Performance monitoring interrupts\n");
73 seq_printf(p, "%*s: ", prec, "IWI");
74 for_each_online_cpu(j)
75 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
76 seq_printf(p, " IRQ work interrupts\n");
77 seq_printf(p, "%*s: ", prec, "RTR");
78 for_each_online_cpu(j)
79 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
80 seq_printf(p, " APIC ICR read retries\n");
81#endif
82 if (x86_platform_ipi_callback) {
83 seq_printf(p, "%*s: ", prec, "PLT");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
86 seq_printf(p, " Platform interrupts\n");
87 }
88#ifdef CONFIG_SMP
89 seq_printf(p, "%*s: ", prec, "RES");
90 for_each_online_cpu(j)
91 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
92 seq_printf(p, " Rescheduling interrupts\n");
93 seq_printf(p, "%*s: ", prec, "CAL");
94 for_each_online_cpu(j)
95 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
96 seq_printf(p, " Function call interrupts\n");
97 seq_printf(p, "%*s: ", prec, "TLB");
98 for_each_online_cpu(j)
99 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
100 seq_printf(p, " TLB shootdowns\n");
101#endif
102#ifdef CONFIG_X86_THERMAL_VECTOR
103 seq_printf(p, "%*s: ", prec, "TRM");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
106 seq_printf(p, " Thermal event interrupts\n");
107#endif
108#ifdef CONFIG_X86_MCE_THRESHOLD
109 seq_printf(p, "%*s: ", prec, "THR");
110 for_each_online_cpu(j)
111 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
112 seq_printf(p, " Threshold APIC interrupts\n");
113#endif
114#ifdef CONFIG_X86_MCE
115 seq_printf(p, "%*s: ", prec, "MCE");
116 for_each_online_cpu(j)
117 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
118 seq_printf(p, " Machine check exceptions\n");
119 seq_printf(p, "%*s: ", prec, "MCP");
120 for_each_online_cpu(j)
121 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
122 seq_printf(p, " Machine check polls\n");
123#endif
124 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
125#if defined(CONFIG_X86_IO_APIC)
126 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
127#endif
128 return 0;
129}
130
131/*
132 * /proc/stat helpers
133 */
134u64 arch_irq_stat_cpu(unsigned int cpu)
135{
136 u64 sum = irq_stats(cpu)->__nmi_count;
137
138#ifdef CONFIG_X86_LOCAL_APIC
139 sum += irq_stats(cpu)->apic_timer_irqs;
140 sum += irq_stats(cpu)->irq_spurious_count;
141 sum += irq_stats(cpu)->apic_perf_irqs;
142 sum += irq_stats(cpu)->apic_irq_work_irqs;
143 sum += irq_stats(cpu)->icr_read_retry_count;
144#endif
145 if (x86_platform_ipi_callback)
146 sum += irq_stats(cpu)->x86_platform_ipis;
147#ifdef CONFIG_SMP
148 sum += irq_stats(cpu)->irq_resched_count;
149 sum += irq_stats(cpu)->irq_call_count;
150 sum += irq_stats(cpu)->irq_tlb_count;
151#endif
152#ifdef CONFIG_X86_THERMAL_VECTOR
153 sum += irq_stats(cpu)->irq_thermal_count;
154#endif
155#ifdef CONFIG_X86_MCE_THRESHOLD
156 sum += irq_stats(cpu)->irq_threshold_count;
157#endif
158#ifdef CONFIG_X86_MCE
159 sum += per_cpu(mce_exception_count, cpu);
160 sum += per_cpu(mce_poll_count, cpu);
161#endif
162 return sum;
163}
164
165u64 arch_irq_stat(void)
166{
167 u64 sum = atomic_read(&irq_err_count);
168
169#ifdef CONFIG_X86_IO_APIC
170 sum += atomic_read(&irq_mis_count);
171#endif
172 return sum;
173}
174
175
176/*
177 * do_IRQ handles all normal device IRQ's (the special
178 * SMP cross-CPU interrupts have their own specific
179 * handlers).
180 */
181unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
182{
183 struct pt_regs *old_regs = set_irq_regs(regs);
184
185 /* high bit used in ret_from_ code */
186 unsigned vector = ~regs->orig_ax;
187 unsigned irq;
188
189 irq_enter();
190 exit_idle();
191
192 irq = __this_cpu_read(vector_irq[vector]);
193
194 if (!handle_irq(irq, regs)) {
195 ack_APIC_irq();
196
197 if (printk_ratelimit())
198 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
199 __func__, smp_processor_id(), vector, irq);
200 }
201
202 irq_exit();
203
204 set_irq_regs(old_regs);
205 return 1;
206}
207
208/*
209 * Handler for X86_PLATFORM_IPI_VECTOR.
210 */
211void smp_x86_platform_ipi(struct pt_regs *regs)
212{
213 struct pt_regs *old_regs = set_irq_regs(regs);
214
215 ack_APIC_irq();
216
217 irq_enter();
218
219 exit_idle();
220
221 inc_irq_stat(x86_platform_ipis);
222
223 if (x86_platform_ipi_callback)
224 x86_platform_ipi_callback();
225
226 irq_exit();
227
228 set_irq_regs(old_regs);
229}
230
231EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
232
233#ifdef CONFIG_HOTPLUG_CPU
234/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
235void fixup_irqs(void)
236{
237 unsigned int irq, vector;
238 static int warned;
239 struct irq_desc *desc;
240 struct irq_data *data;
241 struct irq_chip *chip;
242
243 for_each_irq_desc(irq, desc) {
244 int break_affinity = 0;
245 int set_affinity = 1;
246 const struct cpumask *affinity;
247
248 if (!desc)
249 continue;
250 if (irq == 2)
251 continue;
252
253 /* interrupt's are disabled at this point */
254 raw_spin_lock(&desc->lock);
255
256 data = irq_desc_get_irq_data(desc);
257 affinity = data->affinity;
258 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
259 cpumask_subset(affinity, cpu_online_mask)) {
260 raw_spin_unlock(&desc->lock);
261 continue;
262 }
263
264 /*
265 * Complete the irq move. This cpu is going down and for
266 * non intr-remapping case, we can't wait till this interrupt
267 * arrives at this cpu before completing the irq move.
268 */
269 irq_force_complete_move(irq);
270
271 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
272 break_affinity = 1;
273 affinity = cpu_all_mask;
274 }
275
276 chip = irq_data_get_irq_chip(data);
277 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
278 chip->irq_mask(data);
279
280 if (chip->irq_set_affinity)
281 chip->irq_set_affinity(data, affinity, true);
282 else if (!(warned++))
283 set_affinity = 0;
284
285 /*
286 * We unmask if the irq was not marked masked by the
287 * core code. That respects the lazy irq disable
288 * behaviour.
289 */
290 if (!irqd_can_move_in_process_context(data) &&
291 !irqd_irq_masked(data) && chip->irq_unmask)
292 chip->irq_unmask(data);
293
294 raw_spin_unlock(&desc->lock);
295
296 if (break_affinity && set_affinity)
297 printk("Broke affinity for irq %i\n", irq);
298 else if (!set_affinity)
299 printk("Cannot set affinity for irq %i\n", irq);
300 }
301
302 /*
303 * We can remove mdelay() and then send spuriuous interrupts to
304 * new cpu targets for all the irqs that were handled previously by
305 * this cpu. While it works, I have seen spurious interrupt messages
306 * (nothing wrong but still...).
307 *
308 * So for now, retain mdelay(1) and check the IRR and then send those
309 * interrupts to new targets as this cpu is already offlined...
310 */
311 mdelay(1);
312
313 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
314 unsigned int irr;
315
316 if (__this_cpu_read(vector_irq[vector]) < 0)
317 continue;
318
319 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
320 if (irr & (1 << (vector % 32))) {
321 irq = __this_cpu_read(vector_irq[vector]);
322
323 desc = irq_to_desc(irq);
324 data = irq_desc_get_irq_data(desc);
325 chip = irq_data_get_irq_chip(data);
326 raw_spin_lock(&desc->lock);
327 if (chip->irq_retrigger)
328 chip->irq_retrigger(data);
329 raw_spin_unlock(&desc->lock);
330 }
331 }
332}
333#endif
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12
13#include <asm/apic.h>
14#include <asm/io_apic.h>
15#include <asm/irq.h>
16#include <asm/idle.h>
17#include <asm/mce.h>
18#include <asm/hw_irq.h>
19
20atomic_t irq_err_count;
21
22/* Function pointer for generic interrupt vector handling */
23void (*x86_platform_ipi_callback)(void) = NULL;
24
25/*
26 * 'what should we do if we get a hw irq event on an illegal vector'.
27 * each architecture has to answer this themselves.
28 */
29void ack_bad_irq(unsigned int irq)
30{
31 if (printk_ratelimit())
32 pr_err("unexpected IRQ trap at vector %02x\n", irq);
33
34 /*
35 * Currently unexpected vectors happen only on SMP and APIC.
36 * We _must_ ack these because every local APIC has only N
37 * irq slots per priority level, and a 'hanging, unacked' IRQ
38 * holds up an irq slot - in excessive cases (when multiple
39 * unexpected vectors occur) that might lock up the APIC
40 * completely.
41 * But only ack when the APIC is enabled -AK
42 */
43 ack_APIC_irq();
44}
45
46#define irq_stats(x) (&per_cpu(irq_stat, x))
47/*
48 * /proc/interrupts printing for arch specific interrupts
49 */
50int arch_show_interrupts(struct seq_file *p, int prec)
51{
52 int j;
53
54 seq_printf(p, "%*s: ", prec, "NMI");
55 for_each_online_cpu(j)
56 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
57 seq_printf(p, " Non-maskable interrupts\n");
58#ifdef CONFIG_X86_LOCAL_APIC
59 seq_printf(p, "%*s: ", prec, "LOC");
60 for_each_online_cpu(j)
61 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
62 seq_printf(p, " Local timer interrupts\n");
63
64 seq_printf(p, "%*s: ", prec, "SPU");
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
67 seq_printf(p, " Spurious interrupts\n");
68 seq_printf(p, "%*s: ", prec, "PMI");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
71 seq_printf(p, " Performance monitoring interrupts\n");
72 seq_printf(p, "%*s: ", prec, "IWI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
75 seq_printf(p, " IRQ work interrupts\n");
76#endif
77 if (x86_platform_ipi_callback) {
78 seq_printf(p, "%*s: ", prec, "PLT");
79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
81 seq_printf(p, " Platform interrupts\n");
82 }
83#ifdef CONFIG_SMP
84 seq_printf(p, "%*s: ", prec, "RES");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
87 seq_printf(p, " Rescheduling interrupts\n");
88 seq_printf(p, "%*s: ", prec, "CAL");
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
91 seq_printf(p, " Function call interrupts\n");
92 seq_printf(p, "%*s: ", prec, "TLB");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
95 seq_printf(p, " TLB shootdowns\n");
96#endif
97#ifdef CONFIG_X86_THERMAL_VECTOR
98 seq_printf(p, "%*s: ", prec, "TRM");
99 for_each_online_cpu(j)
100 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
101 seq_printf(p, " Thermal event interrupts\n");
102#endif
103#ifdef CONFIG_X86_MCE_THRESHOLD
104 seq_printf(p, "%*s: ", prec, "THR");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
107 seq_printf(p, " Threshold APIC interrupts\n");
108#endif
109#ifdef CONFIG_X86_MCE
110 seq_printf(p, "%*s: ", prec, "MCE");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
113 seq_printf(p, " Machine check exceptions\n");
114 seq_printf(p, "%*s: ", prec, "MCP");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
117 seq_printf(p, " Machine check polls\n");
118#endif
119 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
120#if defined(CONFIG_X86_IO_APIC)
121 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
122#endif
123 return 0;
124}
125
126/*
127 * /proc/stat helpers
128 */
129u64 arch_irq_stat_cpu(unsigned int cpu)
130{
131 u64 sum = irq_stats(cpu)->__nmi_count;
132
133#ifdef CONFIG_X86_LOCAL_APIC
134 sum += irq_stats(cpu)->apic_timer_irqs;
135 sum += irq_stats(cpu)->irq_spurious_count;
136 sum += irq_stats(cpu)->apic_perf_irqs;
137 sum += irq_stats(cpu)->apic_irq_work_irqs;
138#endif
139 if (x86_platform_ipi_callback)
140 sum += irq_stats(cpu)->x86_platform_ipis;
141#ifdef CONFIG_SMP
142 sum += irq_stats(cpu)->irq_resched_count;
143 sum += irq_stats(cpu)->irq_call_count;
144 sum += irq_stats(cpu)->irq_tlb_count;
145#endif
146#ifdef CONFIG_X86_THERMAL_VECTOR
147 sum += irq_stats(cpu)->irq_thermal_count;
148#endif
149#ifdef CONFIG_X86_MCE_THRESHOLD
150 sum += irq_stats(cpu)->irq_threshold_count;
151#endif
152#ifdef CONFIG_X86_MCE
153 sum += per_cpu(mce_exception_count, cpu);
154 sum += per_cpu(mce_poll_count, cpu);
155#endif
156 return sum;
157}
158
159u64 arch_irq_stat(void)
160{
161 u64 sum = atomic_read(&irq_err_count);
162
163#ifdef CONFIG_X86_IO_APIC
164 sum += atomic_read(&irq_mis_count);
165#endif
166 return sum;
167}
168
169
170/*
171 * do_IRQ handles all normal device IRQ's (the special
172 * SMP cross-CPU interrupts have their own specific
173 * handlers).
174 */
175unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
176{
177 struct pt_regs *old_regs = set_irq_regs(regs);
178
179 /* high bit used in ret_from_ code */
180 unsigned vector = ~regs->orig_ax;
181 unsigned irq;
182
183 exit_idle();
184 irq_enter();
185
186 irq = __this_cpu_read(vector_irq[vector]);
187
188 if (!handle_irq(irq, regs)) {
189 ack_APIC_irq();
190
191 if (printk_ratelimit())
192 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
193 __func__, smp_processor_id(), vector, irq);
194 }
195
196 irq_exit();
197
198 set_irq_regs(old_regs);
199 return 1;
200}
201
202/*
203 * Handler for X86_PLATFORM_IPI_VECTOR.
204 */
205void smp_x86_platform_ipi(struct pt_regs *regs)
206{
207 struct pt_regs *old_regs = set_irq_regs(regs);
208
209 ack_APIC_irq();
210
211 exit_idle();
212
213 irq_enter();
214
215 inc_irq_stat(x86_platform_ipis);
216
217 if (x86_platform_ipi_callback)
218 x86_platform_ipi_callback();
219
220 irq_exit();
221
222 set_irq_regs(old_regs);
223}
224
225EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
226
227#ifdef CONFIG_HOTPLUG_CPU
228/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
229void fixup_irqs(void)
230{
231 unsigned int irq, vector;
232 static int warned;
233 struct irq_desc *desc;
234 struct irq_data *data;
235 struct irq_chip *chip;
236
237 for_each_irq_desc(irq, desc) {
238 int break_affinity = 0;
239 int set_affinity = 1;
240 const struct cpumask *affinity;
241
242 if (!desc)
243 continue;
244 if (irq == 2)
245 continue;
246
247 /* interrupt's are disabled at this point */
248 raw_spin_lock(&desc->lock);
249
250 data = irq_desc_get_irq_data(desc);
251 affinity = data->affinity;
252 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
253 cpumask_subset(affinity, cpu_online_mask)) {
254 raw_spin_unlock(&desc->lock);
255 continue;
256 }
257
258 /*
259 * Complete the irq move. This cpu is going down and for
260 * non intr-remapping case, we can't wait till this interrupt
261 * arrives at this cpu before completing the irq move.
262 */
263 irq_force_complete_move(irq);
264
265 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
266 break_affinity = 1;
267 affinity = cpu_all_mask;
268 }
269
270 chip = irq_data_get_irq_chip(data);
271 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
272 chip->irq_mask(data);
273
274 if (chip->irq_set_affinity)
275 chip->irq_set_affinity(data, affinity, true);
276 else if (!(warned++))
277 set_affinity = 0;
278
279 if (!irqd_can_move_in_process_context(data) &&
280 !irqd_irq_disabled(data) && chip->irq_unmask)
281 chip->irq_unmask(data);
282
283 raw_spin_unlock(&desc->lock);
284
285 if (break_affinity && set_affinity)
286 printk("Broke affinity for irq %i\n", irq);
287 else if (!set_affinity)
288 printk("Cannot set affinity for irq %i\n", irq);
289 }
290
291 /*
292 * We can remove mdelay() and then send spuriuous interrupts to
293 * new cpu targets for all the irqs that were handled previously by
294 * this cpu. While it works, I have seen spurious interrupt messages
295 * (nothing wrong but still...).
296 *
297 * So for now, retain mdelay(1) and check the IRR and then send those
298 * interrupts to new targets as this cpu is already offlined...
299 */
300 mdelay(1);
301
302 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
303 unsigned int irr;
304
305 if (__this_cpu_read(vector_irq[vector]) < 0)
306 continue;
307
308 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
309 if (irr & (1 << (vector % 32))) {
310 irq = __this_cpu_read(vector_irq[vector]);
311
312 desc = irq_to_desc(irq);
313 data = irq_desc_get_irq_data(desc);
314 chip = irq_data_get_irq_chip(data);
315 raw_spin_lock(&desc->lock);
316 if (chip->irq_retrigger)
317 chip->irq_retrigger(data);
318 raw_spin_unlock(&desc->lock);
319 }
320 }
321}
322#endif