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1/*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * Based on spi-sh.c:
7 * Copyright (C) 2011 Renesas Solutions Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
31#include <linux/platform_device.h>
32#include <linux/io.h>
33#include <linux/clk.h>
34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/sh_dma.h>
37#include <linux/spi/spi.h>
38#include <linux/spi/rspi.h>
39
40#define RSPI_SPCR 0x00
41#define RSPI_SSLP 0x01
42#define RSPI_SPPCR 0x02
43#define RSPI_SPSR 0x03
44#define RSPI_SPDR 0x04
45#define RSPI_SPSCR 0x08
46#define RSPI_SPSSR 0x09
47#define RSPI_SPBR 0x0a
48#define RSPI_SPDCR 0x0b
49#define RSPI_SPCKD 0x0c
50#define RSPI_SSLND 0x0d
51#define RSPI_SPND 0x0e
52#define RSPI_SPCR2 0x0f
53#define RSPI_SPCMD0 0x10
54#define RSPI_SPCMD1 0x12
55#define RSPI_SPCMD2 0x14
56#define RSPI_SPCMD3 0x16
57#define RSPI_SPCMD4 0x18
58#define RSPI_SPCMD5 0x1a
59#define RSPI_SPCMD6 0x1c
60#define RSPI_SPCMD7 0x1e
61
62/* SPCR */
63#define SPCR_SPRIE 0x80
64#define SPCR_SPE 0x40
65#define SPCR_SPTIE 0x20
66#define SPCR_SPEIE 0x10
67#define SPCR_MSTR 0x08
68#define SPCR_MODFEN 0x04
69#define SPCR_TXMD 0x02
70#define SPCR_SPMS 0x01
71
72/* SSLP */
73#define SSLP_SSL1P 0x02
74#define SSLP_SSL0P 0x01
75
76/* SPPCR */
77#define SPPCR_MOIFE 0x20
78#define SPPCR_MOIFV 0x10
79#define SPPCR_SPOM 0x04
80#define SPPCR_SPLP2 0x02
81#define SPPCR_SPLP 0x01
82
83/* SPSR */
84#define SPSR_SPRF 0x80
85#define SPSR_SPTEF 0x20
86#define SPSR_PERF 0x08
87#define SPSR_MODF 0x04
88#define SPSR_IDLNF 0x02
89#define SPSR_OVRF 0x01
90
91/* SPSCR */
92#define SPSCR_SPSLN_MASK 0x07
93
94/* SPSSR */
95#define SPSSR_SPECM_MASK 0x70
96#define SPSSR_SPCP_MASK 0x07
97
98/* SPDCR */
99#define SPDCR_SPLW 0x20
100#define SPDCR_SPRDTD 0x10
101#define SPDCR_SLSEL1 0x08
102#define SPDCR_SLSEL0 0x04
103#define SPDCR_SLSEL_MASK 0x0c
104#define SPDCR_SPFC1 0x02
105#define SPDCR_SPFC0 0x01
106
107/* SPCKD */
108#define SPCKD_SCKDL_MASK 0x07
109
110/* SSLND */
111#define SSLND_SLNDL_MASK 0x07
112
113/* SPND */
114#define SPND_SPNDL_MASK 0x07
115
116/* SPCR2 */
117#define SPCR2_PTE 0x08
118#define SPCR2_SPIE 0x04
119#define SPCR2_SPOE 0x02
120#define SPCR2_SPPE 0x01
121
122/* SPCMDn */
123#define SPCMD_SCKDEN 0x8000
124#define SPCMD_SLNDEN 0x4000
125#define SPCMD_SPNDEN 0x2000
126#define SPCMD_LSBF 0x1000
127#define SPCMD_SPB_MASK 0x0f00
128#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
129#define SPCMD_SPB_20BIT 0x0000
130#define SPCMD_SPB_24BIT 0x0100
131#define SPCMD_SPB_32BIT 0x0200
132#define SPCMD_SSLKP 0x0080
133#define SPCMD_SSLA_MASK 0x0030
134#define SPCMD_BRDV_MASK 0x000c
135#define SPCMD_CPOL 0x0002
136#define SPCMD_CPHA 0x0001
137
138struct rspi_data {
139 void __iomem *addr;
140 u32 max_speed_hz;
141 struct spi_master *master;
142 struct list_head queue;
143 struct work_struct ws;
144 wait_queue_head_t wait;
145 spinlock_t lock;
146 struct clk *clk;
147 unsigned char spsr;
148
149 /* for dmaengine */
150 struct sh_dmae_slave dma_tx;
151 struct sh_dmae_slave dma_rx;
152 struct dma_chan *chan_tx;
153 struct dma_chan *chan_rx;
154 int irq;
155
156 unsigned dma_width_16bit:1;
157 unsigned dma_callbacked:1;
158};
159
160static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
161{
162 iowrite8(data, rspi->addr + offset);
163}
164
165static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
166{
167 iowrite16(data, rspi->addr + offset);
168}
169
170static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
171{
172 return ioread8(rspi->addr + offset);
173}
174
175static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
176{
177 return ioread16(rspi->addr + offset);
178}
179
180static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
181{
182 int tmp;
183 unsigned char spbr;
184
185 tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
186 spbr = clamp(tmp, 0, 255);
187
188 return spbr;
189}
190
191static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
192{
193 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
194}
195
196static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
197{
198 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
199}
200
201static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
202 u8 enable_bit)
203{
204 int ret;
205
206 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
207 rspi_enable_irq(rspi, enable_bit);
208 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
209 if (ret == 0 && !(rspi->spsr & wait_mask))
210 return -ETIMEDOUT;
211
212 return 0;
213}
214
215static void rspi_assert_ssl(struct rspi_data *rspi)
216{
217 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
218}
219
220static void rspi_negate_ssl(struct rspi_data *rspi)
221{
222 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
223}
224
225static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
226{
227 /* Sets output mode(CMOS) and MOSI signal(from previous transfer) */
228 rspi_write8(rspi, 0x00, RSPI_SPPCR);
229
230 /* Sets transfer bit rate */
231 rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
232
233 /* Sets number of frames to be used: 1 frame */
234 rspi_write8(rspi, 0x00, RSPI_SPDCR);
235
236 /* Sets RSPCK, SSL, next-access delay value */
237 rspi_write8(rspi, 0x00, RSPI_SPCKD);
238 rspi_write8(rspi, 0x00, RSPI_SSLND);
239 rspi_write8(rspi, 0x00, RSPI_SPND);
240
241 /* Sets parity, interrupt mask */
242 rspi_write8(rspi, 0x00, RSPI_SPCR2);
243
244 /* Sets SPCMD */
245 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
246 RSPI_SPCMD0);
247
248 /* Sets RSPI mode */
249 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
250
251 return 0;
252}
253
254static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
255 struct spi_transfer *t)
256{
257 int remain = t->len;
258 u8 *data;
259
260 data = (u8 *)t->tx_buf;
261 while (remain > 0) {
262 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
263 RSPI_SPCR);
264
265 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
266 dev_err(&rspi->master->dev,
267 "%s: tx empty timeout\n", __func__);
268 return -ETIMEDOUT;
269 }
270
271 rspi_write16(rspi, *data, RSPI_SPDR);
272 data++;
273 remain--;
274 }
275
276 /* Waiting for the last transmition */
277 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
278
279 return 0;
280}
281
282static void rspi_dma_complete(void *arg)
283{
284 struct rspi_data *rspi = arg;
285
286 rspi->dma_callbacked = 1;
287 wake_up_interruptible(&rspi->wait);
288}
289
290static int rspi_dma_map_sg(struct scatterlist *sg, void *buf, unsigned len,
291 struct dma_chan *chan,
292 enum dma_transfer_direction dir)
293{
294 sg_init_table(sg, 1);
295 sg_set_buf(sg, buf, len);
296 sg_dma_len(sg) = len;
297 return dma_map_sg(chan->device->dev, sg, 1, dir);
298}
299
300static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
301 enum dma_transfer_direction dir)
302{
303 dma_unmap_sg(chan->device->dev, sg, 1, dir);
304}
305
306static void rspi_memory_to_8bit(void *buf, const void *data, unsigned len)
307{
308 u16 *dst = buf;
309 const u8 *src = data;
310
311 while (len) {
312 *dst++ = (u16)(*src++);
313 len--;
314 }
315}
316
317static void rspi_memory_from_8bit(void *buf, const void *data, unsigned len)
318{
319 u8 *dst = buf;
320 const u16 *src = data;
321
322 while (len) {
323 *dst++ = (u8)*src++;
324 len--;
325 }
326}
327
328static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
329{
330 struct scatterlist sg;
331 void *buf = NULL;
332 struct dma_async_tx_descriptor *desc;
333 unsigned len;
334 int ret = 0;
335
336 if (rspi->dma_width_16bit) {
337 /*
338 * If DMAC bus width is 16-bit, the driver allocates a dummy
339 * buffer. And, the driver converts original data into the
340 * DMAC data as the following format:
341 * original data: 1st byte, 2nd byte ...
342 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
343 */
344 len = t->len * 2;
345 buf = kmalloc(len, GFP_KERNEL);
346 if (!buf)
347 return -ENOMEM;
348 rspi_memory_to_8bit(buf, t->tx_buf, t->len);
349 } else {
350 len = t->len;
351 buf = (void *)t->tx_buf;
352 }
353
354 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE)) {
355 ret = -EFAULT;
356 goto end_nomap;
357 }
358 desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
359 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
360 if (!desc) {
361 ret = -EIO;
362 goto end;
363 }
364
365 /*
366 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
367 * called. So, this driver disables the IRQ while DMA transfer.
368 */
369 disable_irq(rspi->irq);
370
371 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
372 rspi_enable_irq(rspi, SPCR_SPTIE);
373 rspi->dma_callbacked = 0;
374
375 desc->callback = rspi_dma_complete;
376 desc->callback_param = rspi;
377 dmaengine_submit(desc);
378 dma_async_issue_pending(rspi->chan_tx);
379
380 ret = wait_event_interruptible_timeout(rspi->wait,
381 rspi->dma_callbacked, HZ);
382 if (ret > 0 && rspi->dma_callbacked)
383 ret = 0;
384 else if (!ret)
385 ret = -ETIMEDOUT;
386 rspi_disable_irq(rspi, SPCR_SPTIE);
387
388 enable_irq(rspi->irq);
389
390end:
391 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
392end_nomap:
393 if (rspi->dma_width_16bit)
394 kfree(buf);
395
396 return ret;
397}
398
399static void rspi_receive_init(struct rspi_data *rspi)
400{
401 unsigned char spsr;
402
403 spsr = rspi_read8(rspi, RSPI_SPSR);
404 if (spsr & SPSR_SPRF)
405 rspi_read16(rspi, RSPI_SPDR); /* dummy read */
406 if (spsr & SPSR_OVRF)
407 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
408 RSPI_SPCR);
409}
410
411static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
412 struct spi_transfer *t)
413{
414 int remain = t->len;
415 u8 *data;
416
417 rspi_receive_init(rspi);
418
419 data = (u8 *)t->rx_buf;
420 while (remain > 0) {
421 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
422 RSPI_SPCR);
423
424 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
425 dev_err(&rspi->master->dev,
426 "%s: tx empty timeout\n", __func__);
427 return -ETIMEDOUT;
428 }
429 /* dummy write for generate clock */
430 rspi_write16(rspi, 0x00, RSPI_SPDR);
431
432 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
433 dev_err(&rspi->master->dev,
434 "%s: receive timeout\n", __func__);
435 return -ETIMEDOUT;
436 }
437 /* SPDR allows 16 or 32-bit access only */
438 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
439
440 data++;
441 remain--;
442 }
443
444 return 0;
445}
446
447static int rspi_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
448{
449 struct scatterlist sg, sg_dummy;
450 void *dummy = NULL, *rx_buf = NULL;
451 struct dma_async_tx_descriptor *desc, *desc_dummy;
452 unsigned len;
453 int ret = 0;
454
455 if (rspi->dma_width_16bit) {
456 /*
457 * If DMAC bus width is 16-bit, the driver allocates a dummy
458 * buffer. And, finally the driver converts the DMAC data into
459 * actual data as the following format:
460 * DMAC data: 1st byte, dummy, 2nd byte, dummy ...
461 * actual data: 1st byte, 2nd byte ...
462 */
463 len = t->len * 2;
464 rx_buf = kmalloc(len, GFP_KERNEL);
465 if (!rx_buf)
466 return -ENOMEM;
467 } else {
468 len = t->len;
469 rx_buf = t->rx_buf;
470 }
471
472 /* prepare dummy transfer to generate SPI clocks */
473 dummy = kzalloc(len, GFP_KERNEL);
474 if (!dummy) {
475 ret = -ENOMEM;
476 goto end_nomap;
477 }
478 if (!rspi_dma_map_sg(&sg_dummy, dummy, len, rspi->chan_tx,
479 DMA_TO_DEVICE)) {
480 ret = -EFAULT;
481 goto end_nomap;
482 }
483 desc_dummy = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_dummy, 1,
484 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 if (!desc_dummy) {
486 ret = -EIO;
487 goto end_dummy_mapped;
488 }
489
490 /* prepare receive transfer */
491 if (!rspi_dma_map_sg(&sg, rx_buf, len, rspi->chan_rx,
492 DMA_FROM_DEVICE)) {
493 ret = -EFAULT;
494 goto end_dummy_mapped;
495
496 }
497 desc = dmaengine_prep_slave_sg(rspi->chan_rx, &sg, 1, DMA_FROM_DEVICE,
498 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
499 if (!desc) {
500 ret = -EIO;
501 goto end;
502 }
503
504 rspi_receive_init(rspi);
505
506 /*
507 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
508 * called. So, this driver disables the IRQ while DMA transfer.
509 */
510 disable_irq(rspi->irq);
511
512 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
513 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
514 rspi->dma_callbacked = 0;
515
516 desc->callback = rspi_dma_complete;
517 desc->callback_param = rspi;
518 dmaengine_submit(desc);
519 dma_async_issue_pending(rspi->chan_rx);
520
521 desc_dummy->callback = NULL; /* No callback */
522 dmaengine_submit(desc_dummy);
523 dma_async_issue_pending(rspi->chan_tx);
524
525 ret = wait_event_interruptible_timeout(rspi->wait,
526 rspi->dma_callbacked, HZ);
527 if (ret > 0 && rspi->dma_callbacked)
528 ret = 0;
529 else if (!ret)
530 ret = -ETIMEDOUT;
531 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
532
533 enable_irq(rspi->irq);
534
535end:
536 rspi_dma_unmap_sg(&sg, rspi->chan_rx, DMA_FROM_DEVICE);
537end_dummy_mapped:
538 rspi_dma_unmap_sg(&sg_dummy, rspi->chan_tx, DMA_TO_DEVICE);
539end_nomap:
540 if (rspi->dma_width_16bit) {
541 if (!ret)
542 rspi_memory_from_8bit(t->rx_buf, rx_buf, t->len);
543 kfree(rx_buf);
544 }
545 kfree(dummy);
546
547 return ret;
548}
549
550static int rspi_is_dma(struct rspi_data *rspi, struct spi_transfer *t)
551{
552 if (t->tx_buf && rspi->chan_tx)
553 return 1;
554 /* If the module receives data by DMAC, it also needs TX DMAC */
555 if (t->rx_buf && rspi->chan_tx && rspi->chan_rx)
556 return 1;
557
558 return 0;
559}
560
561static void rspi_work(struct work_struct *work)
562{
563 struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
564 struct spi_message *mesg;
565 struct spi_transfer *t;
566 unsigned long flags;
567 int ret;
568
569 spin_lock_irqsave(&rspi->lock, flags);
570 while (!list_empty(&rspi->queue)) {
571 mesg = list_entry(rspi->queue.next, struct spi_message, queue);
572 list_del_init(&mesg->queue);
573 spin_unlock_irqrestore(&rspi->lock, flags);
574
575 rspi_assert_ssl(rspi);
576
577 list_for_each_entry(t, &mesg->transfers, transfer_list) {
578 if (t->tx_buf) {
579 if (rspi_is_dma(rspi, t))
580 ret = rspi_send_dma(rspi, t);
581 else
582 ret = rspi_send_pio(rspi, mesg, t);
583 if (ret < 0)
584 goto error;
585 }
586 if (t->rx_buf) {
587 if (rspi_is_dma(rspi, t))
588 ret = rspi_receive_dma(rspi, t);
589 else
590 ret = rspi_receive_pio(rspi, mesg, t);
591 if (ret < 0)
592 goto error;
593 }
594 mesg->actual_length += t->len;
595 }
596 rspi_negate_ssl(rspi);
597
598 mesg->status = 0;
599 mesg->complete(mesg->context);
600
601 spin_lock_irqsave(&rspi->lock, flags);
602 }
603
604 return;
605
606error:
607 mesg->status = ret;
608 mesg->complete(mesg->context);
609}
610
611static int rspi_setup(struct spi_device *spi)
612{
613 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
614
615 if (!spi->bits_per_word)
616 spi->bits_per_word = 8;
617 rspi->max_speed_hz = spi->max_speed_hz;
618
619 rspi_set_config_register(rspi, 8);
620
621 return 0;
622}
623
624static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
625{
626 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
627 unsigned long flags;
628
629 mesg->actual_length = 0;
630 mesg->status = -EINPROGRESS;
631
632 spin_lock_irqsave(&rspi->lock, flags);
633 list_add_tail(&mesg->queue, &rspi->queue);
634 schedule_work(&rspi->ws);
635 spin_unlock_irqrestore(&rspi->lock, flags);
636
637 return 0;
638}
639
640static void rspi_cleanup(struct spi_device *spi)
641{
642}
643
644static irqreturn_t rspi_irq(int irq, void *_sr)
645{
646 struct rspi_data *rspi = (struct rspi_data *)_sr;
647 unsigned long spsr;
648 irqreturn_t ret = IRQ_NONE;
649 unsigned char disable_irq = 0;
650
651 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
652 if (spsr & SPSR_SPRF)
653 disable_irq |= SPCR_SPRIE;
654 if (spsr & SPSR_SPTEF)
655 disable_irq |= SPCR_SPTIE;
656
657 if (disable_irq) {
658 ret = IRQ_HANDLED;
659 rspi_disable_irq(rspi, disable_irq);
660 wake_up(&rspi->wait);
661 }
662
663 return ret;
664}
665
666static bool rspi_filter(struct dma_chan *chan, void *filter_param)
667{
668 chan->private = filter_param;
669 return true;
670}
671
672static void __devinit rspi_request_dma(struct rspi_data *rspi,
673 struct platform_device *pdev)
674{
675 struct rspi_plat_data *rspi_pd = pdev->dev.platform_data;
676 dma_cap_mask_t mask;
677
678 if (!rspi_pd)
679 return;
680
681 rspi->dma_width_16bit = rspi_pd->dma_width_16bit;
682
683 /* If the module receives data by DMAC, it also needs TX DMAC */
684 if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
685 dma_cap_zero(mask);
686 dma_cap_set(DMA_SLAVE, mask);
687 rspi->dma_rx.slave_id = rspi_pd->dma_rx_id;
688 rspi->chan_rx = dma_request_channel(mask, rspi_filter,
689 &rspi->dma_rx);
690 if (rspi->chan_rx)
691 dev_info(&pdev->dev, "Use DMA when rx.\n");
692 }
693 if (rspi_pd->dma_tx_id) {
694 dma_cap_zero(mask);
695 dma_cap_set(DMA_SLAVE, mask);
696 rspi->dma_tx.slave_id = rspi_pd->dma_tx_id;
697 rspi->chan_tx = dma_request_channel(mask, rspi_filter,
698 &rspi->dma_tx);
699 if (rspi->chan_tx)
700 dev_info(&pdev->dev, "Use DMA when tx\n");
701 }
702}
703
704static void __devexit rspi_release_dma(struct rspi_data *rspi)
705{
706 if (rspi->chan_tx)
707 dma_release_channel(rspi->chan_tx);
708 if (rspi->chan_rx)
709 dma_release_channel(rspi->chan_rx);
710}
711
712static int __devexit rspi_remove(struct platform_device *pdev)
713{
714 struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
715
716 spi_unregister_master(rspi->master);
717 rspi_release_dma(rspi);
718 free_irq(platform_get_irq(pdev, 0), rspi);
719 clk_put(rspi->clk);
720 iounmap(rspi->addr);
721 spi_master_put(rspi->master);
722
723 return 0;
724}
725
726static int __devinit rspi_probe(struct platform_device *pdev)
727{
728 struct resource *res;
729 struct spi_master *master;
730 struct rspi_data *rspi;
731 int ret, irq;
732 char clk_name[16];
733
734 /* get base addr */
735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 if (unlikely(res == NULL)) {
737 dev_err(&pdev->dev, "invalid resource\n");
738 return -EINVAL;
739 }
740
741 irq = platform_get_irq(pdev, 0);
742 if (irq < 0) {
743 dev_err(&pdev->dev, "platform_get_irq error\n");
744 return -ENODEV;
745 }
746
747 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
748 if (master == NULL) {
749 dev_err(&pdev->dev, "spi_alloc_master error.\n");
750 return -ENOMEM;
751 }
752
753 rspi = spi_master_get_devdata(master);
754 dev_set_drvdata(&pdev->dev, rspi);
755
756 rspi->master = master;
757 rspi->addr = ioremap(res->start, resource_size(res));
758 if (rspi->addr == NULL) {
759 dev_err(&pdev->dev, "ioremap error.\n");
760 ret = -ENOMEM;
761 goto error1;
762 }
763
764 snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
765 rspi->clk = clk_get(&pdev->dev, clk_name);
766 if (IS_ERR(rspi->clk)) {
767 dev_err(&pdev->dev, "cannot get clock\n");
768 ret = PTR_ERR(rspi->clk);
769 goto error2;
770 }
771 clk_enable(rspi->clk);
772
773 INIT_LIST_HEAD(&rspi->queue);
774 spin_lock_init(&rspi->lock);
775 INIT_WORK(&rspi->ws, rspi_work);
776 init_waitqueue_head(&rspi->wait);
777
778 master->num_chipselect = 2;
779 master->bus_num = pdev->id;
780 master->setup = rspi_setup;
781 master->transfer = rspi_transfer;
782 master->cleanup = rspi_cleanup;
783
784 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
785 if (ret < 0) {
786 dev_err(&pdev->dev, "request_irq error\n");
787 goto error3;
788 }
789
790 rspi->irq = irq;
791 rspi_request_dma(rspi, pdev);
792
793 ret = spi_register_master(master);
794 if (ret < 0) {
795 dev_err(&pdev->dev, "spi_register_master error.\n");
796 goto error4;
797 }
798
799 dev_info(&pdev->dev, "probed\n");
800
801 return 0;
802
803error4:
804 rspi_release_dma(rspi);
805 free_irq(irq, rspi);
806error3:
807 clk_put(rspi->clk);
808error2:
809 iounmap(rspi->addr);
810error1:
811 spi_master_put(master);
812
813 return ret;
814}
815
816static struct platform_driver rspi_driver = {
817 .probe = rspi_probe,
818 .remove = __devexit_p(rspi_remove),
819 .driver = {
820 .name = "rspi",
821 .owner = THIS_MODULE,
822 },
823};
824module_platform_driver(rspi_driver);
825
826MODULE_DESCRIPTION("Renesas RSPI bus driver");
827MODULE_LICENSE("GPL v2");
828MODULE_AUTHOR("Yoshihiro Shimoda");
829MODULE_ALIAS("platform:rspi");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH RSPI driver
4 *
5 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
6 * Copyright (C) 2014 Glider bvba
7 *
8 * Based on spi-sh.c:
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/of_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/sh_dma.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/rspi.h>
27#include <linux/spinlock.h>
28
29#define RSPI_SPCR 0x00 /* Control Register */
30#define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
31#define RSPI_SPPCR 0x02 /* Pin Control Register */
32#define RSPI_SPSR 0x03 /* Status Register */
33#define RSPI_SPDR 0x04 /* Data Register */
34#define RSPI_SPSCR 0x08 /* Sequence Control Register */
35#define RSPI_SPSSR 0x09 /* Sequence Status Register */
36#define RSPI_SPBR 0x0a /* Bit Rate Register */
37#define RSPI_SPDCR 0x0b /* Data Control Register */
38#define RSPI_SPCKD 0x0c /* Clock Delay Register */
39#define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
40#define RSPI_SPND 0x0e /* Next-Access Delay Register */
41#define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
42#define RSPI_SPCMD0 0x10 /* Command Register 0 */
43#define RSPI_SPCMD1 0x12 /* Command Register 1 */
44#define RSPI_SPCMD2 0x14 /* Command Register 2 */
45#define RSPI_SPCMD3 0x16 /* Command Register 3 */
46#define RSPI_SPCMD4 0x18 /* Command Register 4 */
47#define RSPI_SPCMD5 0x1a /* Command Register 5 */
48#define RSPI_SPCMD6 0x1c /* Command Register 6 */
49#define RSPI_SPCMD7 0x1e /* Command Register 7 */
50#define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
51#define RSPI_NUM_SPCMD 8
52#define RSPI_RZ_NUM_SPCMD 4
53#define QSPI_NUM_SPCMD 4
54
55/* RSPI on RZ only */
56#define RSPI_SPBFCR 0x20 /* Buffer Control Register */
57#define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
58
59/* QSPI only */
60#define QSPI_SPBFCR 0x18 /* Buffer Control Register */
61#define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
62#define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
63#define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
64#define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
65#define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
66#define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
67
68/* SPCR - Control Register */
69#define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
70#define SPCR_SPE 0x40 /* Function Enable */
71#define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
72#define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
73#define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
74#define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
75/* RSPI on SH only */
76#define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
77#define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
78/* QSPI on R-Car Gen2 only */
79#define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
80#define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
81
82/* SSLP - Slave Select Polarity Register */
83#define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */
84
85/* SPPCR - Pin Control Register */
86#define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
87#define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
88#define SPPCR_SPOM 0x04
89#define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
90#define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
91
92#define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
93#define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
94
95/* SPSR - Status Register */
96#define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
97#define SPSR_TEND 0x40 /* Transmit End */
98#define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
99#define SPSR_PERF 0x08 /* Parity Error Flag */
100#define SPSR_MODF 0x04 /* Mode Fault Error Flag */
101#define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
102#define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
103
104/* SPSCR - Sequence Control Register */
105#define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
106
107/* SPSSR - Sequence Status Register */
108#define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
109#define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
110
111/* SPDCR - Data Control Register */
112#define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
113#define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
114#define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
115#define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
116#define SPDCR_SPLWORD SPDCR_SPLW1
117#define SPDCR_SPLBYTE SPDCR_SPLW0
118#define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
119#define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
120#define SPDCR_SLSEL1 0x08
121#define SPDCR_SLSEL0 0x04
122#define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
123#define SPDCR_SPFC1 0x02
124#define SPDCR_SPFC0 0x01
125#define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
126
127/* SPCKD - Clock Delay Register */
128#define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
129
130/* SSLND - Slave Select Negation Delay Register */
131#define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
132
133/* SPND - Next-Access Delay Register */
134#define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
135
136/* SPCR2 - Control Register 2 */
137#define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
138#define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
139#define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
140#define SPCR2_SPPE 0x01 /* Parity Enable */
141
142/* SPCMDn - Command Registers */
143#define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
144#define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
145#define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
146#define SPCMD_LSBF 0x1000 /* LSB First */
147#define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
148#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
149#define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
150#define SPCMD_SPB_16BIT 0x0100
151#define SPCMD_SPB_20BIT 0x0000
152#define SPCMD_SPB_24BIT 0x0100
153#define SPCMD_SPB_32BIT 0x0200
154#define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
155#define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
156#define SPCMD_SPIMOD1 0x0040
157#define SPCMD_SPIMOD0 0x0020
158#define SPCMD_SPIMOD_SINGLE 0
159#define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
160#define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
161#define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
162#define SPCMD_SSLA(i) ((i) << 4) /* SSL Assert Signal Setting */
163#define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
164#define SPCMD_BRDV(brdv) ((brdv) << 2)
165#define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
166#define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
167
168/* SPBFCR - Buffer Control Register */
169#define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
170#define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
171#define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
172#define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
173/* QSPI on R-Car Gen2 */
174#define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
175#define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
176#define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
177#define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
178
179#define QSPI_BUFFER_SIZE 32u
180
181struct rspi_data {
182 void __iomem *addr;
183 u32 speed_hz;
184 struct spi_controller *ctlr;
185 struct platform_device *pdev;
186 wait_queue_head_t wait;
187 spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */
188 struct clk *clk;
189 u16 spcmd;
190 u8 spsr;
191 u8 sppcr;
192 int rx_irq, tx_irq;
193 const struct spi_ops *ops;
194
195 unsigned dma_callbacked:1;
196 unsigned byte_access:1;
197};
198
199static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
200{
201 iowrite8(data, rspi->addr + offset);
202}
203
204static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
205{
206 iowrite16(data, rspi->addr + offset);
207}
208
209static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
210{
211 iowrite32(data, rspi->addr + offset);
212}
213
214static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
215{
216 return ioread8(rspi->addr + offset);
217}
218
219static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
220{
221 return ioread16(rspi->addr + offset);
222}
223
224static void rspi_write_data(const struct rspi_data *rspi, u16 data)
225{
226 if (rspi->byte_access)
227 rspi_write8(rspi, data, RSPI_SPDR);
228 else /* 16 bit */
229 rspi_write16(rspi, data, RSPI_SPDR);
230}
231
232static u16 rspi_read_data(const struct rspi_data *rspi)
233{
234 if (rspi->byte_access)
235 return rspi_read8(rspi, RSPI_SPDR);
236 else /* 16 bit */
237 return rspi_read16(rspi, RSPI_SPDR);
238}
239
240/* optional functions */
241struct spi_ops {
242 int (*set_config_register)(struct rspi_data *rspi, int access_size);
243 int (*transfer_one)(struct spi_controller *ctlr,
244 struct spi_device *spi, struct spi_transfer *xfer);
245 u16 extra_mode_bits;
246 u16 min_div;
247 u16 max_div;
248 u16 flags;
249 u16 fifo_size;
250 u8 num_hw_ss;
251};
252
253static void rspi_set_rate(struct rspi_data *rspi)
254{
255 unsigned long clksrc;
256 int brdv = 0, spbr;
257
258 clksrc = clk_get_rate(rspi->clk);
259 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
260 while (spbr > 255 && brdv < 3) {
261 brdv++;
262 spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
263 }
264
265 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
266 rspi->spcmd |= SPCMD_BRDV(brdv);
267 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
268}
269
270/*
271 * functions for RSPI on legacy SH
272 */
273static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
274{
275 /* Sets output mode, MOSI signal, and (optionally) loopback */
276 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
277
278 /* Sets transfer bit rate */
279 rspi_set_rate(rspi);
280
281 /* Disable dummy transmission, set 16-bit word access, 1 frame */
282 rspi_write8(rspi, 0, RSPI_SPDCR);
283 rspi->byte_access = 0;
284
285 /* Sets RSPCK, SSL, next-access delay value */
286 rspi_write8(rspi, 0x00, RSPI_SPCKD);
287 rspi_write8(rspi, 0x00, RSPI_SSLND);
288 rspi_write8(rspi, 0x00, RSPI_SPND);
289
290 /* Sets parity, interrupt mask */
291 rspi_write8(rspi, 0x00, RSPI_SPCR2);
292
293 /* Resets sequencer */
294 rspi_write8(rspi, 0, RSPI_SPSCR);
295 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
296 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
297
298 /* Sets RSPI mode */
299 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
300
301 return 0;
302}
303
304/*
305 * functions for RSPI on RZ
306 */
307static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
308{
309 /* Sets output mode, MOSI signal, and (optionally) loopback */
310 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
311
312 /* Sets transfer bit rate */
313 rspi_set_rate(rspi);
314
315 /* Disable dummy transmission, set byte access */
316 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
317 rspi->byte_access = 1;
318
319 /* Sets RSPCK, SSL, next-access delay value */
320 rspi_write8(rspi, 0x00, RSPI_SPCKD);
321 rspi_write8(rspi, 0x00, RSPI_SSLND);
322 rspi_write8(rspi, 0x00, RSPI_SPND);
323
324 /* Resets sequencer */
325 rspi_write8(rspi, 0, RSPI_SPSCR);
326 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
327 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
328
329 /* Sets RSPI mode */
330 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
331
332 return 0;
333}
334
335/*
336 * functions for QSPI
337 */
338static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
339{
340 unsigned long clksrc;
341 int brdv = 0, spbr;
342
343 /* Sets output mode, MOSI signal, and (optionally) loopback */
344 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
345
346 /* Sets transfer bit rate */
347 clksrc = clk_get_rate(rspi->clk);
348 if (rspi->speed_hz >= clksrc) {
349 spbr = 0;
350 rspi->speed_hz = clksrc;
351 } else {
352 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
353 while (spbr > 255 && brdv < 3) {
354 brdv++;
355 spbr = DIV_ROUND_UP(spbr, 2);
356 }
357 spbr = clamp(spbr, 0, 255);
358 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
359 }
360 rspi_write8(rspi, spbr, RSPI_SPBR);
361 rspi->spcmd |= SPCMD_BRDV(brdv);
362
363 /* Disable dummy transmission, set byte access */
364 rspi_write8(rspi, 0, RSPI_SPDCR);
365 rspi->byte_access = 1;
366
367 /* Sets RSPCK, SSL, next-access delay value */
368 rspi_write8(rspi, 0x00, RSPI_SPCKD);
369 rspi_write8(rspi, 0x00, RSPI_SSLND);
370 rspi_write8(rspi, 0x00, RSPI_SPND);
371
372 /* Data Length Setting */
373 if (access_size == 8)
374 rspi->spcmd |= SPCMD_SPB_8BIT;
375 else if (access_size == 16)
376 rspi->spcmd |= SPCMD_SPB_16BIT;
377 else
378 rspi->spcmd |= SPCMD_SPB_32BIT;
379
380 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
381
382 /* Resets transfer data length */
383 rspi_write32(rspi, 0, QSPI_SPBMUL0);
384
385 /* Resets transmit and receive buffer */
386 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
387 /* Sets buffer to allow normal operation */
388 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
389
390 /* Resets sequencer */
391 rspi_write8(rspi, 0, RSPI_SPSCR);
392 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
393
394 /* Sets RSPI mode */
395 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
396
397 return 0;
398}
399
400static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
401{
402 u8 data;
403
404 data = rspi_read8(rspi, reg);
405 data &= ~mask;
406 data |= (val & mask);
407 rspi_write8(rspi, data, reg);
408}
409
410static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
411 unsigned int len)
412{
413 unsigned int n;
414
415 n = min(len, QSPI_BUFFER_SIZE);
416
417 if (len >= QSPI_BUFFER_SIZE) {
418 /* sets triggering number to 32 bytes */
419 qspi_update(rspi, SPBFCR_TXTRG_MASK,
420 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
421 } else {
422 /* sets triggering number to 1 byte */
423 qspi_update(rspi, SPBFCR_TXTRG_MASK,
424 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
425 }
426
427 return n;
428}
429
430static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
431{
432 unsigned int n;
433
434 n = min(len, QSPI_BUFFER_SIZE);
435
436 if (len >= QSPI_BUFFER_SIZE) {
437 /* sets triggering number to 32 bytes */
438 qspi_update(rspi, SPBFCR_RXTRG_MASK,
439 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
440 } else {
441 /* sets triggering number to 1 byte */
442 qspi_update(rspi, SPBFCR_RXTRG_MASK,
443 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
444 }
445 return n;
446}
447
448static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
449{
450 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
451}
452
453static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
454{
455 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
456}
457
458static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
459 u8 enable_bit)
460{
461 int ret;
462
463 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
464 if (rspi->spsr & wait_mask)
465 return 0;
466
467 rspi_enable_irq(rspi, enable_bit);
468 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
469 if (ret == 0 && !(rspi->spsr & wait_mask))
470 return -ETIMEDOUT;
471
472 return 0;
473}
474
475static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
476{
477 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
478}
479
480static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
481{
482 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
483}
484
485static int rspi_data_out(struct rspi_data *rspi, u8 data)
486{
487 int error = rspi_wait_for_tx_empty(rspi);
488 if (error < 0) {
489 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
490 return error;
491 }
492 rspi_write_data(rspi, data);
493 return 0;
494}
495
496static int rspi_data_in(struct rspi_data *rspi)
497{
498 int error;
499 u8 data;
500
501 error = rspi_wait_for_rx_full(rspi);
502 if (error < 0) {
503 dev_err(&rspi->ctlr->dev, "receive timeout\n");
504 return error;
505 }
506 data = rspi_read_data(rspi);
507 return data;
508}
509
510static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
511 unsigned int n)
512{
513 while (n-- > 0) {
514 if (tx) {
515 int ret = rspi_data_out(rspi, *tx++);
516 if (ret < 0)
517 return ret;
518 }
519 if (rx) {
520 int ret = rspi_data_in(rspi);
521 if (ret < 0)
522 return ret;
523 *rx++ = ret;
524 }
525 }
526
527 return 0;
528}
529
530static void rspi_dma_complete(void *arg)
531{
532 struct rspi_data *rspi = arg;
533
534 rspi->dma_callbacked = 1;
535 wake_up_interruptible(&rspi->wait);
536}
537
538static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
539 struct sg_table *rx)
540{
541 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
542 u8 irq_mask = 0;
543 unsigned int other_irq = 0;
544 dma_cookie_t cookie;
545 int ret;
546
547 /* First prepare and submit the DMA request(s), as this may fail */
548 if (rx) {
549 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
550 rx->nents, DMA_DEV_TO_MEM,
551 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
552 if (!desc_rx) {
553 ret = -EAGAIN;
554 goto no_dma_rx;
555 }
556
557 desc_rx->callback = rspi_dma_complete;
558 desc_rx->callback_param = rspi;
559 cookie = dmaengine_submit(desc_rx);
560 if (dma_submit_error(cookie)) {
561 ret = cookie;
562 goto no_dma_rx;
563 }
564
565 irq_mask |= SPCR_SPRIE;
566 }
567
568 if (tx) {
569 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
570 tx->nents, DMA_MEM_TO_DEV,
571 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
572 if (!desc_tx) {
573 ret = -EAGAIN;
574 goto no_dma_tx;
575 }
576
577 if (rx) {
578 /* No callback */
579 desc_tx->callback = NULL;
580 } else {
581 desc_tx->callback = rspi_dma_complete;
582 desc_tx->callback_param = rspi;
583 }
584 cookie = dmaengine_submit(desc_tx);
585 if (dma_submit_error(cookie)) {
586 ret = cookie;
587 goto no_dma_tx;
588 }
589
590 irq_mask |= SPCR_SPTIE;
591 }
592
593 /*
594 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
595 * called. So, this driver disables the IRQ while DMA transfer.
596 */
597 if (tx)
598 disable_irq(other_irq = rspi->tx_irq);
599 if (rx && rspi->rx_irq != other_irq)
600 disable_irq(rspi->rx_irq);
601
602 rspi_enable_irq(rspi, irq_mask);
603 rspi->dma_callbacked = 0;
604
605 /* Now start DMA */
606 if (rx)
607 dma_async_issue_pending(rspi->ctlr->dma_rx);
608 if (tx)
609 dma_async_issue_pending(rspi->ctlr->dma_tx);
610
611 ret = wait_event_interruptible_timeout(rspi->wait,
612 rspi->dma_callbacked, HZ);
613 if (ret > 0 && rspi->dma_callbacked) {
614 ret = 0;
615 } else {
616 if (!ret) {
617 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
618 ret = -ETIMEDOUT;
619 }
620 if (tx)
621 dmaengine_terminate_sync(rspi->ctlr->dma_tx);
622 if (rx)
623 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
624 }
625
626 rspi_disable_irq(rspi, irq_mask);
627
628 if (tx)
629 enable_irq(rspi->tx_irq);
630 if (rx && rspi->rx_irq != other_irq)
631 enable_irq(rspi->rx_irq);
632
633 return ret;
634
635no_dma_tx:
636 if (rx)
637 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
638no_dma_rx:
639 if (ret == -EAGAIN) {
640 dev_warn_once(&rspi->ctlr->dev,
641 "DMA not available, falling back to PIO\n");
642 }
643 return ret;
644}
645
646static void rspi_receive_init(const struct rspi_data *rspi)
647{
648 u8 spsr;
649
650 spsr = rspi_read8(rspi, RSPI_SPSR);
651 if (spsr & SPSR_SPRF)
652 rspi_read_data(rspi); /* dummy read */
653 if (spsr & SPSR_OVRF)
654 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
655 RSPI_SPSR);
656}
657
658static void rspi_rz_receive_init(const struct rspi_data *rspi)
659{
660 rspi_receive_init(rspi);
661 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
662 rspi_write8(rspi, 0, RSPI_SPBFCR);
663}
664
665static void qspi_receive_init(const struct rspi_data *rspi)
666{
667 u8 spsr;
668
669 spsr = rspi_read8(rspi, RSPI_SPSR);
670 if (spsr & SPSR_SPRF)
671 rspi_read_data(rspi); /* dummy read */
672 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
673 rspi_write8(rspi, 0, QSPI_SPBFCR);
674}
675
676static bool __rspi_can_dma(const struct rspi_data *rspi,
677 const struct spi_transfer *xfer)
678{
679 return xfer->len > rspi->ops->fifo_size;
680}
681
682static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
683 struct spi_transfer *xfer)
684{
685 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
686
687 return __rspi_can_dma(rspi, xfer);
688}
689
690static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
691 struct spi_transfer *xfer)
692{
693 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
694 return -EAGAIN;
695
696 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
697 return rspi_dma_transfer(rspi, &xfer->tx_sg,
698 xfer->rx_buf ? &xfer->rx_sg : NULL);
699}
700
701static int rspi_common_transfer(struct rspi_data *rspi,
702 struct spi_transfer *xfer)
703{
704 int ret;
705
706 xfer->effective_speed_hz = rspi->speed_hz;
707
708 ret = rspi_dma_check_then_transfer(rspi, xfer);
709 if (ret != -EAGAIN)
710 return ret;
711
712 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
713 if (ret < 0)
714 return ret;
715
716 /* Wait for the last transmission */
717 rspi_wait_for_tx_empty(rspi);
718
719 return 0;
720}
721
722static int rspi_transfer_one(struct spi_controller *ctlr,
723 struct spi_device *spi, struct spi_transfer *xfer)
724{
725 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
726 u8 spcr;
727
728 spcr = rspi_read8(rspi, RSPI_SPCR);
729 if (xfer->rx_buf) {
730 rspi_receive_init(rspi);
731 spcr &= ~SPCR_TXMD;
732 } else {
733 spcr |= SPCR_TXMD;
734 }
735 rspi_write8(rspi, spcr, RSPI_SPCR);
736
737 return rspi_common_transfer(rspi, xfer);
738}
739
740static int rspi_rz_transfer_one(struct spi_controller *ctlr,
741 struct spi_device *spi,
742 struct spi_transfer *xfer)
743{
744 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
745
746 rspi_rz_receive_init(rspi);
747
748 return rspi_common_transfer(rspi, xfer);
749}
750
751static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
752 u8 *rx, unsigned int len)
753{
754 unsigned int i, n;
755 int ret;
756
757 while (len > 0) {
758 n = qspi_set_send_trigger(rspi, len);
759 qspi_set_receive_trigger(rspi, len);
760 ret = rspi_wait_for_tx_empty(rspi);
761 if (ret < 0) {
762 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
763 return ret;
764 }
765 for (i = 0; i < n; i++)
766 rspi_write_data(rspi, *tx++);
767
768 ret = rspi_wait_for_rx_full(rspi);
769 if (ret < 0) {
770 dev_err(&rspi->ctlr->dev, "receive timeout\n");
771 return ret;
772 }
773 for (i = 0; i < n; i++)
774 *rx++ = rspi_read_data(rspi);
775
776 len -= n;
777 }
778
779 return 0;
780}
781
782static int qspi_transfer_out_in(struct rspi_data *rspi,
783 struct spi_transfer *xfer)
784{
785 int ret;
786
787 qspi_receive_init(rspi);
788
789 ret = rspi_dma_check_then_transfer(rspi, xfer);
790 if (ret != -EAGAIN)
791 return ret;
792
793 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
794 xfer->rx_buf, xfer->len);
795}
796
797static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
798{
799 const u8 *tx = xfer->tx_buf;
800 unsigned int n = xfer->len;
801 unsigned int i, len;
802 int ret;
803
804 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
805 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
806 if (ret != -EAGAIN)
807 return ret;
808 }
809
810 while (n > 0) {
811 len = qspi_set_send_trigger(rspi, n);
812 ret = rspi_wait_for_tx_empty(rspi);
813 if (ret < 0) {
814 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
815 return ret;
816 }
817 for (i = 0; i < len; i++)
818 rspi_write_data(rspi, *tx++);
819
820 n -= len;
821 }
822
823 /* Wait for the last transmission */
824 rspi_wait_for_tx_empty(rspi);
825
826 return 0;
827}
828
829static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
830{
831 u8 *rx = xfer->rx_buf;
832 unsigned int n = xfer->len;
833 unsigned int i, len;
834 int ret;
835
836 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
837 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
838 if (ret != -EAGAIN)
839 return ret;
840 }
841
842 while (n > 0) {
843 len = qspi_set_receive_trigger(rspi, n);
844 ret = rspi_wait_for_rx_full(rspi);
845 if (ret < 0) {
846 dev_err(&rspi->ctlr->dev, "receive timeout\n");
847 return ret;
848 }
849 for (i = 0; i < len; i++)
850 *rx++ = rspi_read_data(rspi);
851
852 n -= len;
853 }
854
855 return 0;
856}
857
858static int qspi_transfer_one(struct spi_controller *ctlr,
859 struct spi_device *spi, struct spi_transfer *xfer)
860{
861 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
862
863 xfer->effective_speed_hz = rspi->speed_hz;
864 if (spi->mode & SPI_LOOP) {
865 return qspi_transfer_out_in(rspi, xfer);
866 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
867 /* Quad or Dual SPI Write */
868 return qspi_transfer_out(rspi, xfer);
869 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
870 /* Quad or Dual SPI Read */
871 return qspi_transfer_in(rspi, xfer);
872 } else {
873 /* Single SPI Transfer */
874 return qspi_transfer_out_in(rspi, xfer);
875 }
876}
877
878static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
879{
880 if (xfer->tx_buf)
881 switch (xfer->tx_nbits) {
882 case SPI_NBITS_QUAD:
883 return SPCMD_SPIMOD_QUAD;
884 case SPI_NBITS_DUAL:
885 return SPCMD_SPIMOD_DUAL;
886 default:
887 return 0;
888 }
889 if (xfer->rx_buf)
890 switch (xfer->rx_nbits) {
891 case SPI_NBITS_QUAD:
892 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
893 case SPI_NBITS_DUAL:
894 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
895 default:
896 return 0;
897 }
898
899 return 0;
900}
901
902static int qspi_setup_sequencer(struct rspi_data *rspi,
903 const struct spi_message *msg)
904{
905 const struct spi_transfer *xfer;
906 unsigned int i = 0, len = 0;
907 u16 current_mode = 0xffff, mode;
908
909 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
910 mode = qspi_transfer_mode(xfer);
911 if (mode == current_mode) {
912 len += xfer->len;
913 continue;
914 }
915
916 /* Transfer mode change */
917 if (i) {
918 /* Set transfer data length of previous transfer */
919 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
920 }
921
922 if (i >= QSPI_NUM_SPCMD) {
923 dev_err(&msg->spi->dev,
924 "Too many different transfer modes");
925 return -EINVAL;
926 }
927
928 /* Program transfer mode for this transfer */
929 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
930 current_mode = mode;
931 len = xfer->len;
932 i++;
933 }
934 if (i) {
935 /* Set final transfer data length and sequence length */
936 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
937 rspi_write8(rspi, i - 1, RSPI_SPSCR);
938 }
939
940 return 0;
941}
942
943static int rspi_setup(struct spi_device *spi)
944{
945 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
946 u8 sslp;
947
948 if (spi->cs_gpiod)
949 return 0;
950
951 pm_runtime_get_sync(&rspi->pdev->dev);
952 spin_lock_irq(&rspi->lock);
953
954 sslp = rspi_read8(rspi, RSPI_SSLP);
955 if (spi->mode & SPI_CS_HIGH)
956 sslp |= SSLP_SSLP(spi->chip_select);
957 else
958 sslp &= ~SSLP_SSLP(spi->chip_select);
959 rspi_write8(rspi, sslp, RSPI_SSLP);
960
961 spin_unlock_irq(&rspi->lock);
962 pm_runtime_put(&rspi->pdev->dev);
963 return 0;
964}
965
966static int rspi_prepare_message(struct spi_controller *ctlr,
967 struct spi_message *msg)
968{
969 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
970 struct spi_device *spi = msg->spi;
971 const struct spi_transfer *xfer;
972 int ret;
973
974 /*
975 * As the Bit Rate Register must not be changed while the device is
976 * active, all transfers in a message must use the same bit rate.
977 * In theory, the sequencer could be enabled, and each Command Register
978 * could divide the base bit rate by a different value.
979 * However, most RSPI variants do not have Transfer Data Length
980 * Multiplier Setting Registers, so each sequence step would be limited
981 * to a single word, making this feature unsuitable for large
982 * transfers, which would gain most from it.
983 */
984 rspi->speed_hz = spi->max_speed_hz;
985 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
986 if (xfer->speed_hz < rspi->speed_hz)
987 rspi->speed_hz = xfer->speed_hz;
988 }
989
990 rspi->spcmd = SPCMD_SSLKP;
991 if (spi->mode & SPI_CPOL)
992 rspi->spcmd |= SPCMD_CPOL;
993 if (spi->mode & SPI_CPHA)
994 rspi->spcmd |= SPCMD_CPHA;
995 if (spi->mode & SPI_LSB_FIRST)
996 rspi->spcmd |= SPCMD_LSBF;
997
998 /* Configure slave signal to assert */
999 rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs
1000 : spi->chip_select);
1001
1002 /* CMOS output mode and MOSI signal from previous transfer */
1003 rspi->sppcr = 0;
1004 if (spi->mode & SPI_LOOP)
1005 rspi->sppcr |= SPPCR_SPLP;
1006
1007 rspi->ops->set_config_register(rspi, 8);
1008
1009 if (msg->spi->mode &
1010 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
1011 /* Setup sequencer for messages with multiple transfer modes */
1012 ret = qspi_setup_sequencer(rspi, msg);
1013 if (ret < 0)
1014 return ret;
1015 }
1016
1017 /* Enable SPI function in master mode */
1018 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1019 return 0;
1020}
1021
1022static int rspi_unprepare_message(struct spi_controller *ctlr,
1023 struct spi_message *msg)
1024{
1025 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1026
1027 /* Disable SPI function */
1028 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1029
1030 /* Reset sequencer for Single SPI Transfers */
1031 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1032 rspi_write8(rspi, 0, RSPI_SPSCR);
1033 return 0;
1034}
1035
1036static irqreturn_t rspi_irq_mux(int irq, void *_sr)
1037{
1038 struct rspi_data *rspi = _sr;
1039 u8 spsr;
1040 irqreturn_t ret = IRQ_NONE;
1041 u8 disable_irq = 0;
1042
1043 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1044 if (spsr & SPSR_SPRF)
1045 disable_irq |= SPCR_SPRIE;
1046 if (spsr & SPSR_SPTEF)
1047 disable_irq |= SPCR_SPTIE;
1048
1049 if (disable_irq) {
1050 ret = IRQ_HANDLED;
1051 rspi_disable_irq(rspi, disable_irq);
1052 wake_up(&rspi->wait);
1053 }
1054
1055 return ret;
1056}
1057
1058static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1059{
1060 struct rspi_data *rspi = _sr;
1061 u8 spsr;
1062
1063 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1064 if (spsr & SPSR_SPRF) {
1065 rspi_disable_irq(rspi, SPCR_SPRIE);
1066 wake_up(&rspi->wait);
1067 return IRQ_HANDLED;
1068 }
1069
1070 return 0;
1071}
1072
1073static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1074{
1075 struct rspi_data *rspi = _sr;
1076 u8 spsr;
1077
1078 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1079 if (spsr & SPSR_SPTEF) {
1080 rspi_disable_irq(rspi, SPCR_SPTIE);
1081 wake_up(&rspi->wait);
1082 return IRQ_HANDLED;
1083 }
1084
1085 return 0;
1086}
1087
1088static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1089 enum dma_transfer_direction dir,
1090 unsigned int id,
1091 dma_addr_t port_addr)
1092{
1093 dma_cap_mask_t mask;
1094 struct dma_chan *chan;
1095 struct dma_slave_config cfg;
1096 int ret;
1097
1098 dma_cap_zero(mask);
1099 dma_cap_set(DMA_SLAVE, mask);
1100
1101 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1102 (void *)(unsigned long)id, dev,
1103 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1104 if (!chan) {
1105 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1106 return NULL;
1107 }
1108
1109 memset(&cfg, 0, sizeof(cfg));
1110 cfg.direction = dir;
1111 if (dir == DMA_MEM_TO_DEV) {
1112 cfg.dst_addr = port_addr;
1113 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1114 } else {
1115 cfg.src_addr = port_addr;
1116 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1117 }
1118
1119 ret = dmaengine_slave_config(chan, &cfg);
1120 if (ret) {
1121 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1122 dma_release_channel(chan);
1123 return NULL;
1124 }
1125
1126 return chan;
1127}
1128
1129static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1130 const struct resource *res)
1131{
1132 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1133 unsigned int dma_tx_id, dma_rx_id;
1134
1135 if (dev->of_node) {
1136 /* In the OF case we will get the slave IDs from the DT */
1137 dma_tx_id = 0;
1138 dma_rx_id = 0;
1139 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1140 dma_tx_id = rspi_pd->dma_tx_id;
1141 dma_rx_id = rspi_pd->dma_rx_id;
1142 } else {
1143 /* The driver assumes no error. */
1144 return 0;
1145 }
1146
1147 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1148 res->start + RSPI_SPDR);
1149 if (!ctlr->dma_tx)
1150 return -ENODEV;
1151
1152 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1153 res->start + RSPI_SPDR);
1154 if (!ctlr->dma_rx) {
1155 dma_release_channel(ctlr->dma_tx);
1156 ctlr->dma_tx = NULL;
1157 return -ENODEV;
1158 }
1159
1160 ctlr->can_dma = rspi_can_dma;
1161 dev_info(dev, "DMA available");
1162 return 0;
1163}
1164
1165static void rspi_release_dma(struct spi_controller *ctlr)
1166{
1167 if (ctlr->dma_tx)
1168 dma_release_channel(ctlr->dma_tx);
1169 if (ctlr->dma_rx)
1170 dma_release_channel(ctlr->dma_rx);
1171}
1172
1173static int rspi_remove(struct platform_device *pdev)
1174{
1175 struct rspi_data *rspi = platform_get_drvdata(pdev);
1176
1177 rspi_release_dma(rspi->ctlr);
1178 pm_runtime_disable(&pdev->dev);
1179
1180 return 0;
1181}
1182
1183static const struct spi_ops rspi_ops = {
1184 .set_config_register = rspi_set_config_register,
1185 .transfer_one = rspi_transfer_one,
1186 .min_div = 2,
1187 .max_div = 4096,
1188 .flags = SPI_CONTROLLER_MUST_TX,
1189 .fifo_size = 8,
1190 .num_hw_ss = 2,
1191};
1192
1193static const struct spi_ops rspi_rz_ops = {
1194 .set_config_register = rspi_rz_set_config_register,
1195 .transfer_one = rspi_rz_transfer_one,
1196 .min_div = 2,
1197 .max_div = 4096,
1198 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1199 .fifo_size = 8, /* 8 for TX, 32 for RX */
1200 .num_hw_ss = 1,
1201};
1202
1203static const struct spi_ops qspi_ops = {
1204 .set_config_register = qspi_set_config_register,
1205 .transfer_one = qspi_transfer_one,
1206 .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD |
1207 SPI_RX_DUAL | SPI_RX_QUAD,
1208 .min_div = 1,
1209 .max_div = 4080,
1210 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1211 .fifo_size = 32,
1212 .num_hw_ss = 1,
1213};
1214
1215#ifdef CONFIG_OF
1216static const struct of_device_id rspi_of_match[] = {
1217 /* RSPI on legacy SH */
1218 { .compatible = "renesas,rspi", .data = &rspi_ops },
1219 /* RSPI on RZ/A1H */
1220 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1221 /* QSPI on R-Car Gen2 */
1222 { .compatible = "renesas,qspi", .data = &qspi_ops },
1223 { /* sentinel */ }
1224};
1225
1226MODULE_DEVICE_TABLE(of, rspi_of_match);
1227
1228static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1229{
1230 u32 num_cs;
1231 int error;
1232
1233 /* Parse DT properties */
1234 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1235 if (error) {
1236 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1237 return error;
1238 }
1239
1240 ctlr->num_chipselect = num_cs;
1241 return 0;
1242}
1243#else
1244#define rspi_of_match NULL
1245static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1246{
1247 return -EINVAL;
1248}
1249#endif /* CONFIG_OF */
1250
1251static int rspi_request_irq(struct device *dev, unsigned int irq,
1252 irq_handler_t handler, const char *suffix,
1253 void *dev_id)
1254{
1255 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1256 dev_name(dev), suffix);
1257 if (!name)
1258 return -ENOMEM;
1259
1260 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1261}
1262
1263static int rspi_probe(struct platform_device *pdev)
1264{
1265 struct resource *res;
1266 struct spi_controller *ctlr;
1267 struct rspi_data *rspi;
1268 int ret;
1269 const struct rspi_plat_data *rspi_pd;
1270 const struct spi_ops *ops;
1271 unsigned long clksrc;
1272
1273 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1274 if (ctlr == NULL)
1275 return -ENOMEM;
1276
1277 ops = of_device_get_match_data(&pdev->dev);
1278 if (ops) {
1279 ret = rspi_parse_dt(&pdev->dev, ctlr);
1280 if (ret)
1281 goto error1;
1282 } else {
1283 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1284 rspi_pd = dev_get_platdata(&pdev->dev);
1285 if (rspi_pd && rspi_pd->num_chipselect)
1286 ctlr->num_chipselect = rspi_pd->num_chipselect;
1287 else
1288 ctlr->num_chipselect = 2; /* default */
1289 }
1290
1291 rspi = spi_controller_get_devdata(ctlr);
1292 platform_set_drvdata(pdev, rspi);
1293 rspi->ops = ops;
1294 rspi->ctlr = ctlr;
1295
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1298 if (IS_ERR(rspi->addr)) {
1299 ret = PTR_ERR(rspi->addr);
1300 goto error1;
1301 }
1302
1303 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1304 if (IS_ERR(rspi->clk)) {
1305 dev_err(&pdev->dev, "cannot get clock\n");
1306 ret = PTR_ERR(rspi->clk);
1307 goto error1;
1308 }
1309
1310 rspi->pdev = pdev;
1311 pm_runtime_enable(&pdev->dev);
1312
1313 init_waitqueue_head(&rspi->wait);
1314 spin_lock_init(&rspi->lock);
1315
1316 ctlr->bus_num = pdev->id;
1317 ctlr->setup = rspi_setup;
1318 ctlr->auto_runtime_pm = true;
1319 ctlr->transfer_one = ops->transfer_one;
1320 ctlr->prepare_message = rspi_prepare_message;
1321 ctlr->unprepare_message = rspi_unprepare_message;
1322 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1323 SPI_LOOP | ops->extra_mode_bits;
1324 clksrc = clk_get_rate(rspi->clk);
1325 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, ops->max_div);
1326 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, ops->min_div);
1327 ctlr->flags = ops->flags;
1328 ctlr->dev.of_node = pdev->dev.of_node;
1329 ctlr->use_gpio_descriptors = true;
1330 ctlr->max_native_cs = rspi->ops->num_hw_ss;
1331
1332 ret = platform_get_irq_byname_optional(pdev, "rx");
1333 if (ret < 0) {
1334 ret = platform_get_irq_byname_optional(pdev, "mux");
1335 if (ret < 0)
1336 ret = platform_get_irq(pdev, 0);
1337 if (ret >= 0)
1338 rspi->rx_irq = rspi->tx_irq = ret;
1339 } else {
1340 rspi->rx_irq = ret;
1341 ret = platform_get_irq_byname(pdev, "tx");
1342 if (ret >= 0)
1343 rspi->tx_irq = ret;
1344 }
1345
1346 if (rspi->rx_irq == rspi->tx_irq) {
1347 /* Single multiplexed interrupt */
1348 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1349 "mux", rspi);
1350 } else {
1351 /* Multi-interrupt mode, only SPRI and SPTI are used */
1352 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1353 "rx", rspi);
1354 if (!ret)
1355 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1356 rspi_irq_tx, "tx", rspi);
1357 }
1358 if (ret < 0) {
1359 dev_err(&pdev->dev, "request_irq error\n");
1360 goto error2;
1361 }
1362
1363 ret = rspi_request_dma(&pdev->dev, ctlr, res);
1364 if (ret < 0)
1365 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1366
1367 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1368 if (ret < 0) {
1369 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1370 goto error3;
1371 }
1372
1373 dev_info(&pdev->dev, "probed\n");
1374
1375 return 0;
1376
1377error3:
1378 rspi_release_dma(ctlr);
1379error2:
1380 pm_runtime_disable(&pdev->dev);
1381error1:
1382 spi_controller_put(ctlr);
1383
1384 return ret;
1385}
1386
1387static const struct platform_device_id spi_driver_ids[] = {
1388 { "rspi", (kernel_ulong_t)&rspi_ops },
1389 {},
1390};
1391
1392MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1393
1394#ifdef CONFIG_PM_SLEEP
1395static int rspi_suspend(struct device *dev)
1396{
1397 struct rspi_data *rspi = dev_get_drvdata(dev);
1398
1399 return spi_controller_suspend(rspi->ctlr);
1400}
1401
1402static int rspi_resume(struct device *dev)
1403{
1404 struct rspi_data *rspi = dev_get_drvdata(dev);
1405
1406 return spi_controller_resume(rspi->ctlr);
1407}
1408
1409static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1410#define DEV_PM_OPS &rspi_pm_ops
1411#else
1412#define DEV_PM_OPS NULL
1413#endif /* CONFIG_PM_SLEEP */
1414
1415static struct platform_driver rspi_driver = {
1416 .probe = rspi_probe,
1417 .remove = rspi_remove,
1418 .id_table = spi_driver_ids,
1419 .driver = {
1420 .name = "renesas_spi",
1421 .pm = DEV_PM_OPS,
1422 .of_match_table = of_match_ptr(rspi_of_match),
1423 },
1424};
1425module_platform_driver(rspi_driver);
1426
1427MODULE_DESCRIPTION("Renesas RSPI bus driver");
1428MODULE_LICENSE("GPL v2");
1429MODULE_AUTHOR("Yoshihiro Shimoda");
1430MODULE_ALIAS("platform:rspi");