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1/*
2 * User-space Probes (UProbes) for x86
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2008-2011
19 * Authors:
20 * Srikar Dronamraju
21 * Jim Keniston
22 */
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/uaccess.h>
28
29#include <linux/kdebug.h>
30#include <asm/processor.h>
31#include <asm/insn.h>
32
33/* Post-execution fixups. */
34
35/* No fixup needed */
36#define UPROBE_FIX_NONE 0x0
37
38/* Adjust IP back to vicinity of actual insn */
39#define UPROBE_FIX_IP 0x1
40
41/* Adjust the return address of a call insn */
42#define UPROBE_FIX_CALL 0x2
43
44#define UPROBE_FIX_RIP_AX 0x8000
45#define UPROBE_FIX_RIP_CX 0x4000
46
47#define UPROBE_TRAP_NR UINT_MAX
48
49/* Adaptations for mhiramat x86 decoder v14. */
50#define OPCODE1(insn) ((insn)->opcode.bytes[0])
51#define OPCODE2(insn) ((insn)->opcode.bytes[1])
52#define OPCODE3(insn) ((insn)->opcode.bytes[2])
53#define MODRM_REG(insn) X86_MODRM_REG(insn->modrm.value)
54
55#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
56 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
57 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
58 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
59 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
60 << (row % 32))
61
62/*
63 * Good-instruction tables for 32-bit apps. This is non-const and volatile
64 * to keep gcc from statically optimizing it out, as variable_test_bit makes
65 * some versions of gcc to think only *(unsigned long*) is used.
66 */
67static volatile u32 good_insns_32[256 / 32] = {
68 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
69 /* ---------------------------------------------- */
70 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */
71 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
72 W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */
73 W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */
74 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
75 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
76 W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
77 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
78 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
79 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
80 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
81 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
82 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
83 W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
84 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
85 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
86 /* ---------------------------------------------- */
87 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
88};
89
90/* Using this for both 64-bit and 32-bit apps */
91static volatile u32 good_2byte_insns[256 / 32] = {
92 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
93 /* ---------------------------------------------- */
94 W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */
95 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
96 W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
97 W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */
98 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
99 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
100 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
101 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */
102 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
103 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
104 W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
105 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
106 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
107 W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
108 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
109 W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */
110 /* ---------------------------------------------- */
111 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
112};
113
114#ifdef CONFIG_X86_64
115/* Good-instruction tables for 64-bit apps */
116static volatile u32 good_insns_64[256 / 32] = {
117 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
118 /* ---------------------------------------------- */
119 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */
120 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
121 W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */
122 W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */
123 W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */
124 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
125 W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
126 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
127 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
128 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
129 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
130 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
131 W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
132 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
133 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
134 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
135 /* ---------------------------------------------- */
136 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
137};
138#endif
139#undef W
140
141/*
142 * opcodes we'll probably never support:
143 *
144 * 6c-6d, e4-e5, ec-ed - in
145 * 6e-6f, e6-e7, ee-ef - out
146 * cc, cd - int3, int
147 * cf - iret
148 * d6 - illegal instruction
149 * f1 - int1/icebp
150 * f4 - hlt
151 * fa, fb - cli, sti
152 * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2
153 *
154 * invalid opcodes in 64-bit mode:
155 *
156 * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5
157 * 63 - we support this opcode in x86_64 but not in i386.
158 *
159 * opcodes we may need to refine support for:
160 *
161 * 0f - 2-byte instructions: For many of these instructions, the validity
162 * depends on the prefix and/or the reg field. On such instructions, we
163 * just consider the opcode combination valid if it corresponds to any
164 * valid instruction.
165 *
166 * 8f - Group 1 - only reg = 0 is OK
167 * c6-c7 - Group 11 - only reg = 0 is OK
168 * d9-df - fpu insns with some illegal encodings
169 * f2, f3 - repnz, repz prefixes. These are also the first byte for
170 * certain floating-point instructions, such as addsd.
171 *
172 * fe - Group 4 - only reg = 0 or 1 is OK
173 * ff - Group 5 - only reg = 0-6 is OK
174 *
175 * others -- Do we need to support these?
176 *
177 * 0f - (floating-point?) prefetch instructions
178 * 07, 17, 1f - pop es, pop ss, pop ds
179 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
180 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
181 * 67 - addr16 prefix
182 * ce - into
183 * f0 - lock prefix
184 */
185
186/*
187 * TODO:
188 * - Where necessary, examine the modrm byte and allow only valid instructions
189 * in the different Groups and fpu instructions.
190 */
191
192static bool is_prefix_bad(struct insn *insn)
193{
194 int i;
195
196 for (i = 0; i < insn->prefixes.nbytes; i++) {
197 switch (insn->prefixes.bytes[i]) {
198 case 0x26: /* INAT_PFX_ES */
199 case 0x2E: /* INAT_PFX_CS */
200 case 0x36: /* INAT_PFX_DS */
201 case 0x3E: /* INAT_PFX_SS */
202 case 0xF0: /* INAT_PFX_LOCK */
203 return true;
204 }
205 }
206 return false;
207}
208
209static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn)
210{
211 insn_init(insn, auprobe->insn, false);
212
213 /* Skip good instruction prefixes; reject "bad" ones. */
214 insn_get_opcode(insn);
215 if (is_prefix_bad(insn))
216 return -ENOTSUPP;
217
218 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32))
219 return 0;
220
221 if (insn->opcode.nbytes == 2) {
222 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
223 return 0;
224 }
225
226 return -ENOTSUPP;
227}
228
229/*
230 * Figure out which fixups arch_uprobe_post_xol() will need to perform, and
231 * annotate arch_uprobe->fixups accordingly. To start with,
232 * arch_uprobe->fixups is either zero or it reflects rip-related fixups.
233 */
234static void prepare_fixups(struct arch_uprobe *auprobe, struct insn *insn)
235{
236 bool fix_ip = true, fix_call = false; /* defaults */
237 int reg;
238
239 insn_get_opcode(insn); /* should be a nop */
240
241 switch (OPCODE1(insn)) {
242 case 0xc3: /* ret/lret */
243 case 0xcb:
244 case 0xc2:
245 case 0xca:
246 /* ip is correct */
247 fix_ip = false;
248 break;
249 case 0xe8: /* call relative - Fix return addr */
250 fix_call = true;
251 break;
252 case 0x9a: /* call absolute - Fix return addr, not ip */
253 fix_call = true;
254 fix_ip = false;
255 break;
256 case 0xff:
257 insn_get_modrm(insn);
258 reg = MODRM_REG(insn);
259 if (reg == 2 || reg == 3) {
260 /* call or lcall, indirect */
261 /* Fix return addr; ip is correct. */
262 fix_call = true;
263 fix_ip = false;
264 } else if (reg == 4 || reg == 5) {
265 /* jmp or ljmp, indirect */
266 /* ip is correct. */
267 fix_ip = false;
268 }
269 break;
270 case 0xea: /* jmp absolute -- ip is correct */
271 fix_ip = false;
272 break;
273 default:
274 break;
275 }
276 if (fix_ip)
277 auprobe->fixups |= UPROBE_FIX_IP;
278 if (fix_call)
279 auprobe->fixups |= UPROBE_FIX_CALL;
280}
281
282#ifdef CONFIG_X86_64
283/*
284 * If arch_uprobe->insn doesn't use rip-relative addressing, return
285 * immediately. Otherwise, rewrite the instruction so that it accesses
286 * its memory operand indirectly through a scratch register. Set
287 * arch_uprobe->fixups and arch_uprobe->rip_rela_target_address
288 * accordingly. (The contents of the scratch register will be saved
289 * before we single-step the modified instruction, and restored
290 * afterward.)
291 *
292 * We do this because a rip-relative instruction can access only a
293 * relatively small area (+/- 2 GB from the instruction), and the XOL
294 * area typically lies beyond that area. At least for instructions
295 * that store to memory, we can't execute the original instruction
296 * and "fix things up" later, because the misdirected store could be
297 * disastrous.
298 *
299 * Some useful facts about rip-relative instructions:
300 *
301 * - There's always a modrm byte.
302 * - There's never a SIB byte.
303 * - The displacement is always 4 bytes.
304 */
305static void
306handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
307{
308 u8 *cursor;
309 u8 reg;
310
311 if (mm->context.ia32_compat)
312 return;
313
314 auprobe->rip_rela_target_address = 0x0;
315 if (!insn_rip_relative(insn))
316 return;
317
318 /*
319 * insn_rip_relative() would have decoded rex_prefix, modrm.
320 * Clear REX.b bit (extension of MODRM.rm field):
321 * we want to encode rax/rcx, not r8/r9.
322 */
323 if (insn->rex_prefix.nbytes) {
324 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
325 *cursor &= 0xfe; /* Clearing REX.B bit */
326 }
327
328 /*
329 * Point cursor at the modrm byte. The next 4 bytes are the
330 * displacement. Beyond the displacement, for some instructions,
331 * is the immediate operand.
332 */
333 cursor = auprobe->insn + insn_offset_modrm(insn);
334 insn_get_length(insn);
335
336 /*
337 * Convert from rip-relative addressing to indirect addressing
338 * via a scratch register. Change the r/m field from 0x5 (%rip)
339 * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field.
340 */
341 reg = MODRM_REG(insn);
342 if (reg == 0) {
343 /*
344 * The register operand (if any) is either the A register
345 * (%rax, %eax, etc.) or (if the 0x4 bit is set in the
346 * REX prefix) %r8. In any case, we know the C register
347 * is NOT the register operand, so we use %rcx (register
348 * #1) for the scratch register.
349 */
350 auprobe->fixups = UPROBE_FIX_RIP_CX;
351 /* Change modrm from 00 000 101 to 00 000 001. */
352 *cursor = 0x1;
353 } else {
354 /* Use %rax (register #0) for the scratch register. */
355 auprobe->fixups = UPROBE_FIX_RIP_AX;
356 /* Change modrm from 00 xxx 101 to 00 xxx 000 */
357 *cursor = (reg << 3);
358 }
359
360 /* Target address = address of next instruction + (signed) offset */
361 auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value;
362
363 /* Displacement field is gone; slide immediate field (if any) over. */
364 if (insn->immediate.nbytes) {
365 cursor++;
366 memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes);
367 }
368 return;
369}
370
371static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn)
372{
373 insn_init(insn, auprobe->insn, true);
374
375 /* Skip good instruction prefixes; reject "bad" ones. */
376 insn_get_opcode(insn);
377 if (is_prefix_bad(insn))
378 return -ENOTSUPP;
379
380 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64))
381 return 0;
382
383 if (insn->opcode.nbytes == 2) {
384 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
385 return 0;
386 }
387 return -ENOTSUPP;
388}
389
390static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
391{
392 if (mm->context.ia32_compat)
393 return validate_insn_32bits(auprobe, insn);
394 return validate_insn_64bits(auprobe, insn);
395}
396#else /* 32-bit: */
397static void handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
398{
399 /* No RIP-relative addressing on 32-bit */
400}
401
402static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
403{
404 return validate_insn_32bits(auprobe, insn);
405}
406#endif /* CONFIG_X86_64 */
407
408/**
409 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
410 * @mm: the probed address space.
411 * @arch_uprobe: the probepoint information.
412 * Return 0 on success or a -ve number on error.
413 */
414int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm)
415{
416 int ret;
417 struct insn insn;
418
419 auprobe->fixups = 0;
420 ret = validate_insn_bits(auprobe, mm, &insn);
421 if (ret != 0)
422 return ret;
423
424 handle_riprel_insn(auprobe, mm, &insn);
425 prepare_fixups(auprobe, &insn);
426
427 return 0;
428}
429
430#ifdef CONFIG_X86_64
431/*
432 * If we're emulating a rip-relative instruction, save the contents
433 * of the scratch register and store the target address in that register.
434 */
435static void
436pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
437 struct arch_uprobe_task *autask)
438{
439 if (auprobe->fixups & UPROBE_FIX_RIP_AX) {
440 autask->saved_scratch_register = regs->ax;
441 regs->ax = current->utask->vaddr;
442 regs->ax += auprobe->rip_rela_target_address;
443 } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) {
444 autask->saved_scratch_register = regs->cx;
445 regs->cx = current->utask->vaddr;
446 regs->cx += auprobe->rip_rela_target_address;
447 }
448}
449#else
450static void
451pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
452 struct arch_uprobe_task *autask)
453{
454 /* No RIP-relative addressing on 32-bit */
455}
456#endif
457
458/*
459 * arch_uprobe_pre_xol - prepare to execute out of line.
460 * @auprobe: the probepoint information.
461 * @regs: reflects the saved user state of current task.
462 */
463int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
464{
465 struct arch_uprobe_task *autask;
466
467 autask = ¤t->utask->autask;
468 autask->saved_trap_nr = current->thread.trap_nr;
469 current->thread.trap_nr = UPROBE_TRAP_NR;
470 regs->ip = current->utask->xol_vaddr;
471 pre_xol_rip_insn(auprobe, regs, autask);
472
473 return 0;
474}
475
476/*
477 * This function is called by arch_uprobe_post_xol() to adjust the return
478 * address pushed by a call instruction executed out of line.
479 */
480static int adjust_ret_addr(unsigned long sp, long correction)
481{
482 int rasize, ncopied;
483 long ra = 0;
484
485 if (is_ia32_task())
486 rasize = 4;
487 else
488 rasize = 8;
489
490 ncopied = copy_from_user(&ra, (void __user *)sp, rasize);
491 if (unlikely(ncopied))
492 return -EFAULT;
493
494 ra += correction;
495 ncopied = copy_to_user((void __user *)sp, &ra, rasize);
496 if (unlikely(ncopied))
497 return -EFAULT;
498
499 return 0;
500}
501
502#ifdef CONFIG_X86_64
503static bool is_riprel_insn(struct arch_uprobe *auprobe)
504{
505 return ((auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) != 0);
506}
507
508static void
509handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
510{
511 if (is_riprel_insn(auprobe)) {
512 struct arch_uprobe_task *autask;
513
514 autask = ¤t->utask->autask;
515 if (auprobe->fixups & UPROBE_FIX_RIP_AX)
516 regs->ax = autask->saved_scratch_register;
517 else
518 regs->cx = autask->saved_scratch_register;
519
520 /*
521 * The original instruction includes a displacement, and so
522 * is 4 bytes longer than what we've just single-stepped.
523 * Fall through to handle stuff like "jmpq *...(%rip)" and
524 * "callq *...(%rip)".
525 */
526 if (correction)
527 *correction += 4;
528 }
529}
530#else
531static void
532handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
533{
534 /* No RIP-relative addressing on 32-bit */
535}
536#endif
537
538/*
539 * If xol insn itself traps and generates a signal(Say,
540 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
541 * instruction jumps back to its own address. It is assumed that anything
542 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
543 *
544 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
545 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
546 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
547 */
548bool arch_uprobe_xol_was_trapped(struct task_struct *t)
549{
550 if (t->thread.trap_nr != UPROBE_TRAP_NR)
551 return true;
552
553 return false;
554}
555
556/*
557 * Called after single-stepping. To avoid the SMP problems that can
558 * occur when we temporarily put back the original opcode to
559 * single-step, we single-stepped a copy of the instruction.
560 *
561 * This function prepares to resume execution after the single-step.
562 * We have to fix things up as follows:
563 *
564 * Typically, the new ip is relative to the copied instruction. We need
565 * to make it relative to the original instruction (FIX_IP). Exceptions
566 * are return instructions and absolute or indirect jump or call instructions.
567 *
568 * If the single-stepped instruction was a call, the return address that
569 * is atop the stack is the address following the copied instruction. We
570 * need to make it the address following the original instruction (FIX_CALL).
571 *
572 * If the original instruction was a rip-relative instruction such as
573 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
574 * instruction using a scratch register -- e.g., "movl %edx,(%rax)".
575 * We need to restore the contents of the scratch register and adjust
576 * the ip, keeping in mind that the instruction we executed is 4 bytes
577 * shorter than the original instruction (since we squeezed out the offset
578 * field). (FIX_RIP_AX or FIX_RIP_CX)
579 */
580int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
581{
582 struct uprobe_task *utask;
583 long correction;
584 int result = 0;
585
586 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
587
588 utask = current->utask;
589 current->thread.trap_nr = utask->autask.saved_trap_nr;
590 correction = (long)(utask->vaddr - utask->xol_vaddr);
591 handle_riprel_post_xol(auprobe, regs, &correction);
592 if (auprobe->fixups & UPROBE_FIX_IP)
593 regs->ip += correction;
594
595 if (auprobe->fixups & UPROBE_FIX_CALL)
596 result = adjust_ret_addr(regs->sp, correction);
597
598 return result;
599}
600
601/* callback routine for handling exceptions. */
602int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
603{
604 struct die_args *args = data;
605 struct pt_regs *regs = args->regs;
606 int ret = NOTIFY_DONE;
607
608 /* We are only interested in userspace traps */
609 if (regs && !user_mode_vm(regs))
610 return NOTIFY_DONE;
611
612 switch (val) {
613 case DIE_INT3:
614 if (uprobe_pre_sstep_notifier(regs))
615 ret = NOTIFY_STOP;
616
617 break;
618
619 case DIE_DEBUG:
620 if (uprobe_post_sstep_notifier(regs))
621 ret = NOTIFY_STOP;
622
623 default:
624 break;
625 }
626
627 return ret;
628}
629
630/*
631 * This function gets called when XOL instruction either gets trapped or
632 * the thread has a fatal signal, so reset the instruction pointer to its
633 * probed address.
634 */
635void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
636{
637 struct uprobe_task *utask = current->utask;
638
639 current->thread.trap_nr = utask->autask.saved_trap_nr;
640 handle_riprel_post_xol(auprobe, regs, NULL);
641 instruction_pointer_set(regs, utask->vaddr);
642}
643
644/*
645 * Skip these instructions as per the currently known x86 ISA.
646 * 0x66* { 0x90 | 0x0f 0x1f | 0x0f 0x19 | 0x87 0xc0 }
647 */
648bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
649{
650 int i;
651
652 for (i = 0; i < MAX_UINSN_BYTES; i++) {
653 if ((auprobe->insn[i] == 0x66))
654 continue;
655
656 if (auprobe->insn[i] == 0x90)
657 return true;
658
659 if (i == (MAX_UINSN_BYTES - 1))
660 break;
661
662 if ((auprobe->insn[i] == 0x0f) && (auprobe->insn[i+1] == 0x1f))
663 return true;
664
665 if ((auprobe->insn[i] == 0x0f) && (auprobe->insn[i+1] == 0x19))
666 return true;
667
668 if ((auprobe->insn[i] == 0x87) && (auprobe->insn[i+1] == 0xc0))
669 return true;
670
671 break;
672 }
673 return false;
674}
1/*
2 * User-space Probes (UProbes) for x86
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2008-2011
19 * Authors:
20 * Srikar Dronamraju
21 * Jim Keniston
22 */
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/uaccess.h>
28
29#include <linux/kdebug.h>
30#include <asm/processor.h>
31#include <asm/insn.h>
32#include <asm/mmu_context.h>
33
34/* Post-execution fixups. */
35
36/* Adjust IP back to vicinity of actual insn */
37#define UPROBE_FIX_IP 0x01
38
39/* Adjust the return address of a call insn */
40#define UPROBE_FIX_CALL 0x02
41
42/* Instruction will modify TF, don't change it */
43#define UPROBE_FIX_SETF 0x04
44
45#define UPROBE_FIX_RIP_SI 0x08
46#define UPROBE_FIX_RIP_DI 0x10
47#define UPROBE_FIX_RIP_BX 0x20
48#define UPROBE_FIX_RIP_MASK \
49 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
50
51#define UPROBE_TRAP_NR UINT_MAX
52
53/* Adaptations for mhiramat x86 decoder v14. */
54#define OPCODE1(insn) ((insn)->opcode.bytes[0])
55#define OPCODE2(insn) ((insn)->opcode.bytes[1])
56#define OPCODE3(insn) ((insn)->opcode.bytes[2])
57#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
58
59#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
60 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
61 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
62 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
63 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
64 << (row % 32))
65
66/*
67 * Good-instruction tables for 32-bit apps. This is non-const and volatile
68 * to keep gcc from statically optimizing it out, as variable_test_bit makes
69 * some versions of gcc to think only *(unsigned long*) is used.
70 *
71 * Opcodes we'll probably never support:
72 * 6c-6f - ins,outs. SEGVs if used in userspace
73 * e4-e7 - in,out imm. SEGVs if used in userspace
74 * ec-ef - in,out acc. SEGVs if used in userspace
75 * cc - int3. SIGTRAP if used in userspace
76 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
77 * (why we support bound (62) then? it's similar, and similarly unused...)
78 * f1 - int1. SIGTRAP if used in userspace
79 * f4 - hlt. SEGVs if used in userspace
80 * fa - cli. SEGVs if used in userspace
81 * fb - sti. SEGVs if used in userspace
82 *
83 * Opcodes which need some work to be supported:
84 * 07,17,1f - pop es/ss/ds
85 * Normally not used in userspace, but would execute if used.
86 * Can cause GP or stack exception if tries to load wrong segment descriptor.
87 * We hesitate to run them under single step since kernel's handling
88 * of userspace single-stepping (TF flag) is fragile.
89 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
90 * on the same grounds that they are never used.
91 * cd - int N.
92 * Used by userspace for "int 80" syscall entry. (Other "int N"
93 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
94 * Not supported since kernel's handling of userspace single-stepping
95 * (TF flag) is fragile.
96 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
97 */
98#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
99static volatile u32 good_insns_32[256 / 32] = {
100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
101 /* ---------------------------------------------- */
102 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
103 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
104 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
105 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
106 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
107 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
108 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
109 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
110 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
111 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
112 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
113 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
114 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
115 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
116 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
117 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
118 /* ---------------------------------------------- */
119 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
120};
121#else
122#define good_insns_32 NULL
123#endif
124
125/* Good-instruction tables for 64-bit apps.
126 *
127 * Genuinely invalid opcodes:
128 * 06,07 - formerly push/pop es
129 * 0e - formerly push cs
130 * 16,17 - formerly push/pop ss
131 * 1e,1f - formerly push/pop ds
132 * 27,2f,37,3f - formerly daa/das/aaa/aas
133 * 60,61 - formerly pusha/popa
134 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
135 * 82 - formerly redundant encoding of Group1
136 * 9a - formerly call seg:ofs
137 * ce - formerly into
138 * d4,d5 - formerly aam/aad
139 * d6 - formerly undocumented salc
140 * ea - formerly jmp seg:ofs
141 *
142 * Opcodes we'll probably never support:
143 * 6c-6f - ins,outs. SEGVs if used in userspace
144 * e4-e7 - in,out imm. SEGVs if used in userspace
145 * ec-ef - in,out acc. SEGVs if used in userspace
146 * cc - int3. SIGTRAP if used in userspace
147 * f1 - int1. SIGTRAP if used in userspace
148 * f4 - hlt. SEGVs if used in userspace
149 * fa - cli. SEGVs if used in userspace
150 * fb - sti. SEGVs if used in userspace
151 *
152 * Opcodes which need some work to be supported:
153 * cd - int N.
154 * Used by userspace for "int 80" syscall entry. (Other "int N"
155 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
156 * Not supported since kernel's handling of userspace single-stepping
157 * (TF flag) is fragile.
158 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
159 */
160#if defined(CONFIG_X86_64)
161static volatile u32 good_insns_64[256 / 32] = {
162 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
163 /* ---------------------------------------------- */
164 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
165 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
166 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
167 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
168 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
169 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
170 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
171 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
172 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
173 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
174 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
175 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
176 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
177 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
178 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
179 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
180 /* ---------------------------------------------- */
181 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
182};
183#else
184#define good_insns_64 NULL
185#endif
186
187/* Using this for both 64-bit and 32-bit apps.
188 * Opcodes we don't support:
189 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
190 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
191 * Also encodes tons of other system insns if mod=11.
192 * Some are in fact non-system: xend, xtest, rdtscp, maybe more
193 * 0f 05 - syscall
194 * 0f 06 - clts (CPL0 insn)
195 * 0f 07 - sysret
196 * 0f 08 - invd (CPL0 insn)
197 * 0f 09 - wbinvd (CPL0 insn)
198 * 0f 0b - ud2
199 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
200 * 0f 34 - sysenter
201 * 0f 35 - sysexit
202 * 0f 37 - getsec
203 * 0f 78 - vmread (Intel VMX. CPL0 insn)
204 * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
205 * Note: with prefixes, these two opcodes are
206 * extrq/insertq/AVX512 convert vector ops.
207 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
208 * {rd,wr}{fs,gs}base,{s,l,m}fence.
209 * Why? They are all user-executable.
210 */
211static volatile u32 good_2byte_insns[256 / 32] = {
212 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
213 /* ---------------------------------------------- */
214 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
215 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
216 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
217 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
218 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
219 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
220 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
221 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
222 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
223 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
224 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
225 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
226 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
227 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
228 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
229 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */
230 /* ---------------------------------------------- */
231 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
232};
233#undef W
234
235/*
236 * opcodes we may need to refine support for:
237 *
238 * 0f - 2-byte instructions: For many of these instructions, the validity
239 * depends on the prefix and/or the reg field. On such instructions, we
240 * just consider the opcode combination valid if it corresponds to any
241 * valid instruction.
242 *
243 * 8f - Group 1 - only reg = 0 is OK
244 * c6-c7 - Group 11 - only reg = 0 is OK
245 * d9-df - fpu insns with some illegal encodings
246 * f2, f3 - repnz, repz prefixes. These are also the first byte for
247 * certain floating-point instructions, such as addsd.
248 *
249 * fe - Group 4 - only reg = 0 or 1 is OK
250 * ff - Group 5 - only reg = 0-6 is OK
251 *
252 * others -- Do we need to support these?
253 *
254 * 0f - (floating-point?) prefetch instructions
255 * 07, 17, 1f - pop es, pop ss, pop ds
256 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
257 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
258 * 67 - addr16 prefix
259 * ce - into
260 * f0 - lock prefix
261 */
262
263/*
264 * TODO:
265 * - Where necessary, examine the modrm byte and allow only valid instructions
266 * in the different Groups and fpu instructions.
267 */
268
269static bool is_prefix_bad(struct insn *insn)
270{
271 int i;
272
273 for (i = 0; i < insn->prefixes.nbytes; i++) {
274 switch (insn->prefixes.bytes[i]) {
275 case 0x26: /* INAT_PFX_ES */
276 case 0x2E: /* INAT_PFX_CS */
277 case 0x36: /* INAT_PFX_DS */
278 case 0x3E: /* INAT_PFX_SS */
279 case 0xF0: /* INAT_PFX_LOCK */
280 return true;
281 }
282 }
283 return false;
284}
285
286static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
287{
288 u32 volatile *good_insns;
289
290 insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
291 /* has the side-effect of processing the entire instruction */
292 insn_get_length(insn);
293 if (WARN_ON_ONCE(!insn_complete(insn)))
294 return -ENOEXEC;
295
296 if (is_prefix_bad(insn))
297 return -ENOTSUPP;
298
299 if (x86_64)
300 good_insns = good_insns_64;
301 else
302 good_insns = good_insns_32;
303
304 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
305 return 0;
306
307 if (insn->opcode.nbytes == 2) {
308 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
309 return 0;
310 }
311
312 return -ENOTSUPP;
313}
314
315#ifdef CONFIG_X86_64
316/*
317 * If arch_uprobe->insn doesn't use rip-relative addressing, return
318 * immediately. Otherwise, rewrite the instruction so that it accesses
319 * its memory operand indirectly through a scratch register. Set
320 * defparam->fixups accordingly. (The contents of the scratch register
321 * will be saved before we single-step the modified instruction,
322 * and restored afterward).
323 *
324 * We do this because a rip-relative instruction can access only a
325 * relatively small area (+/- 2 GB from the instruction), and the XOL
326 * area typically lies beyond that area. At least for instructions
327 * that store to memory, we can't execute the original instruction
328 * and "fix things up" later, because the misdirected store could be
329 * disastrous.
330 *
331 * Some useful facts about rip-relative instructions:
332 *
333 * - There's always a modrm byte with bit layout "00 reg 101".
334 * - There's never a SIB byte.
335 * - The displacement is always 4 bytes.
336 * - REX.B=1 bit in REX prefix, which normally extends r/m field,
337 * has no effect on rip-relative mode. It doesn't make modrm byte
338 * with r/m=101 refer to register 1101 = R13.
339 */
340static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
341{
342 u8 *cursor;
343 u8 reg;
344 u8 reg2;
345
346 if (!insn_rip_relative(insn))
347 return;
348
349 /*
350 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
351 * Clear REX.b bit (extension of MODRM.rm field):
352 * we want to encode low numbered reg, not r8+.
353 */
354 if (insn->rex_prefix.nbytes) {
355 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
356 /* REX byte has 0100wrxb layout, clearing REX.b bit */
357 *cursor &= 0xfe;
358 }
359 /*
360 * Similar treatment for VEX3/EVEX prefix.
361 * TODO: add XOP treatment when insn decoder supports them
362 */
363 if (insn->vex_prefix.nbytes >= 3) {
364 /*
365 * vex2: c5 rvvvvLpp (has no b bit)
366 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
367 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa
368 * Setting VEX3.b (setting because it has inverted meaning).
369 * Setting EVEX.x since (in non-SIB encoding) EVEX.x
370 * is the 4th bit of MODRM.rm, and needs the same treatment.
371 * For VEX3-encoded insns, VEX3.x value has no effect in
372 * non-SIB encoding, the change is superfluous but harmless.
373 */
374 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
375 *cursor |= 0x60;
376 }
377
378 /*
379 * Convert from rip-relative addressing to register-relative addressing
380 * via a scratch register.
381 *
382 * This is tricky since there are insns with modrm byte
383 * which also use registers not encoded in modrm byte:
384 * [i]div/[i]mul: implicitly use dx:ax
385 * shift ops: implicitly use cx
386 * cmpxchg: implicitly uses ax
387 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
388 * Encoding: 0f c7/1 modrm
389 * The code below thinks that reg=1 (cx), chooses si as scratch.
390 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
391 * First appeared in Haswell (BMI2 insn). It is vex-encoded.
392 * Example where none of bx,cx,dx can be used as scratch reg:
393 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx
394 * [v]pcmpistri: implicitly uses cx, xmm0
395 * [v]pcmpistrm: implicitly uses xmm0
396 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
397 * [v]pcmpestrm: implicitly uses ax, dx, xmm0
398 * Evil SSE4.2 string comparison ops from hell.
399 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
400 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
401 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
402 * AMD says it has no 3-operand form (vex.vvvv must be 1111)
403 * and that it can have only register operands, not mem
404 * (its modrm byte must have mode=11).
405 * If these restrictions will ever be lifted,
406 * we'll need code to prevent selection of di as scratch reg!
407 *
408 * Summary: I don't know any insns with modrm byte which
409 * use SI register implicitly. DI register is used only
410 * by one insn (maskmovq) and BX register is used
411 * only by one too (cmpxchg8b).
412 * BP is stack-segment based (may be a problem?).
413 * AX, DX, CX are off-limits (many implicit users).
414 * SP is unusable (it's stack pointer - think about "pop mem";
415 * also, rsp+disp32 needs sib encoding -> insn length change).
416 */
417
418 reg = MODRM_REG(insn); /* Fetch modrm.reg */
419 reg2 = 0xff; /* Fetch vex.vvvv */
420 if (insn->vex_prefix.nbytes)
421 reg2 = insn->vex_prefix.bytes[2];
422 /*
423 * TODO: add XOP vvvv reading.
424 *
425 * vex.vvvv field is in bits 6-3, bits are inverted.
426 * But in 32-bit mode, high-order bit may be ignored.
427 * Therefore, let's consider only 3 low-order bits.
428 */
429 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
430 /*
431 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
432 *
433 * Choose scratch reg. Order is important: must not select bx
434 * if we can use si (cmpxchg8b case!)
435 */
436 if (reg != 6 && reg2 != 6) {
437 reg2 = 6;
438 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
439 } else if (reg != 7 && reg2 != 7) {
440 reg2 = 7;
441 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
442 /* TODO (paranoia): force maskmovq to not use di */
443 } else {
444 reg2 = 3;
445 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
446 }
447 /*
448 * Point cursor at the modrm byte. The next 4 bytes are the
449 * displacement. Beyond the displacement, for some instructions,
450 * is the immediate operand.
451 */
452 cursor = auprobe->insn + insn_offset_modrm(insn);
453 /*
454 * Change modrm from "00 reg 101" to "10 reg reg2". Example:
455 * 89 05 disp32 mov %eax,disp32(%rip) becomes
456 * 89 86 disp32 mov %eax,disp32(%rsi)
457 */
458 *cursor = 0x80 | (reg << 3) | reg2;
459}
460
461static inline unsigned long *
462scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
463{
464 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
465 return ®s->si;
466 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
467 return ®s->di;
468 return ®s->bx;
469}
470
471/*
472 * If we're emulating a rip-relative instruction, save the contents
473 * of the scratch register and store the target address in that register.
474 */
475static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
476{
477 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
478 struct uprobe_task *utask = current->utask;
479 unsigned long *sr = scratch_reg(auprobe, regs);
480
481 utask->autask.saved_scratch_register = *sr;
482 *sr = utask->vaddr + auprobe->defparam.ilen;
483 }
484}
485
486static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
487{
488 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
489 struct uprobe_task *utask = current->utask;
490 unsigned long *sr = scratch_reg(auprobe, regs);
491
492 *sr = utask->autask.saved_scratch_register;
493 }
494}
495#else /* 32-bit: */
496/*
497 * No RIP-relative addressing on 32-bit
498 */
499static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
500{
501}
502static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
503{
504}
505static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
506{
507}
508#endif /* CONFIG_X86_64 */
509
510struct uprobe_xol_ops {
511 bool (*emulate)(struct arch_uprobe *, struct pt_regs *);
512 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
513 int (*post_xol)(struct arch_uprobe *, struct pt_regs *);
514 void (*abort)(struct arch_uprobe *, struct pt_regs *);
515};
516
517static inline int sizeof_long(void)
518{
519 return in_ia32_syscall() ? 4 : 8;
520}
521
522static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
523{
524 riprel_pre_xol(auprobe, regs);
525 return 0;
526}
527
528static int push_ret_address(struct pt_regs *regs, unsigned long ip)
529{
530 unsigned long new_sp = regs->sp - sizeof_long();
531
532 if (copy_to_user((void __user *)new_sp, &ip, sizeof_long()))
533 return -EFAULT;
534
535 regs->sp = new_sp;
536 return 0;
537}
538
539/*
540 * We have to fix things up as follows:
541 *
542 * Typically, the new ip is relative to the copied instruction. We need
543 * to make it relative to the original instruction (FIX_IP). Exceptions
544 * are return instructions and absolute or indirect jump or call instructions.
545 *
546 * If the single-stepped instruction was a call, the return address that
547 * is atop the stack is the address following the copied instruction. We
548 * need to make it the address following the original instruction (FIX_CALL).
549 *
550 * If the original instruction was a rip-relative instruction such as
551 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
552 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
553 * We need to restore the contents of the scratch register
554 * (FIX_RIP_reg).
555 */
556static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
557{
558 struct uprobe_task *utask = current->utask;
559
560 riprel_post_xol(auprobe, regs);
561 if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
562 long correction = utask->vaddr - utask->xol_vaddr;
563 regs->ip += correction;
564 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
565 regs->sp += sizeof_long(); /* Pop incorrect return address */
566 if (push_ret_address(regs, utask->vaddr + auprobe->defparam.ilen))
567 return -ERESTART;
568 }
569 /* popf; tell the caller to not touch TF */
570 if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
571 utask->autask.saved_tf = true;
572
573 return 0;
574}
575
576static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
577{
578 riprel_post_xol(auprobe, regs);
579}
580
581static const struct uprobe_xol_ops default_xol_ops = {
582 .pre_xol = default_pre_xol_op,
583 .post_xol = default_post_xol_op,
584 .abort = default_abort_op,
585};
586
587static bool branch_is_call(struct arch_uprobe *auprobe)
588{
589 return auprobe->branch.opc1 == 0xe8;
590}
591
592#define CASE_COND \
593 COND(70, 71, XF(OF)) \
594 COND(72, 73, XF(CF)) \
595 COND(74, 75, XF(ZF)) \
596 COND(78, 79, XF(SF)) \
597 COND(7a, 7b, XF(PF)) \
598 COND(76, 77, XF(CF) || XF(ZF)) \
599 COND(7c, 7d, XF(SF) != XF(OF)) \
600 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
601
602#define COND(op_y, op_n, expr) \
603 case 0x ## op_y: DO((expr) != 0) \
604 case 0x ## op_n: DO((expr) == 0)
605
606#define XF(xf) (!!(flags & X86_EFLAGS_ ## xf))
607
608static bool is_cond_jmp_opcode(u8 opcode)
609{
610 switch (opcode) {
611 #define DO(expr) \
612 return true;
613 CASE_COND
614 #undef DO
615
616 default:
617 return false;
618 }
619}
620
621static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
622{
623 unsigned long flags = regs->flags;
624
625 switch (auprobe->branch.opc1) {
626 #define DO(expr) \
627 return expr;
628 CASE_COND
629 #undef DO
630
631 default: /* not a conditional jmp */
632 return true;
633 }
634}
635
636#undef XF
637#undef COND
638#undef CASE_COND
639
640static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
641{
642 unsigned long new_ip = regs->ip += auprobe->branch.ilen;
643 unsigned long offs = (long)auprobe->branch.offs;
644
645 if (branch_is_call(auprobe)) {
646 /*
647 * If it fails we execute this (mangled, see the comment in
648 * branch_clear_offset) insn out-of-line. In the likely case
649 * this should trigger the trap, and the probed application
650 * should die or restart the same insn after it handles the
651 * signal, arch_uprobe_post_xol() won't be even called.
652 *
653 * But there is corner case, see the comment in ->post_xol().
654 */
655 if (push_ret_address(regs, new_ip))
656 return false;
657 } else if (!check_jmp_cond(auprobe, regs)) {
658 offs = 0;
659 }
660
661 regs->ip = new_ip + offs;
662 return true;
663}
664
665static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
666{
667 BUG_ON(!branch_is_call(auprobe));
668 /*
669 * We can only get here if branch_emulate_op() failed to push the ret
670 * address _and_ another thread expanded our stack before the (mangled)
671 * "call" insn was executed out-of-line. Just restore ->sp and restart.
672 * We could also restore ->ip and try to call branch_emulate_op() again.
673 */
674 regs->sp += sizeof_long();
675 return -ERESTART;
676}
677
678static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
679{
680 /*
681 * Turn this insn into "call 1f; 1:", this is what we will execute
682 * out-of-line if ->emulate() fails. We only need this to generate
683 * a trap, so that the probed task receives the correct signal with
684 * the properly filled siginfo.
685 *
686 * But see the comment in ->post_xol(), in the unlikely case it can
687 * succeed. So we need to ensure that the new ->ip can not fall into
688 * the non-canonical area and trigger #GP.
689 *
690 * We could turn it into (say) "pushf", but then we would need to
691 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
692 * of ->insn[] for set_orig_insn().
693 */
694 memset(auprobe->insn + insn_offset_immediate(insn),
695 0, insn->immediate.nbytes);
696}
697
698static const struct uprobe_xol_ops branch_xol_ops = {
699 .emulate = branch_emulate_op,
700 .post_xol = branch_post_xol_op,
701};
702
703/* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
704static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
705{
706 u8 opc1 = OPCODE1(insn);
707 int i;
708
709 switch (opc1) {
710 case 0xeb: /* jmp 8 */
711 case 0xe9: /* jmp 32 */
712 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */
713 break;
714
715 case 0xe8: /* call relative */
716 branch_clear_offset(auprobe, insn);
717 break;
718
719 case 0x0f:
720 if (insn->opcode.nbytes != 2)
721 return -ENOSYS;
722 /*
723 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
724 * OPCODE1() of the "short" jmp which checks the same condition.
725 */
726 opc1 = OPCODE2(insn) - 0x10;
727 default:
728 if (!is_cond_jmp_opcode(opc1))
729 return -ENOSYS;
730 }
731
732 /*
733 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
734 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
735 * No one uses these insns, reject any branch insns with such prefix.
736 */
737 for (i = 0; i < insn->prefixes.nbytes; i++) {
738 if (insn->prefixes.bytes[i] == 0x66)
739 return -ENOTSUPP;
740 }
741
742 auprobe->branch.opc1 = opc1;
743 auprobe->branch.ilen = insn->length;
744 auprobe->branch.offs = insn->immediate.value;
745
746 auprobe->ops = &branch_xol_ops;
747 return 0;
748}
749
750/**
751 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
752 * @mm: the probed address space.
753 * @arch_uprobe: the probepoint information.
754 * @addr: virtual address at which to install the probepoint
755 * Return 0 on success or a -ve number on error.
756 */
757int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
758{
759 struct insn insn;
760 u8 fix_ip_or_call = UPROBE_FIX_IP;
761 int ret;
762
763 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
764 if (ret)
765 return ret;
766
767 ret = branch_setup_xol_ops(auprobe, &insn);
768 if (ret != -ENOSYS)
769 return ret;
770
771 /*
772 * Figure out which fixups default_post_xol_op() will need to perform,
773 * and annotate defparam->fixups accordingly.
774 */
775 switch (OPCODE1(&insn)) {
776 case 0x9d: /* popf */
777 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
778 break;
779 case 0xc3: /* ret or lret -- ip is correct */
780 case 0xcb:
781 case 0xc2:
782 case 0xca:
783 case 0xea: /* jmp absolute -- ip is correct */
784 fix_ip_or_call = 0;
785 break;
786 case 0x9a: /* call absolute - Fix return addr, not ip */
787 fix_ip_or_call = UPROBE_FIX_CALL;
788 break;
789 case 0xff:
790 switch (MODRM_REG(&insn)) {
791 case 2: case 3: /* call or lcall, indirect */
792 fix_ip_or_call = UPROBE_FIX_CALL;
793 break;
794 case 4: case 5: /* jmp or ljmp, indirect */
795 fix_ip_or_call = 0;
796 break;
797 }
798 /* fall through */
799 default:
800 riprel_analyze(auprobe, &insn);
801 }
802
803 auprobe->defparam.ilen = insn.length;
804 auprobe->defparam.fixups |= fix_ip_or_call;
805
806 auprobe->ops = &default_xol_ops;
807 return 0;
808}
809
810/*
811 * arch_uprobe_pre_xol - prepare to execute out of line.
812 * @auprobe: the probepoint information.
813 * @regs: reflects the saved user state of current task.
814 */
815int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
816{
817 struct uprobe_task *utask = current->utask;
818
819 if (auprobe->ops->pre_xol) {
820 int err = auprobe->ops->pre_xol(auprobe, regs);
821 if (err)
822 return err;
823 }
824
825 regs->ip = utask->xol_vaddr;
826 utask->autask.saved_trap_nr = current->thread.trap_nr;
827 current->thread.trap_nr = UPROBE_TRAP_NR;
828
829 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
830 regs->flags |= X86_EFLAGS_TF;
831 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
832 set_task_blockstep(current, false);
833
834 return 0;
835}
836
837/*
838 * If xol insn itself traps and generates a signal(Say,
839 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
840 * instruction jumps back to its own address. It is assumed that anything
841 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
842 *
843 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
844 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
845 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
846 */
847bool arch_uprobe_xol_was_trapped(struct task_struct *t)
848{
849 if (t->thread.trap_nr != UPROBE_TRAP_NR)
850 return true;
851
852 return false;
853}
854
855/*
856 * Called after single-stepping. To avoid the SMP problems that can
857 * occur when we temporarily put back the original opcode to
858 * single-step, we single-stepped a copy of the instruction.
859 *
860 * This function prepares to resume execution after the single-step.
861 */
862int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
863{
864 struct uprobe_task *utask = current->utask;
865 bool send_sigtrap = utask->autask.saved_tf;
866 int err = 0;
867
868 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
869 current->thread.trap_nr = utask->autask.saved_trap_nr;
870
871 if (auprobe->ops->post_xol) {
872 err = auprobe->ops->post_xol(auprobe, regs);
873 if (err) {
874 /*
875 * Restore ->ip for restart or post mortem analysis.
876 * ->post_xol() must not return -ERESTART unless this
877 * is really possible.
878 */
879 regs->ip = utask->vaddr;
880 if (err == -ERESTART)
881 err = 0;
882 send_sigtrap = false;
883 }
884 }
885 /*
886 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
887 * so we can get an extra SIGTRAP if we do not clear TF. We need
888 * to examine the opcode to make it right.
889 */
890 if (send_sigtrap)
891 send_sig(SIGTRAP, current, 0);
892
893 if (!utask->autask.saved_tf)
894 regs->flags &= ~X86_EFLAGS_TF;
895
896 return err;
897}
898
899/* callback routine for handling exceptions. */
900int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
901{
902 struct die_args *args = data;
903 struct pt_regs *regs = args->regs;
904 int ret = NOTIFY_DONE;
905
906 /* We are only interested in userspace traps */
907 if (regs && !user_mode(regs))
908 return NOTIFY_DONE;
909
910 switch (val) {
911 case DIE_INT3:
912 if (uprobe_pre_sstep_notifier(regs))
913 ret = NOTIFY_STOP;
914
915 break;
916
917 case DIE_DEBUG:
918 if (uprobe_post_sstep_notifier(regs))
919 ret = NOTIFY_STOP;
920
921 default:
922 break;
923 }
924
925 return ret;
926}
927
928/*
929 * This function gets called when XOL instruction either gets trapped or
930 * the thread has a fatal signal. Reset the instruction pointer to its
931 * probed address for the potential restart or for post mortem analysis.
932 */
933void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
934{
935 struct uprobe_task *utask = current->utask;
936
937 if (auprobe->ops->abort)
938 auprobe->ops->abort(auprobe, regs);
939
940 current->thread.trap_nr = utask->autask.saved_trap_nr;
941 regs->ip = utask->vaddr;
942 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
943 if (!utask->autask.saved_tf)
944 regs->flags &= ~X86_EFLAGS_TF;
945}
946
947static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
948{
949 if (auprobe->ops->emulate)
950 return auprobe->ops->emulate(auprobe, regs);
951 return false;
952}
953
954bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
955{
956 bool ret = __skip_sstep(auprobe, regs);
957 if (ret && (regs->flags & X86_EFLAGS_TF))
958 send_sig(SIGTRAP, current, 0);
959 return ret;
960}
961
962unsigned long
963arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
964{
965 int rasize = sizeof_long(), nleft;
966 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
967
968 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
969 return -1;
970
971 /* check whether address has been already hijacked */
972 if (orig_ret_vaddr == trampoline_vaddr)
973 return orig_ret_vaddr;
974
975 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
976 if (likely(!nleft))
977 return orig_ret_vaddr;
978
979 if (nleft != rasize) {
980 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
981 "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
982
983 force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
984 }
985
986 return -1;
987}
988
989bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
990 struct pt_regs *regs)
991{
992 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
993 return regs->sp < ret->stack;
994 else
995 return regs->sp <= ret->stack;
996}