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1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include <asm-generic/pci-bridge.h>
29#include "pci.h"
30
31unsigned int pci_flags;
32
33struct pci_dev_resource {
34 struct list_head list;
35 struct resource *res;
36 struct pci_dev *dev;
37 resource_size_t start;
38 resource_size_t end;
39 resource_size_t add_size;
40 resource_size_t min_align;
41 unsigned long flags;
42};
43
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
53
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
63static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
66{
67 struct pci_dev_resource *tmp;
68
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 if (!tmp) {
71 pr_warning("add_to_list: kmalloc() failed!\n");
72 return -ENOMEM;
73 }
74
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
82
83 list_add(&tmp->list, head);
84
85 return 0;
86}
87
88static void remove_from_list(struct list_head *head,
89 struct resource *res)
90{
91 struct pci_dev_resource *dev_res, *tmp;
92
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
97 break;
98 }
99 }
100}
101
102static resource_size_t get_res_add_size(struct list_head *head,
103 struct resource *res)
104{
105 struct pci_dev_resource *dev_res;
106
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
110
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
113 idx, dev_res->res,
114 (unsigned long long)dev_res->add_size);
115
116 return dev_res->add_size;
117 }
118 }
119
120 return 0;
121}
122
123/* Sort resources by alignment */
124static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
125{
126 int i;
127
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129 struct resource *r;
130 struct pci_dev_resource *dev_res, *tmp;
131 resource_size_t r_align;
132 struct list_head *n;
133
134 r = &dev->resource[i];
135
136 if (r->flags & IORESOURCE_PCI_FIXED)
137 continue;
138
139 if (!(r->flags) || r->parent)
140 continue;
141
142 r_align = pci_resource_alignment(dev, r);
143 if (!r_align) {
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145 i, r);
146 continue;
147 }
148
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150 if (!tmp)
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
153 tmp->res = r;
154 tmp->dev = dev;
155
156 /* fallback is smallest one or list is empty*/
157 n = head;
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
160
161 align = pci_resource_alignment(dev_res->dev,
162 dev_res->res);
163
164 if (r_align > align) {
165 n = &dev_res->list;
166 break;
167 }
168 }
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
171 }
172}
173
174static void __dev_sort_resources(struct pci_dev *dev,
175 struct list_head *head)
176{
177 u16 class = dev->class >> 8;
178
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181 return;
182
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
185 u16 command;
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188 return;
189 }
190
191 pdev_sort_resources(dev, head);
192}
193
194static inline void reset_resource(struct resource *res)
195{
196 res->start = 0;
197 res->end = 0;
198 res->flags = 0;
199}
200
201/**
202 * reassign_resources_sorted() - satisfy any additional resource requests
203 *
204 * @realloc_head : head of the list tracking requests requiring additional
205 * resources
206 * @head : head of the list tracking requests with allocated
207 * resources
208 *
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
212 */
213static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
215{
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size;
220 int idx;
221
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
224
225 res = add_res->res;
226 /* skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
236 }
237 if (!found_match)/* just skip */
238 continue;
239
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 if (!resource_size(res)) {
243 res->start = add_res->start;
244 res->end = res->start + add_size - 1;
245 if (pci_assign_resource(add_res->dev, idx))
246 reset_resource(res);
247 } else {
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
252 add_size, align))
253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
256 idx, res);
257 }
258out:
259 list_del(&add_res->list);
260 kfree(add_res);
261 }
262}
263
264/**
265 * assign_requested_resources_sorted() - satisfy resource requests
266 *
267 * @head : head of the list tracking requests for resources
268 * @failed_list : head of the list tracking requests that could
269 * not be allocated
270 *
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
273 */
274static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
276{
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
279 int idx;
280
281 list_for_each_entry(dev_res, head, list) {
282 res = dev_res->res;
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
286 if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) {
287 /*
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* dont care */,
296 0 /* dont care */);
297 }
298 reset_resource(res);
299 }
300 }
301}
302
303static void __assign_resources_sorted(struct list_head *head,
304 struct list_head *realloc_head,
305 struct list_head *fail_head)
306{
307 /*
308 * Should not assign requested resources at first.
309 * they could be adjacent, so later reassign can not reallocate
310 * them one by one in parent resource window.
311 * Try to assign requested + add_size at begining
312 * if could do that, could get out early.
313 * if could not do that, we still try to assign requested at first,
314 * then try to reassign add_size for some resources.
315 */
316 LIST_HEAD(save_head);
317 LIST_HEAD(local_fail_head);
318 struct pci_dev_resource *save_res;
319 struct pci_dev_resource *dev_res;
320
321 /* Check if optional add_size is there */
322 if (!realloc_head || list_empty(realloc_head))
323 goto requested_and_reassign;
324
325 /* Save original start, end, flags etc at first */
326 list_for_each_entry(dev_res, head, list) {
327 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
328 free_list(&save_head);
329 goto requested_and_reassign;
330 }
331 }
332
333 /* Update res in head list with add_size in realloc_head list */
334 list_for_each_entry(dev_res, head, list)
335 dev_res->res->end += get_res_add_size(realloc_head,
336 dev_res->res);
337
338 /* Try updated head list with add_size added */
339 assign_requested_resources_sorted(head, &local_fail_head);
340
341 /* all assigned with add_size ? */
342 if (list_empty(&local_fail_head)) {
343 /* Remove head list from realloc_head list */
344 list_for_each_entry(dev_res, head, list)
345 remove_from_list(realloc_head, dev_res->res);
346 free_list(&save_head);
347 free_list(head);
348 return;
349 }
350
351 free_list(&local_fail_head);
352 /* Release assigned resource */
353 list_for_each_entry(dev_res, head, list)
354 if (dev_res->res->parent)
355 release_resource(dev_res->res);
356 /* Restore start/end/flags from saved list */
357 list_for_each_entry(save_res, &save_head, list) {
358 struct resource *res = save_res->res;
359
360 res->start = save_res->start;
361 res->end = save_res->end;
362 res->flags = save_res->flags;
363 }
364 free_list(&save_head);
365
366requested_and_reassign:
367 /* Satisfy the must-have resource requests */
368 assign_requested_resources_sorted(head, fail_head);
369
370 /* Try to satisfy any additional optional resource
371 requests */
372 if (realloc_head)
373 reassign_resources_sorted(realloc_head, head);
374 free_list(head);
375}
376
377static void pdev_assign_resources_sorted(struct pci_dev *dev,
378 struct list_head *add_head,
379 struct list_head *fail_head)
380{
381 LIST_HEAD(head);
382
383 __dev_sort_resources(dev, &head);
384 __assign_resources_sorted(&head, add_head, fail_head);
385
386}
387
388static void pbus_assign_resources_sorted(const struct pci_bus *bus,
389 struct list_head *realloc_head,
390 struct list_head *fail_head)
391{
392 struct pci_dev *dev;
393 LIST_HEAD(head);
394
395 list_for_each_entry(dev, &bus->devices, bus_list)
396 __dev_sort_resources(dev, &head);
397
398 __assign_resources_sorted(&head, realloc_head, fail_head);
399}
400
401void pci_setup_cardbus(struct pci_bus *bus)
402{
403 struct pci_dev *bridge = bus->self;
404 struct resource *res;
405 struct pci_bus_region region;
406
407 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
408 bus->secondary, bus->subordinate);
409
410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, ®ion, res);
412 if (res->flags & IORESOURCE_IO) {
413 /*
414 * The IO resource is allocated a range twice as large as it
415 * would normally need. This allows us to set both IO regs.
416 */
417 dev_info(&bridge->dev, " bridge window %pR\n", res);
418 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
419 region.start);
420 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
421 region.end);
422 }
423
424 res = bus->resource[1];
425 pcibios_resource_to_bus(bridge, ®ion, res);
426 if (res->flags & IORESOURCE_IO) {
427 dev_info(&bridge->dev, " bridge window %pR\n", res);
428 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
429 region.start);
430 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
431 region.end);
432 }
433
434 res = bus->resource[2];
435 pcibios_resource_to_bus(bridge, ®ion, res);
436 if (res->flags & IORESOURCE_MEM) {
437 dev_info(&bridge->dev, " bridge window %pR\n", res);
438 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
439 region.start);
440 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
441 region.end);
442 }
443
444 res = bus->resource[3];
445 pcibios_resource_to_bus(bridge, ®ion, res);
446 if (res->flags & IORESOURCE_MEM) {
447 dev_info(&bridge->dev, " bridge window %pR\n", res);
448 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
449 region.start);
450 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
451 region.end);
452 }
453}
454EXPORT_SYMBOL(pci_setup_cardbus);
455
456/* Initialize bridges with base/limit values we have collected.
457 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
458 requires that if there is no I/O ports or memory behind the
459 bridge, corresponding range must be turned off by writing base
460 value greater than limit to the bridge's base/limit registers.
461
462 Note: care must be taken when updating I/O base/limit registers
463 of bridges which support 32-bit I/O. This update requires two
464 config space writes, so it's quite possible that an I/O window of
465 the bridge will have some undesirable address (e.g. 0) after the
466 first write. Ditto 64-bit prefetchable MMIO. */
467static void pci_setup_bridge_io(struct pci_bus *bus)
468{
469 struct pci_dev *bridge = bus->self;
470 struct resource *res;
471 struct pci_bus_region region;
472 u32 l, io_upper16;
473
474 /* Set up the top and bottom of the PCI I/O segment for this bus. */
475 res = bus->resource[0];
476 pcibios_resource_to_bus(bridge, ®ion, res);
477 if (res->flags & IORESOURCE_IO) {
478 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
479 l &= 0xffff0000;
480 l |= (region.start >> 8) & 0x00f0;
481 l |= region.end & 0xf000;
482 /* Set up upper 16 bits of I/O base/limit. */
483 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
484 dev_info(&bridge->dev, " bridge window %pR\n", res);
485 } else {
486 /* Clear upper 16 bits of I/O base/limit. */
487 io_upper16 = 0;
488 l = 0x00f0;
489 }
490 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
491 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
492 /* Update lower 16 bits of I/O base/limit. */
493 pci_write_config_dword(bridge, PCI_IO_BASE, l);
494 /* Update upper 16 bits of I/O base/limit. */
495 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
496}
497
498static void pci_setup_bridge_mmio(struct pci_bus *bus)
499{
500 struct pci_dev *bridge = bus->self;
501 struct resource *res;
502 struct pci_bus_region region;
503 u32 l;
504
505 /* Set up the top and bottom of the PCI Memory segment for this bus. */
506 res = bus->resource[1];
507 pcibios_resource_to_bus(bridge, ®ion, res);
508 if (res->flags & IORESOURCE_MEM) {
509 l = (region.start >> 16) & 0xfff0;
510 l |= region.end & 0xfff00000;
511 dev_info(&bridge->dev, " bridge window %pR\n", res);
512 } else {
513 l = 0x0000fff0;
514 }
515 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
516}
517
518static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
519{
520 struct pci_dev *bridge = bus->self;
521 struct resource *res;
522 struct pci_bus_region region;
523 u32 l, bu, lu;
524
525 /* Clear out the upper 32 bits of PREF limit.
526 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
527 disables PREF range, which is ok. */
528 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
529
530 /* Set up PREF base/limit. */
531 bu = lu = 0;
532 res = bus->resource[2];
533 pcibios_resource_to_bus(bridge, ®ion, res);
534 if (res->flags & IORESOURCE_PREFETCH) {
535 l = (region.start >> 16) & 0xfff0;
536 l |= region.end & 0xfff00000;
537 if (res->flags & IORESOURCE_MEM_64) {
538 bu = upper_32_bits(region.start);
539 lu = upper_32_bits(region.end);
540 }
541 dev_info(&bridge->dev, " bridge window %pR\n", res);
542 } else {
543 l = 0x0000fff0;
544 }
545 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
546
547 /* Set the upper 32 bits of PREF base & limit. */
548 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
549 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
550}
551
552static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
553{
554 struct pci_dev *bridge = bus->self;
555
556 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
557 bus->secondary, bus->subordinate);
558
559 if (type & IORESOURCE_IO)
560 pci_setup_bridge_io(bus);
561
562 if (type & IORESOURCE_MEM)
563 pci_setup_bridge_mmio(bus);
564
565 if (type & IORESOURCE_PREFETCH)
566 pci_setup_bridge_mmio_pref(bus);
567
568 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
569}
570
571void pci_setup_bridge(struct pci_bus *bus)
572{
573 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
574 IORESOURCE_PREFETCH;
575
576 __pci_setup_bridge(bus, type);
577}
578
579/* Check whether the bridge supports optional I/O and
580 prefetchable memory ranges. If not, the respective
581 base/limit registers must be read-only and read as 0. */
582static void pci_bridge_check_ranges(struct pci_bus *bus)
583{
584 u16 io;
585 u32 pmem;
586 struct pci_dev *bridge = bus->self;
587 struct resource *b_res;
588
589 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
590 b_res[1].flags |= IORESOURCE_MEM;
591
592 pci_read_config_word(bridge, PCI_IO_BASE, &io);
593 if (!io) {
594 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
595 pci_read_config_word(bridge, PCI_IO_BASE, &io);
596 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
597 }
598 if (io)
599 b_res[0].flags |= IORESOURCE_IO;
600 /* DECchip 21050 pass 2 errata: the bridge may miss an address
601 disconnect boundary by one PCI data phase.
602 Workaround: do not use prefetching on this device. */
603 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
604 return;
605 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
606 if (!pmem) {
607 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
608 0xfff0fff0);
609 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
610 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
611 }
612 if (pmem) {
613 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
614 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
615 PCI_PREF_RANGE_TYPE_64) {
616 b_res[2].flags |= IORESOURCE_MEM_64;
617 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
618 }
619 }
620
621 /* double check if bridge does support 64 bit pref */
622 if (b_res[2].flags & IORESOURCE_MEM_64) {
623 u32 mem_base_hi, tmp;
624 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
625 &mem_base_hi);
626 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
627 0xffffffff);
628 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
629 if (!tmp)
630 b_res[2].flags &= ~IORESOURCE_MEM_64;
631 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
632 mem_base_hi);
633 }
634}
635
636/* Helper function for sizing routines: find first available
637 bus resource of a given type. Note: we intentionally skip
638 the bus resources which have already been assigned (that is,
639 have non-NULL parent resource). */
640static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
641{
642 int i;
643 struct resource *r;
644 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
645 IORESOURCE_PREFETCH;
646
647 pci_bus_for_each_resource(bus, r, i) {
648 if (r == &ioport_resource || r == &iomem_resource)
649 continue;
650 if (r && (r->flags & type_mask) == type && !r->parent)
651 return r;
652 }
653 return NULL;
654}
655
656static resource_size_t calculate_iosize(resource_size_t size,
657 resource_size_t min_size,
658 resource_size_t size1,
659 resource_size_t old_size,
660 resource_size_t align)
661{
662 if (size < min_size)
663 size = min_size;
664 if (old_size == 1 )
665 old_size = 0;
666 /* To be fixed in 2.5: we should have sort of HAVE_ISA
667 flag in the struct pci_bus. */
668#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
669 size = (size & 0xff) + ((size & ~0xffUL) << 2);
670#endif
671 size = ALIGN(size + size1, align);
672 if (size < old_size)
673 size = old_size;
674 return size;
675}
676
677static resource_size_t calculate_memsize(resource_size_t size,
678 resource_size_t min_size,
679 resource_size_t size1,
680 resource_size_t old_size,
681 resource_size_t align)
682{
683 if (size < min_size)
684 size = min_size;
685 if (old_size == 1 )
686 old_size = 0;
687 if (size < old_size)
688 size = old_size;
689 size = ALIGN(size + size1, align);
690 return size;
691}
692
693/**
694 * pbus_size_io() - size the io window of a given bus
695 *
696 * @bus : the bus
697 * @min_size : the minimum io window that must to be allocated
698 * @add_size : additional optional io window
699 * @realloc_head : track the additional io window on this list
700 *
701 * Sizing the IO windows of the PCI-PCI bridge is trivial,
702 * since these windows have 4K granularity and the IO ranges
703 * of non-bridge PCI devices are limited to 256 bytes.
704 * We must be careful with the ISA aliasing though.
705 */
706static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
707 resource_size_t add_size, struct list_head *realloc_head)
708{
709 struct pci_dev *dev;
710 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
711 unsigned long size = 0, size0 = 0, size1 = 0;
712 resource_size_t children_add_size = 0;
713
714 if (!b_res)
715 return;
716
717 list_for_each_entry(dev, &bus->devices, bus_list) {
718 int i;
719
720 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
721 struct resource *r = &dev->resource[i];
722 unsigned long r_size;
723
724 if (r->parent || !(r->flags & IORESOURCE_IO))
725 continue;
726 r_size = resource_size(r);
727
728 if (r_size < 0x400)
729 /* Might be re-aligned for ISA */
730 size += r_size;
731 else
732 size1 += r_size;
733
734 if (realloc_head)
735 children_add_size += get_res_add_size(realloc_head, r);
736 }
737 }
738 size0 = calculate_iosize(size, min_size, size1,
739 resource_size(b_res), 4096);
740 if (children_add_size > add_size)
741 add_size = children_add_size;
742 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
743 calculate_iosize(size, min_size, add_size + size1,
744 resource_size(b_res), 4096);
745 if (!size0 && !size1) {
746 if (b_res->start || b_res->end)
747 dev_info(&bus->self->dev, "disabling bridge window "
748 "%pR to [bus %02x-%02x] (unused)\n", b_res,
749 bus->secondary, bus->subordinate);
750 b_res->flags = 0;
751 return;
752 }
753 /* Alignment of the IO window is always 4K */
754 b_res->start = 4096;
755 b_res->end = b_res->start + size0 - 1;
756 b_res->flags |= IORESOURCE_STARTALIGN;
757 if (size1 > size0 && realloc_head) {
758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760 "%pR to [bus %02x-%02x] add_size %lx\n", b_res,
761 bus->secondary, bus->subordinate, size1-size0);
762 }
763}
764
765/**
766 * pbus_size_mem() - size the memory window of a given bus
767 *
768 * @bus : the bus
769 * @min_size : the minimum memory window that must to be allocated
770 * @add_size : additional optional memory window
771 * @realloc_head : track the additional memory window on this list
772 *
773 * Calculate the size of the bus and minimal alignment which
774 * guarantees that all child resources fit in this size.
775 */
776static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
777 unsigned long type, resource_size_t min_size,
778 resource_size_t add_size,
779 struct list_head *realloc_head)
780{
781 struct pci_dev *dev;
782 resource_size_t min_align, align, size, size0, size1;
783 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
784 int order, max_order;
785 struct resource *b_res = find_free_bus_resource(bus, type);
786 unsigned int mem64_mask = 0;
787 resource_size_t children_add_size = 0;
788
789 if (!b_res)
790 return 0;
791
792 memset(aligns, 0, sizeof(aligns));
793 max_order = 0;
794 size = 0;
795
796 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
797 b_res->flags &= ~IORESOURCE_MEM_64;
798
799 list_for_each_entry(dev, &bus->devices, bus_list) {
800 int i;
801
802 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
803 struct resource *r = &dev->resource[i];
804 resource_size_t r_size;
805
806 if (r->parent || (r->flags & mask) != type)
807 continue;
808 r_size = resource_size(r);
809#ifdef CONFIG_PCI_IOV
810 /* put SRIOV requested res to the optional list */
811 if (realloc_head && i >= PCI_IOV_RESOURCES &&
812 i <= PCI_IOV_RESOURCE_END) {
813 r->end = r->start - 1;
814 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
815 children_add_size += r_size;
816 continue;
817 }
818#endif
819 /* For bridges size != alignment */
820 align = pci_resource_alignment(dev, r);
821 order = __ffs(align) - 20;
822 if (order > 11) {
823 dev_warn(&dev->dev, "disabling BAR %d: %pR "
824 "(bad alignment %#llx)\n", i, r,
825 (unsigned long long) align);
826 r->flags = 0;
827 continue;
828 }
829 size += r_size;
830 if (order < 0)
831 order = 0;
832 /* Exclude ranges with size > align from
833 calculation of the alignment. */
834 if (r_size == align)
835 aligns[order] += align;
836 if (order > max_order)
837 max_order = order;
838 mem64_mask &= r->flags & IORESOURCE_MEM_64;
839
840 if (realloc_head)
841 children_add_size += get_res_add_size(realloc_head, r);
842 }
843 }
844 align = 0;
845 min_align = 0;
846 for (order = 0; order <= max_order; order++) {
847 resource_size_t align1 = 1;
848
849 align1 <<= (order + 20);
850
851 if (!align)
852 min_align = align1;
853 else if (ALIGN(align + min_align, min_align) < align1)
854 min_align = align1 >> 1;
855 align += aligns[order];
856 }
857 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
858 if (children_add_size > add_size)
859 add_size = children_add_size;
860 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
861 calculate_memsize(size, min_size, add_size,
862 resource_size(b_res), min_align);
863 if (!size0 && !size1) {
864 if (b_res->start || b_res->end)
865 dev_info(&bus->self->dev, "disabling bridge window "
866 "%pR to [bus %02x-%02x] (unused)\n", b_res,
867 bus->secondary, bus->subordinate);
868 b_res->flags = 0;
869 return 1;
870 }
871 b_res->start = min_align;
872 b_res->end = size0 + min_align - 1;
873 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
874 if (size1 > size0 && realloc_head) {
875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to [bus %02x-%02x] add_size %llx\n", b_res,
878 bus->secondary, bus->subordinate, (unsigned long long)size1-size0);
879 }
880 return 1;
881}
882
883unsigned long pci_cardbus_resource_alignment(struct resource *res)
884{
885 if (res->flags & IORESOURCE_IO)
886 return pci_cardbus_io_size;
887 if (res->flags & IORESOURCE_MEM)
888 return pci_cardbus_mem_size;
889 return 0;
890}
891
892static void pci_bus_size_cardbus(struct pci_bus *bus,
893 struct list_head *realloc_head)
894{
895 struct pci_dev *bridge = bus->self;
896 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
897 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
898 u16 ctrl;
899
900 if (b_res[0].parent)
901 goto handle_b_res_1;
902 /*
903 * Reserve some resources for CardBus. We reserve
904 * a fixed amount of bus space for CardBus bridges.
905 */
906 b_res[0].start = pci_cardbus_io_size;
907 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
908 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
909 if (realloc_head) {
910 b_res[0].end -= pci_cardbus_io_size;
911 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
912 pci_cardbus_io_size);
913 }
914
915handle_b_res_1:
916 if (b_res[1].parent)
917 goto handle_b_res_2;
918 b_res[1].start = pci_cardbus_io_size;
919 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
920 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
921 if (realloc_head) {
922 b_res[1].end -= pci_cardbus_io_size;
923 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
924 pci_cardbus_io_size);
925 }
926
927handle_b_res_2:
928 /* MEM1 must not be pref mmio */
929 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
930 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
931 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
932 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
933 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
934 }
935
936 /*
937 * Check whether prefetchable memory is supported
938 * by this bridge.
939 */
940 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
941 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
942 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
943 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
944 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
945 }
946
947 if (b_res[2].parent)
948 goto handle_b_res_3;
949 /*
950 * If we have prefetchable memory support, allocate
951 * two regions. Otherwise, allocate one region of
952 * twice the size.
953 */
954 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
955 b_res[2].start = pci_cardbus_mem_size;
956 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
957 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
958 IORESOURCE_STARTALIGN;
959 if (realloc_head) {
960 b_res[2].end -= pci_cardbus_mem_size;
961 add_to_list(realloc_head, bridge, b_res+2,
962 pci_cardbus_mem_size, pci_cardbus_mem_size);
963 }
964
965 /* reduce that to half */
966 b_res_3_size = pci_cardbus_mem_size;
967 }
968
969handle_b_res_3:
970 if (b_res[3].parent)
971 goto handle_done;
972 b_res[3].start = pci_cardbus_mem_size;
973 b_res[3].end = b_res[3].start + b_res_3_size - 1;
974 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
975 if (realloc_head) {
976 b_res[3].end -= b_res_3_size;
977 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
978 pci_cardbus_mem_size);
979 }
980
981handle_done:
982 ;
983}
984
985void __ref __pci_bus_size_bridges(struct pci_bus *bus,
986 struct list_head *realloc_head)
987{
988 struct pci_dev *dev;
989 unsigned long mask, prefmask;
990 resource_size_t additional_mem_size = 0, additional_io_size = 0;
991
992 list_for_each_entry(dev, &bus->devices, bus_list) {
993 struct pci_bus *b = dev->subordinate;
994 if (!b)
995 continue;
996
997 switch (dev->class >> 8) {
998 case PCI_CLASS_BRIDGE_CARDBUS:
999 pci_bus_size_cardbus(b, realloc_head);
1000 break;
1001
1002 case PCI_CLASS_BRIDGE_PCI:
1003 default:
1004 __pci_bus_size_bridges(b, realloc_head);
1005 break;
1006 }
1007 }
1008
1009 /* The root bus? */
1010 if (!bus->self)
1011 return;
1012
1013 switch (bus->self->class >> 8) {
1014 case PCI_CLASS_BRIDGE_CARDBUS:
1015 /* don't size cardbuses yet. */
1016 break;
1017
1018 case PCI_CLASS_BRIDGE_PCI:
1019 pci_bridge_check_ranges(bus);
1020 if (bus->self->is_hotplug_bridge) {
1021 additional_io_size = pci_hotplug_io_size;
1022 additional_mem_size = pci_hotplug_mem_size;
1023 }
1024 /*
1025 * Follow thru
1026 */
1027 default:
1028 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1029 additional_io_size, realloc_head);
1030 /* If the bridge supports prefetchable range, size it
1031 separately. If it doesn't, or its prefetchable window
1032 has already been allocated by arch code, try
1033 non-prefetchable range for both types of PCI memory
1034 resources. */
1035 mask = IORESOURCE_MEM;
1036 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1037 if (pbus_size_mem(bus, prefmask, prefmask,
1038 realloc_head ? 0 : additional_mem_size,
1039 additional_mem_size, realloc_head))
1040 mask = prefmask; /* Success, size non-prefetch only. */
1041 else
1042 additional_mem_size += additional_mem_size;
1043 pbus_size_mem(bus, mask, IORESOURCE_MEM,
1044 realloc_head ? 0 : additional_mem_size,
1045 additional_mem_size, realloc_head);
1046 break;
1047 }
1048}
1049
1050void __ref pci_bus_size_bridges(struct pci_bus *bus)
1051{
1052 __pci_bus_size_bridges(bus, NULL);
1053}
1054EXPORT_SYMBOL(pci_bus_size_bridges);
1055
1056static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1057 struct list_head *realloc_head,
1058 struct list_head *fail_head)
1059{
1060 struct pci_bus *b;
1061 struct pci_dev *dev;
1062
1063 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1064
1065 list_for_each_entry(dev, &bus->devices, bus_list) {
1066 b = dev->subordinate;
1067 if (!b)
1068 continue;
1069
1070 __pci_bus_assign_resources(b, realloc_head, fail_head);
1071
1072 switch (dev->class >> 8) {
1073 case PCI_CLASS_BRIDGE_PCI:
1074 if (!pci_is_enabled(dev))
1075 pci_setup_bridge(b);
1076 break;
1077
1078 case PCI_CLASS_BRIDGE_CARDBUS:
1079 pci_setup_cardbus(b);
1080 break;
1081
1082 default:
1083 dev_info(&dev->dev, "not setting up bridge for bus "
1084 "%04x:%02x\n", pci_domain_nr(b), b->number);
1085 break;
1086 }
1087 }
1088}
1089
1090void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1091{
1092 __pci_bus_assign_resources(bus, NULL, NULL);
1093}
1094EXPORT_SYMBOL(pci_bus_assign_resources);
1095
1096static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1097 struct list_head *add_head,
1098 struct list_head *fail_head)
1099{
1100 struct pci_bus *b;
1101
1102 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1103 add_head, fail_head);
1104
1105 b = bridge->subordinate;
1106 if (!b)
1107 return;
1108
1109 __pci_bus_assign_resources(b, add_head, fail_head);
1110
1111 switch (bridge->class >> 8) {
1112 case PCI_CLASS_BRIDGE_PCI:
1113 pci_setup_bridge(b);
1114 break;
1115
1116 case PCI_CLASS_BRIDGE_CARDBUS:
1117 pci_setup_cardbus(b);
1118 break;
1119
1120 default:
1121 dev_info(&bridge->dev, "not setting up bridge for bus "
1122 "%04x:%02x\n", pci_domain_nr(b), b->number);
1123 break;
1124 }
1125}
1126static void pci_bridge_release_resources(struct pci_bus *bus,
1127 unsigned long type)
1128{
1129 int idx;
1130 bool changed = false;
1131 struct pci_dev *dev;
1132 struct resource *r;
1133 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1134 IORESOURCE_PREFETCH;
1135
1136 dev = bus->self;
1137 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1138 idx++) {
1139 r = &dev->resource[idx];
1140 if ((r->flags & type_mask) != type)
1141 continue;
1142 if (!r->parent)
1143 continue;
1144 /*
1145 * if there are children under that, we should release them
1146 * all
1147 */
1148 release_child_resources(r);
1149 if (!release_resource(r)) {
1150 dev_printk(KERN_DEBUG, &dev->dev,
1151 "resource %d %pR released\n", idx, r);
1152 /* keep the old size */
1153 r->end = resource_size(r) - 1;
1154 r->start = 0;
1155 r->flags = 0;
1156 changed = true;
1157 }
1158 }
1159
1160 if (changed) {
1161 /* avoiding touch the one without PREF */
1162 if (type & IORESOURCE_PREFETCH)
1163 type = IORESOURCE_PREFETCH;
1164 __pci_setup_bridge(bus, type);
1165 }
1166}
1167
1168enum release_type {
1169 leaf_only,
1170 whole_subtree,
1171};
1172/*
1173 * try to release pci bridge resources that is from leaf bridge,
1174 * so we can allocate big new one later
1175 */
1176static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1177 unsigned long type,
1178 enum release_type rel_type)
1179{
1180 struct pci_dev *dev;
1181 bool is_leaf_bridge = true;
1182
1183 list_for_each_entry(dev, &bus->devices, bus_list) {
1184 struct pci_bus *b = dev->subordinate;
1185 if (!b)
1186 continue;
1187
1188 is_leaf_bridge = false;
1189
1190 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1191 continue;
1192
1193 if (rel_type == whole_subtree)
1194 pci_bus_release_bridge_resources(b, type,
1195 whole_subtree);
1196 }
1197
1198 if (pci_is_root_bus(bus))
1199 return;
1200
1201 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1202 return;
1203
1204 if ((rel_type == whole_subtree) || is_leaf_bridge)
1205 pci_bridge_release_resources(bus, type);
1206}
1207
1208static void pci_bus_dump_res(struct pci_bus *bus)
1209{
1210 struct resource *res;
1211 int i;
1212
1213 pci_bus_for_each_resource(bus, res, i) {
1214 if (!res || !res->end || !res->flags)
1215 continue;
1216
1217 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1218 }
1219}
1220
1221static void pci_bus_dump_resources(struct pci_bus *bus)
1222{
1223 struct pci_bus *b;
1224 struct pci_dev *dev;
1225
1226
1227 pci_bus_dump_res(bus);
1228
1229 list_for_each_entry(dev, &bus->devices, bus_list) {
1230 b = dev->subordinate;
1231 if (!b)
1232 continue;
1233
1234 pci_bus_dump_resources(b);
1235 }
1236}
1237
1238static int __init pci_bus_get_depth(struct pci_bus *bus)
1239{
1240 int depth = 0;
1241 struct pci_dev *dev;
1242
1243 list_for_each_entry(dev, &bus->devices, bus_list) {
1244 int ret;
1245 struct pci_bus *b = dev->subordinate;
1246 if (!b)
1247 continue;
1248
1249 ret = pci_bus_get_depth(b);
1250 if (ret + 1 > depth)
1251 depth = ret + 1;
1252 }
1253
1254 return depth;
1255}
1256static int __init pci_get_max_depth(void)
1257{
1258 int depth = 0;
1259 struct pci_bus *bus;
1260
1261 list_for_each_entry(bus, &pci_root_buses, node) {
1262 int ret;
1263
1264 ret = pci_bus_get_depth(bus);
1265 if (ret > depth)
1266 depth = ret;
1267 }
1268
1269 return depth;
1270}
1271
1272/*
1273 * -1: undefined, will auto detect later
1274 * 0: disabled by user
1275 * 1: disabled by auto detect
1276 * 2: enabled by user
1277 * 3: enabled by auto detect
1278 */
1279enum enable_type {
1280 undefined = -1,
1281 user_disabled,
1282 auto_disabled,
1283 user_enabled,
1284 auto_enabled,
1285};
1286
1287static enum enable_type pci_realloc_enable __initdata = undefined;
1288void __init pci_realloc_get_opt(char *str)
1289{
1290 if (!strncmp(str, "off", 3))
1291 pci_realloc_enable = user_disabled;
1292 else if (!strncmp(str, "on", 2))
1293 pci_realloc_enable = user_enabled;
1294}
1295static bool __init pci_realloc_enabled(void)
1296{
1297 return pci_realloc_enable >= user_enabled;
1298}
1299
1300static void __init pci_realloc_detect(void)
1301{
1302#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1303 struct pci_dev *dev = NULL;
1304
1305 if (pci_realloc_enable != undefined)
1306 return;
1307
1308 for_each_pci_dev(dev) {
1309 int i;
1310
1311 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1312 struct resource *r = &dev->resource[i];
1313
1314 /* Not assigned, or rejected by kernel ? */
1315 if (r->flags && !r->start) {
1316 pci_realloc_enable = auto_enabled;
1317
1318 return;
1319 }
1320 }
1321 }
1322#endif
1323}
1324
1325/*
1326 * first try will not touch pci bridge res
1327 * second and later try will clear small leaf bridge res
1328 * will stop till to the max deepth if can not find good one
1329 */
1330void __init
1331pci_assign_unassigned_resources(void)
1332{
1333 struct pci_bus *bus;
1334 LIST_HEAD(realloc_head); /* list of resources that
1335 want additional resources */
1336 struct list_head *add_list = NULL;
1337 int tried_times = 0;
1338 enum release_type rel_type = leaf_only;
1339 LIST_HEAD(fail_head);
1340 struct pci_dev_resource *fail_res;
1341 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1342 IORESOURCE_PREFETCH;
1343 int pci_try_num = 1;
1344
1345 /* don't realloc if asked to do so */
1346 pci_realloc_detect();
1347 if (pci_realloc_enabled()) {
1348 int max_depth = pci_get_max_depth();
1349
1350 pci_try_num = max_depth + 1;
1351 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1352 max_depth, pci_try_num);
1353 }
1354
1355again:
1356 /*
1357 * last try will use add_list, otherwise will try good to have as
1358 * must have, so can realloc parent bridge resource
1359 */
1360 if (tried_times + 1 == pci_try_num)
1361 add_list = &realloc_head;
1362 /* Depth first, calculate sizes and alignments of all
1363 subordinate buses. */
1364 list_for_each_entry(bus, &pci_root_buses, node)
1365 __pci_bus_size_bridges(bus, add_list);
1366
1367 /* Depth last, allocate resources and update the hardware. */
1368 list_for_each_entry(bus, &pci_root_buses, node)
1369 __pci_bus_assign_resources(bus, add_list, &fail_head);
1370 if (add_list)
1371 BUG_ON(!list_empty(add_list));
1372 tried_times++;
1373
1374 /* any device complain? */
1375 if (list_empty(&fail_head))
1376 goto enable_and_dump;
1377
1378 if (tried_times >= pci_try_num) {
1379 if (pci_realloc_enable == undefined)
1380 printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1381 else if (pci_realloc_enable == auto_enabled)
1382 printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1383
1384 free_list(&fail_head);
1385 goto enable_and_dump;
1386 }
1387
1388 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1389 tried_times + 1);
1390
1391 /* third times and later will not check if it is leaf */
1392 if ((tried_times + 1) > 2)
1393 rel_type = whole_subtree;
1394
1395 /*
1396 * Try to release leaf bridge's resources that doesn't fit resource of
1397 * child device under that bridge
1398 */
1399 list_for_each_entry(fail_res, &fail_head, list) {
1400 bus = fail_res->dev->bus;
1401 pci_bus_release_bridge_resources(bus,
1402 fail_res->flags & type_mask,
1403 rel_type);
1404 }
1405 /* restore size and flags */
1406 list_for_each_entry(fail_res, &fail_head, list) {
1407 struct resource *res = fail_res->res;
1408
1409 res->start = fail_res->start;
1410 res->end = fail_res->end;
1411 res->flags = fail_res->flags;
1412 if (fail_res->dev->subordinate)
1413 res->flags = 0;
1414 }
1415 free_list(&fail_head);
1416
1417 goto again;
1418
1419enable_and_dump:
1420 /* Depth last, update the hardware. */
1421 list_for_each_entry(bus, &pci_root_buses, node)
1422 pci_enable_bridges(bus);
1423
1424 /* dump the resource on buses */
1425 list_for_each_entry(bus, &pci_root_buses, node)
1426 pci_bus_dump_resources(bus);
1427}
1428
1429void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1430{
1431 struct pci_bus *parent = bridge->subordinate;
1432 LIST_HEAD(add_list); /* list of resources that
1433 want additional resources */
1434 int tried_times = 0;
1435 LIST_HEAD(fail_head);
1436 struct pci_dev_resource *fail_res;
1437 int retval;
1438 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1439 IORESOURCE_PREFETCH;
1440
1441again:
1442 __pci_bus_size_bridges(parent, &add_list);
1443 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1444 BUG_ON(!list_empty(&add_list));
1445 tried_times++;
1446
1447 if (list_empty(&fail_head))
1448 goto enable_all;
1449
1450 if (tried_times >= 2) {
1451 /* still fail, don't need to try more */
1452 free_list(&fail_head);
1453 goto enable_all;
1454 }
1455
1456 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1457 tried_times + 1);
1458
1459 /*
1460 * Try to release leaf bridge's resources that doesn't fit resource of
1461 * child device under that bridge
1462 */
1463 list_for_each_entry(fail_res, &fail_head, list) {
1464 struct pci_bus *bus = fail_res->dev->bus;
1465 unsigned long flags = fail_res->flags;
1466
1467 pci_bus_release_bridge_resources(bus, flags & type_mask,
1468 whole_subtree);
1469 }
1470 /* restore size and flags */
1471 list_for_each_entry(fail_res, &fail_head, list) {
1472 struct resource *res = fail_res->res;
1473
1474 res->start = fail_res->start;
1475 res->end = fail_res->end;
1476 res->flags = fail_res->flags;
1477 if (fail_res->dev->subordinate)
1478 res->flags = 0;
1479 }
1480 free_list(&fail_head);
1481
1482 goto again;
1483
1484enable_all:
1485 retval = pci_reenable_device(bridge);
1486 pci_set_master(bridge);
1487 pci_enable_bridges(parent);
1488}
1489EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1490
1491#ifdef CONFIG_HOTPLUG
1492/**
1493 * pci_rescan_bus - scan a PCI bus for devices.
1494 * @bus: PCI bus to scan
1495 *
1496 * Scan a PCI bus and child buses for new devices, adds them,
1497 * and enables them.
1498 *
1499 * Returns the max number of subordinate bus discovered.
1500 */
1501unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1502{
1503 unsigned int max;
1504 struct pci_dev *dev;
1505 LIST_HEAD(add_list); /* list of resources that
1506 want additional resources */
1507
1508 max = pci_scan_child_bus(bus);
1509
1510 down_read(&pci_bus_sem);
1511 list_for_each_entry(dev, &bus->devices, bus_list)
1512 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1513 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1514 if (dev->subordinate)
1515 __pci_bus_size_bridges(dev->subordinate,
1516 &add_list);
1517 up_read(&pci_bus_sem);
1518 __pci_bus_assign_resources(bus, &add_list, NULL);
1519 BUG_ON(!list_empty(&add_list));
1520
1521 pci_enable_bridges(bus);
1522 pci_bus_add_devices(bus);
1523
1524 return max;
1525}
1526EXPORT_SYMBOL_GPL(pci_rescan_bus);
1527#endif
1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include <linux/acpi.h>
29#include "pci.h"
30
31unsigned int pci_flags;
32
33struct pci_dev_resource {
34 struct list_head list;
35 struct resource *res;
36 struct pci_dev *dev;
37 resource_size_t start;
38 resource_size_t end;
39 resource_size_t add_size;
40 resource_size_t min_align;
41 unsigned long flags;
42};
43
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
53
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
63static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
66{
67 struct pci_dev_resource *tmp;
68
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 if (!tmp) {
71 pr_warn("add_to_list: kmalloc() failed!\n");
72 return -ENOMEM;
73 }
74
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
82
83 list_add(&tmp->list, head);
84
85 return 0;
86}
87
88static void remove_from_list(struct list_head *head,
89 struct resource *res)
90{
91 struct pci_dev_resource *dev_res, *tmp;
92
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
97 break;
98 }
99 }
100}
101
102static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
103 struct resource *res)
104{
105 struct pci_dev_resource *dev_res;
106
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
110
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n",
113 idx, dev_res->res,
114 (unsigned long long)dev_res->add_size,
115 (unsigned long long)dev_res->min_align);
116
117 return dev_res;
118 }
119 }
120
121 return NULL;
122}
123
124static resource_size_t get_res_add_size(struct list_head *head,
125 struct resource *res)
126{
127 struct pci_dev_resource *dev_res;
128
129 dev_res = res_to_dev_res(head, res);
130 return dev_res ? dev_res->add_size : 0;
131}
132
133static resource_size_t get_res_add_align(struct list_head *head,
134 struct resource *res)
135{
136 struct pci_dev_resource *dev_res;
137
138 dev_res = res_to_dev_res(head, res);
139 return dev_res ? dev_res->min_align : 0;
140}
141
142
143/* Sort resources by alignment */
144static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
145{
146 int i;
147
148 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
149 struct resource *r;
150 struct pci_dev_resource *dev_res, *tmp;
151 resource_size_t r_align;
152 struct list_head *n;
153
154 r = &dev->resource[i];
155
156 if (r->flags & IORESOURCE_PCI_FIXED)
157 continue;
158
159 if (!(r->flags) || r->parent)
160 continue;
161
162 r_align = pci_resource_alignment(dev, r);
163 if (!r_align) {
164 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
165 i, r);
166 continue;
167 }
168
169 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
170 if (!tmp)
171 panic("pdev_sort_resources(): kmalloc() failed!\n");
172 tmp->res = r;
173 tmp->dev = dev;
174
175 /* fallback is smallest one or list is empty*/
176 n = head;
177 list_for_each_entry(dev_res, head, list) {
178 resource_size_t align;
179
180 align = pci_resource_alignment(dev_res->dev,
181 dev_res->res);
182
183 if (r_align > align) {
184 n = &dev_res->list;
185 break;
186 }
187 }
188 /* Insert it just before n*/
189 list_add_tail(&tmp->list, n);
190 }
191}
192
193static void __dev_sort_resources(struct pci_dev *dev,
194 struct list_head *head)
195{
196 u16 class = dev->class >> 8;
197
198 /* Don't touch classless devices or host bridges or ioapics. */
199 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
200 return;
201
202 /* Don't touch ioapic devices already enabled by firmware */
203 if (class == PCI_CLASS_SYSTEM_PIC) {
204 u16 command;
205 pci_read_config_word(dev, PCI_COMMAND, &command);
206 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
207 return;
208 }
209
210 pdev_sort_resources(dev, head);
211}
212
213static inline void reset_resource(struct resource *res)
214{
215 res->start = 0;
216 res->end = 0;
217 res->flags = 0;
218}
219
220/**
221 * reassign_resources_sorted() - satisfy any additional resource requests
222 *
223 * @realloc_head : head of the list tracking requests requiring additional
224 * resources
225 * @head : head of the list tracking requests with allocated
226 * resources
227 *
228 * Walk through each element of the realloc_head and try to procure
229 * additional resources for the element, provided the element
230 * is in the head list.
231 */
232static void reassign_resources_sorted(struct list_head *realloc_head,
233 struct list_head *head)
234{
235 struct resource *res;
236 struct pci_dev_resource *add_res, *tmp;
237 struct pci_dev_resource *dev_res;
238 resource_size_t add_size, align;
239 int idx;
240
241 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
242 bool found_match = false;
243
244 res = add_res->res;
245 /* skip resource that has been reset */
246 if (!res->flags)
247 goto out;
248
249 /* skip this resource if not found in head list */
250 list_for_each_entry(dev_res, head, list) {
251 if (dev_res->res == res) {
252 found_match = true;
253 break;
254 }
255 }
256 if (!found_match)/* just skip */
257 continue;
258
259 idx = res - &add_res->dev->resource[0];
260 add_size = add_res->add_size;
261 align = add_res->min_align;
262 if (!resource_size(res)) {
263 res->start = align;
264 res->end = res->start + add_size - 1;
265 if (pci_assign_resource(add_res->dev, idx))
266 reset_resource(res);
267 } else {
268 res->flags |= add_res->flags &
269 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
270 if (pci_reassign_resource(add_res->dev, idx,
271 add_size, align))
272 dev_printk(KERN_DEBUG, &add_res->dev->dev,
273 "failed to add %llx res[%d]=%pR\n",
274 (unsigned long long)add_size,
275 idx, res);
276 }
277out:
278 list_del(&add_res->list);
279 kfree(add_res);
280 }
281}
282
283/**
284 * assign_requested_resources_sorted() - satisfy resource requests
285 *
286 * @head : head of the list tracking requests for resources
287 * @fail_head : head of the list tracking requests that could
288 * not be allocated
289 *
290 * Satisfy resource requests of each element in the list. Add
291 * requests that could not satisfied to the failed_list.
292 */
293static void assign_requested_resources_sorted(struct list_head *head,
294 struct list_head *fail_head)
295{
296 struct resource *res;
297 struct pci_dev_resource *dev_res;
298 int idx;
299
300 list_for_each_entry(dev_res, head, list) {
301 res = dev_res->res;
302 idx = res - &dev_res->dev->resource[0];
303 if (resource_size(res) &&
304 pci_assign_resource(dev_res->dev, idx)) {
305 if (fail_head) {
306 /*
307 * if the failed res is for ROM BAR, and it will
308 * be enabled later, don't add it to the list
309 */
310 if (!((idx == PCI_ROM_RESOURCE) &&
311 (!(res->flags & IORESOURCE_ROM_ENABLE))))
312 add_to_list(fail_head,
313 dev_res->dev, res,
314 0 /* don't care */,
315 0 /* don't care */);
316 }
317 reset_resource(res);
318 }
319 }
320}
321
322static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
323{
324 struct pci_dev_resource *fail_res;
325 unsigned long mask = 0;
326
327 /* check failed type */
328 list_for_each_entry(fail_res, fail_head, list)
329 mask |= fail_res->flags;
330
331 /*
332 * one pref failed resource will set IORESOURCE_MEM,
333 * as we can allocate pref in non-pref range.
334 * Will release all assigned non-pref sibling resources
335 * according to that bit.
336 */
337 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
338}
339
340static bool pci_need_to_release(unsigned long mask, struct resource *res)
341{
342 if (res->flags & IORESOURCE_IO)
343 return !!(mask & IORESOURCE_IO);
344
345 /* check pref at first */
346 if (res->flags & IORESOURCE_PREFETCH) {
347 if (mask & IORESOURCE_PREFETCH)
348 return true;
349 /* count pref if its parent is non-pref */
350 else if ((mask & IORESOURCE_MEM) &&
351 !(res->parent->flags & IORESOURCE_PREFETCH))
352 return true;
353 else
354 return false;
355 }
356
357 if (res->flags & IORESOURCE_MEM)
358 return !!(mask & IORESOURCE_MEM);
359
360 return false; /* should not get here */
361}
362
363static void __assign_resources_sorted(struct list_head *head,
364 struct list_head *realloc_head,
365 struct list_head *fail_head)
366{
367 /*
368 * Should not assign requested resources at first.
369 * they could be adjacent, so later reassign can not reallocate
370 * them one by one in parent resource window.
371 * Try to assign requested + add_size at beginning
372 * if could do that, could get out early.
373 * if could not do that, we still try to assign requested at first,
374 * then try to reassign add_size for some resources.
375 *
376 * Separate three resource type checking if we need to release
377 * assigned resource after requested + add_size try.
378 * 1. if there is io port assign fail, will release assigned
379 * io port.
380 * 2. if there is pref mmio assign fail, release assigned
381 * pref mmio.
382 * if assigned pref mmio's parent is non-pref mmio and there
383 * is non-pref mmio assign fail, will release that assigned
384 * pref mmio.
385 * 3. if there is non-pref mmio assign fail or pref mmio
386 * assigned fail, will release assigned non-pref mmio.
387 */
388 LIST_HEAD(save_head);
389 LIST_HEAD(local_fail_head);
390 struct pci_dev_resource *save_res;
391 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
392 unsigned long fail_type;
393 resource_size_t add_align, align;
394
395 /* Check if optional add_size is there */
396 if (!realloc_head || list_empty(realloc_head))
397 goto requested_and_reassign;
398
399 /* Save original start, end, flags etc at first */
400 list_for_each_entry(dev_res, head, list) {
401 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
402 free_list(&save_head);
403 goto requested_and_reassign;
404 }
405 }
406
407 /* Update res in head list with add_size in realloc_head list */
408 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
409 dev_res->res->end += get_res_add_size(realloc_head,
410 dev_res->res);
411
412 /*
413 * There are two kinds of additional resources in the list:
414 * 1. bridge resource -- IORESOURCE_STARTALIGN
415 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
416 * Here just fix the additional alignment for bridge
417 */
418 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
419 continue;
420
421 add_align = get_res_add_align(realloc_head, dev_res->res);
422
423 /*
424 * The "head" list is sorted by the alignment to make sure
425 * resources with bigger alignment will be assigned first.
426 * After we change the alignment of a dev_res in "head" list,
427 * we need to reorder the list by alignment to make it
428 * consistent.
429 */
430 if (add_align > dev_res->res->start) {
431 resource_size_t r_size = resource_size(dev_res->res);
432
433 dev_res->res->start = add_align;
434 dev_res->res->end = add_align + r_size - 1;
435
436 list_for_each_entry(dev_res2, head, list) {
437 align = pci_resource_alignment(dev_res2->dev,
438 dev_res2->res);
439 if (add_align > align) {
440 list_move_tail(&dev_res->list,
441 &dev_res2->list);
442 break;
443 }
444 }
445 }
446
447 }
448
449 /* Try updated head list with add_size added */
450 assign_requested_resources_sorted(head, &local_fail_head);
451
452 /* all assigned with add_size ? */
453 if (list_empty(&local_fail_head)) {
454 /* Remove head list from realloc_head list */
455 list_for_each_entry(dev_res, head, list)
456 remove_from_list(realloc_head, dev_res->res);
457 free_list(&save_head);
458 free_list(head);
459 return;
460 }
461
462 /* check failed type */
463 fail_type = pci_fail_res_type_mask(&local_fail_head);
464 /* remove not need to be released assigned res from head list etc */
465 list_for_each_entry_safe(dev_res, tmp_res, head, list)
466 if (dev_res->res->parent &&
467 !pci_need_to_release(fail_type, dev_res->res)) {
468 /* remove it from realloc_head list */
469 remove_from_list(realloc_head, dev_res->res);
470 remove_from_list(&save_head, dev_res->res);
471 list_del(&dev_res->list);
472 kfree(dev_res);
473 }
474
475 free_list(&local_fail_head);
476 /* Release assigned resource */
477 list_for_each_entry(dev_res, head, list)
478 if (dev_res->res->parent)
479 release_resource(dev_res->res);
480 /* Restore start/end/flags from saved list */
481 list_for_each_entry(save_res, &save_head, list) {
482 struct resource *res = save_res->res;
483
484 res->start = save_res->start;
485 res->end = save_res->end;
486 res->flags = save_res->flags;
487 }
488 free_list(&save_head);
489
490requested_and_reassign:
491 /* Satisfy the must-have resource requests */
492 assign_requested_resources_sorted(head, fail_head);
493
494 /* Try to satisfy any additional optional resource
495 requests */
496 if (realloc_head)
497 reassign_resources_sorted(realloc_head, head);
498 free_list(head);
499}
500
501static void pdev_assign_resources_sorted(struct pci_dev *dev,
502 struct list_head *add_head,
503 struct list_head *fail_head)
504{
505 LIST_HEAD(head);
506
507 __dev_sort_resources(dev, &head);
508 __assign_resources_sorted(&head, add_head, fail_head);
509
510}
511
512static void pbus_assign_resources_sorted(const struct pci_bus *bus,
513 struct list_head *realloc_head,
514 struct list_head *fail_head)
515{
516 struct pci_dev *dev;
517 LIST_HEAD(head);
518
519 list_for_each_entry(dev, &bus->devices, bus_list)
520 __dev_sort_resources(dev, &head);
521
522 __assign_resources_sorted(&head, realloc_head, fail_head);
523}
524
525void pci_setup_cardbus(struct pci_bus *bus)
526{
527 struct pci_dev *bridge = bus->self;
528 struct resource *res;
529 struct pci_bus_region region;
530
531 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
532 &bus->busn_res);
533
534 res = bus->resource[0];
535 pcibios_resource_to_bus(bridge->bus, ®ion, res);
536 if (res->flags & IORESOURCE_IO) {
537 /*
538 * The IO resource is allocated a range twice as large as it
539 * would normally need. This allows us to set both IO regs.
540 */
541 dev_info(&bridge->dev, " bridge window %pR\n", res);
542 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
543 region.start);
544 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
545 region.end);
546 }
547
548 res = bus->resource[1];
549 pcibios_resource_to_bus(bridge->bus, ®ion, res);
550 if (res->flags & IORESOURCE_IO) {
551 dev_info(&bridge->dev, " bridge window %pR\n", res);
552 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
553 region.start);
554 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
555 region.end);
556 }
557
558 res = bus->resource[2];
559 pcibios_resource_to_bus(bridge->bus, ®ion, res);
560 if (res->flags & IORESOURCE_MEM) {
561 dev_info(&bridge->dev, " bridge window %pR\n", res);
562 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
563 region.start);
564 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
565 region.end);
566 }
567
568 res = bus->resource[3];
569 pcibios_resource_to_bus(bridge->bus, ®ion, res);
570 if (res->flags & IORESOURCE_MEM) {
571 dev_info(&bridge->dev, " bridge window %pR\n", res);
572 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
573 region.start);
574 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
575 region.end);
576 }
577}
578EXPORT_SYMBOL(pci_setup_cardbus);
579
580/* Initialize bridges with base/limit values we have collected.
581 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
582 requires that if there is no I/O ports or memory behind the
583 bridge, corresponding range must be turned off by writing base
584 value greater than limit to the bridge's base/limit registers.
585
586 Note: care must be taken when updating I/O base/limit registers
587 of bridges which support 32-bit I/O. This update requires two
588 config space writes, so it's quite possible that an I/O window of
589 the bridge will have some undesirable address (e.g. 0) after the
590 first write. Ditto 64-bit prefetchable MMIO. */
591static void pci_setup_bridge_io(struct pci_dev *bridge)
592{
593 struct resource *res;
594 struct pci_bus_region region;
595 unsigned long io_mask;
596 u8 io_base_lo, io_limit_lo;
597 u16 l;
598 u32 io_upper16;
599
600 io_mask = PCI_IO_RANGE_MASK;
601 if (bridge->io_window_1k)
602 io_mask = PCI_IO_1K_RANGE_MASK;
603
604 /* Set up the top and bottom of the PCI I/O segment for this bus. */
605 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
606 pcibios_resource_to_bus(bridge->bus, ®ion, res);
607 if (res->flags & IORESOURCE_IO) {
608 pci_read_config_word(bridge, PCI_IO_BASE, &l);
609 io_base_lo = (region.start >> 8) & io_mask;
610 io_limit_lo = (region.end >> 8) & io_mask;
611 l = ((u16) io_limit_lo << 8) | io_base_lo;
612 /* Set up upper 16 bits of I/O base/limit. */
613 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
614 dev_info(&bridge->dev, " bridge window %pR\n", res);
615 } else {
616 /* Clear upper 16 bits of I/O base/limit. */
617 io_upper16 = 0;
618 l = 0x00f0;
619 }
620 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
621 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
622 /* Update lower 16 bits of I/O base/limit. */
623 pci_write_config_word(bridge, PCI_IO_BASE, l);
624 /* Update upper 16 bits of I/O base/limit. */
625 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
626}
627
628static void pci_setup_bridge_mmio(struct pci_dev *bridge)
629{
630 struct resource *res;
631 struct pci_bus_region region;
632 u32 l;
633
634 /* Set up the top and bottom of the PCI Memory segment for this bus. */
635 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
636 pcibios_resource_to_bus(bridge->bus, ®ion, res);
637 if (res->flags & IORESOURCE_MEM) {
638 l = (region.start >> 16) & 0xfff0;
639 l |= region.end & 0xfff00000;
640 dev_info(&bridge->dev, " bridge window %pR\n", res);
641 } else {
642 l = 0x0000fff0;
643 }
644 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
645}
646
647static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
648{
649 struct resource *res;
650 struct pci_bus_region region;
651 u32 l, bu, lu;
652
653 /* Clear out the upper 32 bits of PREF limit.
654 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
655 disables PREF range, which is ok. */
656 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
657
658 /* Set up PREF base/limit. */
659 bu = lu = 0;
660 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
661 pcibios_resource_to_bus(bridge->bus, ®ion, res);
662 if (res->flags & IORESOURCE_PREFETCH) {
663 l = (region.start >> 16) & 0xfff0;
664 l |= region.end & 0xfff00000;
665 if (res->flags & IORESOURCE_MEM_64) {
666 bu = upper_32_bits(region.start);
667 lu = upper_32_bits(region.end);
668 }
669 dev_info(&bridge->dev, " bridge window %pR\n", res);
670 } else {
671 l = 0x0000fff0;
672 }
673 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
674
675 /* Set the upper 32 bits of PREF base & limit. */
676 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
677 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
678}
679
680static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
681{
682 struct pci_dev *bridge = bus->self;
683
684 dev_info(&bridge->dev, "PCI bridge to %pR\n",
685 &bus->busn_res);
686
687 if (type & IORESOURCE_IO)
688 pci_setup_bridge_io(bridge);
689
690 if (type & IORESOURCE_MEM)
691 pci_setup_bridge_mmio(bridge);
692
693 if (type & IORESOURCE_PREFETCH)
694 pci_setup_bridge_mmio_pref(bridge);
695
696 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
697}
698
699void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
700{
701}
702
703void pci_setup_bridge(struct pci_bus *bus)
704{
705 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
706 IORESOURCE_PREFETCH;
707
708 pcibios_setup_bridge(bus, type);
709 __pci_setup_bridge(bus, type);
710}
711
712
713int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
714{
715 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
716 return 0;
717
718 if (pci_claim_resource(bridge, i) == 0)
719 return 0; /* claimed the window */
720
721 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
722 return 0;
723
724 if (!pci_bus_clip_resource(bridge, i))
725 return -EINVAL; /* clipping didn't change anything */
726
727 switch (i - PCI_BRIDGE_RESOURCES) {
728 case 0:
729 pci_setup_bridge_io(bridge);
730 break;
731 case 1:
732 pci_setup_bridge_mmio(bridge);
733 break;
734 case 2:
735 pci_setup_bridge_mmio_pref(bridge);
736 break;
737 default:
738 return -EINVAL;
739 }
740
741 if (pci_claim_resource(bridge, i) == 0)
742 return 0; /* claimed a smaller window */
743
744 return -EINVAL;
745}
746
747/* Check whether the bridge supports optional I/O and
748 prefetchable memory ranges. If not, the respective
749 base/limit registers must be read-only and read as 0. */
750static void pci_bridge_check_ranges(struct pci_bus *bus)
751{
752 u16 io;
753 u32 pmem;
754 struct pci_dev *bridge = bus->self;
755 struct resource *b_res;
756
757 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
758 b_res[1].flags |= IORESOURCE_MEM;
759
760 pci_read_config_word(bridge, PCI_IO_BASE, &io);
761 if (!io) {
762 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
763 pci_read_config_word(bridge, PCI_IO_BASE, &io);
764 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
765 }
766 if (io)
767 b_res[0].flags |= IORESOURCE_IO;
768
769 /* DECchip 21050 pass 2 errata: the bridge may miss an address
770 disconnect boundary by one PCI data phase.
771 Workaround: do not use prefetching on this device. */
772 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
773 return;
774
775 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
776 if (!pmem) {
777 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
778 0xffe0fff0);
779 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
780 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
781 }
782 if (pmem) {
783 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
784 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
785 PCI_PREF_RANGE_TYPE_64) {
786 b_res[2].flags |= IORESOURCE_MEM_64;
787 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
788 }
789 }
790
791 /* double check if bridge does support 64 bit pref */
792 if (b_res[2].flags & IORESOURCE_MEM_64) {
793 u32 mem_base_hi, tmp;
794 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
795 &mem_base_hi);
796 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
797 0xffffffff);
798 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
799 if (!tmp)
800 b_res[2].flags &= ~IORESOURCE_MEM_64;
801 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
802 mem_base_hi);
803 }
804}
805
806/* Helper function for sizing routines: find first available
807 bus resource of a given type. Note: we intentionally skip
808 the bus resources which have already been assigned (that is,
809 have non-NULL parent resource). */
810static struct resource *find_free_bus_resource(struct pci_bus *bus,
811 unsigned long type_mask, unsigned long type)
812{
813 int i;
814 struct resource *r;
815
816 pci_bus_for_each_resource(bus, r, i) {
817 if (r == &ioport_resource || r == &iomem_resource)
818 continue;
819 if (r && (r->flags & type_mask) == type && !r->parent)
820 return r;
821 }
822 return NULL;
823}
824
825static resource_size_t calculate_iosize(resource_size_t size,
826 resource_size_t min_size,
827 resource_size_t size1,
828 resource_size_t old_size,
829 resource_size_t align)
830{
831 if (size < min_size)
832 size = min_size;
833 if (old_size == 1)
834 old_size = 0;
835 /* To be fixed in 2.5: we should have sort of HAVE_ISA
836 flag in the struct pci_bus. */
837#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
838 size = (size & 0xff) + ((size & ~0xffUL) << 2);
839#endif
840 size = ALIGN(size + size1, align);
841 if (size < old_size)
842 size = old_size;
843 return size;
844}
845
846static resource_size_t calculate_memsize(resource_size_t size,
847 resource_size_t min_size,
848 resource_size_t size1,
849 resource_size_t old_size,
850 resource_size_t align)
851{
852 if (size < min_size)
853 size = min_size;
854 if (old_size == 1)
855 old_size = 0;
856 if (size < old_size)
857 size = old_size;
858 size = ALIGN(size + size1, align);
859 return size;
860}
861
862resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
863 unsigned long type)
864{
865 return 1;
866}
867
868#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
869#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
870#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
871
872static resource_size_t window_alignment(struct pci_bus *bus,
873 unsigned long type)
874{
875 resource_size_t align = 1, arch_align;
876
877 if (type & IORESOURCE_MEM)
878 align = PCI_P2P_DEFAULT_MEM_ALIGN;
879 else if (type & IORESOURCE_IO) {
880 /*
881 * Per spec, I/O windows are 4K-aligned, but some
882 * bridges have an extension to support 1K alignment.
883 */
884 if (bus->self->io_window_1k)
885 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
886 else
887 align = PCI_P2P_DEFAULT_IO_ALIGN;
888 }
889
890 arch_align = pcibios_window_alignment(bus, type);
891 return max(align, arch_align);
892}
893
894/**
895 * pbus_size_io() - size the io window of a given bus
896 *
897 * @bus : the bus
898 * @min_size : the minimum io window that must to be allocated
899 * @add_size : additional optional io window
900 * @realloc_head : track the additional io window on this list
901 *
902 * Sizing the IO windows of the PCI-PCI bridge is trivial,
903 * since these windows have 1K or 4K granularity and the IO ranges
904 * of non-bridge PCI devices are limited to 256 bytes.
905 * We must be careful with the ISA aliasing though.
906 */
907static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
908 resource_size_t add_size, struct list_head *realloc_head)
909{
910 struct pci_dev *dev;
911 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
912 IORESOURCE_IO);
913 resource_size_t size = 0, size0 = 0, size1 = 0;
914 resource_size_t children_add_size = 0;
915 resource_size_t min_align, align;
916
917 if (!b_res)
918 return;
919
920 min_align = window_alignment(bus, IORESOURCE_IO);
921 list_for_each_entry(dev, &bus->devices, bus_list) {
922 int i;
923
924 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
925 struct resource *r = &dev->resource[i];
926 unsigned long r_size;
927
928 if (r->parent || !(r->flags & IORESOURCE_IO))
929 continue;
930 r_size = resource_size(r);
931
932 if (r_size < 0x400)
933 /* Might be re-aligned for ISA */
934 size += r_size;
935 else
936 size1 += r_size;
937
938 align = pci_resource_alignment(dev, r);
939 if (align > min_align)
940 min_align = align;
941
942 if (realloc_head)
943 children_add_size += get_res_add_size(realloc_head, r);
944 }
945 }
946
947 size0 = calculate_iosize(size, min_size, size1,
948 resource_size(b_res), min_align);
949 if (children_add_size > add_size)
950 add_size = children_add_size;
951 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
952 calculate_iosize(size, min_size, add_size + size1,
953 resource_size(b_res), min_align);
954 if (!size0 && !size1) {
955 if (b_res->start || b_res->end)
956 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
957 b_res, &bus->busn_res);
958 b_res->flags = 0;
959 return;
960 }
961
962 b_res->start = min_align;
963 b_res->end = b_res->start + size0 - 1;
964 b_res->flags |= IORESOURCE_STARTALIGN;
965 if (size1 > size0 && realloc_head) {
966 add_to_list(realloc_head, bus->self, b_res, size1-size0,
967 min_align);
968 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
969 b_res, &bus->busn_res,
970 (unsigned long long)size1-size0);
971 }
972}
973
974static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
975 int max_order)
976{
977 resource_size_t align = 0;
978 resource_size_t min_align = 0;
979 int order;
980
981 for (order = 0; order <= max_order; order++) {
982 resource_size_t align1 = 1;
983
984 align1 <<= (order + 20);
985
986 if (!align)
987 min_align = align1;
988 else if (ALIGN(align + min_align, min_align) < align1)
989 min_align = align1 >> 1;
990 align += aligns[order];
991 }
992
993 return min_align;
994}
995
996/**
997 * pbus_size_mem() - size the memory window of a given bus
998 *
999 * @bus : the bus
1000 * @mask: mask the resource flag, then compare it with type
1001 * @type: the type of free resource from bridge
1002 * @type2: second match type
1003 * @type3: third match type
1004 * @min_size : the minimum memory window that must to be allocated
1005 * @add_size : additional optional memory window
1006 * @realloc_head : track the additional memory window on this list
1007 *
1008 * Calculate the size of the bus and minimal alignment which
1009 * guarantees that all child resources fit in this size.
1010 *
1011 * Returns -ENOSPC if there's no available bus resource of the desired type.
1012 * Otherwise, sets the bus resource start/end to indicate the required
1013 * size, adds things to realloc_head (if supplied), and returns 0.
1014 */
1015static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1016 unsigned long type, unsigned long type2,
1017 unsigned long type3,
1018 resource_size_t min_size, resource_size_t add_size,
1019 struct list_head *realloc_head)
1020{
1021 struct pci_dev *dev;
1022 resource_size_t min_align, align, size, size0, size1;
1023 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
1024 int order, max_order;
1025 struct resource *b_res = find_free_bus_resource(bus,
1026 mask | IORESOURCE_PREFETCH, type);
1027 resource_size_t children_add_size = 0;
1028 resource_size_t children_add_align = 0;
1029 resource_size_t add_align = 0;
1030
1031 if (!b_res)
1032 return -ENOSPC;
1033
1034 memset(aligns, 0, sizeof(aligns));
1035 max_order = 0;
1036 size = 0;
1037
1038 list_for_each_entry(dev, &bus->devices, bus_list) {
1039 int i;
1040
1041 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1042 struct resource *r = &dev->resource[i];
1043 resource_size_t r_size;
1044
1045 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1046 ((r->flags & mask) != type &&
1047 (r->flags & mask) != type2 &&
1048 (r->flags & mask) != type3))
1049 continue;
1050 r_size = resource_size(r);
1051#ifdef CONFIG_PCI_IOV
1052 /* put SRIOV requested res to the optional list */
1053 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1054 i <= PCI_IOV_RESOURCE_END) {
1055 add_align = max(pci_resource_alignment(dev, r), add_align);
1056 r->end = r->start - 1;
1057 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1058 children_add_size += r_size;
1059 continue;
1060 }
1061#endif
1062 /*
1063 * aligns[0] is for 1MB (since bridge memory
1064 * windows are always at least 1MB aligned), so
1065 * keep "order" from being negative for smaller
1066 * resources.
1067 */
1068 align = pci_resource_alignment(dev, r);
1069 order = __ffs(align) - 20;
1070 if (order < 0)
1071 order = 0;
1072 if (order >= ARRAY_SIZE(aligns)) {
1073 dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1074 i, r, (unsigned long long) align);
1075 r->flags = 0;
1076 continue;
1077 }
1078 size += r_size;
1079 /* Exclude ranges with size > align from
1080 calculation of the alignment. */
1081 if (r_size == align)
1082 aligns[order] += align;
1083 if (order > max_order)
1084 max_order = order;
1085
1086 if (realloc_head) {
1087 children_add_size += get_res_add_size(realloc_head, r);
1088 children_add_align = get_res_add_align(realloc_head, r);
1089 add_align = max(add_align, children_add_align);
1090 }
1091 }
1092 }
1093
1094 min_align = calculate_mem_align(aligns, max_order);
1095 min_align = max(min_align, window_alignment(bus, b_res->flags));
1096 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1097 add_align = max(min_align, add_align);
1098 if (children_add_size > add_size)
1099 add_size = children_add_size;
1100 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1101 calculate_memsize(size, min_size, add_size,
1102 resource_size(b_res), add_align);
1103 if (!size0 && !size1) {
1104 if (b_res->start || b_res->end)
1105 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
1106 b_res, &bus->busn_res);
1107 b_res->flags = 0;
1108 return 0;
1109 }
1110 b_res->start = min_align;
1111 b_res->end = size0 + min_align - 1;
1112 b_res->flags |= IORESOURCE_STARTALIGN;
1113 if (size1 > size0 && realloc_head) {
1114 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1115 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1116 b_res, &bus->busn_res,
1117 (unsigned long long) (size1 - size0),
1118 (unsigned long long) add_align);
1119 }
1120 return 0;
1121}
1122
1123unsigned long pci_cardbus_resource_alignment(struct resource *res)
1124{
1125 if (res->flags & IORESOURCE_IO)
1126 return pci_cardbus_io_size;
1127 if (res->flags & IORESOURCE_MEM)
1128 return pci_cardbus_mem_size;
1129 return 0;
1130}
1131
1132static void pci_bus_size_cardbus(struct pci_bus *bus,
1133 struct list_head *realloc_head)
1134{
1135 struct pci_dev *bridge = bus->self;
1136 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1137 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1138 u16 ctrl;
1139
1140 if (b_res[0].parent)
1141 goto handle_b_res_1;
1142 /*
1143 * Reserve some resources for CardBus. We reserve
1144 * a fixed amount of bus space for CardBus bridges.
1145 */
1146 b_res[0].start = pci_cardbus_io_size;
1147 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1148 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1149 if (realloc_head) {
1150 b_res[0].end -= pci_cardbus_io_size;
1151 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1152 pci_cardbus_io_size);
1153 }
1154
1155handle_b_res_1:
1156 if (b_res[1].parent)
1157 goto handle_b_res_2;
1158 b_res[1].start = pci_cardbus_io_size;
1159 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1160 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1161 if (realloc_head) {
1162 b_res[1].end -= pci_cardbus_io_size;
1163 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1164 pci_cardbus_io_size);
1165 }
1166
1167handle_b_res_2:
1168 /* MEM1 must not be pref mmio */
1169 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1170 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1171 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1172 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1173 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1174 }
1175
1176 /*
1177 * Check whether prefetchable memory is supported
1178 * by this bridge.
1179 */
1180 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1181 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1182 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1183 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1184 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1185 }
1186
1187 if (b_res[2].parent)
1188 goto handle_b_res_3;
1189 /*
1190 * If we have prefetchable memory support, allocate
1191 * two regions. Otherwise, allocate one region of
1192 * twice the size.
1193 */
1194 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1195 b_res[2].start = pci_cardbus_mem_size;
1196 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1197 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1198 IORESOURCE_STARTALIGN;
1199 if (realloc_head) {
1200 b_res[2].end -= pci_cardbus_mem_size;
1201 add_to_list(realloc_head, bridge, b_res+2,
1202 pci_cardbus_mem_size, pci_cardbus_mem_size);
1203 }
1204
1205 /* reduce that to half */
1206 b_res_3_size = pci_cardbus_mem_size;
1207 }
1208
1209handle_b_res_3:
1210 if (b_res[3].parent)
1211 goto handle_done;
1212 b_res[3].start = pci_cardbus_mem_size;
1213 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1214 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1215 if (realloc_head) {
1216 b_res[3].end -= b_res_3_size;
1217 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1218 pci_cardbus_mem_size);
1219 }
1220
1221handle_done:
1222 ;
1223}
1224
1225void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1226{
1227 struct pci_dev *dev;
1228 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1229 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1230 struct resource *b_res;
1231 int ret;
1232
1233 list_for_each_entry(dev, &bus->devices, bus_list) {
1234 struct pci_bus *b = dev->subordinate;
1235 if (!b)
1236 continue;
1237
1238 switch (dev->class >> 8) {
1239 case PCI_CLASS_BRIDGE_CARDBUS:
1240 pci_bus_size_cardbus(b, realloc_head);
1241 break;
1242
1243 case PCI_CLASS_BRIDGE_PCI:
1244 default:
1245 __pci_bus_size_bridges(b, realloc_head);
1246 break;
1247 }
1248 }
1249
1250 /* The root bus? */
1251 if (pci_is_root_bus(bus))
1252 return;
1253
1254 switch (bus->self->class >> 8) {
1255 case PCI_CLASS_BRIDGE_CARDBUS:
1256 /* don't size cardbuses yet. */
1257 break;
1258
1259 case PCI_CLASS_BRIDGE_PCI:
1260 pci_bridge_check_ranges(bus);
1261 if (bus->self->is_hotplug_bridge) {
1262 additional_io_size = pci_hotplug_io_size;
1263 additional_mem_size = pci_hotplug_mem_size;
1264 }
1265 /* Fall through */
1266 default:
1267 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1268 additional_io_size, realloc_head);
1269
1270 /*
1271 * If there's a 64-bit prefetchable MMIO window, compute
1272 * the size required to put all 64-bit prefetchable
1273 * resources in it.
1274 */
1275 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1276 mask = IORESOURCE_MEM;
1277 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1278 if (b_res[2].flags & IORESOURCE_MEM_64) {
1279 prefmask |= IORESOURCE_MEM_64;
1280 ret = pbus_size_mem(bus, prefmask, prefmask,
1281 prefmask, prefmask,
1282 realloc_head ? 0 : additional_mem_size,
1283 additional_mem_size, realloc_head);
1284
1285 /*
1286 * If successful, all non-prefetchable resources
1287 * and any 32-bit prefetchable resources will go in
1288 * the non-prefetchable window.
1289 */
1290 if (ret == 0) {
1291 mask = prefmask;
1292 type2 = prefmask & ~IORESOURCE_MEM_64;
1293 type3 = prefmask & ~IORESOURCE_PREFETCH;
1294 }
1295 }
1296
1297 /*
1298 * If there is no 64-bit prefetchable window, compute the
1299 * size required to put all prefetchable resources in the
1300 * 32-bit prefetchable window (if there is one).
1301 */
1302 if (!type2) {
1303 prefmask &= ~IORESOURCE_MEM_64;
1304 ret = pbus_size_mem(bus, prefmask, prefmask,
1305 prefmask, prefmask,
1306 realloc_head ? 0 : additional_mem_size,
1307 additional_mem_size, realloc_head);
1308
1309 /*
1310 * If successful, only non-prefetchable resources
1311 * will go in the non-prefetchable window.
1312 */
1313 if (ret == 0)
1314 mask = prefmask;
1315 else
1316 additional_mem_size += additional_mem_size;
1317
1318 type2 = type3 = IORESOURCE_MEM;
1319 }
1320
1321 /*
1322 * Compute the size required to put everything else in the
1323 * non-prefetchable window. This includes:
1324 *
1325 * - all non-prefetchable resources
1326 * - 32-bit prefetchable resources if there's a 64-bit
1327 * prefetchable window or no prefetchable window at all
1328 * - 64-bit prefetchable resources if there's no
1329 * prefetchable window at all
1330 *
1331 * Note that the strategy in __pci_assign_resource() must
1332 * match that used here. Specifically, we cannot put a
1333 * 32-bit prefetchable resource in a 64-bit prefetchable
1334 * window.
1335 */
1336 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1337 realloc_head ? 0 : additional_mem_size,
1338 additional_mem_size, realloc_head);
1339 break;
1340 }
1341}
1342
1343void pci_bus_size_bridges(struct pci_bus *bus)
1344{
1345 __pci_bus_size_bridges(bus, NULL);
1346}
1347EXPORT_SYMBOL(pci_bus_size_bridges);
1348
1349static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1350{
1351 int i;
1352 struct resource *parent_r;
1353 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1354 IORESOURCE_PREFETCH;
1355
1356 pci_bus_for_each_resource(b, parent_r, i) {
1357 if (!parent_r)
1358 continue;
1359
1360 if ((r->flags & mask) == (parent_r->flags & mask) &&
1361 resource_contains(parent_r, r))
1362 request_resource(parent_r, r);
1363 }
1364}
1365
1366/*
1367 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1368 * are skipped by pbus_assign_resources_sorted().
1369 */
1370static void pdev_assign_fixed_resources(struct pci_dev *dev)
1371{
1372 int i;
1373
1374 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1375 struct pci_bus *b;
1376 struct resource *r = &dev->resource[i];
1377
1378 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1379 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1380 continue;
1381
1382 b = dev->bus;
1383 while (b && !r->parent) {
1384 assign_fixed_resource_on_bus(b, r);
1385 b = b->parent;
1386 }
1387 }
1388}
1389
1390void __pci_bus_assign_resources(const struct pci_bus *bus,
1391 struct list_head *realloc_head,
1392 struct list_head *fail_head)
1393{
1394 struct pci_bus *b;
1395 struct pci_dev *dev;
1396
1397 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1398
1399 list_for_each_entry(dev, &bus->devices, bus_list) {
1400 pdev_assign_fixed_resources(dev);
1401
1402 b = dev->subordinate;
1403 if (!b)
1404 continue;
1405
1406 __pci_bus_assign_resources(b, realloc_head, fail_head);
1407
1408 switch (dev->class >> 8) {
1409 case PCI_CLASS_BRIDGE_PCI:
1410 if (!pci_is_enabled(dev))
1411 pci_setup_bridge(b);
1412 break;
1413
1414 case PCI_CLASS_BRIDGE_CARDBUS:
1415 pci_setup_cardbus(b);
1416 break;
1417
1418 default:
1419 dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
1420 pci_domain_nr(b), b->number);
1421 break;
1422 }
1423 }
1424}
1425
1426void pci_bus_assign_resources(const struct pci_bus *bus)
1427{
1428 __pci_bus_assign_resources(bus, NULL, NULL);
1429}
1430EXPORT_SYMBOL(pci_bus_assign_resources);
1431
1432static void pci_claim_device_resources(struct pci_dev *dev)
1433{
1434 int i;
1435
1436 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1437 struct resource *r = &dev->resource[i];
1438
1439 if (!r->flags || r->parent)
1440 continue;
1441
1442 pci_claim_resource(dev, i);
1443 }
1444}
1445
1446static void pci_claim_bridge_resources(struct pci_dev *dev)
1447{
1448 int i;
1449
1450 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1451 struct resource *r = &dev->resource[i];
1452
1453 if (!r->flags || r->parent)
1454 continue;
1455
1456 pci_claim_bridge_resource(dev, i);
1457 }
1458}
1459
1460static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1461{
1462 struct pci_dev *dev;
1463 struct pci_bus *child;
1464
1465 list_for_each_entry(dev, &b->devices, bus_list) {
1466 pci_claim_device_resources(dev);
1467
1468 child = dev->subordinate;
1469 if (child)
1470 pci_bus_allocate_dev_resources(child);
1471 }
1472}
1473
1474static void pci_bus_allocate_resources(struct pci_bus *b)
1475{
1476 struct pci_bus *child;
1477
1478 /*
1479 * Carry out a depth-first search on the PCI bus
1480 * tree to allocate bridge apertures. Read the
1481 * programmed bridge bases and recursively claim
1482 * the respective bridge resources.
1483 */
1484 if (b->self) {
1485 pci_read_bridge_bases(b);
1486 pci_claim_bridge_resources(b->self);
1487 }
1488
1489 list_for_each_entry(child, &b->children, node)
1490 pci_bus_allocate_resources(child);
1491}
1492
1493void pci_bus_claim_resources(struct pci_bus *b)
1494{
1495 pci_bus_allocate_resources(b);
1496 pci_bus_allocate_dev_resources(b);
1497}
1498EXPORT_SYMBOL(pci_bus_claim_resources);
1499
1500static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1501 struct list_head *add_head,
1502 struct list_head *fail_head)
1503{
1504 struct pci_bus *b;
1505
1506 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1507 add_head, fail_head);
1508
1509 b = bridge->subordinate;
1510 if (!b)
1511 return;
1512
1513 __pci_bus_assign_resources(b, add_head, fail_head);
1514
1515 switch (bridge->class >> 8) {
1516 case PCI_CLASS_BRIDGE_PCI:
1517 pci_setup_bridge(b);
1518 break;
1519
1520 case PCI_CLASS_BRIDGE_CARDBUS:
1521 pci_setup_cardbus(b);
1522 break;
1523
1524 default:
1525 dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
1526 pci_domain_nr(b), b->number);
1527 break;
1528 }
1529}
1530static void pci_bridge_release_resources(struct pci_bus *bus,
1531 unsigned long type)
1532{
1533 struct pci_dev *dev = bus->self;
1534 struct resource *r;
1535 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1536 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1537 unsigned old_flags = 0;
1538 struct resource *b_res;
1539 int idx = 1;
1540
1541 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1542
1543 /*
1544 * 1. if there is io port assign fail, will release bridge
1545 * io port.
1546 * 2. if there is non pref mmio assign fail, release bridge
1547 * nonpref mmio.
1548 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1549 * is 64bit, release bridge pref mmio.
1550 * 4. if there is pref mmio assign fail, and bridge pref is
1551 * 32bit mmio, release bridge pref mmio
1552 * 5. if there is pref mmio assign fail, and bridge pref is not
1553 * assigned, release bridge nonpref mmio.
1554 */
1555 if (type & IORESOURCE_IO)
1556 idx = 0;
1557 else if (!(type & IORESOURCE_PREFETCH))
1558 idx = 1;
1559 else if ((type & IORESOURCE_MEM_64) &&
1560 (b_res[2].flags & IORESOURCE_MEM_64))
1561 idx = 2;
1562 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1563 (b_res[2].flags & IORESOURCE_PREFETCH))
1564 idx = 2;
1565 else
1566 idx = 1;
1567
1568 r = &b_res[idx];
1569
1570 if (!r->parent)
1571 return;
1572
1573 /*
1574 * if there are children under that, we should release them
1575 * all
1576 */
1577 release_child_resources(r);
1578 if (!release_resource(r)) {
1579 type = old_flags = r->flags & type_mask;
1580 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1581 PCI_BRIDGE_RESOURCES + idx, r);
1582 /* keep the old size */
1583 r->end = resource_size(r) - 1;
1584 r->start = 0;
1585 r->flags = 0;
1586
1587 /* avoiding touch the one without PREF */
1588 if (type & IORESOURCE_PREFETCH)
1589 type = IORESOURCE_PREFETCH;
1590 __pci_setup_bridge(bus, type);
1591 /* for next child res under same bridge */
1592 r->flags = old_flags;
1593 }
1594}
1595
1596enum release_type {
1597 leaf_only,
1598 whole_subtree,
1599};
1600/*
1601 * try to release pci bridge resources that is from leaf bridge,
1602 * so we can allocate big new one later
1603 */
1604static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1605 unsigned long type,
1606 enum release_type rel_type)
1607{
1608 struct pci_dev *dev;
1609 bool is_leaf_bridge = true;
1610
1611 list_for_each_entry(dev, &bus->devices, bus_list) {
1612 struct pci_bus *b = dev->subordinate;
1613 if (!b)
1614 continue;
1615
1616 is_leaf_bridge = false;
1617
1618 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1619 continue;
1620
1621 if (rel_type == whole_subtree)
1622 pci_bus_release_bridge_resources(b, type,
1623 whole_subtree);
1624 }
1625
1626 if (pci_is_root_bus(bus))
1627 return;
1628
1629 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1630 return;
1631
1632 if ((rel_type == whole_subtree) || is_leaf_bridge)
1633 pci_bridge_release_resources(bus, type);
1634}
1635
1636static void pci_bus_dump_res(struct pci_bus *bus)
1637{
1638 struct resource *res;
1639 int i;
1640
1641 pci_bus_for_each_resource(bus, res, i) {
1642 if (!res || !res->end || !res->flags)
1643 continue;
1644
1645 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1646 }
1647}
1648
1649static void pci_bus_dump_resources(struct pci_bus *bus)
1650{
1651 struct pci_bus *b;
1652 struct pci_dev *dev;
1653
1654
1655 pci_bus_dump_res(bus);
1656
1657 list_for_each_entry(dev, &bus->devices, bus_list) {
1658 b = dev->subordinate;
1659 if (!b)
1660 continue;
1661
1662 pci_bus_dump_resources(b);
1663 }
1664}
1665
1666static int pci_bus_get_depth(struct pci_bus *bus)
1667{
1668 int depth = 0;
1669 struct pci_bus *child_bus;
1670
1671 list_for_each_entry(child_bus, &bus->children, node) {
1672 int ret;
1673
1674 ret = pci_bus_get_depth(child_bus);
1675 if (ret + 1 > depth)
1676 depth = ret + 1;
1677 }
1678
1679 return depth;
1680}
1681
1682/*
1683 * -1: undefined, will auto detect later
1684 * 0: disabled by user
1685 * 1: disabled by auto detect
1686 * 2: enabled by user
1687 * 3: enabled by auto detect
1688 */
1689enum enable_type {
1690 undefined = -1,
1691 user_disabled,
1692 auto_disabled,
1693 user_enabled,
1694 auto_enabled,
1695};
1696
1697static enum enable_type pci_realloc_enable = undefined;
1698void __init pci_realloc_get_opt(char *str)
1699{
1700 if (!strncmp(str, "off", 3))
1701 pci_realloc_enable = user_disabled;
1702 else if (!strncmp(str, "on", 2))
1703 pci_realloc_enable = user_enabled;
1704}
1705static bool pci_realloc_enabled(enum enable_type enable)
1706{
1707 return enable >= user_enabled;
1708}
1709
1710#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1711static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1712{
1713 int i;
1714 bool *unassigned = data;
1715
1716 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1717 struct resource *r = &dev->resource[i];
1718 struct pci_bus_region region;
1719
1720 /* Not assigned or rejected by kernel? */
1721 if (!r->flags)
1722 continue;
1723
1724 pcibios_resource_to_bus(dev->bus, ®ion, r);
1725 if (!region.start) {
1726 *unassigned = true;
1727 return 1; /* return early from pci_walk_bus() */
1728 }
1729 }
1730
1731 return 0;
1732}
1733
1734static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1735 enum enable_type enable_local)
1736{
1737 bool unassigned = false;
1738
1739 if (enable_local != undefined)
1740 return enable_local;
1741
1742 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1743 if (unassigned)
1744 return auto_enabled;
1745
1746 return enable_local;
1747}
1748#else
1749static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1750 enum enable_type enable_local)
1751{
1752 return enable_local;
1753}
1754#endif
1755
1756/*
1757 * first try will not touch pci bridge res
1758 * second and later try will clear small leaf bridge res
1759 * will stop till to the max depth if can not find good one
1760 */
1761void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1762{
1763 LIST_HEAD(realloc_head); /* list of resources that
1764 want additional resources */
1765 struct list_head *add_list = NULL;
1766 int tried_times = 0;
1767 enum release_type rel_type = leaf_only;
1768 LIST_HEAD(fail_head);
1769 struct pci_dev_resource *fail_res;
1770 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1771 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1772 int pci_try_num = 1;
1773 enum enable_type enable_local;
1774
1775 /* don't realloc if asked to do so */
1776 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1777 if (pci_realloc_enabled(enable_local)) {
1778 int max_depth = pci_bus_get_depth(bus);
1779
1780 pci_try_num = max_depth + 1;
1781 dev_printk(KERN_DEBUG, &bus->dev,
1782 "max bus depth: %d pci_try_num: %d\n",
1783 max_depth, pci_try_num);
1784 }
1785
1786again:
1787 /*
1788 * last try will use add_list, otherwise will try good to have as
1789 * must have, so can realloc parent bridge resource
1790 */
1791 if (tried_times + 1 == pci_try_num)
1792 add_list = &realloc_head;
1793 /* Depth first, calculate sizes and alignments of all
1794 subordinate buses. */
1795 __pci_bus_size_bridges(bus, add_list);
1796
1797 /* Depth last, allocate resources and update the hardware. */
1798 __pci_bus_assign_resources(bus, add_list, &fail_head);
1799 if (add_list)
1800 BUG_ON(!list_empty(add_list));
1801 tried_times++;
1802
1803 /* any device complain? */
1804 if (list_empty(&fail_head))
1805 goto dump;
1806
1807 if (tried_times >= pci_try_num) {
1808 if (enable_local == undefined)
1809 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1810 else if (enable_local == auto_enabled)
1811 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1812
1813 free_list(&fail_head);
1814 goto dump;
1815 }
1816
1817 dev_printk(KERN_DEBUG, &bus->dev,
1818 "No. %d try to assign unassigned res\n", tried_times + 1);
1819
1820 /* third times and later will not check if it is leaf */
1821 if ((tried_times + 1) > 2)
1822 rel_type = whole_subtree;
1823
1824 /*
1825 * Try to release leaf bridge's resources that doesn't fit resource of
1826 * child device under that bridge
1827 */
1828 list_for_each_entry(fail_res, &fail_head, list)
1829 pci_bus_release_bridge_resources(fail_res->dev->bus,
1830 fail_res->flags & type_mask,
1831 rel_type);
1832
1833 /* restore size and flags */
1834 list_for_each_entry(fail_res, &fail_head, list) {
1835 struct resource *res = fail_res->res;
1836
1837 res->start = fail_res->start;
1838 res->end = fail_res->end;
1839 res->flags = fail_res->flags;
1840 if (fail_res->dev->subordinate)
1841 res->flags = 0;
1842 }
1843 free_list(&fail_head);
1844
1845 goto again;
1846
1847dump:
1848 /* dump the resource on buses */
1849 pci_bus_dump_resources(bus);
1850}
1851
1852void __init pci_assign_unassigned_resources(void)
1853{
1854 struct pci_bus *root_bus;
1855
1856 list_for_each_entry(root_bus, &pci_root_buses, node) {
1857 pci_assign_unassigned_root_bus_resources(root_bus);
1858
1859 /* Make sure the root bridge has a companion ACPI device: */
1860 if (ACPI_HANDLE(root_bus->bridge))
1861 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1862 }
1863}
1864
1865void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1866{
1867 struct pci_bus *parent = bridge->subordinate;
1868 LIST_HEAD(add_list); /* list of resources that
1869 want additional resources */
1870 int tried_times = 0;
1871 LIST_HEAD(fail_head);
1872 struct pci_dev_resource *fail_res;
1873 int retval;
1874 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1875 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1876
1877again:
1878 __pci_bus_size_bridges(parent, &add_list);
1879 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1880 BUG_ON(!list_empty(&add_list));
1881 tried_times++;
1882
1883 if (list_empty(&fail_head))
1884 goto enable_all;
1885
1886 if (tried_times >= 2) {
1887 /* still fail, don't need to try more */
1888 free_list(&fail_head);
1889 goto enable_all;
1890 }
1891
1892 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1893 tried_times + 1);
1894
1895 /*
1896 * Try to release leaf bridge's resources that doesn't fit resource of
1897 * child device under that bridge
1898 */
1899 list_for_each_entry(fail_res, &fail_head, list)
1900 pci_bus_release_bridge_resources(fail_res->dev->bus,
1901 fail_res->flags & type_mask,
1902 whole_subtree);
1903
1904 /* restore size and flags */
1905 list_for_each_entry(fail_res, &fail_head, list) {
1906 struct resource *res = fail_res->res;
1907
1908 res->start = fail_res->start;
1909 res->end = fail_res->end;
1910 res->flags = fail_res->flags;
1911 if (fail_res->dev->subordinate)
1912 res->flags = 0;
1913 }
1914 free_list(&fail_head);
1915
1916 goto again;
1917
1918enable_all:
1919 retval = pci_reenable_device(bridge);
1920 if (retval)
1921 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1922 pci_set_master(bridge);
1923}
1924EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1925
1926void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1927{
1928 struct pci_dev *dev;
1929 LIST_HEAD(add_list); /* list of resources that
1930 want additional resources */
1931
1932 down_read(&pci_bus_sem);
1933 list_for_each_entry(dev, &bus->devices, bus_list)
1934 if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1935 __pci_bus_size_bridges(dev->subordinate,
1936 &add_list);
1937 up_read(&pci_bus_sem);
1938 __pci_bus_assign_resources(bus, &add_list, NULL);
1939 BUG_ON(!list_empty(&add_list));
1940}
1941EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);