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1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include <asm-generic/pci-bridge.h>
29#include "pci.h"
30
31unsigned int pci_flags;
32
33struct pci_dev_resource {
34 struct list_head list;
35 struct resource *res;
36 struct pci_dev *dev;
37 resource_size_t start;
38 resource_size_t end;
39 resource_size_t add_size;
40 resource_size_t min_align;
41 unsigned long flags;
42};
43
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
53
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
63static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
66{
67 struct pci_dev_resource *tmp;
68
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 if (!tmp) {
71 pr_warning("add_to_list: kmalloc() failed!\n");
72 return -ENOMEM;
73 }
74
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
82
83 list_add(&tmp->list, head);
84
85 return 0;
86}
87
88static void remove_from_list(struct list_head *head,
89 struct resource *res)
90{
91 struct pci_dev_resource *dev_res, *tmp;
92
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
97 break;
98 }
99 }
100}
101
102static resource_size_t get_res_add_size(struct list_head *head,
103 struct resource *res)
104{
105 struct pci_dev_resource *dev_res;
106
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
110
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
113 idx, dev_res->res,
114 (unsigned long long)dev_res->add_size);
115
116 return dev_res->add_size;
117 }
118 }
119
120 return 0;
121}
122
123/* Sort resources by alignment */
124static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
125{
126 int i;
127
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129 struct resource *r;
130 struct pci_dev_resource *dev_res, *tmp;
131 resource_size_t r_align;
132 struct list_head *n;
133
134 r = &dev->resource[i];
135
136 if (r->flags & IORESOURCE_PCI_FIXED)
137 continue;
138
139 if (!(r->flags) || r->parent)
140 continue;
141
142 r_align = pci_resource_alignment(dev, r);
143 if (!r_align) {
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145 i, r);
146 continue;
147 }
148
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150 if (!tmp)
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
153 tmp->res = r;
154 tmp->dev = dev;
155
156 /* fallback is smallest one or list is empty*/
157 n = head;
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
160
161 align = pci_resource_alignment(dev_res->dev,
162 dev_res->res);
163
164 if (r_align > align) {
165 n = &dev_res->list;
166 break;
167 }
168 }
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
171 }
172}
173
174static void __dev_sort_resources(struct pci_dev *dev,
175 struct list_head *head)
176{
177 u16 class = dev->class >> 8;
178
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181 return;
182
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
185 u16 command;
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188 return;
189 }
190
191 pdev_sort_resources(dev, head);
192}
193
194static inline void reset_resource(struct resource *res)
195{
196 res->start = 0;
197 res->end = 0;
198 res->flags = 0;
199}
200
201/**
202 * reassign_resources_sorted() - satisfy any additional resource requests
203 *
204 * @realloc_head : head of the list tracking requests requiring additional
205 * resources
206 * @head : head of the list tracking requests with allocated
207 * resources
208 *
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
212 */
213static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
215{
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size;
220 int idx;
221
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
224
225 res = add_res->res;
226 /* skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
236 }
237 if (!found_match)/* just skip */
238 continue;
239
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 if (!resource_size(res)) {
243 res->start = add_res->start;
244 res->end = res->start + add_size - 1;
245 if (pci_assign_resource(add_res->dev, idx))
246 reset_resource(res);
247 } else {
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
252 add_size, align))
253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
256 idx, res);
257 }
258out:
259 list_del(&add_res->list);
260 kfree(add_res);
261 }
262}
263
264/**
265 * assign_requested_resources_sorted() - satisfy resource requests
266 *
267 * @head : head of the list tracking requests for resources
268 * @failed_list : head of the list tracking requests that could
269 * not be allocated
270 *
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
273 */
274static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
276{
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
279 int idx;
280
281 list_for_each_entry(dev_res, head, list) {
282 res = dev_res->res;
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
286 if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) {
287 /*
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* dont care */,
296 0 /* dont care */);
297 }
298 reset_resource(res);
299 }
300 }
301}
302
303static void __assign_resources_sorted(struct list_head *head,
304 struct list_head *realloc_head,
305 struct list_head *fail_head)
306{
307 /*
308 * Should not assign requested resources at first.
309 * they could be adjacent, so later reassign can not reallocate
310 * them one by one in parent resource window.
311 * Try to assign requested + add_size at begining
312 * if could do that, could get out early.
313 * if could not do that, we still try to assign requested at first,
314 * then try to reassign add_size for some resources.
315 */
316 LIST_HEAD(save_head);
317 LIST_HEAD(local_fail_head);
318 struct pci_dev_resource *save_res;
319 struct pci_dev_resource *dev_res;
320
321 /* Check if optional add_size is there */
322 if (!realloc_head || list_empty(realloc_head))
323 goto requested_and_reassign;
324
325 /* Save original start, end, flags etc at first */
326 list_for_each_entry(dev_res, head, list) {
327 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
328 free_list(&save_head);
329 goto requested_and_reassign;
330 }
331 }
332
333 /* Update res in head list with add_size in realloc_head list */
334 list_for_each_entry(dev_res, head, list)
335 dev_res->res->end += get_res_add_size(realloc_head,
336 dev_res->res);
337
338 /* Try updated head list with add_size added */
339 assign_requested_resources_sorted(head, &local_fail_head);
340
341 /* all assigned with add_size ? */
342 if (list_empty(&local_fail_head)) {
343 /* Remove head list from realloc_head list */
344 list_for_each_entry(dev_res, head, list)
345 remove_from_list(realloc_head, dev_res->res);
346 free_list(&save_head);
347 free_list(head);
348 return;
349 }
350
351 free_list(&local_fail_head);
352 /* Release assigned resource */
353 list_for_each_entry(dev_res, head, list)
354 if (dev_res->res->parent)
355 release_resource(dev_res->res);
356 /* Restore start/end/flags from saved list */
357 list_for_each_entry(save_res, &save_head, list) {
358 struct resource *res = save_res->res;
359
360 res->start = save_res->start;
361 res->end = save_res->end;
362 res->flags = save_res->flags;
363 }
364 free_list(&save_head);
365
366requested_and_reassign:
367 /* Satisfy the must-have resource requests */
368 assign_requested_resources_sorted(head, fail_head);
369
370 /* Try to satisfy any additional optional resource
371 requests */
372 if (realloc_head)
373 reassign_resources_sorted(realloc_head, head);
374 free_list(head);
375}
376
377static void pdev_assign_resources_sorted(struct pci_dev *dev,
378 struct list_head *add_head,
379 struct list_head *fail_head)
380{
381 LIST_HEAD(head);
382
383 __dev_sort_resources(dev, &head);
384 __assign_resources_sorted(&head, add_head, fail_head);
385
386}
387
388static void pbus_assign_resources_sorted(const struct pci_bus *bus,
389 struct list_head *realloc_head,
390 struct list_head *fail_head)
391{
392 struct pci_dev *dev;
393 LIST_HEAD(head);
394
395 list_for_each_entry(dev, &bus->devices, bus_list)
396 __dev_sort_resources(dev, &head);
397
398 __assign_resources_sorted(&head, realloc_head, fail_head);
399}
400
401void pci_setup_cardbus(struct pci_bus *bus)
402{
403 struct pci_dev *bridge = bus->self;
404 struct resource *res;
405 struct pci_bus_region region;
406
407 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
408 bus->secondary, bus->subordinate);
409
410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, ®ion, res);
412 if (res->flags & IORESOURCE_IO) {
413 /*
414 * The IO resource is allocated a range twice as large as it
415 * would normally need. This allows us to set both IO regs.
416 */
417 dev_info(&bridge->dev, " bridge window %pR\n", res);
418 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
419 region.start);
420 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
421 region.end);
422 }
423
424 res = bus->resource[1];
425 pcibios_resource_to_bus(bridge, ®ion, res);
426 if (res->flags & IORESOURCE_IO) {
427 dev_info(&bridge->dev, " bridge window %pR\n", res);
428 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
429 region.start);
430 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
431 region.end);
432 }
433
434 res = bus->resource[2];
435 pcibios_resource_to_bus(bridge, ®ion, res);
436 if (res->flags & IORESOURCE_MEM) {
437 dev_info(&bridge->dev, " bridge window %pR\n", res);
438 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
439 region.start);
440 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
441 region.end);
442 }
443
444 res = bus->resource[3];
445 pcibios_resource_to_bus(bridge, ®ion, res);
446 if (res->flags & IORESOURCE_MEM) {
447 dev_info(&bridge->dev, " bridge window %pR\n", res);
448 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
449 region.start);
450 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
451 region.end);
452 }
453}
454EXPORT_SYMBOL(pci_setup_cardbus);
455
456/* Initialize bridges with base/limit values we have collected.
457 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
458 requires that if there is no I/O ports or memory behind the
459 bridge, corresponding range must be turned off by writing base
460 value greater than limit to the bridge's base/limit registers.
461
462 Note: care must be taken when updating I/O base/limit registers
463 of bridges which support 32-bit I/O. This update requires two
464 config space writes, so it's quite possible that an I/O window of
465 the bridge will have some undesirable address (e.g. 0) after the
466 first write. Ditto 64-bit prefetchable MMIO. */
467static void pci_setup_bridge_io(struct pci_bus *bus)
468{
469 struct pci_dev *bridge = bus->self;
470 struct resource *res;
471 struct pci_bus_region region;
472 u32 l, io_upper16;
473
474 /* Set up the top and bottom of the PCI I/O segment for this bus. */
475 res = bus->resource[0];
476 pcibios_resource_to_bus(bridge, ®ion, res);
477 if (res->flags & IORESOURCE_IO) {
478 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
479 l &= 0xffff0000;
480 l |= (region.start >> 8) & 0x00f0;
481 l |= region.end & 0xf000;
482 /* Set up upper 16 bits of I/O base/limit. */
483 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
484 dev_info(&bridge->dev, " bridge window %pR\n", res);
485 } else {
486 /* Clear upper 16 bits of I/O base/limit. */
487 io_upper16 = 0;
488 l = 0x00f0;
489 }
490 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
491 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
492 /* Update lower 16 bits of I/O base/limit. */
493 pci_write_config_dword(bridge, PCI_IO_BASE, l);
494 /* Update upper 16 bits of I/O base/limit. */
495 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
496}
497
498static void pci_setup_bridge_mmio(struct pci_bus *bus)
499{
500 struct pci_dev *bridge = bus->self;
501 struct resource *res;
502 struct pci_bus_region region;
503 u32 l;
504
505 /* Set up the top and bottom of the PCI Memory segment for this bus. */
506 res = bus->resource[1];
507 pcibios_resource_to_bus(bridge, ®ion, res);
508 if (res->flags & IORESOURCE_MEM) {
509 l = (region.start >> 16) & 0xfff0;
510 l |= region.end & 0xfff00000;
511 dev_info(&bridge->dev, " bridge window %pR\n", res);
512 } else {
513 l = 0x0000fff0;
514 }
515 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
516}
517
518static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
519{
520 struct pci_dev *bridge = bus->self;
521 struct resource *res;
522 struct pci_bus_region region;
523 u32 l, bu, lu;
524
525 /* Clear out the upper 32 bits of PREF limit.
526 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
527 disables PREF range, which is ok. */
528 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
529
530 /* Set up PREF base/limit. */
531 bu = lu = 0;
532 res = bus->resource[2];
533 pcibios_resource_to_bus(bridge, ®ion, res);
534 if (res->flags & IORESOURCE_PREFETCH) {
535 l = (region.start >> 16) & 0xfff0;
536 l |= region.end & 0xfff00000;
537 if (res->flags & IORESOURCE_MEM_64) {
538 bu = upper_32_bits(region.start);
539 lu = upper_32_bits(region.end);
540 }
541 dev_info(&bridge->dev, " bridge window %pR\n", res);
542 } else {
543 l = 0x0000fff0;
544 }
545 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
546
547 /* Set the upper 32 bits of PREF base & limit. */
548 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
549 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
550}
551
552static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
553{
554 struct pci_dev *bridge = bus->self;
555
556 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
557 bus->secondary, bus->subordinate);
558
559 if (type & IORESOURCE_IO)
560 pci_setup_bridge_io(bus);
561
562 if (type & IORESOURCE_MEM)
563 pci_setup_bridge_mmio(bus);
564
565 if (type & IORESOURCE_PREFETCH)
566 pci_setup_bridge_mmio_pref(bus);
567
568 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
569}
570
571void pci_setup_bridge(struct pci_bus *bus)
572{
573 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
574 IORESOURCE_PREFETCH;
575
576 __pci_setup_bridge(bus, type);
577}
578
579/* Check whether the bridge supports optional I/O and
580 prefetchable memory ranges. If not, the respective
581 base/limit registers must be read-only and read as 0. */
582static void pci_bridge_check_ranges(struct pci_bus *bus)
583{
584 u16 io;
585 u32 pmem;
586 struct pci_dev *bridge = bus->self;
587 struct resource *b_res;
588
589 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
590 b_res[1].flags |= IORESOURCE_MEM;
591
592 pci_read_config_word(bridge, PCI_IO_BASE, &io);
593 if (!io) {
594 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
595 pci_read_config_word(bridge, PCI_IO_BASE, &io);
596 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
597 }
598 if (io)
599 b_res[0].flags |= IORESOURCE_IO;
600 /* DECchip 21050 pass 2 errata: the bridge may miss an address
601 disconnect boundary by one PCI data phase.
602 Workaround: do not use prefetching on this device. */
603 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
604 return;
605 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
606 if (!pmem) {
607 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
608 0xfff0fff0);
609 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
610 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
611 }
612 if (pmem) {
613 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
614 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
615 PCI_PREF_RANGE_TYPE_64) {
616 b_res[2].flags |= IORESOURCE_MEM_64;
617 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
618 }
619 }
620
621 /* double check if bridge does support 64 bit pref */
622 if (b_res[2].flags & IORESOURCE_MEM_64) {
623 u32 mem_base_hi, tmp;
624 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
625 &mem_base_hi);
626 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
627 0xffffffff);
628 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
629 if (!tmp)
630 b_res[2].flags &= ~IORESOURCE_MEM_64;
631 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
632 mem_base_hi);
633 }
634}
635
636/* Helper function for sizing routines: find first available
637 bus resource of a given type. Note: we intentionally skip
638 the bus resources which have already been assigned (that is,
639 have non-NULL parent resource). */
640static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
641{
642 int i;
643 struct resource *r;
644 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
645 IORESOURCE_PREFETCH;
646
647 pci_bus_for_each_resource(bus, r, i) {
648 if (r == &ioport_resource || r == &iomem_resource)
649 continue;
650 if (r && (r->flags & type_mask) == type && !r->parent)
651 return r;
652 }
653 return NULL;
654}
655
656static resource_size_t calculate_iosize(resource_size_t size,
657 resource_size_t min_size,
658 resource_size_t size1,
659 resource_size_t old_size,
660 resource_size_t align)
661{
662 if (size < min_size)
663 size = min_size;
664 if (old_size == 1 )
665 old_size = 0;
666 /* To be fixed in 2.5: we should have sort of HAVE_ISA
667 flag in the struct pci_bus. */
668#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
669 size = (size & 0xff) + ((size & ~0xffUL) << 2);
670#endif
671 size = ALIGN(size + size1, align);
672 if (size < old_size)
673 size = old_size;
674 return size;
675}
676
677static resource_size_t calculate_memsize(resource_size_t size,
678 resource_size_t min_size,
679 resource_size_t size1,
680 resource_size_t old_size,
681 resource_size_t align)
682{
683 if (size < min_size)
684 size = min_size;
685 if (old_size == 1 )
686 old_size = 0;
687 if (size < old_size)
688 size = old_size;
689 size = ALIGN(size + size1, align);
690 return size;
691}
692
693/**
694 * pbus_size_io() - size the io window of a given bus
695 *
696 * @bus : the bus
697 * @min_size : the minimum io window that must to be allocated
698 * @add_size : additional optional io window
699 * @realloc_head : track the additional io window on this list
700 *
701 * Sizing the IO windows of the PCI-PCI bridge is trivial,
702 * since these windows have 4K granularity and the IO ranges
703 * of non-bridge PCI devices are limited to 256 bytes.
704 * We must be careful with the ISA aliasing though.
705 */
706static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
707 resource_size_t add_size, struct list_head *realloc_head)
708{
709 struct pci_dev *dev;
710 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
711 unsigned long size = 0, size0 = 0, size1 = 0;
712 resource_size_t children_add_size = 0;
713
714 if (!b_res)
715 return;
716
717 list_for_each_entry(dev, &bus->devices, bus_list) {
718 int i;
719
720 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
721 struct resource *r = &dev->resource[i];
722 unsigned long r_size;
723
724 if (r->parent || !(r->flags & IORESOURCE_IO))
725 continue;
726 r_size = resource_size(r);
727
728 if (r_size < 0x400)
729 /* Might be re-aligned for ISA */
730 size += r_size;
731 else
732 size1 += r_size;
733
734 if (realloc_head)
735 children_add_size += get_res_add_size(realloc_head, r);
736 }
737 }
738 size0 = calculate_iosize(size, min_size, size1,
739 resource_size(b_res), 4096);
740 if (children_add_size > add_size)
741 add_size = children_add_size;
742 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
743 calculate_iosize(size, min_size, add_size + size1,
744 resource_size(b_res), 4096);
745 if (!size0 && !size1) {
746 if (b_res->start || b_res->end)
747 dev_info(&bus->self->dev, "disabling bridge window "
748 "%pR to [bus %02x-%02x] (unused)\n", b_res,
749 bus->secondary, bus->subordinate);
750 b_res->flags = 0;
751 return;
752 }
753 /* Alignment of the IO window is always 4K */
754 b_res->start = 4096;
755 b_res->end = b_res->start + size0 - 1;
756 b_res->flags |= IORESOURCE_STARTALIGN;
757 if (size1 > size0 && realloc_head) {
758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760 "%pR to [bus %02x-%02x] add_size %lx\n", b_res,
761 bus->secondary, bus->subordinate, size1-size0);
762 }
763}
764
765/**
766 * pbus_size_mem() - size the memory window of a given bus
767 *
768 * @bus : the bus
769 * @min_size : the minimum memory window that must to be allocated
770 * @add_size : additional optional memory window
771 * @realloc_head : track the additional memory window on this list
772 *
773 * Calculate the size of the bus and minimal alignment which
774 * guarantees that all child resources fit in this size.
775 */
776static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
777 unsigned long type, resource_size_t min_size,
778 resource_size_t add_size,
779 struct list_head *realloc_head)
780{
781 struct pci_dev *dev;
782 resource_size_t min_align, align, size, size0, size1;
783 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
784 int order, max_order;
785 struct resource *b_res = find_free_bus_resource(bus, type);
786 unsigned int mem64_mask = 0;
787 resource_size_t children_add_size = 0;
788
789 if (!b_res)
790 return 0;
791
792 memset(aligns, 0, sizeof(aligns));
793 max_order = 0;
794 size = 0;
795
796 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
797 b_res->flags &= ~IORESOURCE_MEM_64;
798
799 list_for_each_entry(dev, &bus->devices, bus_list) {
800 int i;
801
802 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
803 struct resource *r = &dev->resource[i];
804 resource_size_t r_size;
805
806 if (r->parent || (r->flags & mask) != type)
807 continue;
808 r_size = resource_size(r);
809#ifdef CONFIG_PCI_IOV
810 /* put SRIOV requested res to the optional list */
811 if (realloc_head && i >= PCI_IOV_RESOURCES &&
812 i <= PCI_IOV_RESOURCE_END) {
813 r->end = r->start - 1;
814 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
815 children_add_size += r_size;
816 continue;
817 }
818#endif
819 /* For bridges size != alignment */
820 align = pci_resource_alignment(dev, r);
821 order = __ffs(align) - 20;
822 if (order > 11) {
823 dev_warn(&dev->dev, "disabling BAR %d: %pR "
824 "(bad alignment %#llx)\n", i, r,
825 (unsigned long long) align);
826 r->flags = 0;
827 continue;
828 }
829 size += r_size;
830 if (order < 0)
831 order = 0;
832 /* Exclude ranges with size > align from
833 calculation of the alignment. */
834 if (r_size == align)
835 aligns[order] += align;
836 if (order > max_order)
837 max_order = order;
838 mem64_mask &= r->flags & IORESOURCE_MEM_64;
839
840 if (realloc_head)
841 children_add_size += get_res_add_size(realloc_head, r);
842 }
843 }
844 align = 0;
845 min_align = 0;
846 for (order = 0; order <= max_order; order++) {
847 resource_size_t align1 = 1;
848
849 align1 <<= (order + 20);
850
851 if (!align)
852 min_align = align1;
853 else if (ALIGN(align + min_align, min_align) < align1)
854 min_align = align1 >> 1;
855 align += aligns[order];
856 }
857 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
858 if (children_add_size > add_size)
859 add_size = children_add_size;
860 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
861 calculate_memsize(size, min_size, add_size,
862 resource_size(b_res), min_align);
863 if (!size0 && !size1) {
864 if (b_res->start || b_res->end)
865 dev_info(&bus->self->dev, "disabling bridge window "
866 "%pR to [bus %02x-%02x] (unused)\n", b_res,
867 bus->secondary, bus->subordinate);
868 b_res->flags = 0;
869 return 1;
870 }
871 b_res->start = min_align;
872 b_res->end = size0 + min_align - 1;
873 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
874 if (size1 > size0 && realloc_head) {
875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to [bus %02x-%02x] add_size %llx\n", b_res,
878 bus->secondary, bus->subordinate, (unsigned long long)size1-size0);
879 }
880 return 1;
881}
882
883unsigned long pci_cardbus_resource_alignment(struct resource *res)
884{
885 if (res->flags & IORESOURCE_IO)
886 return pci_cardbus_io_size;
887 if (res->flags & IORESOURCE_MEM)
888 return pci_cardbus_mem_size;
889 return 0;
890}
891
892static void pci_bus_size_cardbus(struct pci_bus *bus,
893 struct list_head *realloc_head)
894{
895 struct pci_dev *bridge = bus->self;
896 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
897 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
898 u16 ctrl;
899
900 if (b_res[0].parent)
901 goto handle_b_res_1;
902 /*
903 * Reserve some resources for CardBus. We reserve
904 * a fixed amount of bus space for CardBus bridges.
905 */
906 b_res[0].start = pci_cardbus_io_size;
907 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
908 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
909 if (realloc_head) {
910 b_res[0].end -= pci_cardbus_io_size;
911 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
912 pci_cardbus_io_size);
913 }
914
915handle_b_res_1:
916 if (b_res[1].parent)
917 goto handle_b_res_2;
918 b_res[1].start = pci_cardbus_io_size;
919 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
920 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
921 if (realloc_head) {
922 b_res[1].end -= pci_cardbus_io_size;
923 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
924 pci_cardbus_io_size);
925 }
926
927handle_b_res_2:
928 /* MEM1 must not be pref mmio */
929 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
930 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
931 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
932 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
933 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
934 }
935
936 /*
937 * Check whether prefetchable memory is supported
938 * by this bridge.
939 */
940 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
941 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
942 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
943 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
944 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
945 }
946
947 if (b_res[2].parent)
948 goto handle_b_res_3;
949 /*
950 * If we have prefetchable memory support, allocate
951 * two regions. Otherwise, allocate one region of
952 * twice the size.
953 */
954 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
955 b_res[2].start = pci_cardbus_mem_size;
956 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
957 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
958 IORESOURCE_STARTALIGN;
959 if (realloc_head) {
960 b_res[2].end -= pci_cardbus_mem_size;
961 add_to_list(realloc_head, bridge, b_res+2,
962 pci_cardbus_mem_size, pci_cardbus_mem_size);
963 }
964
965 /* reduce that to half */
966 b_res_3_size = pci_cardbus_mem_size;
967 }
968
969handle_b_res_3:
970 if (b_res[3].parent)
971 goto handle_done;
972 b_res[3].start = pci_cardbus_mem_size;
973 b_res[3].end = b_res[3].start + b_res_3_size - 1;
974 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
975 if (realloc_head) {
976 b_res[3].end -= b_res_3_size;
977 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
978 pci_cardbus_mem_size);
979 }
980
981handle_done:
982 ;
983}
984
985void __ref __pci_bus_size_bridges(struct pci_bus *bus,
986 struct list_head *realloc_head)
987{
988 struct pci_dev *dev;
989 unsigned long mask, prefmask;
990 resource_size_t additional_mem_size = 0, additional_io_size = 0;
991
992 list_for_each_entry(dev, &bus->devices, bus_list) {
993 struct pci_bus *b = dev->subordinate;
994 if (!b)
995 continue;
996
997 switch (dev->class >> 8) {
998 case PCI_CLASS_BRIDGE_CARDBUS:
999 pci_bus_size_cardbus(b, realloc_head);
1000 break;
1001
1002 case PCI_CLASS_BRIDGE_PCI:
1003 default:
1004 __pci_bus_size_bridges(b, realloc_head);
1005 break;
1006 }
1007 }
1008
1009 /* The root bus? */
1010 if (!bus->self)
1011 return;
1012
1013 switch (bus->self->class >> 8) {
1014 case PCI_CLASS_BRIDGE_CARDBUS:
1015 /* don't size cardbuses yet. */
1016 break;
1017
1018 case PCI_CLASS_BRIDGE_PCI:
1019 pci_bridge_check_ranges(bus);
1020 if (bus->self->is_hotplug_bridge) {
1021 additional_io_size = pci_hotplug_io_size;
1022 additional_mem_size = pci_hotplug_mem_size;
1023 }
1024 /*
1025 * Follow thru
1026 */
1027 default:
1028 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1029 additional_io_size, realloc_head);
1030 /* If the bridge supports prefetchable range, size it
1031 separately. If it doesn't, or its prefetchable window
1032 has already been allocated by arch code, try
1033 non-prefetchable range for both types of PCI memory
1034 resources. */
1035 mask = IORESOURCE_MEM;
1036 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1037 if (pbus_size_mem(bus, prefmask, prefmask,
1038 realloc_head ? 0 : additional_mem_size,
1039 additional_mem_size, realloc_head))
1040 mask = prefmask; /* Success, size non-prefetch only. */
1041 else
1042 additional_mem_size += additional_mem_size;
1043 pbus_size_mem(bus, mask, IORESOURCE_MEM,
1044 realloc_head ? 0 : additional_mem_size,
1045 additional_mem_size, realloc_head);
1046 break;
1047 }
1048}
1049
1050void __ref pci_bus_size_bridges(struct pci_bus *bus)
1051{
1052 __pci_bus_size_bridges(bus, NULL);
1053}
1054EXPORT_SYMBOL(pci_bus_size_bridges);
1055
1056static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1057 struct list_head *realloc_head,
1058 struct list_head *fail_head)
1059{
1060 struct pci_bus *b;
1061 struct pci_dev *dev;
1062
1063 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1064
1065 list_for_each_entry(dev, &bus->devices, bus_list) {
1066 b = dev->subordinate;
1067 if (!b)
1068 continue;
1069
1070 __pci_bus_assign_resources(b, realloc_head, fail_head);
1071
1072 switch (dev->class >> 8) {
1073 case PCI_CLASS_BRIDGE_PCI:
1074 if (!pci_is_enabled(dev))
1075 pci_setup_bridge(b);
1076 break;
1077
1078 case PCI_CLASS_BRIDGE_CARDBUS:
1079 pci_setup_cardbus(b);
1080 break;
1081
1082 default:
1083 dev_info(&dev->dev, "not setting up bridge for bus "
1084 "%04x:%02x\n", pci_domain_nr(b), b->number);
1085 break;
1086 }
1087 }
1088}
1089
1090void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1091{
1092 __pci_bus_assign_resources(bus, NULL, NULL);
1093}
1094EXPORT_SYMBOL(pci_bus_assign_resources);
1095
1096static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1097 struct list_head *add_head,
1098 struct list_head *fail_head)
1099{
1100 struct pci_bus *b;
1101
1102 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1103 add_head, fail_head);
1104
1105 b = bridge->subordinate;
1106 if (!b)
1107 return;
1108
1109 __pci_bus_assign_resources(b, add_head, fail_head);
1110
1111 switch (bridge->class >> 8) {
1112 case PCI_CLASS_BRIDGE_PCI:
1113 pci_setup_bridge(b);
1114 break;
1115
1116 case PCI_CLASS_BRIDGE_CARDBUS:
1117 pci_setup_cardbus(b);
1118 break;
1119
1120 default:
1121 dev_info(&bridge->dev, "not setting up bridge for bus "
1122 "%04x:%02x\n", pci_domain_nr(b), b->number);
1123 break;
1124 }
1125}
1126static void pci_bridge_release_resources(struct pci_bus *bus,
1127 unsigned long type)
1128{
1129 int idx;
1130 bool changed = false;
1131 struct pci_dev *dev;
1132 struct resource *r;
1133 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1134 IORESOURCE_PREFETCH;
1135
1136 dev = bus->self;
1137 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1138 idx++) {
1139 r = &dev->resource[idx];
1140 if ((r->flags & type_mask) != type)
1141 continue;
1142 if (!r->parent)
1143 continue;
1144 /*
1145 * if there are children under that, we should release them
1146 * all
1147 */
1148 release_child_resources(r);
1149 if (!release_resource(r)) {
1150 dev_printk(KERN_DEBUG, &dev->dev,
1151 "resource %d %pR released\n", idx, r);
1152 /* keep the old size */
1153 r->end = resource_size(r) - 1;
1154 r->start = 0;
1155 r->flags = 0;
1156 changed = true;
1157 }
1158 }
1159
1160 if (changed) {
1161 /* avoiding touch the one without PREF */
1162 if (type & IORESOURCE_PREFETCH)
1163 type = IORESOURCE_PREFETCH;
1164 __pci_setup_bridge(bus, type);
1165 }
1166}
1167
1168enum release_type {
1169 leaf_only,
1170 whole_subtree,
1171};
1172/*
1173 * try to release pci bridge resources that is from leaf bridge,
1174 * so we can allocate big new one later
1175 */
1176static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1177 unsigned long type,
1178 enum release_type rel_type)
1179{
1180 struct pci_dev *dev;
1181 bool is_leaf_bridge = true;
1182
1183 list_for_each_entry(dev, &bus->devices, bus_list) {
1184 struct pci_bus *b = dev->subordinate;
1185 if (!b)
1186 continue;
1187
1188 is_leaf_bridge = false;
1189
1190 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1191 continue;
1192
1193 if (rel_type == whole_subtree)
1194 pci_bus_release_bridge_resources(b, type,
1195 whole_subtree);
1196 }
1197
1198 if (pci_is_root_bus(bus))
1199 return;
1200
1201 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1202 return;
1203
1204 if ((rel_type == whole_subtree) || is_leaf_bridge)
1205 pci_bridge_release_resources(bus, type);
1206}
1207
1208static void pci_bus_dump_res(struct pci_bus *bus)
1209{
1210 struct resource *res;
1211 int i;
1212
1213 pci_bus_for_each_resource(bus, res, i) {
1214 if (!res || !res->end || !res->flags)
1215 continue;
1216
1217 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1218 }
1219}
1220
1221static void pci_bus_dump_resources(struct pci_bus *bus)
1222{
1223 struct pci_bus *b;
1224 struct pci_dev *dev;
1225
1226
1227 pci_bus_dump_res(bus);
1228
1229 list_for_each_entry(dev, &bus->devices, bus_list) {
1230 b = dev->subordinate;
1231 if (!b)
1232 continue;
1233
1234 pci_bus_dump_resources(b);
1235 }
1236}
1237
1238static int __init pci_bus_get_depth(struct pci_bus *bus)
1239{
1240 int depth = 0;
1241 struct pci_dev *dev;
1242
1243 list_for_each_entry(dev, &bus->devices, bus_list) {
1244 int ret;
1245 struct pci_bus *b = dev->subordinate;
1246 if (!b)
1247 continue;
1248
1249 ret = pci_bus_get_depth(b);
1250 if (ret + 1 > depth)
1251 depth = ret + 1;
1252 }
1253
1254 return depth;
1255}
1256static int __init pci_get_max_depth(void)
1257{
1258 int depth = 0;
1259 struct pci_bus *bus;
1260
1261 list_for_each_entry(bus, &pci_root_buses, node) {
1262 int ret;
1263
1264 ret = pci_bus_get_depth(bus);
1265 if (ret > depth)
1266 depth = ret;
1267 }
1268
1269 return depth;
1270}
1271
1272/*
1273 * -1: undefined, will auto detect later
1274 * 0: disabled by user
1275 * 1: disabled by auto detect
1276 * 2: enabled by user
1277 * 3: enabled by auto detect
1278 */
1279enum enable_type {
1280 undefined = -1,
1281 user_disabled,
1282 auto_disabled,
1283 user_enabled,
1284 auto_enabled,
1285};
1286
1287static enum enable_type pci_realloc_enable __initdata = undefined;
1288void __init pci_realloc_get_opt(char *str)
1289{
1290 if (!strncmp(str, "off", 3))
1291 pci_realloc_enable = user_disabled;
1292 else if (!strncmp(str, "on", 2))
1293 pci_realloc_enable = user_enabled;
1294}
1295static bool __init pci_realloc_enabled(void)
1296{
1297 return pci_realloc_enable >= user_enabled;
1298}
1299
1300static void __init pci_realloc_detect(void)
1301{
1302#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1303 struct pci_dev *dev = NULL;
1304
1305 if (pci_realloc_enable != undefined)
1306 return;
1307
1308 for_each_pci_dev(dev) {
1309 int i;
1310
1311 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1312 struct resource *r = &dev->resource[i];
1313
1314 /* Not assigned, or rejected by kernel ? */
1315 if (r->flags && !r->start) {
1316 pci_realloc_enable = auto_enabled;
1317
1318 return;
1319 }
1320 }
1321 }
1322#endif
1323}
1324
1325/*
1326 * first try will not touch pci bridge res
1327 * second and later try will clear small leaf bridge res
1328 * will stop till to the max deepth if can not find good one
1329 */
1330void __init
1331pci_assign_unassigned_resources(void)
1332{
1333 struct pci_bus *bus;
1334 LIST_HEAD(realloc_head); /* list of resources that
1335 want additional resources */
1336 struct list_head *add_list = NULL;
1337 int tried_times = 0;
1338 enum release_type rel_type = leaf_only;
1339 LIST_HEAD(fail_head);
1340 struct pci_dev_resource *fail_res;
1341 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1342 IORESOURCE_PREFETCH;
1343 int pci_try_num = 1;
1344
1345 /* don't realloc if asked to do so */
1346 pci_realloc_detect();
1347 if (pci_realloc_enabled()) {
1348 int max_depth = pci_get_max_depth();
1349
1350 pci_try_num = max_depth + 1;
1351 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1352 max_depth, pci_try_num);
1353 }
1354
1355again:
1356 /*
1357 * last try will use add_list, otherwise will try good to have as
1358 * must have, so can realloc parent bridge resource
1359 */
1360 if (tried_times + 1 == pci_try_num)
1361 add_list = &realloc_head;
1362 /* Depth first, calculate sizes and alignments of all
1363 subordinate buses. */
1364 list_for_each_entry(bus, &pci_root_buses, node)
1365 __pci_bus_size_bridges(bus, add_list);
1366
1367 /* Depth last, allocate resources and update the hardware. */
1368 list_for_each_entry(bus, &pci_root_buses, node)
1369 __pci_bus_assign_resources(bus, add_list, &fail_head);
1370 if (add_list)
1371 BUG_ON(!list_empty(add_list));
1372 tried_times++;
1373
1374 /* any device complain? */
1375 if (list_empty(&fail_head))
1376 goto enable_and_dump;
1377
1378 if (tried_times >= pci_try_num) {
1379 if (pci_realloc_enable == undefined)
1380 printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1381 else if (pci_realloc_enable == auto_enabled)
1382 printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1383
1384 free_list(&fail_head);
1385 goto enable_and_dump;
1386 }
1387
1388 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1389 tried_times + 1);
1390
1391 /* third times and later will not check if it is leaf */
1392 if ((tried_times + 1) > 2)
1393 rel_type = whole_subtree;
1394
1395 /*
1396 * Try to release leaf bridge's resources that doesn't fit resource of
1397 * child device under that bridge
1398 */
1399 list_for_each_entry(fail_res, &fail_head, list) {
1400 bus = fail_res->dev->bus;
1401 pci_bus_release_bridge_resources(bus,
1402 fail_res->flags & type_mask,
1403 rel_type);
1404 }
1405 /* restore size and flags */
1406 list_for_each_entry(fail_res, &fail_head, list) {
1407 struct resource *res = fail_res->res;
1408
1409 res->start = fail_res->start;
1410 res->end = fail_res->end;
1411 res->flags = fail_res->flags;
1412 if (fail_res->dev->subordinate)
1413 res->flags = 0;
1414 }
1415 free_list(&fail_head);
1416
1417 goto again;
1418
1419enable_and_dump:
1420 /* Depth last, update the hardware. */
1421 list_for_each_entry(bus, &pci_root_buses, node)
1422 pci_enable_bridges(bus);
1423
1424 /* dump the resource on buses */
1425 list_for_each_entry(bus, &pci_root_buses, node)
1426 pci_bus_dump_resources(bus);
1427}
1428
1429void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1430{
1431 struct pci_bus *parent = bridge->subordinate;
1432 LIST_HEAD(add_list); /* list of resources that
1433 want additional resources */
1434 int tried_times = 0;
1435 LIST_HEAD(fail_head);
1436 struct pci_dev_resource *fail_res;
1437 int retval;
1438 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1439 IORESOURCE_PREFETCH;
1440
1441again:
1442 __pci_bus_size_bridges(parent, &add_list);
1443 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1444 BUG_ON(!list_empty(&add_list));
1445 tried_times++;
1446
1447 if (list_empty(&fail_head))
1448 goto enable_all;
1449
1450 if (tried_times >= 2) {
1451 /* still fail, don't need to try more */
1452 free_list(&fail_head);
1453 goto enable_all;
1454 }
1455
1456 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1457 tried_times + 1);
1458
1459 /*
1460 * Try to release leaf bridge's resources that doesn't fit resource of
1461 * child device under that bridge
1462 */
1463 list_for_each_entry(fail_res, &fail_head, list) {
1464 struct pci_bus *bus = fail_res->dev->bus;
1465 unsigned long flags = fail_res->flags;
1466
1467 pci_bus_release_bridge_resources(bus, flags & type_mask,
1468 whole_subtree);
1469 }
1470 /* restore size and flags */
1471 list_for_each_entry(fail_res, &fail_head, list) {
1472 struct resource *res = fail_res->res;
1473
1474 res->start = fail_res->start;
1475 res->end = fail_res->end;
1476 res->flags = fail_res->flags;
1477 if (fail_res->dev->subordinate)
1478 res->flags = 0;
1479 }
1480 free_list(&fail_head);
1481
1482 goto again;
1483
1484enable_all:
1485 retval = pci_reenable_device(bridge);
1486 pci_set_master(bridge);
1487 pci_enable_bridges(parent);
1488}
1489EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1490
1491#ifdef CONFIG_HOTPLUG
1492/**
1493 * pci_rescan_bus - scan a PCI bus for devices.
1494 * @bus: PCI bus to scan
1495 *
1496 * Scan a PCI bus and child buses for new devices, adds them,
1497 * and enables them.
1498 *
1499 * Returns the max number of subordinate bus discovered.
1500 */
1501unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1502{
1503 unsigned int max;
1504 struct pci_dev *dev;
1505 LIST_HEAD(add_list); /* list of resources that
1506 want additional resources */
1507
1508 max = pci_scan_child_bus(bus);
1509
1510 down_read(&pci_bus_sem);
1511 list_for_each_entry(dev, &bus->devices, bus_list)
1512 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1513 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1514 if (dev->subordinate)
1515 __pci_bus_size_bridges(dev->subordinate,
1516 &add_list);
1517 up_read(&pci_bus_sem);
1518 __pci_bus_assign_resources(bus, &add_list, NULL);
1519 BUG_ON(!list_empty(&add_list));
1520
1521 pci_enable_bridges(bus);
1522 pci_bus_add_devices(bus);
1523
1524 return max;
1525}
1526EXPORT_SYMBOL_GPL(pci_rescan_bus);
1527#endif
1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include "pci.h"
29
30struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39};
40
41#define free_list(type, head) do { \
42 struct type *list, *tmp; \
43 for (list = (head)->next; list;) { \
44 tmp = list; \
45 list = list->next; \
46 kfree(tmp); \
47 } \
48 (head)->next = NULL; \
49} while (0)
50
51int pci_realloc_enable = 0;
52#define pci_realloc_enabled() pci_realloc_enable
53void pci_realloc(void)
54{
55 pci_realloc_enable = 1;
56}
57
58/**
59 * add_to_list() - add a new resource tracker to the list
60 * @head: Head of the list
61 * @dev: device corresponding to which the resource
62 * belongs
63 * @res: The resource to be tracked
64 * @add_size: additional size to be optionally added
65 * to the resource
66 */
67static void add_to_list(struct resource_list_x *head,
68 struct pci_dev *dev, struct resource *res,
69 resource_size_t add_size, resource_size_t min_align)
70{
71 struct resource_list_x *list = head;
72 struct resource_list_x *ln = list->next;
73 struct resource_list_x *tmp;
74
75 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
76 if (!tmp) {
77 pr_warning("add_to_list: kmalloc() failed!\n");
78 return;
79 }
80
81 tmp->next = ln;
82 tmp->res = res;
83 tmp->dev = dev;
84 tmp->start = res->start;
85 tmp->end = res->end;
86 tmp->flags = res->flags;
87 tmp->add_size = add_size;
88 tmp->min_align = min_align;
89 list->next = tmp;
90}
91
92static void add_to_failed_list(struct resource_list_x *head,
93 struct pci_dev *dev, struct resource *res)
94{
95 add_to_list(head, dev, res,
96 0 /* dont care */,
97 0 /* dont care */);
98}
99
100static void __dev_sort_resources(struct pci_dev *dev,
101 struct resource_list *head)
102{
103 u16 class = dev->class >> 8;
104
105 /* Don't touch classless devices or host bridges or ioapics. */
106 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
107 return;
108
109 /* Don't touch ioapic devices already enabled by firmware */
110 if (class == PCI_CLASS_SYSTEM_PIC) {
111 u16 command;
112 pci_read_config_word(dev, PCI_COMMAND, &command);
113 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
114 return;
115 }
116
117 pdev_sort_resources(dev, head);
118}
119
120static inline void reset_resource(struct resource *res)
121{
122 res->start = 0;
123 res->end = 0;
124 res->flags = 0;
125}
126
127/**
128 * reassign_resources_sorted() - satisfy any additional resource requests
129 *
130 * @realloc_head : head of the list tracking requests requiring additional
131 * resources
132 * @head : head of the list tracking requests with allocated
133 * resources
134 *
135 * Walk through each element of the realloc_head and try to procure
136 * additional resources for the element, provided the element
137 * is in the head list.
138 */
139static void reassign_resources_sorted(struct resource_list_x *realloc_head,
140 struct resource_list *head)
141{
142 struct resource *res;
143 struct resource_list_x *list, *tmp, *prev;
144 struct resource_list *hlist;
145 resource_size_t add_size;
146 int idx;
147
148 prev = realloc_head;
149 for (list = realloc_head->next; list;) {
150 res = list->res;
151 /* skip resource that has been reset */
152 if (!res->flags)
153 goto out;
154
155 /* skip this resource if not found in head list */
156 for (hlist = head->next; hlist && hlist->res != res;
157 hlist = hlist->next);
158 if (!hlist) { /* just skip */
159 prev = list;
160 list = list->next;
161 continue;
162 }
163
164 idx = res - &list->dev->resource[0];
165 add_size=list->add_size;
166 if (!resource_size(res)) {
167 res->start = list->start;
168 res->end = res->start + add_size - 1;
169 if(pci_assign_resource(list->dev, idx))
170 reset_resource(res);
171 } else {
172 resource_size_t align = list->min_align;
173 res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
174 if (pci_reassign_resource(list->dev, idx, add_size, align))
175 dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n",
176 res);
177 }
178out:
179 tmp = list;
180 prev->next = list = list->next;
181 kfree(tmp);
182 }
183}
184
185/**
186 * assign_requested_resources_sorted() - satisfy resource requests
187 *
188 * @head : head of the list tracking requests for resources
189 * @failed_list : head of the list tracking requests that could
190 * not be allocated
191 *
192 * Satisfy resource requests of each element in the list. Add
193 * requests that could not satisfied to the failed_list.
194 */
195static void assign_requested_resources_sorted(struct resource_list *head,
196 struct resource_list_x *fail_head)
197{
198 struct resource *res;
199 struct resource_list *list;
200 int idx;
201
202 for (list = head->next; list; list = list->next) {
203 res = list->res;
204 idx = res - &list->dev->resource[0];
205 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
206 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
207 /*
208 * if the failed res is for ROM BAR, and it will
209 * be enabled later, don't add it to the list
210 */
211 if (!((idx == PCI_ROM_RESOURCE) &&
212 (!(res->flags & IORESOURCE_ROM_ENABLE))))
213 add_to_failed_list(fail_head, list->dev, res);
214 }
215 reset_resource(res);
216 }
217 }
218}
219
220static void __assign_resources_sorted(struct resource_list *head,
221 struct resource_list_x *realloc_head,
222 struct resource_list_x *fail_head)
223{
224 /* Satisfy the must-have resource requests */
225 assign_requested_resources_sorted(head, fail_head);
226
227 /* Try to satisfy any additional optional resource
228 requests */
229 if (realloc_head)
230 reassign_resources_sorted(realloc_head, head);
231 free_list(resource_list, head);
232}
233
234static void pdev_assign_resources_sorted(struct pci_dev *dev,
235 struct resource_list_x *fail_head)
236{
237 struct resource_list head;
238
239 head.next = NULL;
240 __dev_sort_resources(dev, &head);
241 __assign_resources_sorted(&head, NULL, fail_head);
242
243}
244
245static void pbus_assign_resources_sorted(const struct pci_bus *bus,
246 struct resource_list_x *realloc_head,
247 struct resource_list_x *fail_head)
248{
249 struct pci_dev *dev;
250 struct resource_list head;
251
252 head.next = NULL;
253 list_for_each_entry(dev, &bus->devices, bus_list)
254 __dev_sort_resources(dev, &head);
255
256 __assign_resources_sorted(&head, realloc_head, fail_head);
257}
258
259void pci_setup_cardbus(struct pci_bus *bus)
260{
261 struct pci_dev *bridge = bus->self;
262 struct resource *res;
263 struct pci_bus_region region;
264
265 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
266 bus->secondary, bus->subordinate);
267
268 res = bus->resource[0];
269 pcibios_resource_to_bus(bridge, ®ion, res);
270 if (res->flags & IORESOURCE_IO) {
271 /*
272 * The IO resource is allocated a range twice as large as it
273 * would normally need. This allows us to set both IO regs.
274 */
275 dev_info(&bridge->dev, " bridge window %pR\n", res);
276 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
277 region.start);
278 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
279 region.end);
280 }
281
282 res = bus->resource[1];
283 pcibios_resource_to_bus(bridge, ®ion, res);
284 if (res->flags & IORESOURCE_IO) {
285 dev_info(&bridge->dev, " bridge window %pR\n", res);
286 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
287 region.start);
288 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
289 region.end);
290 }
291
292 res = bus->resource[2];
293 pcibios_resource_to_bus(bridge, ®ion, res);
294 if (res->flags & IORESOURCE_MEM) {
295 dev_info(&bridge->dev, " bridge window %pR\n", res);
296 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
297 region.start);
298 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
299 region.end);
300 }
301
302 res = bus->resource[3];
303 pcibios_resource_to_bus(bridge, ®ion, res);
304 if (res->flags & IORESOURCE_MEM) {
305 dev_info(&bridge->dev, " bridge window %pR\n", res);
306 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
307 region.start);
308 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
309 region.end);
310 }
311}
312EXPORT_SYMBOL(pci_setup_cardbus);
313
314/* Initialize bridges with base/limit values we have collected.
315 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
316 requires that if there is no I/O ports or memory behind the
317 bridge, corresponding range must be turned off by writing base
318 value greater than limit to the bridge's base/limit registers.
319
320 Note: care must be taken when updating I/O base/limit registers
321 of bridges which support 32-bit I/O. This update requires two
322 config space writes, so it's quite possible that an I/O window of
323 the bridge will have some undesirable address (e.g. 0) after the
324 first write. Ditto 64-bit prefetchable MMIO. */
325static void pci_setup_bridge_io(struct pci_bus *bus)
326{
327 struct pci_dev *bridge = bus->self;
328 struct resource *res;
329 struct pci_bus_region region;
330 u32 l, io_upper16;
331
332 /* Set up the top and bottom of the PCI I/O segment for this bus. */
333 res = bus->resource[0];
334 pcibios_resource_to_bus(bridge, ®ion, res);
335 if (res->flags & IORESOURCE_IO) {
336 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
337 l &= 0xffff0000;
338 l |= (region.start >> 8) & 0x00f0;
339 l |= region.end & 0xf000;
340 /* Set up upper 16 bits of I/O base/limit. */
341 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
342 dev_info(&bridge->dev, " bridge window %pR\n", res);
343 } else {
344 /* Clear upper 16 bits of I/O base/limit. */
345 io_upper16 = 0;
346 l = 0x00f0;
347 }
348 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
349 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
350 /* Update lower 16 bits of I/O base/limit. */
351 pci_write_config_dword(bridge, PCI_IO_BASE, l);
352 /* Update upper 16 bits of I/O base/limit. */
353 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
354}
355
356static void pci_setup_bridge_mmio(struct pci_bus *bus)
357{
358 struct pci_dev *bridge = bus->self;
359 struct resource *res;
360 struct pci_bus_region region;
361 u32 l;
362
363 /* Set up the top and bottom of the PCI Memory segment for this bus. */
364 res = bus->resource[1];
365 pcibios_resource_to_bus(bridge, ®ion, res);
366 if (res->flags & IORESOURCE_MEM) {
367 l = (region.start >> 16) & 0xfff0;
368 l |= region.end & 0xfff00000;
369 dev_info(&bridge->dev, " bridge window %pR\n", res);
370 } else {
371 l = 0x0000fff0;
372 }
373 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
374}
375
376static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
377{
378 struct pci_dev *bridge = bus->self;
379 struct resource *res;
380 struct pci_bus_region region;
381 u32 l, bu, lu;
382
383 /* Clear out the upper 32 bits of PREF limit.
384 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
385 disables PREF range, which is ok. */
386 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
387
388 /* Set up PREF base/limit. */
389 bu = lu = 0;
390 res = bus->resource[2];
391 pcibios_resource_to_bus(bridge, ®ion, res);
392 if (res->flags & IORESOURCE_PREFETCH) {
393 l = (region.start >> 16) & 0xfff0;
394 l |= region.end & 0xfff00000;
395 if (res->flags & IORESOURCE_MEM_64) {
396 bu = upper_32_bits(region.start);
397 lu = upper_32_bits(region.end);
398 }
399 dev_info(&bridge->dev, " bridge window %pR\n", res);
400 } else {
401 l = 0x0000fff0;
402 }
403 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
404
405 /* Set the upper 32 bits of PREF base & limit. */
406 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
407 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
408}
409
410static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
411{
412 struct pci_dev *bridge = bus->self;
413
414 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
415 bus->secondary, bus->subordinate);
416
417 if (type & IORESOURCE_IO)
418 pci_setup_bridge_io(bus);
419
420 if (type & IORESOURCE_MEM)
421 pci_setup_bridge_mmio(bus);
422
423 if (type & IORESOURCE_PREFETCH)
424 pci_setup_bridge_mmio_pref(bus);
425
426 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
427}
428
429static void pci_setup_bridge(struct pci_bus *bus)
430{
431 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
432 IORESOURCE_PREFETCH;
433
434 __pci_setup_bridge(bus, type);
435}
436
437/* Check whether the bridge supports optional I/O and
438 prefetchable memory ranges. If not, the respective
439 base/limit registers must be read-only and read as 0. */
440static void pci_bridge_check_ranges(struct pci_bus *bus)
441{
442 u16 io;
443 u32 pmem;
444 struct pci_dev *bridge = bus->self;
445 struct resource *b_res;
446
447 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
448 b_res[1].flags |= IORESOURCE_MEM;
449
450 pci_read_config_word(bridge, PCI_IO_BASE, &io);
451 if (!io) {
452 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
453 pci_read_config_word(bridge, PCI_IO_BASE, &io);
454 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
455 }
456 if (io)
457 b_res[0].flags |= IORESOURCE_IO;
458 /* DECchip 21050 pass 2 errata: the bridge may miss an address
459 disconnect boundary by one PCI data phase.
460 Workaround: do not use prefetching on this device. */
461 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
462 return;
463 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
464 if (!pmem) {
465 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
466 0xfff0fff0);
467 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
468 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
469 }
470 if (pmem) {
471 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
472 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
473 PCI_PREF_RANGE_TYPE_64) {
474 b_res[2].flags |= IORESOURCE_MEM_64;
475 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
476 }
477 }
478
479 /* double check if bridge does support 64 bit pref */
480 if (b_res[2].flags & IORESOURCE_MEM_64) {
481 u32 mem_base_hi, tmp;
482 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
483 &mem_base_hi);
484 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
485 0xffffffff);
486 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
487 if (!tmp)
488 b_res[2].flags &= ~IORESOURCE_MEM_64;
489 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
490 mem_base_hi);
491 }
492}
493
494/* Helper function for sizing routines: find first available
495 bus resource of a given type. Note: we intentionally skip
496 the bus resources which have already been assigned (that is,
497 have non-NULL parent resource). */
498static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
499{
500 int i;
501 struct resource *r;
502 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
503 IORESOURCE_PREFETCH;
504
505 pci_bus_for_each_resource(bus, r, i) {
506 if (r == &ioport_resource || r == &iomem_resource)
507 continue;
508 if (r && (r->flags & type_mask) == type && !r->parent)
509 return r;
510 }
511 return NULL;
512}
513
514static resource_size_t calculate_iosize(resource_size_t size,
515 resource_size_t min_size,
516 resource_size_t size1,
517 resource_size_t old_size,
518 resource_size_t align)
519{
520 if (size < min_size)
521 size = min_size;
522 if (old_size == 1 )
523 old_size = 0;
524 /* To be fixed in 2.5: we should have sort of HAVE_ISA
525 flag in the struct pci_bus. */
526#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
527 size = (size & 0xff) + ((size & ~0xffUL) << 2);
528#endif
529 size = ALIGN(size + size1, align);
530 if (size < old_size)
531 size = old_size;
532 return size;
533}
534
535static resource_size_t calculate_memsize(resource_size_t size,
536 resource_size_t min_size,
537 resource_size_t size1,
538 resource_size_t old_size,
539 resource_size_t align)
540{
541 if (size < min_size)
542 size = min_size;
543 if (old_size == 1 )
544 old_size = 0;
545 if (size < old_size)
546 size = old_size;
547 size = ALIGN(size + size1, align);
548 return size;
549}
550
551static resource_size_t get_res_add_size(struct resource_list_x *realloc_head,
552 struct resource *res)
553{
554 struct resource_list_x *list;
555
556 /* check if it is in realloc_head list */
557 for (list = realloc_head->next; list && list->res != res;
558 list = list->next);
559 if (list)
560 return list->add_size;
561
562 return 0;
563}
564
565/**
566 * pbus_size_io() - size the io window of a given bus
567 *
568 * @bus : the bus
569 * @min_size : the minimum io window that must to be allocated
570 * @add_size : additional optional io window
571 * @realloc_head : track the additional io window on this list
572 *
573 * Sizing the IO windows of the PCI-PCI bridge is trivial,
574 * since these windows have 4K granularity and the IO ranges
575 * of non-bridge PCI devices are limited to 256 bytes.
576 * We must be careful with the ISA aliasing though.
577 */
578static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
579 resource_size_t add_size, struct resource_list_x *realloc_head)
580{
581 struct pci_dev *dev;
582 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
583 unsigned long size = 0, size0 = 0, size1 = 0;
584 resource_size_t children_add_size = 0;
585
586 if (!b_res)
587 return;
588
589 list_for_each_entry(dev, &bus->devices, bus_list) {
590 int i;
591
592 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
593 struct resource *r = &dev->resource[i];
594 unsigned long r_size;
595
596 if (r->parent || !(r->flags & IORESOURCE_IO))
597 continue;
598 r_size = resource_size(r);
599
600 if (r_size < 0x400)
601 /* Might be re-aligned for ISA */
602 size += r_size;
603 else
604 size1 += r_size;
605
606 if (realloc_head)
607 children_add_size += get_res_add_size(realloc_head, r);
608 }
609 }
610 size0 = calculate_iosize(size, min_size, size1,
611 resource_size(b_res), 4096);
612 if (children_add_size > add_size)
613 add_size = children_add_size;
614 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
615 calculate_iosize(size, min_size+add_size, size1,
616 resource_size(b_res), 4096);
617 if (!size0 && !size1) {
618 if (b_res->start || b_res->end)
619 dev_info(&bus->self->dev, "disabling bridge window "
620 "%pR to [bus %02x-%02x] (unused)\n", b_res,
621 bus->secondary, bus->subordinate);
622 b_res->flags = 0;
623 return;
624 }
625 /* Alignment of the IO window is always 4K */
626 b_res->start = 4096;
627 b_res->end = b_res->start + size0 - 1;
628 b_res->flags |= IORESOURCE_STARTALIGN;
629 if (size1 > size0 && realloc_head)
630 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
631}
632
633/**
634 * pbus_size_mem() - size the memory window of a given bus
635 *
636 * @bus : the bus
637 * @min_size : the minimum memory window that must to be allocated
638 * @add_size : additional optional memory window
639 * @realloc_head : track the additional memory window on this list
640 *
641 * Calculate the size of the bus and minimal alignment which
642 * guarantees that all child resources fit in this size.
643 */
644static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
645 unsigned long type, resource_size_t min_size,
646 resource_size_t add_size,
647 struct resource_list_x *realloc_head)
648{
649 struct pci_dev *dev;
650 resource_size_t min_align, align, size, size0, size1;
651 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
652 int order, max_order;
653 struct resource *b_res = find_free_bus_resource(bus, type);
654 unsigned int mem64_mask = 0;
655 resource_size_t children_add_size = 0;
656
657 if (!b_res)
658 return 0;
659
660 memset(aligns, 0, sizeof(aligns));
661 max_order = 0;
662 size = 0;
663
664 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
665 b_res->flags &= ~IORESOURCE_MEM_64;
666
667 list_for_each_entry(dev, &bus->devices, bus_list) {
668 int i;
669
670 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
671 struct resource *r = &dev->resource[i];
672 resource_size_t r_size;
673
674 if (r->parent || (r->flags & mask) != type)
675 continue;
676 r_size = resource_size(r);
677#ifdef CONFIG_PCI_IOV
678 /* put SRIOV requested res to the optional list */
679 if (realloc_head && i >= PCI_IOV_RESOURCES &&
680 i <= PCI_IOV_RESOURCE_END) {
681 r->end = r->start - 1;
682 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
683 children_add_size += r_size;
684 continue;
685 }
686#endif
687 /* For bridges size != alignment */
688 align = pci_resource_alignment(dev, r);
689 order = __ffs(align) - 20;
690 if (order > 11) {
691 dev_warn(&dev->dev, "disabling BAR %d: %pR "
692 "(bad alignment %#llx)\n", i, r,
693 (unsigned long long) align);
694 r->flags = 0;
695 continue;
696 }
697 size += r_size;
698 if (order < 0)
699 order = 0;
700 /* Exclude ranges with size > align from
701 calculation of the alignment. */
702 if (r_size == align)
703 aligns[order] += align;
704 if (order > max_order)
705 max_order = order;
706 mem64_mask &= r->flags & IORESOURCE_MEM_64;
707
708 if (realloc_head)
709 children_add_size += get_res_add_size(realloc_head, r);
710 }
711 }
712 align = 0;
713 min_align = 0;
714 for (order = 0; order <= max_order; order++) {
715 resource_size_t align1 = 1;
716
717 align1 <<= (order + 20);
718
719 if (!align)
720 min_align = align1;
721 else if (ALIGN(align + min_align, min_align) < align1)
722 min_align = align1 >> 1;
723 align += aligns[order];
724 }
725 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
726 if (children_add_size > add_size)
727 add_size = children_add_size;
728 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
729 calculate_memsize(size, min_size+add_size, 0,
730 resource_size(b_res), min_align);
731 if (!size0 && !size1) {
732 if (b_res->start || b_res->end)
733 dev_info(&bus->self->dev, "disabling bridge window "
734 "%pR to [bus %02x-%02x] (unused)\n", b_res,
735 bus->secondary, bus->subordinate);
736 b_res->flags = 0;
737 return 1;
738 }
739 b_res->start = min_align;
740 b_res->end = size0 + min_align - 1;
741 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
742 if (size1 > size0 && realloc_head)
743 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
744 return 1;
745}
746
747unsigned long pci_cardbus_resource_alignment(struct resource *res)
748{
749 if (res->flags & IORESOURCE_IO)
750 return pci_cardbus_io_size;
751 if (res->flags & IORESOURCE_MEM)
752 return pci_cardbus_mem_size;
753 return 0;
754}
755
756static void pci_bus_size_cardbus(struct pci_bus *bus,
757 struct resource_list_x *realloc_head)
758{
759 struct pci_dev *bridge = bus->self;
760 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
761 u16 ctrl;
762
763 /*
764 * Reserve some resources for CardBus. We reserve
765 * a fixed amount of bus space for CardBus bridges.
766 */
767 b_res[0].start = 0;
768 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
769 if (realloc_head)
770 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */);
771
772 b_res[1].start = 0;
773 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
774 if (realloc_head)
775 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
776
777 /*
778 * Check whether prefetchable memory is supported
779 * by this bridge.
780 */
781 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
782 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
783 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
784 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
785 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
786 }
787
788 /*
789 * If we have prefetchable memory support, allocate
790 * two regions. Otherwise, allocate one region of
791 * twice the size.
792 */
793 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
794 b_res[2].start = 0;
795 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
796 if (realloc_head)
797 add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */);
798
799 b_res[3].start = 0;
800 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
801 if (realloc_head)
802 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */);
803 } else {
804 b_res[3].start = 0;
805 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
806 if (realloc_head)
807 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */);
808 }
809
810 /* set the size of the resource to zero, so that the resource does not
811 * get assigned during required-resource allocation cycle but gets assigned
812 * during the optional-resource allocation cycle.
813 */
814 b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1;
815 b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0;
816}
817
818void __ref __pci_bus_size_bridges(struct pci_bus *bus,
819 struct resource_list_x *realloc_head)
820{
821 struct pci_dev *dev;
822 unsigned long mask, prefmask;
823 resource_size_t additional_mem_size = 0, additional_io_size = 0;
824
825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 struct pci_bus *b = dev->subordinate;
827 if (!b)
828 continue;
829
830 switch (dev->class >> 8) {
831 case PCI_CLASS_BRIDGE_CARDBUS:
832 pci_bus_size_cardbus(b, realloc_head);
833 break;
834
835 case PCI_CLASS_BRIDGE_PCI:
836 default:
837 __pci_bus_size_bridges(b, realloc_head);
838 break;
839 }
840 }
841
842 /* The root bus? */
843 if (!bus->self)
844 return;
845
846 switch (bus->self->class >> 8) {
847 case PCI_CLASS_BRIDGE_CARDBUS:
848 /* don't size cardbuses yet. */
849 break;
850
851 case PCI_CLASS_BRIDGE_PCI:
852 pci_bridge_check_ranges(bus);
853 if (bus->self->is_hotplug_bridge) {
854 additional_io_size = pci_hotplug_io_size;
855 additional_mem_size = pci_hotplug_mem_size;
856 }
857 /*
858 * Follow thru
859 */
860 default:
861 pbus_size_io(bus, 0, additional_io_size, realloc_head);
862 /* If the bridge supports prefetchable range, size it
863 separately. If it doesn't, or its prefetchable window
864 has already been allocated by arch code, try
865 non-prefetchable range for both types of PCI memory
866 resources. */
867 mask = IORESOURCE_MEM;
868 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
869 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head))
870 mask = prefmask; /* Success, size non-prefetch only. */
871 else
872 additional_mem_size += additional_mem_size;
873 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head);
874 break;
875 }
876}
877
878void __ref pci_bus_size_bridges(struct pci_bus *bus)
879{
880 __pci_bus_size_bridges(bus, NULL);
881}
882EXPORT_SYMBOL(pci_bus_size_bridges);
883
884static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
885 struct resource_list_x *realloc_head,
886 struct resource_list_x *fail_head)
887{
888 struct pci_bus *b;
889 struct pci_dev *dev;
890
891 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
892
893 list_for_each_entry(dev, &bus->devices, bus_list) {
894 b = dev->subordinate;
895 if (!b)
896 continue;
897
898 __pci_bus_assign_resources(b, realloc_head, fail_head);
899
900 switch (dev->class >> 8) {
901 case PCI_CLASS_BRIDGE_PCI:
902 if (!pci_is_enabled(dev))
903 pci_setup_bridge(b);
904 break;
905
906 case PCI_CLASS_BRIDGE_CARDBUS:
907 pci_setup_cardbus(b);
908 break;
909
910 default:
911 dev_info(&dev->dev, "not setting up bridge for bus "
912 "%04x:%02x\n", pci_domain_nr(b), b->number);
913 break;
914 }
915 }
916}
917
918void __ref pci_bus_assign_resources(const struct pci_bus *bus)
919{
920 __pci_bus_assign_resources(bus, NULL, NULL);
921}
922EXPORT_SYMBOL(pci_bus_assign_resources);
923
924static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
925 struct resource_list_x *fail_head)
926{
927 struct pci_bus *b;
928
929 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
930
931 b = bridge->subordinate;
932 if (!b)
933 return;
934
935 __pci_bus_assign_resources(b, NULL, fail_head);
936
937 switch (bridge->class >> 8) {
938 case PCI_CLASS_BRIDGE_PCI:
939 pci_setup_bridge(b);
940 break;
941
942 case PCI_CLASS_BRIDGE_CARDBUS:
943 pci_setup_cardbus(b);
944 break;
945
946 default:
947 dev_info(&bridge->dev, "not setting up bridge for bus "
948 "%04x:%02x\n", pci_domain_nr(b), b->number);
949 break;
950 }
951}
952static void pci_bridge_release_resources(struct pci_bus *bus,
953 unsigned long type)
954{
955 int idx;
956 bool changed = false;
957 struct pci_dev *dev;
958 struct resource *r;
959 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
960 IORESOURCE_PREFETCH;
961
962 dev = bus->self;
963 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
964 idx++) {
965 r = &dev->resource[idx];
966 if ((r->flags & type_mask) != type)
967 continue;
968 if (!r->parent)
969 continue;
970 /*
971 * if there are children under that, we should release them
972 * all
973 */
974 release_child_resources(r);
975 if (!release_resource(r)) {
976 dev_printk(KERN_DEBUG, &dev->dev,
977 "resource %d %pR released\n", idx, r);
978 /* keep the old size */
979 r->end = resource_size(r) - 1;
980 r->start = 0;
981 r->flags = 0;
982 changed = true;
983 }
984 }
985
986 if (changed) {
987 /* avoiding touch the one without PREF */
988 if (type & IORESOURCE_PREFETCH)
989 type = IORESOURCE_PREFETCH;
990 __pci_setup_bridge(bus, type);
991 }
992}
993
994enum release_type {
995 leaf_only,
996 whole_subtree,
997};
998/*
999 * try to release pci bridge resources that is from leaf bridge,
1000 * so we can allocate big new one later
1001 */
1002static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1003 unsigned long type,
1004 enum release_type rel_type)
1005{
1006 struct pci_dev *dev;
1007 bool is_leaf_bridge = true;
1008
1009 list_for_each_entry(dev, &bus->devices, bus_list) {
1010 struct pci_bus *b = dev->subordinate;
1011 if (!b)
1012 continue;
1013
1014 is_leaf_bridge = false;
1015
1016 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1017 continue;
1018
1019 if (rel_type == whole_subtree)
1020 pci_bus_release_bridge_resources(b, type,
1021 whole_subtree);
1022 }
1023
1024 if (pci_is_root_bus(bus))
1025 return;
1026
1027 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1028 return;
1029
1030 if ((rel_type == whole_subtree) || is_leaf_bridge)
1031 pci_bridge_release_resources(bus, type);
1032}
1033
1034static void pci_bus_dump_res(struct pci_bus *bus)
1035{
1036 struct resource *res;
1037 int i;
1038
1039 pci_bus_for_each_resource(bus, res, i) {
1040 if (!res || !res->end || !res->flags)
1041 continue;
1042
1043 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1044 }
1045}
1046
1047static void pci_bus_dump_resources(struct pci_bus *bus)
1048{
1049 struct pci_bus *b;
1050 struct pci_dev *dev;
1051
1052
1053 pci_bus_dump_res(bus);
1054
1055 list_for_each_entry(dev, &bus->devices, bus_list) {
1056 b = dev->subordinate;
1057 if (!b)
1058 continue;
1059
1060 pci_bus_dump_resources(b);
1061 }
1062}
1063
1064static int __init pci_bus_get_depth(struct pci_bus *bus)
1065{
1066 int depth = 0;
1067 struct pci_dev *dev;
1068
1069 list_for_each_entry(dev, &bus->devices, bus_list) {
1070 int ret;
1071 struct pci_bus *b = dev->subordinate;
1072 if (!b)
1073 continue;
1074
1075 ret = pci_bus_get_depth(b);
1076 if (ret + 1 > depth)
1077 depth = ret + 1;
1078 }
1079
1080 return depth;
1081}
1082static int __init pci_get_max_depth(void)
1083{
1084 int depth = 0;
1085 struct pci_bus *bus;
1086
1087 list_for_each_entry(bus, &pci_root_buses, node) {
1088 int ret;
1089
1090 ret = pci_bus_get_depth(bus);
1091 if (ret > depth)
1092 depth = ret;
1093 }
1094
1095 return depth;
1096}
1097
1098
1099/*
1100 * first try will not touch pci bridge res
1101 * second and later try will clear small leaf bridge res
1102 * will stop till to the max deepth if can not find good one
1103 */
1104void __init
1105pci_assign_unassigned_resources(void)
1106{
1107 struct pci_bus *bus;
1108 struct resource_list_x realloc_list; /* list of resources that
1109 want additional resources */
1110 int tried_times = 0;
1111 enum release_type rel_type = leaf_only;
1112 struct resource_list_x head, *list;
1113 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1114 IORESOURCE_PREFETCH;
1115 unsigned long failed_type;
1116 int max_depth = pci_get_max_depth();
1117 int pci_try_num;
1118
1119
1120 head.next = NULL;
1121 realloc_list.next = NULL;
1122
1123 pci_try_num = max_depth + 1;
1124 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1125 max_depth, pci_try_num);
1126
1127again:
1128 /* Depth first, calculate sizes and alignments of all
1129 subordinate buses. */
1130 list_for_each_entry(bus, &pci_root_buses, node)
1131 __pci_bus_size_bridges(bus, &realloc_list);
1132
1133 /* Depth last, allocate resources and update the hardware. */
1134 list_for_each_entry(bus, &pci_root_buses, node)
1135 __pci_bus_assign_resources(bus, &realloc_list, &head);
1136 BUG_ON(realloc_list.next);
1137 tried_times++;
1138
1139 /* any device complain? */
1140 if (!head.next)
1141 goto enable_and_dump;
1142
1143 /* don't realloc if asked to do so */
1144 if (!pci_realloc_enabled()) {
1145 free_list(resource_list_x, &head);
1146 goto enable_and_dump;
1147 }
1148
1149 failed_type = 0;
1150 for (list = head.next; list;) {
1151 failed_type |= list->flags;
1152 list = list->next;
1153 }
1154 /*
1155 * io port are tight, don't try extra
1156 * or if reach the limit, don't want to try more
1157 */
1158 failed_type &= type_mask;
1159 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1160 free_list(resource_list_x, &head);
1161 goto enable_and_dump;
1162 }
1163
1164 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1165 tried_times + 1);
1166
1167 /* third times and later will not check if it is leaf */
1168 if ((tried_times + 1) > 2)
1169 rel_type = whole_subtree;
1170
1171 /*
1172 * Try to release leaf bridge's resources that doesn't fit resource of
1173 * child device under that bridge
1174 */
1175 for (list = head.next; list;) {
1176 bus = list->dev->bus;
1177 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1178 rel_type);
1179 list = list->next;
1180 }
1181 /* restore size and flags */
1182 for (list = head.next; list;) {
1183 struct resource *res = list->res;
1184
1185 res->start = list->start;
1186 res->end = list->end;
1187 res->flags = list->flags;
1188 if (list->dev->subordinate)
1189 res->flags = 0;
1190
1191 list = list->next;
1192 }
1193 free_list(resource_list_x, &head);
1194
1195 goto again;
1196
1197enable_and_dump:
1198 /* Depth last, update the hardware. */
1199 list_for_each_entry(bus, &pci_root_buses, node)
1200 pci_enable_bridges(bus);
1201
1202 /* dump the resource on buses */
1203 list_for_each_entry(bus, &pci_root_buses, node)
1204 pci_bus_dump_resources(bus);
1205}
1206
1207void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1208{
1209 struct pci_bus *parent = bridge->subordinate;
1210 int tried_times = 0;
1211 struct resource_list_x head, *list;
1212 int retval;
1213 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1214 IORESOURCE_PREFETCH;
1215
1216 head.next = NULL;
1217
1218again:
1219 pci_bus_size_bridges(parent);
1220 __pci_bridge_assign_resources(bridge, &head);
1221
1222 tried_times++;
1223
1224 if (!head.next)
1225 goto enable_all;
1226
1227 if (tried_times >= 2) {
1228 /* still fail, don't need to try more */
1229 free_list(resource_list_x, &head);
1230 goto enable_all;
1231 }
1232
1233 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1234 tried_times + 1);
1235
1236 /*
1237 * Try to release leaf bridge's resources that doesn't fit resource of
1238 * child device under that bridge
1239 */
1240 for (list = head.next; list;) {
1241 struct pci_bus *bus = list->dev->bus;
1242 unsigned long flags = list->flags;
1243
1244 pci_bus_release_bridge_resources(bus, flags & type_mask,
1245 whole_subtree);
1246 list = list->next;
1247 }
1248 /* restore size and flags */
1249 for (list = head.next; list;) {
1250 struct resource *res = list->res;
1251
1252 res->start = list->start;
1253 res->end = list->end;
1254 res->flags = list->flags;
1255 if (list->dev->subordinate)
1256 res->flags = 0;
1257
1258 list = list->next;
1259 }
1260 free_list(resource_list_x, &head);
1261
1262 goto again;
1263
1264enable_all:
1265 retval = pci_reenable_device(bridge);
1266 pci_set_master(bridge);
1267 pci_enable_bridges(parent);
1268}
1269EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);