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1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include <asm-generic/pci-bridge.h>
29#include "pci.h"
30
31unsigned int pci_flags;
32
33struct pci_dev_resource {
34 struct list_head list;
35 struct resource *res;
36 struct pci_dev *dev;
37 resource_size_t start;
38 resource_size_t end;
39 resource_size_t add_size;
40 resource_size_t min_align;
41 unsigned long flags;
42};
43
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
53
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
63static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
66{
67 struct pci_dev_resource *tmp;
68
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 if (!tmp) {
71 pr_warning("add_to_list: kmalloc() failed!\n");
72 return -ENOMEM;
73 }
74
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
82
83 list_add(&tmp->list, head);
84
85 return 0;
86}
87
88static void remove_from_list(struct list_head *head,
89 struct resource *res)
90{
91 struct pci_dev_resource *dev_res, *tmp;
92
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
97 break;
98 }
99 }
100}
101
102static resource_size_t get_res_add_size(struct list_head *head,
103 struct resource *res)
104{
105 struct pci_dev_resource *dev_res;
106
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
110
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
113 idx, dev_res->res,
114 (unsigned long long)dev_res->add_size);
115
116 return dev_res->add_size;
117 }
118 }
119
120 return 0;
121}
122
123/* Sort resources by alignment */
124static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
125{
126 int i;
127
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129 struct resource *r;
130 struct pci_dev_resource *dev_res, *tmp;
131 resource_size_t r_align;
132 struct list_head *n;
133
134 r = &dev->resource[i];
135
136 if (r->flags & IORESOURCE_PCI_FIXED)
137 continue;
138
139 if (!(r->flags) || r->parent)
140 continue;
141
142 r_align = pci_resource_alignment(dev, r);
143 if (!r_align) {
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145 i, r);
146 continue;
147 }
148
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150 if (!tmp)
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
153 tmp->res = r;
154 tmp->dev = dev;
155
156 /* fallback is smallest one or list is empty*/
157 n = head;
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
160
161 align = pci_resource_alignment(dev_res->dev,
162 dev_res->res);
163
164 if (r_align > align) {
165 n = &dev_res->list;
166 break;
167 }
168 }
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
171 }
172}
173
174static void __dev_sort_resources(struct pci_dev *dev,
175 struct list_head *head)
176{
177 u16 class = dev->class >> 8;
178
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181 return;
182
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
185 u16 command;
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188 return;
189 }
190
191 pdev_sort_resources(dev, head);
192}
193
194static inline void reset_resource(struct resource *res)
195{
196 res->start = 0;
197 res->end = 0;
198 res->flags = 0;
199}
200
201/**
202 * reassign_resources_sorted() - satisfy any additional resource requests
203 *
204 * @realloc_head : head of the list tracking requests requiring additional
205 * resources
206 * @head : head of the list tracking requests with allocated
207 * resources
208 *
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
212 */
213static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
215{
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size;
220 int idx;
221
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
224
225 res = add_res->res;
226 /* skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
236 }
237 if (!found_match)/* just skip */
238 continue;
239
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 if (!resource_size(res)) {
243 res->start = add_res->start;
244 res->end = res->start + add_size - 1;
245 if (pci_assign_resource(add_res->dev, idx))
246 reset_resource(res);
247 } else {
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
252 add_size, align))
253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
256 idx, res);
257 }
258out:
259 list_del(&add_res->list);
260 kfree(add_res);
261 }
262}
263
264/**
265 * assign_requested_resources_sorted() - satisfy resource requests
266 *
267 * @head : head of the list tracking requests for resources
268 * @failed_list : head of the list tracking requests that could
269 * not be allocated
270 *
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
273 */
274static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
276{
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
279 int idx;
280
281 list_for_each_entry(dev_res, head, list) {
282 res = dev_res->res;
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
286 if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) {
287 /*
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* dont care */,
296 0 /* dont care */);
297 }
298 reset_resource(res);
299 }
300 }
301}
302
303static void __assign_resources_sorted(struct list_head *head,
304 struct list_head *realloc_head,
305 struct list_head *fail_head)
306{
307 /*
308 * Should not assign requested resources at first.
309 * they could be adjacent, so later reassign can not reallocate
310 * them one by one in parent resource window.
311 * Try to assign requested + add_size at begining
312 * if could do that, could get out early.
313 * if could not do that, we still try to assign requested at first,
314 * then try to reassign add_size for some resources.
315 */
316 LIST_HEAD(save_head);
317 LIST_HEAD(local_fail_head);
318 struct pci_dev_resource *save_res;
319 struct pci_dev_resource *dev_res;
320
321 /* Check if optional add_size is there */
322 if (!realloc_head || list_empty(realloc_head))
323 goto requested_and_reassign;
324
325 /* Save original start, end, flags etc at first */
326 list_for_each_entry(dev_res, head, list) {
327 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
328 free_list(&save_head);
329 goto requested_and_reassign;
330 }
331 }
332
333 /* Update res in head list with add_size in realloc_head list */
334 list_for_each_entry(dev_res, head, list)
335 dev_res->res->end += get_res_add_size(realloc_head,
336 dev_res->res);
337
338 /* Try updated head list with add_size added */
339 assign_requested_resources_sorted(head, &local_fail_head);
340
341 /* all assigned with add_size ? */
342 if (list_empty(&local_fail_head)) {
343 /* Remove head list from realloc_head list */
344 list_for_each_entry(dev_res, head, list)
345 remove_from_list(realloc_head, dev_res->res);
346 free_list(&save_head);
347 free_list(head);
348 return;
349 }
350
351 free_list(&local_fail_head);
352 /* Release assigned resource */
353 list_for_each_entry(dev_res, head, list)
354 if (dev_res->res->parent)
355 release_resource(dev_res->res);
356 /* Restore start/end/flags from saved list */
357 list_for_each_entry(save_res, &save_head, list) {
358 struct resource *res = save_res->res;
359
360 res->start = save_res->start;
361 res->end = save_res->end;
362 res->flags = save_res->flags;
363 }
364 free_list(&save_head);
365
366requested_and_reassign:
367 /* Satisfy the must-have resource requests */
368 assign_requested_resources_sorted(head, fail_head);
369
370 /* Try to satisfy any additional optional resource
371 requests */
372 if (realloc_head)
373 reassign_resources_sorted(realloc_head, head);
374 free_list(head);
375}
376
377static void pdev_assign_resources_sorted(struct pci_dev *dev,
378 struct list_head *add_head,
379 struct list_head *fail_head)
380{
381 LIST_HEAD(head);
382
383 __dev_sort_resources(dev, &head);
384 __assign_resources_sorted(&head, add_head, fail_head);
385
386}
387
388static void pbus_assign_resources_sorted(const struct pci_bus *bus,
389 struct list_head *realloc_head,
390 struct list_head *fail_head)
391{
392 struct pci_dev *dev;
393 LIST_HEAD(head);
394
395 list_for_each_entry(dev, &bus->devices, bus_list)
396 __dev_sort_resources(dev, &head);
397
398 __assign_resources_sorted(&head, realloc_head, fail_head);
399}
400
401void pci_setup_cardbus(struct pci_bus *bus)
402{
403 struct pci_dev *bridge = bus->self;
404 struct resource *res;
405 struct pci_bus_region region;
406
407 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
408 bus->secondary, bus->subordinate);
409
410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, ®ion, res);
412 if (res->flags & IORESOURCE_IO) {
413 /*
414 * The IO resource is allocated a range twice as large as it
415 * would normally need. This allows us to set both IO regs.
416 */
417 dev_info(&bridge->dev, " bridge window %pR\n", res);
418 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
419 region.start);
420 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
421 region.end);
422 }
423
424 res = bus->resource[1];
425 pcibios_resource_to_bus(bridge, ®ion, res);
426 if (res->flags & IORESOURCE_IO) {
427 dev_info(&bridge->dev, " bridge window %pR\n", res);
428 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
429 region.start);
430 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
431 region.end);
432 }
433
434 res = bus->resource[2];
435 pcibios_resource_to_bus(bridge, ®ion, res);
436 if (res->flags & IORESOURCE_MEM) {
437 dev_info(&bridge->dev, " bridge window %pR\n", res);
438 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
439 region.start);
440 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
441 region.end);
442 }
443
444 res = bus->resource[3];
445 pcibios_resource_to_bus(bridge, ®ion, res);
446 if (res->flags & IORESOURCE_MEM) {
447 dev_info(&bridge->dev, " bridge window %pR\n", res);
448 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
449 region.start);
450 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
451 region.end);
452 }
453}
454EXPORT_SYMBOL(pci_setup_cardbus);
455
456/* Initialize bridges with base/limit values we have collected.
457 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
458 requires that if there is no I/O ports or memory behind the
459 bridge, corresponding range must be turned off by writing base
460 value greater than limit to the bridge's base/limit registers.
461
462 Note: care must be taken when updating I/O base/limit registers
463 of bridges which support 32-bit I/O. This update requires two
464 config space writes, so it's quite possible that an I/O window of
465 the bridge will have some undesirable address (e.g. 0) after the
466 first write. Ditto 64-bit prefetchable MMIO. */
467static void pci_setup_bridge_io(struct pci_bus *bus)
468{
469 struct pci_dev *bridge = bus->self;
470 struct resource *res;
471 struct pci_bus_region region;
472 u32 l, io_upper16;
473
474 /* Set up the top and bottom of the PCI I/O segment for this bus. */
475 res = bus->resource[0];
476 pcibios_resource_to_bus(bridge, ®ion, res);
477 if (res->flags & IORESOURCE_IO) {
478 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
479 l &= 0xffff0000;
480 l |= (region.start >> 8) & 0x00f0;
481 l |= region.end & 0xf000;
482 /* Set up upper 16 bits of I/O base/limit. */
483 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
484 dev_info(&bridge->dev, " bridge window %pR\n", res);
485 } else {
486 /* Clear upper 16 bits of I/O base/limit. */
487 io_upper16 = 0;
488 l = 0x00f0;
489 }
490 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
491 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
492 /* Update lower 16 bits of I/O base/limit. */
493 pci_write_config_dword(bridge, PCI_IO_BASE, l);
494 /* Update upper 16 bits of I/O base/limit. */
495 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
496}
497
498static void pci_setup_bridge_mmio(struct pci_bus *bus)
499{
500 struct pci_dev *bridge = bus->self;
501 struct resource *res;
502 struct pci_bus_region region;
503 u32 l;
504
505 /* Set up the top and bottom of the PCI Memory segment for this bus. */
506 res = bus->resource[1];
507 pcibios_resource_to_bus(bridge, ®ion, res);
508 if (res->flags & IORESOURCE_MEM) {
509 l = (region.start >> 16) & 0xfff0;
510 l |= region.end & 0xfff00000;
511 dev_info(&bridge->dev, " bridge window %pR\n", res);
512 } else {
513 l = 0x0000fff0;
514 }
515 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
516}
517
518static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
519{
520 struct pci_dev *bridge = bus->self;
521 struct resource *res;
522 struct pci_bus_region region;
523 u32 l, bu, lu;
524
525 /* Clear out the upper 32 bits of PREF limit.
526 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
527 disables PREF range, which is ok. */
528 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
529
530 /* Set up PREF base/limit. */
531 bu = lu = 0;
532 res = bus->resource[2];
533 pcibios_resource_to_bus(bridge, ®ion, res);
534 if (res->flags & IORESOURCE_PREFETCH) {
535 l = (region.start >> 16) & 0xfff0;
536 l |= region.end & 0xfff00000;
537 if (res->flags & IORESOURCE_MEM_64) {
538 bu = upper_32_bits(region.start);
539 lu = upper_32_bits(region.end);
540 }
541 dev_info(&bridge->dev, " bridge window %pR\n", res);
542 } else {
543 l = 0x0000fff0;
544 }
545 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
546
547 /* Set the upper 32 bits of PREF base & limit. */
548 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
549 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
550}
551
552static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
553{
554 struct pci_dev *bridge = bus->self;
555
556 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
557 bus->secondary, bus->subordinate);
558
559 if (type & IORESOURCE_IO)
560 pci_setup_bridge_io(bus);
561
562 if (type & IORESOURCE_MEM)
563 pci_setup_bridge_mmio(bus);
564
565 if (type & IORESOURCE_PREFETCH)
566 pci_setup_bridge_mmio_pref(bus);
567
568 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
569}
570
571void pci_setup_bridge(struct pci_bus *bus)
572{
573 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
574 IORESOURCE_PREFETCH;
575
576 __pci_setup_bridge(bus, type);
577}
578
579/* Check whether the bridge supports optional I/O and
580 prefetchable memory ranges. If not, the respective
581 base/limit registers must be read-only and read as 0. */
582static void pci_bridge_check_ranges(struct pci_bus *bus)
583{
584 u16 io;
585 u32 pmem;
586 struct pci_dev *bridge = bus->self;
587 struct resource *b_res;
588
589 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
590 b_res[1].flags |= IORESOURCE_MEM;
591
592 pci_read_config_word(bridge, PCI_IO_BASE, &io);
593 if (!io) {
594 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
595 pci_read_config_word(bridge, PCI_IO_BASE, &io);
596 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
597 }
598 if (io)
599 b_res[0].flags |= IORESOURCE_IO;
600 /* DECchip 21050 pass 2 errata: the bridge may miss an address
601 disconnect boundary by one PCI data phase.
602 Workaround: do not use prefetching on this device. */
603 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
604 return;
605 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
606 if (!pmem) {
607 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
608 0xfff0fff0);
609 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
610 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
611 }
612 if (pmem) {
613 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
614 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
615 PCI_PREF_RANGE_TYPE_64) {
616 b_res[2].flags |= IORESOURCE_MEM_64;
617 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
618 }
619 }
620
621 /* double check if bridge does support 64 bit pref */
622 if (b_res[2].flags & IORESOURCE_MEM_64) {
623 u32 mem_base_hi, tmp;
624 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
625 &mem_base_hi);
626 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
627 0xffffffff);
628 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
629 if (!tmp)
630 b_res[2].flags &= ~IORESOURCE_MEM_64;
631 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
632 mem_base_hi);
633 }
634}
635
636/* Helper function for sizing routines: find first available
637 bus resource of a given type. Note: we intentionally skip
638 the bus resources which have already been assigned (that is,
639 have non-NULL parent resource). */
640static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
641{
642 int i;
643 struct resource *r;
644 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
645 IORESOURCE_PREFETCH;
646
647 pci_bus_for_each_resource(bus, r, i) {
648 if (r == &ioport_resource || r == &iomem_resource)
649 continue;
650 if (r && (r->flags & type_mask) == type && !r->parent)
651 return r;
652 }
653 return NULL;
654}
655
656static resource_size_t calculate_iosize(resource_size_t size,
657 resource_size_t min_size,
658 resource_size_t size1,
659 resource_size_t old_size,
660 resource_size_t align)
661{
662 if (size < min_size)
663 size = min_size;
664 if (old_size == 1 )
665 old_size = 0;
666 /* To be fixed in 2.5: we should have sort of HAVE_ISA
667 flag in the struct pci_bus. */
668#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
669 size = (size & 0xff) + ((size & ~0xffUL) << 2);
670#endif
671 size = ALIGN(size + size1, align);
672 if (size < old_size)
673 size = old_size;
674 return size;
675}
676
677static resource_size_t calculate_memsize(resource_size_t size,
678 resource_size_t min_size,
679 resource_size_t size1,
680 resource_size_t old_size,
681 resource_size_t align)
682{
683 if (size < min_size)
684 size = min_size;
685 if (old_size == 1 )
686 old_size = 0;
687 if (size < old_size)
688 size = old_size;
689 size = ALIGN(size + size1, align);
690 return size;
691}
692
693/**
694 * pbus_size_io() - size the io window of a given bus
695 *
696 * @bus : the bus
697 * @min_size : the minimum io window that must to be allocated
698 * @add_size : additional optional io window
699 * @realloc_head : track the additional io window on this list
700 *
701 * Sizing the IO windows of the PCI-PCI bridge is trivial,
702 * since these windows have 4K granularity and the IO ranges
703 * of non-bridge PCI devices are limited to 256 bytes.
704 * We must be careful with the ISA aliasing though.
705 */
706static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
707 resource_size_t add_size, struct list_head *realloc_head)
708{
709 struct pci_dev *dev;
710 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
711 unsigned long size = 0, size0 = 0, size1 = 0;
712 resource_size_t children_add_size = 0;
713
714 if (!b_res)
715 return;
716
717 list_for_each_entry(dev, &bus->devices, bus_list) {
718 int i;
719
720 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
721 struct resource *r = &dev->resource[i];
722 unsigned long r_size;
723
724 if (r->parent || !(r->flags & IORESOURCE_IO))
725 continue;
726 r_size = resource_size(r);
727
728 if (r_size < 0x400)
729 /* Might be re-aligned for ISA */
730 size += r_size;
731 else
732 size1 += r_size;
733
734 if (realloc_head)
735 children_add_size += get_res_add_size(realloc_head, r);
736 }
737 }
738 size0 = calculate_iosize(size, min_size, size1,
739 resource_size(b_res), 4096);
740 if (children_add_size > add_size)
741 add_size = children_add_size;
742 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
743 calculate_iosize(size, min_size, add_size + size1,
744 resource_size(b_res), 4096);
745 if (!size0 && !size1) {
746 if (b_res->start || b_res->end)
747 dev_info(&bus->self->dev, "disabling bridge window "
748 "%pR to [bus %02x-%02x] (unused)\n", b_res,
749 bus->secondary, bus->subordinate);
750 b_res->flags = 0;
751 return;
752 }
753 /* Alignment of the IO window is always 4K */
754 b_res->start = 4096;
755 b_res->end = b_res->start + size0 - 1;
756 b_res->flags |= IORESOURCE_STARTALIGN;
757 if (size1 > size0 && realloc_head) {
758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760 "%pR to [bus %02x-%02x] add_size %lx\n", b_res,
761 bus->secondary, bus->subordinate, size1-size0);
762 }
763}
764
765/**
766 * pbus_size_mem() - size the memory window of a given bus
767 *
768 * @bus : the bus
769 * @min_size : the minimum memory window that must to be allocated
770 * @add_size : additional optional memory window
771 * @realloc_head : track the additional memory window on this list
772 *
773 * Calculate the size of the bus and minimal alignment which
774 * guarantees that all child resources fit in this size.
775 */
776static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
777 unsigned long type, resource_size_t min_size,
778 resource_size_t add_size,
779 struct list_head *realloc_head)
780{
781 struct pci_dev *dev;
782 resource_size_t min_align, align, size, size0, size1;
783 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
784 int order, max_order;
785 struct resource *b_res = find_free_bus_resource(bus, type);
786 unsigned int mem64_mask = 0;
787 resource_size_t children_add_size = 0;
788
789 if (!b_res)
790 return 0;
791
792 memset(aligns, 0, sizeof(aligns));
793 max_order = 0;
794 size = 0;
795
796 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
797 b_res->flags &= ~IORESOURCE_MEM_64;
798
799 list_for_each_entry(dev, &bus->devices, bus_list) {
800 int i;
801
802 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
803 struct resource *r = &dev->resource[i];
804 resource_size_t r_size;
805
806 if (r->parent || (r->flags & mask) != type)
807 continue;
808 r_size = resource_size(r);
809#ifdef CONFIG_PCI_IOV
810 /* put SRIOV requested res to the optional list */
811 if (realloc_head && i >= PCI_IOV_RESOURCES &&
812 i <= PCI_IOV_RESOURCE_END) {
813 r->end = r->start - 1;
814 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
815 children_add_size += r_size;
816 continue;
817 }
818#endif
819 /* For bridges size != alignment */
820 align = pci_resource_alignment(dev, r);
821 order = __ffs(align) - 20;
822 if (order > 11) {
823 dev_warn(&dev->dev, "disabling BAR %d: %pR "
824 "(bad alignment %#llx)\n", i, r,
825 (unsigned long long) align);
826 r->flags = 0;
827 continue;
828 }
829 size += r_size;
830 if (order < 0)
831 order = 0;
832 /* Exclude ranges with size > align from
833 calculation of the alignment. */
834 if (r_size == align)
835 aligns[order] += align;
836 if (order > max_order)
837 max_order = order;
838 mem64_mask &= r->flags & IORESOURCE_MEM_64;
839
840 if (realloc_head)
841 children_add_size += get_res_add_size(realloc_head, r);
842 }
843 }
844 align = 0;
845 min_align = 0;
846 for (order = 0; order <= max_order; order++) {
847 resource_size_t align1 = 1;
848
849 align1 <<= (order + 20);
850
851 if (!align)
852 min_align = align1;
853 else if (ALIGN(align + min_align, min_align) < align1)
854 min_align = align1 >> 1;
855 align += aligns[order];
856 }
857 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
858 if (children_add_size > add_size)
859 add_size = children_add_size;
860 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
861 calculate_memsize(size, min_size, add_size,
862 resource_size(b_res), min_align);
863 if (!size0 && !size1) {
864 if (b_res->start || b_res->end)
865 dev_info(&bus->self->dev, "disabling bridge window "
866 "%pR to [bus %02x-%02x] (unused)\n", b_res,
867 bus->secondary, bus->subordinate);
868 b_res->flags = 0;
869 return 1;
870 }
871 b_res->start = min_align;
872 b_res->end = size0 + min_align - 1;
873 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
874 if (size1 > size0 && realloc_head) {
875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to [bus %02x-%02x] add_size %llx\n", b_res,
878 bus->secondary, bus->subordinate, (unsigned long long)size1-size0);
879 }
880 return 1;
881}
882
883unsigned long pci_cardbus_resource_alignment(struct resource *res)
884{
885 if (res->flags & IORESOURCE_IO)
886 return pci_cardbus_io_size;
887 if (res->flags & IORESOURCE_MEM)
888 return pci_cardbus_mem_size;
889 return 0;
890}
891
892static void pci_bus_size_cardbus(struct pci_bus *bus,
893 struct list_head *realloc_head)
894{
895 struct pci_dev *bridge = bus->self;
896 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
897 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
898 u16 ctrl;
899
900 if (b_res[0].parent)
901 goto handle_b_res_1;
902 /*
903 * Reserve some resources for CardBus. We reserve
904 * a fixed amount of bus space for CardBus bridges.
905 */
906 b_res[0].start = pci_cardbus_io_size;
907 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
908 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
909 if (realloc_head) {
910 b_res[0].end -= pci_cardbus_io_size;
911 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
912 pci_cardbus_io_size);
913 }
914
915handle_b_res_1:
916 if (b_res[1].parent)
917 goto handle_b_res_2;
918 b_res[1].start = pci_cardbus_io_size;
919 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
920 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
921 if (realloc_head) {
922 b_res[1].end -= pci_cardbus_io_size;
923 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
924 pci_cardbus_io_size);
925 }
926
927handle_b_res_2:
928 /* MEM1 must not be pref mmio */
929 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
930 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
931 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
932 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
933 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
934 }
935
936 /*
937 * Check whether prefetchable memory is supported
938 * by this bridge.
939 */
940 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
941 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
942 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
943 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
944 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
945 }
946
947 if (b_res[2].parent)
948 goto handle_b_res_3;
949 /*
950 * If we have prefetchable memory support, allocate
951 * two regions. Otherwise, allocate one region of
952 * twice the size.
953 */
954 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
955 b_res[2].start = pci_cardbus_mem_size;
956 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
957 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
958 IORESOURCE_STARTALIGN;
959 if (realloc_head) {
960 b_res[2].end -= pci_cardbus_mem_size;
961 add_to_list(realloc_head, bridge, b_res+2,
962 pci_cardbus_mem_size, pci_cardbus_mem_size);
963 }
964
965 /* reduce that to half */
966 b_res_3_size = pci_cardbus_mem_size;
967 }
968
969handle_b_res_3:
970 if (b_res[3].parent)
971 goto handle_done;
972 b_res[3].start = pci_cardbus_mem_size;
973 b_res[3].end = b_res[3].start + b_res_3_size - 1;
974 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
975 if (realloc_head) {
976 b_res[3].end -= b_res_3_size;
977 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
978 pci_cardbus_mem_size);
979 }
980
981handle_done:
982 ;
983}
984
985void __ref __pci_bus_size_bridges(struct pci_bus *bus,
986 struct list_head *realloc_head)
987{
988 struct pci_dev *dev;
989 unsigned long mask, prefmask;
990 resource_size_t additional_mem_size = 0, additional_io_size = 0;
991
992 list_for_each_entry(dev, &bus->devices, bus_list) {
993 struct pci_bus *b = dev->subordinate;
994 if (!b)
995 continue;
996
997 switch (dev->class >> 8) {
998 case PCI_CLASS_BRIDGE_CARDBUS:
999 pci_bus_size_cardbus(b, realloc_head);
1000 break;
1001
1002 case PCI_CLASS_BRIDGE_PCI:
1003 default:
1004 __pci_bus_size_bridges(b, realloc_head);
1005 break;
1006 }
1007 }
1008
1009 /* The root bus? */
1010 if (!bus->self)
1011 return;
1012
1013 switch (bus->self->class >> 8) {
1014 case PCI_CLASS_BRIDGE_CARDBUS:
1015 /* don't size cardbuses yet. */
1016 break;
1017
1018 case PCI_CLASS_BRIDGE_PCI:
1019 pci_bridge_check_ranges(bus);
1020 if (bus->self->is_hotplug_bridge) {
1021 additional_io_size = pci_hotplug_io_size;
1022 additional_mem_size = pci_hotplug_mem_size;
1023 }
1024 /*
1025 * Follow thru
1026 */
1027 default:
1028 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1029 additional_io_size, realloc_head);
1030 /* If the bridge supports prefetchable range, size it
1031 separately. If it doesn't, or its prefetchable window
1032 has already been allocated by arch code, try
1033 non-prefetchable range for both types of PCI memory
1034 resources. */
1035 mask = IORESOURCE_MEM;
1036 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1037 if (pbus_size_mem(bus, prefmask, prefmask,
1038 realloc_head ? 0 : additional_mem_size,
1039 additional_mem_size, realloc_head))
1040 mask = prefmask; /* Success, size non-prefetch only. */
1041 else
1042 additional_mem_size += additional_mem_size;
1043 pbus_size_mem(bus, mask, IORESOURCE_MEM,
1044 realloc_head ? 0 : additional_mem_size,
1045 additional_mem_size, realloc_head);
1046 break;
1047 }
1048}
1049
1050void __ref pci_bus_size_bridges(struct pci_bus *bus)
1051{
1052 __pci_bus_size_bridges(bus, NULL);
1053}
1054EXPORT_SYMBOL(pci_bus_size_bridges);
1055
1056static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1057 struct list_head *realloc_head,
1058 struct list_head *fail_head)
1059{
1060 struct pci_bus *b;
1061 struct pci_dev *dev;
1062
1063 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1064
1065 list_for_each_entry(dev, &bus->devices, bus_list) {
1066 b = dev->subordinate;
1067 if (!b)
1068 continue;
1069
1070 __pci_bus_assign_resources(b, realloc_head, fail_head);
1071
1072 switch (dev->class >> 8) {
1073 case PCI_CLASS_BRIDGE_PCI:
1074 if (!pci_is_enabled(dev))
1075 pci_setup_bridge(b);
1076 break;
1077
1078 case PCI_CLASS_BRIDGE_CARDBUS:
1079 pci_setup_cardbus(b);
1080 break;
1081
1082 default:
1083 dev_info(&dev->dev, "not setting up bridge for bus "
1084 "%04x:%02x\n", pci_domain_nr(b), b->number);
1085 break;
1086 }
1087 }
1088}
1089
1090void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1091{
1092 __pci_bus_assign_resources(bus, NULL, NULL);
1093}
1094EXPORT_SYMBOL(pci_bus_assign_resources);
1095
1096static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1097 struct list_head *add_head,
1098 struct list_head *fail_head)
1099{
1100 struct pci_bus *b;
1101
1102 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1103 add_head, fail_head);
1104
1105 b = bridge->subordinate;
1106 if (!b)
1107 return;
1108
1109 __pci_bus_assign_resources(b, add_head, fail_head);
1110
1111 switch (bridge->class >> 8) {
1112 case PCI_CLASS_BRIDGE_PCI:
1113 pci_setup_bridge(b);
1114 break;
1115
1116 case PCI_CLASS_BRIDGE_CARDBUS:
1117 pci_setup_cardbus(b);
1118 break;
1119
1120 default:
1121 dev_info(&bridge->dev, "not setting up bridge for bus "
1122 "%04x:%02x\n", pci_domain_nr(b), b->number);
1123 break;
1124 }
1125}
1126static void pci_bridge_release_resources(struct pci_bus *bus,
1127 unsigned long type)
1128{
1129 int idx;
1130 bool changed = false;
1131 struct pci_dev *dev;
1132 struct resource *r;
1133 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1134 IORESOURCE_PREFETCH;
1135
1136 dev = bus->self;
1137 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1138 idx++) {
1139 r = &dev->resource[idx];
1140 if ((r->flags & type_mask) != type)
1141 continue;
1142 if (!r->parent)
1143 continue;
1144 /*
1145 * if there are children under that, we should release them
1146 * all
1147 */
1148 release_child_resources(r);
1149 if (!release_resource(r)) {
1150 dev_printk(KERN_DEBUG, &dev->dev,
1151 "resource %d %pR released\n", idx, r);
1152 /* keep the old size */
1153 r->end = resource_size(r) - 1;
1154 r->start = 0;
1155 r->flags = 0;
1156 changed = true;
1157 }
1158 }
1159
1160 if (changed) {
1161 /* avoiding touch the one without PREF */
1162 if (type & IORESOURCE_PREFETCH)
1163 type = IORESOURCE_PREFETCH;
1164 __pci_setup_bridge(bus, type);
1165 }
1166}
1167
1168enum release_type {
1169 leaf_only,
1170 whole_subtree,
1171};
1172/*
1173 * try to release pci bridge resources that is from leaf bridge,
1174 * so we can allocate big new one later
1175 */
1176static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1177 unsigned long type,
1178 enum release_type rel_type)
1179{
1180 struct pci_dev *dev;
1181 bool is_leaf_bridge = true;
1182
1183 list_for_each_entry(dev, &bus->devices, bus_list) {
1184 struct pci_bus *b = dev->subordinate;
1185 if (!b)
1186 continue;
1187
1188 is_leaf_bridge = false;
1189
1190 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1191 continue;
1192
1193 if (rel_type == whole_subtree)
1194 pci_bus_release_bridge_resources(b, type,
1195 whole_subtree);
1196 }
1197
1198 if (pci_is_root_bus(bus))
1199 return;
1200
1201 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1202 return;
1203
1204 if ((rel_type == whole_subtree) || is_leaf_bridge)
1205 pci_bridge_release_resources(bus, type);
1206}
1207
1208static void pci_bus_dump_res(struct pci_bus *bus)
1209{
1210 struct resource *res;
1211 int i;
1212
1213 pci_bus_for_each_resource(bus, res, i) {
1214 if (!res || !res->end || !res->flags)
1215 continue;
1216
1217 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1218 }
1219}
1220
1221static void pci_bus_dump_resources(struct pci_bus *bus)
1222{
1223 struct pci_bus *b;
1224 struct pci_dev *dev;
1225
1226
1227 pci_bus_dump_res(bus);
1228
1229 list_for_each_entry(dev, &bus->devices, bus_list) {
1230 b = dev->subordinate;
1231 if (!b)
1232 continue;
1233
1234 pci_bus_dump_resources(b);
1235 }
1236}
1237
1238static int __init pci_bus_get_depth(struct pci_bus *bus)
1239{
1240 int depth = 0;
1241 struct pci_dev *dev;
1242
1243 list_for_each_entry(dev, &bus->devices, bus_list) {
1244 int ret;
1245 struct pci_bus *b = dev->subordinate;
1246 if (!b)
1247 continue;
1248
1249 ret = pci_bus_get_depth(b);
1250 if (ret + 1 > depth)
1251 depth = ret + 1;
1252 }
1253
1254 return depth;
1255}
1256static int __init pci_get_max_depth(void)
1257{
1258 int depth = 0;
1259 struct pci_bus *bus;
1260
1261 list_for_each_entry(bus, &pci_root_buses, node) {
1262 int ret;
1263
1264 ret = pci_bus_get_depth(bus);
1265 if (ret > depth)
1266 depth = ret;
1267 }
1268
1269 return depth;
1270}
1271
1272/*
1273 * -1: undefined, will auto detect later
1274 * 0: disabled by user
1275 * 1: disabled by auto detect
1276 * 2: enabled by user
1277 * 3: enabled by auto detect
1278 */
1279enum enable_type {
1280 undefined = -1,
1281 user_disabled,
1282 auto_disabled,
1283 user_enabled,
1284 auto_enabled,
1285};
1286
1287static enum enable_type pci_realloc_enable __initdata = undefined;
1288void __init pci_realloc_get_opt(char *str)
1289{
1290 if (!strncmp(str, "off", 3))
1291 pci_realloc_enable = user_disabled;
1292 else if (!strncmp(str, "on", 2))
1293 pci_realloc_enable = user_enabled;
1294}
1295static bool __init pci_realloc_enabled(void)
1296{
1297 return pci_realloc_enable >= user_enabled;
1298}
1299
1300static void __init pci_realloc_detect(void)
1301{
1302#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1303 struct pci_dev *dev = NULL;
1304
1305 if (pci_realloc_enable != undefined)
1306 return;
1307
1308 for_each_pci_dev(dev) {
1309 int i;
1310
1311 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1312 struct resource *r = &dev->resource[i];
1313
1314 /* Not assigned, or rejected by kernel ? */
1315 if (r->flags && !r->start) {
1316 pci_realloc_enable = auto_enabled;
1317
1318 return;
1319 }
1320 }
1321 }
1322#endif
1323}
1324
1325/*
1326 * first try will not touch pci bridge res
1327 * second and later try will clear small leaf bridge res
1328 * will stop till to the max deepth if can not find good one
1329 */
1330void __init
1331pci_assign_unassigned_resources(void)
1332{
1333 struct pci_bus *bus;
1334 LIST_HEAD(realloc_head); /* list of resources that
1335 want additional resources */
1336 struct list_head *add_list = NULL;
1337 int tried_times = 0;
1338 enum release_type rel_type = leaf_only;
1339 LIST_HEAD(fail_head);
1340 struct pci_dev_resource *fail_res;
1341 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1342 IORESOURCE_PREFETCH;
1343 int pci_try_num = 1;
1344
1345 /* don't realloc if asked to do so */
1346 pci_realloc_detect();
1347 if (pci_realloc_enabled()) {
1348 int max_depth = pci_get_max_depth();
1349
1350 pci_try_num = max_depth + 1;
1351 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1352 max_depth, pci_try_num);
1353 }
1354
1355again:
1356 /*
1357 * last try will use add_list, otherwise will try good to have as
1358 * must have, so can realloc parent bridge resource
1359 */
1360 if (tried_times + 1 == pci_try_num)
1361 add_list = &realloc_head;
1362 /* Depth first, calculate sizes and alignments of all
1363 subordinate buses. */
1364 list_for_each_entry(bus, &pci_root_buses, node)
1365 __pci_bus_size_bridges(bus, add_list);
1366
1367 /* Depth last, allocate resources and update the hardware. */
1368 list_for_each_entry(bus, &pci_root_buses, node)
1369 __pci_bus_assign_resources(bus, add_list, &fail_head);
1370 if (add_list)
1371 BUG_ON(!list_empty(add_list));
1372 tried_times++;
1373
1374 /* any device complain? */
1375 if (list_empty(&fail_head))
1376 goto enable_and_dump;
1377
1378 if (tried_times >= pci_try_num) {
1379 if (pci_realloc_enable == undefined)
1380 printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1381 else if (pci_realloc_enable == auto_enabled)
1382 printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1383
1384 free_list(&fail_head);
1385 goto enable_and_dump;
1386 }
1387
1388 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1389 tried_times + 1);
1390
1391 /* third times and later will not check if it is leaf */
1392 if ((tried_times + 1) > 2)
1393 rel_type = whole_subtree;
1394
1395 /*
1396 * Try to release leaf bridge's resources that doesn't fit resource of
1397 * child device under that bridge
1398 */
1399 list_for_each_entry(fail_res, &fail_head, list) {
1400 bus = fail_res->dev->bus;
1401 pci_bus_release_bridge_resources(bus,
1402 fail_res->flags & type_mask,
1403 rel_type);
1404 }
1405 /* restore size and flags */
1406 list_for_each_entry(fail_res, &fail_head, list) {
1407 struct resource *res = fail_res->res;
1408
1409 res->start = fail_res->start;
1410 res->end = fail_res->end;
1411 res->flags = fail_res->flags;
1412 if (fail_res->dev->subordinate)
1413 res->flags = 0;
1414 }
1415 free_list(&fail_head);
1416
1417 goto again;
1418
1419enable_and_dump:
1420 /* Depth last, update the hardware. */
1421 list_for_each_entry(bus, &pci_root_buses, node)
1422 pci_enable_bridges(bus);
1423
1424 /* dump the resource on buses */
1425 list_for_each_entry(bus, &pci_root_buses, node)
1426 pci_bus_dump_resources(bus);
1427}
1428
1429void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1430{
1431 struct pci_bus *parent = bridge->subordinate;
1432 LIST_HEAD(add_list); /* list of resources that
1433 want additional resources */
1434 int tried_times = 0;
1435 LIST_HEAD(fail_head);
1436 struct pci_dev_resource *fail_res;
1437 int retval;
1438 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1439 IORESOURCE_PREFETCH;
1440
1441again:
1442 __pci_bus_size_bridges(parent, &add_list);
1443 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1444 BUG_ON(!list_empty(&add_list));
1445 tried_times++;
1446
1447 if (list_empty(&fail_head))
1448 goto enable_all;
1449
1450 if (tried_times >= 2) {
1451 /* still fail, don't need to try more */
1452 free_list(&fail_head);
1453 goto enable_all;
1454 }
1455
1456 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1457 tried_times + 1);
1458
1459 /*
1460 * Try to release leaf bridge's resources that doesn't fit resource of
1461 * child device under that bridge
1462 */
1463 list_for_each_entry(fail_res, &fail_head, list) {
1464 struct pci_bus *bus = fail_res->dev->bus;
1465 unsigned long flags = fail_res->flags;
1466
1467 pci_bus_release_bridge_resources(bus, flags & type_mask,
1468 whole_subtree);
1469 }
1470 /* restore size and flags */
1471 list_for_each_entry(fail_res, &fail_head, list) {
1472 struct resource *res = fail_res->res;
1473
1474 res->start = fail_res->start;
1475 res->end = fail_res->end;
1476 res->flags = fail_res->flags;
1477 if (fail_res->dev->subordinate)
1478 res->flags = 0;
1479 }
1480 free_list(&fail_head);
1481
1482 goto again;
1483
1484enable_all:
1485 retval = pci_reenable_device(bridge);
1486 pci_set_master(bridge);
1487 pci_enable_bridges(parent);
1488}
1489EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1490
1491#ifdef CONFIG_HOTPLUG
1492/**
1493 * pci_rescan_bus - scan a PCI bus for devices.
1494 * @bus: PCI bus to scan
1495 *
1496 * Scan a PCI bus and child buses for new devices, adds them,
1497 * and enables them.
1498 *
1499 * Returns the max number of subordinate bus discovered.
1500 */
1501unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1502{
1503 unsigned int max;
1504 struct pci_dev *dev;
1505 LIST_HEAD(add_list); /* list of resources that
1506 want additional resources */
1507
1508 max = pci_scan_child_bus(bus);
1509
1510 down_read(&pci_bus_sem);
1511 list_for_each_entry(dev, &bus->devices, bus_list)
1512 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1513 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1514 if (dev->subordinate)
1515 __pci_bus_size_bridges(dev->subordinate,
1516 &add_list);
1517 up_read(&pci_bus_sem);
1518 __pci_bus_assign_resources(bus, &add_list, NULL);
1519 BUG_ON(!list_empty(&add_list));
1520
1521 pci_enable_bridges(bus);
1522 pci_bus_add_devices(bus);
1523
1524 return max;
1525}
1526EXPORT_SYMBOL_GPL(pci_rescan_bus);
1527#endif
1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include <asm-generic/pci-bridge.h>
29#include "pci.h"
30
31unsigned int pci_flags;
32
33struct pci_dev_resource {
34 struct list_head list;
35 struct resource *res;
36 struct pci_dev *dev;
37 resource_size_t start;
38 resource_size_t end;
39 resource_size_t add_size;
40 resource_size_t min_align;
41 unsigned long flags;
42};
43
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
53
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
63static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
66{
67 struct pci_dev_resource *tmp;
68
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70 if (!tmp) {
71 pr_warning("add_to_list: kmalloc() failed!\n");
72 return -ENOMEM;
73 }
74
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
82
83 list_add(&tmp->list, head);
84
85 return 0;
86}
87
88static void remove_from_list(struct list_head *head,
89 struct resource *res)
90{
91 struct pci_dev_resource *dev_res, *tmp;
92
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
97 break;
98 }
99 }
100}
101
102static resource_size_t get_res_add_size(struct list_head *head,
103 struct resource *res)
104{
105 struct pci_dev_resource *dev_res;
106
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
110
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
113 idx, dev_res->res,
114 (unsigned long long)dev_res->add_size);
115
116 return dev_res->add_size;
117 }
118 }
119
120 return 0;
121}
122
123/* Sort resources by alignment */
124static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
125{
126 int i;
127
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129 struct resource *r;
130 struct pci_dev_resource *dev_res, *tmp;
131 resource_size_t r_align;
132 struct list_head *n;
133
134 r = &dev->resource[i];
135
136 if (r->flags & IORESOURCE_PCI_FIXED)
137 continue;
138
139 if (!(r->flags) || r->parent)
140 continue;
141
142 r_align = pci_resource_alignment(dev, r);
143 if (!r_align) {
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145 i, r);
146 continue;
147 }
148
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150 if (!tmp)
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
153 tmp->res = r;
154 tmp->dev = dev;
155
156 /* fallback is smallest one or list is empty*/
157 n = head;
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
160
161 align = pci_resource_alignment(dev_res->dev,
162 dev_res->res);
163
164 if (r_align > align) {
165 n = &dev_res->list;
166 break;
167 }
168 }
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
171 }
172}
173
174static void __dev_sort_resources(struct pci_dev *dev,
175 struct list_head *head)
176{
177 u16 class = dev->class >> 8;
178
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181 return;
182
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
185 u16 command;
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188 return;
189 }
190
191 pdev_sort_resources(dev, head);
192}
193
194static inline void reset_resource(struct resource *res)
195{
196 res->start = 0;
197 res->end = 0;
198 res->flags = 0;
199}
200
201/**
202 * reassign_resources_sorted() - satisfy any additional resource requests
203 *
204 * @realloc_head : head of the list tracking requests requiring additional
205 * resources
206 * @head : head of the list tracking requests with allocated
207 * resources
208 *
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
212 */
213static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
215{
216 struct resource *res;
217 struct pci_dev_resource *add_res, *tmp;
218 struct pci_dev_resource *dev_res;
219 resource_size_t add_size;
220 int idx;
221
222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
223 bool found_match = false;
224
225 res = add_res->res;
226 /* skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
236 }
237 if (!found_match)/* just skip */
238 continue;
239
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
242 if (!resource_size(res)) {
243 res->start = add_res->start;
244 res->end = res->start + add_size - 1;
245 if (pci_assign_resource(add_res->dev, idx))
246 reset_resource(res);
247 } else {
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
251 if (pci_reassign_resource(add_res->dev, idx,
252 add_size, align))
253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
256 idx, res);
257 }
258out:
259 list_del(&add_res->list);
260 kfree(add_res);
261 }
262}
263
264/**
265 * assign_requested_resources_sorted() - satisfy resource requests
266 *
267 * @head : head of the list tracking requests for resources
268 * @fail_head : head of the list tracking requests that could
269 * not be allocated
270 *
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
273 */
274static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
276{
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
279 int idx;
280
281 list_for_each_entry(dev_res, head, list) {
282 res = dev_res->res;
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
286 if (fail_head) {
287 /*
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* don't care */,
296 0 /* don't care */);
297 }
298 reset_resource(res);
299 }
300 }
301}
302
303static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
304{
305 struct pci_dev_resource *fail_res;
306 unsigned long mask = 0;
307
308 /* check failed type */
309 list_for_each_entry(fail_res, fail_head, list)
310 mask |= fail_res->flags;
311
312 /*
313 * one pref failed resource will set IORESOURCE_MEM,
314 * as we can allocate pref in non-pref range.
315 * Will release all assigned non-pref sibling resources
316 * according to that bit.
317 */
318 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
319}
320
321static bool pci_need_to_release(unsigned long mask, struct resource *res)
322{
323 if (res->flags & IORESOURCE_IO)
324 return !!(mask & IORESOURCE_IO);
325
326 /* check pref at first */
327 if (res->flags & IORESOURCE_PREFETCH) {
328 if (mask & IORESOURCE_PREFETCH)
329 return true;
330 /* count pref if its parent is non-pref */
331 else if ((mask & IORESOURCE_MEM) &&
332 !(res->parent->flags & IORESOURCE_PREFETCH))
333 return true;
334 else
335 return false;
336 }
337
338 if (res->flags & IORESOURCE_MEM)
339 return !!(mask & IORESOURCE_MEM);
340
341 return false; /* should not get here */
342}
343
344static void __assign_resources_sorted(struct list_head *head,
345 struct list_head *realloc_head,
346 struct list_head *fail_head)
347{
348 /*
349 * Should not assign requested resources at first.
350 * they could be adjacent, so later reassign can not reallocate
351 * them one by one in parent resource window.
352 * Try to assign requested + add_size at beginning
353 * if could do that, could get out early.
354 * if could not do that, we still try to assign requested at first,
355 * then try to reassign add_size for some resources.
356 *
357 * Separate three resource type checking if we need to release
358 * assigned resource after requested + add_size try.
359 * 1. if there is io port assign fail, will release assigned
360 * io port.
361 * 2. if there is pref mmio assign fail, release assigned
362 * pref mmio.
363 * if assigned pref mmio's parent is non-pref mmio and there
364 * is non-pref mmio assign fail, will release that assigned
365 * pref mmio.
366 * 3. if there is non-pref mmio assign fail or pref mmio
367 * assigned fail, will release assigned non-pref mmio.
368 */
369 LIST_HEAD(save_head);
370 LIST_HEAD(local_fail_head);
371 struct pci_dev_resource *save_res;
372 struct pci_dev_resource *dev_res, *tmp_res;
373 unsigned long fail_type;
374
375 /* Check if optional add_size is there */
376 if (!realloc_head || list_empty(realloc_head))
377 goto requested_and_reassign;
378
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res, head, list) {
381 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
382 free_list(&save_head);
383 goto requested_and_reassign;
384 }
385 }
386
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry(dev_res, head, list)
389 dev_res->res->end += get_res_add_size(realloc_head,
390 dev_res->res);
391
392 /* Try updated head list with add_size added */
393 assign_requested_resources_sorted(head, &local_fail_head);
394
395 /* all assigned with add_size ? */
396 if (list_empty(&local_fail_head)) {
397 /* Remove head list from realloc_head list */
398 list_for_each_entry(dev_res, head, list)
399 remove_from_list(realloc_head, dev_res->res);
400 free_list(&save_head);
401 free_list(head);
402 return;
403 }
404
405 /* check failed type */
406 fail_type = pci_fail_res_type_mask(&local_fail_head);
407 /* remove not need to be released assigned res from head list etc */
408 list_for_each_entry_safe(dev_res, tmp_res, head, list)
409 if (dev_res->res->parent &&
410 !pci_need_to_release(fail_type, dev_res->res)) {
411 /* remove it from realloc_head list */
412 remove_from_list(realloc_head, dev_res->res);
413 remove_from_list(&save_head, dev_res->res);
414 list_del(&dev_res->list);
415 kfree(dev_res);
416 }
417
418 free_list(&local_fail_head);
419 /* Release assigned resource */
420 list_for_each_entry(dev_res, head, list)
421 if (dev_res->res->parent)
422 release_resource(dev_res->res);
423 /* Restore start/end/flags from saved list */
424 list_for_each_entry(save_res, &save_head, list) {
425 struct resource *res = save_res->res;
426
427 res->start = save_res->start;
428 res->end = save_res->end;
429 res->flags = save_res->flags;
430 }
431 free_list(&save_head);
432
433requested_and_reassign:
434 /* Satisfy the must-have resource requests */
435 assign_requested_resources_sorted(head, fail_head);
436
437 /* Try to satisfy any additional optional resource
438 requests */
439 if (realloc_head)
440 reassign_resources_sorted(realloc_head, head);
441 free_list(head);
442}
443
444static void pdev_assign_resources_sorted(struct pci_dev *dev,
445 struct list_head *add_head,
446 struct list_head *fail_head)
447{
448 LIST_HEAD(head);
449
450 __dev_sort_resources(dev, &head);
451 __assign_resources_sorted(&head, add_head, fail_head);
452
453}
454
455static void pbus_assign_resources_sorted(const struct pci_bus *bus,
456 struct list_head *realloc_head,
457 struct list_head *fail_head)
458{
459 struct pci_dev *dev;
460 LIST_HEAD(head);
461
462 list_for_each_entry(dev, &bus->devices, bus_list)
463 __dev_sort_resources(dev, &head);
464
465 __assign_resources_sorted(&head, realloc_head, fail_head);
466}
467
468void pci_setup_cardbus(struct pci_bus *bus)
469{
470 struct pci_dev *bridge = bus->self;
471 struct resource *res;
472 struct pci_bus_region region;
473
474 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
475 &bus->busn_res);
476
477 res = bus->resource[0];
478 pcibios_resource_to_bus(bridge->bus, ®ion, res);
479 if (res->flags & IORESOURCE_IO) {
480 /*
481 * The IO resource is allocated a range twice as large as it
482 * would normally need. This allows us to set both IO regs.
483 */
484 dev_info(&bridge->dev, " bridge window %pR\n", res);
485 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
486 region.start);
487 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
488 region.end);
489 }
490
491 res = bus->resource[1];
492 pcibios_resource_to_bus(bridge->bus, ®ion, res);
493 if (res->flags & IORESOURCE_IO) {
494 dev_info(&bridge->dev, " bridge window %pR\n", res);
495 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
496 region.start);
497 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
498 region.end);
499 }
500
501 res = bus->resource[2];
502 pcibios_resource_to_bus(bridge->bus, ®ion, res);
503 if (res->flags & IORESOURCE_MEM) {
504 dev_info(&bridge->dev, " bridge window %pR\n", res);
505 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
506 region.start);
507 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
508 region.end);
509 }
510
511 res = bus->resource[3];
512 pcibios_resource_to_bus(bridge->bus, ®ion, res);
513 if (res->flags & IORESOURCE_MEM) {
514 dev_info(&bridge->dev, " bridge window %pR\n", res);
515 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
516 region.start);
517 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
518 region.end);
519 }
520}
521EXPORT_SYMBOL(pci_setup_cardbus);
522
523/* Initialize bridges with base/limit values we have collected.
524 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
525 requires that if there is no I/O ports or memory behind the
526 bridge, corresponding range must be turned off by writing base
527 value greater than limit to the bridge's base/limit registers.
528
529 Note: care must be taken when updating I/O base/limit registers
530 of bridges which support 32-bit I/O. This update requires two
531 config space writes, so it's quite possible that an I/O window of
532 the bridge will have some undesirable address (e.g. 0) after the
533 first write. Ditto 64-bit prefetchable MMIO. */
534static void pci_setup_bridge_io(struct pci_bus *bus)
535{
536 struct pci_dev *bridge = bus->self;
537 struct resource *res;
538 struct pci_bus_region region;
539 unsigned long io_mask;
540 u8 io_base_lo, io_limit_lo;
541 u16 l;
542 u32 io_upper16;
543
544 io_mask = PCI_IO_RANGE_MASK;
545 if (bridge->io_window_1k)
546 io_mask = PCI_IO_1K_RANGE_MASK;
547
548 /* Set up the top and bottom of the PCI I/O segment for this bus. */
549 res = bus->resource[0];
550 pcibios_resource_to_bus(bridge->bus, ®ion, res);
551 if (res->flags & IORESOURCE_IO) {
552 pci_read_config_word(bridge, PCI_IO_BASE, &l);
553 io_base_lo = (region.start >> 8) & io_mask;
554 io_limit_lo = (region.end >> 8) & io_mask;
555 l = ((u16) io_limit_lo << 8) | io_base_lo;
556 /* Set up upper 16 bits of I/O base/limit. */
557 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
558 dev_info(&bridge->dev, " bridge window %pR\n", res);
559 } else {
560 /* Clear upper 16 bits of I/O base/limit. */
561 io_upper16 = 0;
562 l = 0x00f0;
563 }
564 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
565 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
566 /* Update lower 16 bits of I/O base/limit. */
567 pci_write_config_word(bridge, PCI_IO_BASE, l);
568 /* Update upper 16 bits of I/O base/limit. */
569 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
570}
571
572static void pci_setup_bridge_mmio(struct pci_bus *bus)
573{
574 struct pci_dev *bridge = bus->self;
575 struct resource *res;
576 struct pci_bus_region region;
577 u32 l;
578
579 /* Set up the top and bottom of the PCI Memory segment for this bus. */
580 res = bus->resource[1];
581 pcibios_resource_to_bus(bridge->bus, ®ion, res);
582 if (res->flags & IORESOURCE_MEM) {
583 l = (region.start >> 16) & 0xfff0;
584 l |= region.end & 0xfff00000;
585 dev_info(&bridge->dev, " bridge window %pR\n", res);
586 } else {
587 l = 0x0000fff0;
588 }
589 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
590}
591
592static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
593{
594 struct pci_dev *bridge = bus->self;
595 struct resource *res;
596 struct pci_bus_region region;
597 u32 l, bu, lu;
598
599 /* Clear out the upper 32 bits of PREF limit.
600 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
601 disables PREF range, which is ok. */
602 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
603
604 /* Set up PREF base/limit. */
605 bu = lu = 0;
606 res = bus->resource[2];
607 pcibios_resource_to_bus(bridge->bus, ®ion, res);
608 if (res->flags & IORESOURCE_PREFETCH) {
609 l = (region.start >> 16) & 0xfff0;
610 l |= region.end & 0xfff00000;
611 if (res->flags & IORESOURCE_MEM_64) {
612 bu = upper_32_bits(region.start);
613 lu = upper_32_bits(region.end);
614 }
615 dev_info(&bridge->dev, " bridge window %pR\n", res);
616 } else {
617 l = 0x0000fff0;
618 }
619 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
620
621 /* Set the upper 32 bits of PREF base & limit. */
622 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
623 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
624}
625
626static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
627{
628 struct pci_dev *bridge = bus->self;
629
630 dev_info(&bridge->dev, "PCI bridge to %pR\n",
631 &bus->busn_res);
632
633 if (type & IORESOURCE_IO)
634 pci_setup_bridge_io(bus);
635
636 if (type & IORESOURCE_MEM)
637 pci_setup_bridge_mmio(bus);
638
639 if (type & IORESOURCE_PREFETCH)
640 pci_setup_bridge_mmio_pref(bus);
641
642 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
643}
644
645void pci_setup_bridge(struct pci_bus *bus)
646{
647 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
648 IORESOURCE_PREFETCH;
649
650 __pci_setup_bridge(bus, type);
651}
652
653/* Check whether the bridge supports optional I/O and
654 prefetchable memory ranges. If not, the respective
655 base/limit registers must be read-only and read as 0. */
656static void pci_bridge_check_ranges(struct pci_bus *bus)
657{
658 u16 io;
659 u32 pmem;
660 struct pci_dev *bridge = bus->self;
661 struct resource *b_res;
662
663 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
664 b_res[1].flags |= IORESOURCE_MEM;
665
666 pci_read_config_word(bridge, PCI_IO_BASE, &io);
667 if (!io) {
668 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
669 pci_read_config_word(bridge, PCI_IO_BASE, &io);
670 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
671 }
672 if (io)
673 b_res[0].flags |= IORESOURCE_IO;
674
675 /* DECchip 21050 pass 2 errata: the bridge may miss an address
676 disconnect boundary by one PCI data phase.
677 Workaround: do not use prefetching on this device. */
678 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
679 return;
680
681 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
682 if (!pmem) {
683 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
684 0xffe0fff0);
685 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
686 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
687 }
688 if (pmem) {
689 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
690 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
691 PCI_PREF_RANGE_TYPE_64) {
692 b_res[2].flags |= IORESOURCE_MEM_64;
693 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
694 }
695 }
696
697 /* double check if bridge does support 64 bit pref */
698 if (b_res[2].flags & IORESOURCE_MEM_64) {
699 u32 mem_base_hi, tmp;
700 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
701 &mem_base_hi);
702 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
703 0xffffffff);
704 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
705 if (!tmp)
706 b_res[2].flags &= ~IORESOURCE_MEM_64;
707 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
708 mem_base_hi);
709 }
710}
711
712/* Helper function for sizing routines: find first available
713 bus resource of a given type. Note: we intentionally skip
714 the bus resources which have already been assigned (that is,
715 have non-NULL parent resource). */
716static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
717{
718 int i;
719 struct resource *r;
720 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
721 IORESOURCE_PREFETCH;
722
723 pci_bus_for_each_resource(bus, r, i) {
724 if (r == &ioport_resource || r == &iomem_resource)
725 continue;
726 if (r && (r->flags & type_mask) == type && !r->parent)
727 return r;
728 }
729 return NULL;
730}
731
732static resource_size_t calculate_iosize(resource_size_t size,
733 resource_size_t min_size,
734 resource_size_t size1,
735 resource_size_t old_size,
736 resource_size_t align)
737{
738 if (size < min_size)
739 size = min_size;
740 if (old_size == 1 )
741 old_size = 0;
742 /* To be fixed in 2.5: we should have sort of HAVE_ISA
743 flag in the struct pci_bus. */
744#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
745 size = (size & 0xff) + ((size & ~0xffUL) << 2);
746#endif
747 size = ALIGN(size + size1, align);
748 if (size < old_size)
749 size = old_size;
750 return size;
751}
752
753static resource_size_t calculate_memsize(resource_size_t size,
754 resource_size_t min_size,
755 resource_size_t size1,
756 resource_size_t old_size,
757 resource_size_t align)
758{
759 if (size < min_size)
760 size = min_size;
761 if (old_size == 1 )
762 old_size = 0;
763 if (size < old_size)
764 size = old_size;
765 size = ALIGN(size + size1, align);
766 return size;
767}
768
769resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
770 unsigned long type)
771{
772 return 1;
773}
774
775#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
776#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
777#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
778
779static resource_size_t window_alignment(struct pci_bus *bus,
780 unsigned long type)
781{
782 resource_size_t align = 1, arch_align;
783
784 if (type & IORESOURCE_MEM)
785 align = PCI_P2P_DEFAULT_MEM_ALIGN;
786 else if (type & IORESOURCE_IO) {
787 /*
788 * Per spec, I/O windows are 4K-aligned, but some
789 * bridges have an extension to support 1K alignment.
790 */
791 if (bus->self->io_window_1k)
792 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
793 else
794 align = PCI_P2P_DEFAULT_IO_ALIGN;
795 }
796
797 arch_align = pcibios_window_alignment(bus, type);
798 return max(align, arch_align);
799}
800
801/**
802 * pbus_size_io() - size the io window of a given bus
803 *
804 * @bus : the bus
805 * @min_size : the minimum io window that must to be allocated
806 * @add_size : additional optional io window
807 * @realloc_head : track the additional io window on this list
808 *
809 * Sizing the IO windows of the PCI-PCI bridge is trivial,
810 * since these windows have 1K or 4K granularity and the IO ranges
811 * of non-bridge PCI devices are limited to 256 bytes.
812 * We must be careful with the ISA aliasing though.
813 */
814static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
815 resource_size_t add_size, struct list_head *realloc_head)
816{
817 struct pci_dev *dev;
818 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
819 resource_size_t size = 0, size0 = 0, size1 = 0;
820 resource_size_t children_add_size = 0;
821 resource_size_t min_align, align;
822
823 if (!b_res)
824 return;
825
826 min_align = window_alignment(bus, IORESOURCE_IO);
827 list_for_each_entry(dev, &bus->devices, bus_list) {
828 int i;
829
830 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
831 struct resource *r = &dev->resource[i];
832 unsigned long r_size;
833
834 if (r->parent || !(r->flags & IORESOURCE_IO))
835 continue;
836 r_size = resource_size(r);
837
838 if (r_size < 0x400)
839 /* Might be re-aligned for ISA */
840 size += r_size;
841 else
842 size1 += r_size;
843
844 align = pci_resource_alignment(dev, r);
845 if (align > min_align)
846 min_align = align;
847
848 if (realloc_head)
849 children_add_size += get_res_add_size(realloc_head, r);
850 }
851 }
852
853 size0 = calculate_iosize(size, min_size, size1,
854 resource_size(b_res), min_align);
855 if (children_add_size > add_size)
856 add_size = children_add_size;
857 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
858 calculate_iosize(size, min_size, add_size + size1,
859 resource_size(b_res), min_align);
860 if (!size0 && !size1) {
861 if (b_res->start || b_res->end)
862 dev_info(&bus->self->dev, "disabling bridge window "
863 "%pR to %pR (unused)\n", b_res,
864 &bus->busn_res);
865 b_res->flags = 0;
866 return;
867 }
868
869 b_res->start = min_align;
870 b_res->end = b_res->start + size0 - 1;
871 b_res->flags |= IORESOURCE_STARTALIGN;
872 if (size1 > size0 && realloc_head) {
873 add_to_list(realloc_head, bus->self, b_res, size1-size0,
874 min_align);
875 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
876 "%pR to %pR add_size %llx\n", b_res,
877 &bus->busn_res,
878 (unsigned long long)size1-size0);
879 }
880}
881
882static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
883 int max_order)
884{
885 resource_size_t align = 0;
886 resource_size_t min_align = 0;
887 int order;
888
889 for (order = 0; order <= max_order; order++) {
890 resource_size_t align1 = 1;
891
892 align1 <<= (order + 20);
893
894 if (!align)
895 min_align = align1;
896 else if (ALIGN(align + min_align, min_align) < align1)
897 min_align = align1 >> 1;
898 align += aligns[order];
899 }
900
901 return min_align;
902}
903
904/**
905 * pbus_size_mem() - size the memory window of a given bus
906 *
907 * @bus : the bus
908 * @mask: mask the resource flag, then compare it with type
909 * @type: the type of free resource from bridge
910 * @min_size : the minimum memory window that must to be allocated
911 * @add_size : additional optional memory window
912 * @realloc_head : track the additional memory window on this list
913 *
914 * Calculate the size of the bus and minimal alignment which
915 * guarantees that all child resources fit in this size.
916 */
917static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
918 unsigned long type, resource_size_t min_size,
919 resource_size_t add_size,
920 struct list_head *realloc_head)
921{
922 struct pci_dev *dev;
923 resource_size_t min_align, align, size, size0, size1;
924 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
925 int order, max_order;
926 struct resource *b_res = find_free_bus_resource(bus, type);
927 unsigned int mem64_mask = 0;
928 resource_size_t children_add_size = 0;
929
930 if (!b_res)
931 return 0;
932
933 memset(aligns, 0, sizeof(aligns));
934 max_order = 0;
935 size = 0;
936
937 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
938 b_res->flags &= ~IORESOURCE_MEM_64;
939
940 list_for_each_entry(dev, &bus->devices, bus_list) {
941 int i;
942
943 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
944 struct resource *r = &dev->resource[i];
945 resource_size_t r_size;
946
947 if (r->parent || (r->flags & mask) != type)
948 continue;
949 r_size = resource_size(r);
950#ifdef CONFIG_PCI_IOV
951 /* put SRIOV requested res to the optional list */
952 if (realloc_head && i >= PCI_IOV_RESOURCES &&
953 i <= PCI_IOV_RESOURCE_END) {
954 r->end = r->start - 1;
955 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
956 children_add_size += r_size;
957 continue;
958 }
959#endif
960 /* For bridges size != alignment */
961 align = pci_resource_alignment(dev, r);
962 order = __ffs(align) - 20;
963 if (order > 11) {
964 dev_warn(&dev->dev, "disabling BAR %d: %pR "
965 "(bad alignment %#llx)\n", i, r,
966 (unsigned long long) align);
967 r->flags = 0;
968 continue;
969 }
970 size += r_size;
971 if (order < 0)
972 order = 0;
973 /* Exclude ranges with size > align from
974 calculation of the alignment. */
975 if (r_size == align)
976 aligns[order] += align;
977 if (order > max_order)
978 max_order = order;
979 mem64_mask &= r->flags & IORESOURCE_MEM_64;
980
981 if (realloc_head)
982 children_add_size += get_res_add_size(realloc_head, r);
983 }
984 }
985
986 min_align = calculate_mem_align(aligns, max_order);
987 min_align = max(min_align, window_alignment(bus, b_res->flags));
988 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
989 if (children_add_size > add_size)
990 add_size = children_add_size;
991 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
992 calculate_memsize(size, min_size, add_size,
993 resource_size(b_res), min_align);
994 if (!size0 && !size1) {
995 if (b_res->start || b_res->end)
996 dev_info(&bus->self->dev, "disabling bridge window "
997 "%pR to %pR (unused)\n", b_res,
998 &bus->busn_res);
999 b_res->flags = 0;
1000 return 1;
1001 }
1002 b_res->start = min_align;
1003 b_res->end = size0 + min_align - 1;
1004 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
1005 if (size1 > size0 && realloc_head) {
1006 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
1007 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
1008 "%pR to %pR add_size %llx\n", b_res,
1009 &bus->busn_res, (unsigned long long)size1-size0);
1010 }
1011 return 1;
1012}
1013
1014unsigned long pci_cardbus_resource_alignment(struct resource *res)
1015{
1016 if (res->flags & IORESOURCE_IO)
1017 return pci_cardbus_io_size;
1018 if (res->flags & IORESOURCE_MEM)
1019 return pci_cardbus_mem_size;
1020 return 0;
1021}
1022
1023static void pci_bus_size_cardbus(struct pci_bus *bus,
1024 struct list_head *realloc_head)
1025{
1026 struct pci_dev *bridge = bus->self;
1027 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1028 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1029 u16 ctrl;
1030
1031 if (b_res[0].parent)
1032 goto handle_b_res_1;
1033 /*
1034 * Reserve some resources for CardBus. We reserve
1035 * a fixed amount of bus space for CardBus bridges.
1036 */
1037 b_res[0].start = pci_cardbus_io_size;
1038 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1039 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1040 if (realloc_head) {
1041 b_res[0].end -= pci_cardbus_io_size;
1042 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1043 pci_cardbus_io_size);
1044 }
1045
1046handle_b_res_1:
1047 if (b_res[1].parent)
1048 goto handle_b_res_2;
1049 b_res[1].start = pci_cardbus_io_size;
1050 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1051 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1052 if (realloc_head) {
1053 b_res[1].end -= pci_cardbus_io_size;
1054 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1055 pci_cardbus_io_size);
1056 }
1057
1058handle_b_res_2:
1059 /* MEM1 must not be pref mmio */
1060 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1061 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1062 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1063 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1064 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1065 }
1066
1067 /*
1068 * Check whether prefetchable memory is supported
1069 * by this bridge.
1070 */
1071 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1072 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1073 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1074 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1075 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1076 }
1077
1078 if (b_res[2].parent)
1079 goto handle_b_res_3;
1080 /*
1081 * If we have prefetchable memory support, allocate
1082 * two regions. Otherwise, allocate one region of
1083 * twice the size.
1084 */
1085 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1086 b_res[2].start = pci_cardbus_mem_size;
1087 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1088 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1089 IORESOURCE_STARTALIGN;
1090 if (realloc_head) {
1091 b_res[2].end -= pci_cardbus_mem_size;
1092 add_to_list(realloc_head, bridge, b_res+2,
1093 pci_cardbus_mem_size, pci_cardbus_mem_size);
1094 }
1095
1096 /* reduce that to half */
1097 b_res_3_size = pci_cardbus_mem_size;
1098 }
1099
1100handle_b_res_3:
1101 if (b_res[3].parent)
1102 goto handle_done;
1103 b_res[3].start = pci_cardbus_mem_size;
1104 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1105 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1106 if (realloc_head) {
1107 b_res[3].end -= b_res_3_size;
1108 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1109 pci_cardbus_mem_size);
1110 }
1111
1112handle_done:
1113 ;
1114}
1115
1116void __ref __pci_bus_size_bridges(struct pci_bus *bus,
1117 struct list_head *realloc_head)
1118{
1119 struct pci_dev *dev;
1120 unsigned long mask, prefmask;
1121 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1122
1123 list_for_each_entry(dev, &bus->devices, bus_list) {
1124 struct pci_bus *b = dev->subordinate;
1125 if (!b)
1126 continue;
1127
1128 switch (dev->class >> 8) {
1129 case PCI_CLASS_BRIDGE_CARDBUS:
1130 pci_bus_size_cardbus(b, realloc_head);
1131 break;
1132
1133 case PCI_CLASS_BRIDGE_PCI:
1134 default:
1135 __pci_bus_size_bridges(b, realloc_head);
1136 break;
1137 }
1138 }
1139
1140 /* The root bus? */
1141 if (pci_is_root_bus(bus))
1142 return;
1143
1144 switch (bus->self->class >> 8) {
1145 case PCI_CLASS_BRIDGE_CARDBUS:
1146 /* don't size cardbuses yet. */
1147 break;
1148
1149 case PCI_CLASS_BRIDGE_PCI:
1150 pci_bridge_check_ranges(bus);
1151 if (bus->self->is_hotplug_bridge) {
1152 additional_io_size = pci_hotplug_io_size;
1153 additional_mem_size = pci_hotplug_mem_size;
1154 }
1155 /*
1156 * Follow thru
1157 */
1158 default:
1159 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1160 additional_io_size, realloc_head);
1161 /* If the bridge supports prefetchable range, size it
1162 separately. If it doesn't, or its prefetchable window
1163 has already been allocated by arch code, try
1164 non-prefetchable range for both types of PCI memory
1165 resources. */
1166 mask = IORESOURCE_MEM;
1167 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1168 if (pbus_size_mem(bus, prefmask, prefmask,
1169 realloc_head ? 0 : additional_mem_size,
1170 additional_mem_size, realloc_head))
1171 mask = prefmask; /* Success, size non-prefetch only. */
1172 else
1173 additional_mem_size += additional_mem_size;
1174 pbus_size_mem(bus, mask, IORESOURCE_MEM,
1175 realloc_head ? 0 : additional_mem_size,
1176 additional_mem_size, realloc_head);
1177 break;
1178 }
1179}
1180
1181void __ref pci_bus_size_bridges(struct pci_bus *bus)
1182{
1183 __pci_bus_size_bridges(bus, NULL);
1184}
1185EXPORT_SYMBOL(pci_bus_size_bridges);
1186
1187void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
1188 struct list_head *realloc_head,
1189 struct list_head *fail_head)
1190{
1191 struct pci_bus *b;
1192 struct pci_dev *dev;
1193
1194 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1195
1196 list_for_each_entry(dev, &bus->devices, bus_list) {
1197 b = dev->subordinate;
1198 if (!b)
1199 continue;
1200
1201 __pci_bus_assign_resources(b, realloc_head, fail_head);
1202
1203 switch (dev->class >> 8) {
1204 case PCI_CLASS_BRIDGE_PCI:
1205 if (!pci_is_enabled(dev))
1206 pci_setup_bridge(b);
1207 break;
1208
1209 case PCI_CLASS_BRIDGE_CARDBUS:
1210 pci_setup_cardbus(b);
1211 break;
1212
1213 default:
1214 dev_info(&dev->dev, "not setting up bridge for bus "
1215 "%04x:%02x\n", pci_domain_nr(b), b->number);
1216 break;
1217 }
1218 }
1219}
1220
1221void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1222{
1223 __pci_bus_assign_resources(bus, NULL, NULL);
1224}
1225EXPORT_SYMBOL(pci_bus_assign_resources);
1226
1227static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
1228 struct list_head *add_head,
1229 struct list_head *fail_head)
1230{
1231 struct pci_bus *b;
1232
1233 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1234 add_head, fail_head);
1235
1236 b = bridge->subordinate;
1237 if (!b)
1238 return;
1239
1240 __pci_bus_assign_resources(b, add_head, fail_head);
1241
1242 switch (bridge->class >> 8) {
1243 case PCI_CLASS_BRIDGE_PCI:
1244 pci_setup_bridge(b);
1245 break;
1246
1247 case PCI_CLASS_BRIDGE_CARDBUS:
1248 pci_setup_cardbus(b);
1249 break;
1250
1251 default:
1252 dev_info(&bridge->dev, "not setting up bridge for bus "
1253 "%04x:%02x\n", pci_domain_nr(b), b->number);
1254 break;
1255 }
1256}
1257static void pci_bridge_release_resources(struct pci_bus *bus,
1258 unsigned long type)
1259{
1260 int idx;
1261 bool changed = false;
1262 struct pci_dev *dev;
1263 struct resource *r;
1264 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1265 IORESOURCE_PREFETCH;
1266
1267 dev = bus->self;
1268 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1269 idx++) {
1270 r = &dev->resource[idx];
1271 if ((r->flags & type_mask) != type)
1272 continue;
1273 if (!r->parent)
1274 continue;
1275 /*
1276 * if there are children under that, we should release them
1277 * all
1278 */
1279 release_child_resources(r);
1280 if (!release_resource(r)) {
1281 dev_printk(KERN_DEBUG, &dev->dev,
1282 "resource %d %pR released\n", idx, r);
1283 /* keep the old size */
1284 r->end = resource_size(r) - 1;
1285 r->start = 0;
1286 r->flags = 0;
1287 changed = true;
1288 }
1289 }
1290
1291 if (changed) {
1292 /* avoiding touch the one without PREF */
1293 if (type & IORESOURCE_PREFETCH)
1294 type = IORESOURCE_PREFETCH;
1295 __pci_setup_bridge(bus, type);
1296 }
1297}
1298
1299enum release_type {
1300 leaf_only,
1301 whole_subtree,
1302};
1303/*
1304 * try to release pci bridge resources that is from leaf bridge,
1305 * so we can allocate big new one later
1306 */
1307static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1308 unsigned long type,
1309 enum release_type rel_type)
1310{
1311 struct pci_dev *dev;
1312 bool is_leaf_bridge = true;
1313
1314 list_for_each_entry(dev, &bus->devices, bus_list) {
1315 struct pci_bus *b = dev->subordinate;
1316 if (!b)
1317 continue;
1318
1319 is_leaf_bridge = false;
1320
1321 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1322 continue;
1323
1324 if (rel_type == whole_subtree)
1325 pci_bus_release_bridge_resources(b, type,
1326 whole_subtree);
1327 }
1328
1329 if (pci_is_root_bus(bus))
1330 return;
1331
1332 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1333 return;
1334
1335 if ((rel_type == whole_subtree) || is_leaf_bridge)
1336 pci_bridge_release_resources(bus, type);
1337}
1338
1339static void pci_bus_dump_res(struct pci_bus *bus)
1340{
1341 struct resource *res;
1342 int i;
1343
1344 pci_bus_for_each_resource(bus, res, i) {
1345 if (!res || !res->end || !res->flags)
1346 continue;
1347
1348 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1349 }
1350}
1351
1352static void pci_bus_dump_resources(struct pci_bus *bus)
1353{
1354 struct pci_bus *b;
1355 struct pci_dev *dev;
1356
1357
1358 pci_bus_dump_res(bus);
1359
1360 list_for_each_entry(dev, &bus->devices, bus_list) {
1361 b = dev->subordinate;
1362 if (!b)
1363 continue;
1364
1365 pci_bus_dump_resources(b);
1366 }
1367}
1368
1369static int pci_bus_get_depth(struct pci_bus *bus)
1370{
1371 int depth = 0;
1372 struct pci_bus *child_bus;
1373
1374 list_for_each_entry(child_bus, &bus->children, node){
1375 int ret;
1376
1377 ret = pci_bus_get_depth(child_bus);
1378 if (ret + 1 > depth)
1379 depth = ret + 1;
1380 }
1381
1382 return depth;
1383}
1384
1385/*
1386 * -1: undefined, will auto detect later
1387 * 0: disabled by user
1388 * 1: disabled by auto detect
1389 * 2: enabled by user
1390 * 3: enabled by auto detect
1391 */
1392enum enable_type {
1393 undefined = -1,
1394 user_disabled,
1395 auto_disabled,
1396 user_enabled,
1397 auto_enabled,
1398};
1399
1400static enum enable_type pci_realloc_enable = undefined;
1401void __init pci_realloc_get_opt(char *str)
1402{
1403 if (!strncmp(str, "off", 3))
1404 pci_realloc_enable = user_disabled;
1405 else if (!strncmp(str, "on", 2))
1406 pci_realloc_enable = user_enabled;
1407}
1408static bool pci_realloc_enabled(enum enable_type enable)
1409{
1410 return enable >= user_enabled;
1411}
1412
1413#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1414static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1415{
1416 int i;
1417 bool *unassigned = data;
1418
1419 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1420 struct resource *r = &dev->resource[i];
1421 struct pci_bus_region region;
1422
1423 /* Not assigned or rejected by kernel? */
1424 if (!r->flags)
1425 continue;
1426
1427 pcibios_resource_to_bus(dev->bus, ®ion, r);
1428 if (!region.start) {
1429 *unassigned = true;
1430 return 1; /* return early from pci_walk_bus() */
1431 }
1432 }
1433
1434 return 0;
1435}
1436
1437static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1438 enum enable_type enable_local)
1439{
1440 bool unassigned = false;
1441
1442 if (enable_local != undefined)
1443 return enable_local;
1444
1445 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1446 if (unassigned)
1447 return auto_enabled;
1448
1449 return enable_local;
1450}
1451#else
1452static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1453 enum enable_type enable_local)
1454{
1455 return enable_local;
1456}
1457#endif
1458
1459/*
1460 * first try will not touch pci bridge res
1461 * second and later try will clear small leaf bridge res
1462 * will stop till to the max depth if can not find good one
1463 */
1464void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1465{
1466 LIST_HEAD(realloc_head); /* list of resources that
1467 want additional resources */
1468 struct list_head *add_list = NULL;
1469 int tried_times = 0;
1470 enum release_type rel_type = leaf_only;
1471 LIST_HEAD(fail_head);
1472 struct pci_dev_resource *fail_res;
1473 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1474 IORESOURCE_PREFETCH;
1475 int pci_try_num = 1;
1476 enum enable_type enable_local;
1477
1478 /* don't realloc if asked to do so */
1479 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1480 if (pci_realloc_enabled(enable_local)) {
1481 int max_depth = pci_bus_get_depth(bus);
1482
1483 pci_try_num = max_depth + 1;
1484 dev_printk(KERN_DEBUG, &bus->dev,
1485 "max bus depth: %d pci_try_num: %d\n",
1486 max_depth, pci_try_num);
1487 }
1488
1489again:
1490 /*
1491 * last try will use add_list, otherwise will try good to have as
1492 * must have, so can realloc parent bridge resource
1493 */
1494 if (tried_times + 1 == pci_try_num)
1495 add_list = &realloc_head;
1496 /* Depth first, calculate sizes and alignments of all
1497 subordinate buses. */
1498 __pci_bus_size_bridges(bus, add_list);
1499
1500 /* Depth last, allocate resources and update the hardware. */
1501 __pci_bus_assign_resources(bus, add_list, &fail_head);
1502 if (add_list)
1503 BUG_ON(!list_empty(add_list));
1504 tried_times++;
1505
1506 /* any device complain? */
1507 if (list_empty(&fail_head))
1508 goto dump;
1509
1510 if (tried_times >= pci_try_num) {
1511 if (enable_local == undefined)
1512 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1513 else if (enable_local == auto_enabled)
1514 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1515
1516 free_list(&fail_head);
1517 goto dump;
1518 }
1519
1520 dev_printk(KERN_DEBUG, &bus->dev,
1521 "No. %d try to assign unassigned res\n", tried_times + 1);
1522
1523 /* third times and later will not check if it is leaf */
1524 if ((tried_times + 1) > 2)
1525 rel_type = whole_subtree;
1526
1527 /*
1528 * Try to release leaf bridge's resources that doesn't fit resource of
1529 * child device under that bridge
1530 */
1531 list_for_each_entry(fail_res, &fail_head, list)
1532 pci_bus_release_bridge_resources(fail_res->dev->bus,
1533 fail_res->flags & type_mask,
1534 rel_type);
1535
1536 /* restore size and flags */
1537 list_for_each_entry(fail_res, &fail_head, list) {
1538 struct resource *res = fail_res->res;
1539
1540 res->start = fail_res->start;
1541 res->end = fail_res->end;
1542 res->flags = fail_res->flags;
1543 if (fail_res->dev->subordinate)
1544 res->flags = 0;
1545 }
1546 free_list(&fail_head);
1547
1548 goto again;
1549
1550dump:
1551 /* dump the resource on buses */
1552 pci_bus_dump_resources(bus);
1553}
1554
1555void __init pci_assign_unassigned_resources(void)
1556{
1557 struct pci_bus *root_bus;
1558
1559 list_for_each_entry(root_bus, &pci_root_buses, node)
1560 pci_assign_unassigned_root_bus_resources(root_bus);
1561}
1562
1563void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1564{
1565 struct pci_bus *parent = bridge->subordinate;
1566 LIST_HEAD(add_list); /* list of resources that
1567 want additional resources */
1568 int tried_times = 0;
1569 LIST_HEAD(fail_head);
1570 struct pci_dev_resource *fail_res;
1571 int retval;
1572 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1573 IORESOURCE_PREFETCH;
1574
1575again:
1576 __pci_bus_size_bridges(parent, &add_list);
1577 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1578 BUG_ON(!list_empty(&add_list));
1579 tried_times++;
1580
1581 if (list_empty(&fail_head))
1582 goto enable_all;
1583
1584 if (tried_times >= 2) {
1585 /* still fail, don't need to try more */
1586 free_list(&fail_head);
1587 goto enable_all;
1588 }
1589
1590 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1591 tried_times + 1);
1592
1593 /*
1594 * Try to release leaf bridge's resources that doesn't fit resource of
1595 * child device under that bridge
1596 */
1597 list_for_each_entry(fail_res, &fail_head, list)
1598 pci_bus_release_bridge_resources(fail_res->dev->bus,
1599 fail_res->flags & type_mask,
1600 whole_subtree);
1601
1602 /* restore size and flags */
1603 list_for_each_entry(fail_res, &fail_head, list) {
1604 struct resource *res = fail_res->res;
1605
1606 res->start = fail_res->start;
1607 res->end = fail_res->end;
1608 res->flags = fail_res->flags;
1609 if (fail_res->dev->subordinate)
1610 res->flags = 0;
1611 }
1612 free_list(&fail_head);
1613
1614 goto again;
1615
1616enable_all:
1617 retval = pci_reenable_device(bridge);
1618 if (retval)
1619 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1620 pci_set_master(bridge);
1621}
1622EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1623
1624void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1625{
1626 struct pci_dev *dev;
1627 LIST_HEAD(add_list); /* list of resources that
1628 want additional resources */
1629
1630 down_read(&pci_bus_sem);
1631 list_for_each_entry(dev, &bus->devices, bus_list)
1632 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1633 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1634 if (dev->subordinate)
1635 __pci_bus_size_bridges(dev->subordinate,
1636 &add_list);
1637 up_read(&pci_bus_sem);
1638 __pci_bus_assign_resources(bus, &add_list, NULL);
1639 BUG_ON(!list_empty(&add_list));
1640}