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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Ross Biro
7 * Copyright (C) Linus Torvalds
8 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
9 * Copyright (C) 1996 David S. Miller
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 1999 MIPS Technologies, Inc.
12 * Copyright (C) 2000 Ulf Carlsson
13 *
14 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
15 * binaries.
16 */
17#include <linux/compiler.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/errno.h>
22#include <linux/ptrace.h>
23#include <linux/smp.h>
24#include <linux/user.h>
25#include <linux/security.h>
26#include <linux/audit.h>
27#include <linux/seccomp.h>
28
29#include <asm/byteorder.h>
30#include <asm/cpu.h>
31#include <asm/dsp.h>
32#include <asm/fpu.h>
33#include <asm/mipsregs.h>
34#include <asm/mipsmtregs.h>
35#include <asm/pgtable.h>
36#include <asm/page.h>
37#include <asm/uaccess.h>
38#include <asm/bootinfo.h>
39#include <asm/reg.h>
40
41/*
42 * Called by kernel/ptrace.c when detaching..
43 *
44 * Make sure single step bits etc are not set.
45 */
46void ptrace_disable(struct task_struct *child)
47{
48 /* Don't load the watchpoint registers for the ex-child. */
49 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
50}
51
52/*
53 * Read a general register set. We always use the 64-bit format, even
54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
55 * Registers are sign extended to fill the available space.
56 */
57int ptrace_getregs(struct task_struct *child, __s64 __user *data)
58{
59 struct pt_regs *regs;
60 int i;
61
62 if (!access_ok(VERIFY_WRITE, data, 38 * 8))
63 return -EIO;
64
65 regs = task_pt_regs(child);
66
67 for (i = 0; i < 32; i++)
68 __put_user((long)regs->regs[i], data + i);
69 __put_user((long)regs->lo, data + EF_LO - EF_R0);
70 __put_user((long)regs->hi, data + EF_HI - EF_R0);
71 __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
72 __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
73 __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
74 __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
75
76 return 0;
77}
78
79/*
80 * Write a general register set. As for PTRACE_GETREGS, we always use
81 * the 64-bit format. On a 32-bit kernel only the lower order half
82 * (according to endianness) will be used.
83 */
84int ptrace_setregs(struct task_struct *child, __s64 __user *data)
85{
86 struct pt_regs *regs;
87 int i;
88
89 if (!access_ok(VERIFY_READ, data, 38 * 8))
90 return -EIO;
91
92 regs = task_pt_regs(child);
93
94 for (i = 0; i < 32; i++)
95 __get_user(regs->regs[i], data + i);
96 __get_user(regs->lo, data + EF_LO - EF_R0);
97 __get_user(regs->hi, data + EF_HI - EF_R0);
98 __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
99
100 /* badvaddr, status, and cause may not be written. */
101
102 return 0;
103}
104
105int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
106{
107 int i;
108 unsigned int tmp;
109
110 if (!access_ok(VERIFY_WRITE, data, 33 * 8))
111 return -EIO;
112
113 if (tsk_used_math(child)) {
114 fpureg_t *fregs = get_fpu_regs(child);
115 for (i = 0; i < 32; i++)
116 __put_user(fregs[i], i + (__u64 __user *) data);
117 } else {
118 for (i = 0; i < 32; i++)
119 __put_user((__u64) -1, i + (__u64 __user *) data);
120 }
121
122 __put_user(child->thread.fpu.fcr31, data + 64);
123
124 preempt_disable();
125 if (cpu_has_fpu) {
126 unsigned int flags;
127
128 if (cpu_has_mipsmt) {
129 unsigned int vpflags = dvpe();
130 flags = read_c0_status();
131 __enable_fpu();
132 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
133 write_c0_status(flags);
134 evpe(vpflags);
135 } else {
136 flags = read_c0_status();
137 __enable_fpu();
138 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
139 write_c0_status(flags);
140 }
141 } else {
142 tmp = 0;
143 }
144 preempt_enable();
145 __put_user(tmp, data + 65);
146
147 return 0;
148}
149
150int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
151{
152 fpureg_t *fregs;
153 int i;
154
155 if (!access_ok(VERIFY_READ, data, 33 * 8))
156 return -EIO;
157
158 fregs = get_fpu_regs(child);
159
160 for (i = 0; i < 32; i++)
161 __get_user(fregs[i], i + (__u64 __user *) data);
162
163 __get_user(child->thread.fpu.fcr31, data + 64);
164
165 /* FIR may not be written. */
166
167 return 0;
168}
169
170int ptrace_get_watch_regs(struct task_struct *child,
171 struct pt_watch_regs __user *addr)
172{
173 enum pt_watch_style style;
174 int i;
175
176 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
177 return -EIO;
178 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
179 return -EIO;
180
181#ifdef CONFIG_32BIT
182 style = pt_watch_style_mips32;
183#define WATCH_STYLE mips32
184#else
185 style = pt_watch_style_mips64;
186#define WATCH_STYLE mips64
187#endif
188
189 __put_user(style, &addr->style);
190 __put_user(current_cpu_data.watch_reg_use_cnt,
191 &addr->WATCH_STYLE.num_valid);
192 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
193 __put_user(child->thread.watch.mips3264.watchlo[i],
194 &addr->WATCH_STYLE.watchlo[i]);
195 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
196 &addr->WATCH_STYLE.watchhi[i]);
197 __put_user(current_cpu_data.watch_reg_masks[i],
198 &addr->WATCH_STYLE.watch_masks[i]);
199 }
200 for (; i < 8; i++) {
201 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
202 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
203 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
204 }
205
206 return 0;
207}
208
209int ptrace_set_watch_regs(struct task_struct *child,
210 struct pt_watch_regs __user *addr)
211{
212 int i;
213 int watch_active = 0;
214 unsigned long lt[NUM_WATCH_REGS];
215 u16 ht[NUM_WATCH_REGS];
216
217 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
218 return -EIO;
219 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
220 return -EIO;
221 /* Check the values. */
222 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
223 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
224#ifdef CONFIG_32BIT
225 if (lt[i] & __UA_LIMIT)
226 return -EINVAL;
227#else
228 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
229 if (lt[i] & 0xffffffff80000000UL)
230 return -EINVAL;
231 } else {
232 if (lt[i] & __UA_LIMIT)
233 return -EINVAL;
234 }
235#endif
236 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
237 if (ht[i] & ~0xff8)
238 return -EINVAL;
239 }
240 /* Install them. */
241 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
242 if (lt[i] & 7)
243 watch_active = 1;
244 child->thread.watch.mips3264.watchlo[i] = lt[i];
245 /* Set the G bit. */
246 child->thread.watch.mips3264.watchhi[i] = ht[i];
247 }
248
249 if (watch_active)
250 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
251 else
252 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
253
254 return 0;
255}
256
257long arch_ptrace(struct task_struct *child, long request,
258 unsigned long addr, unsigned long data)
259{
260 int ret;
261 void __user *addrp = (void __user *) addr;
262 void __user *datavp = (void __user *) data;
263 unsigned long __user *datalp = (void __user *) data;
264
265 switch (request) {
266 /* when I and D space are separate, these will need to be fixed. */
267 case PTRACE_PEEKTEXT: /* read word at location addr. */
268 case PTRACE_PEEKDATA:
269 ret = generic_ptrace_peekdata(child, addr, data);
270 break;
271
272 /* Read the word at location addr in the USER area. */
273 case PTRACE_PEEKUSR: {
274 struct pt_regs *regs;
275 unsigned long tmp = 0;
276
277 regs = task_pt_regs(child);
278 ret = 0; /* Default return value. */
279
280 switch (addr) {
281 case 0 ... 31:
282 tmp = regs->regs[addr];
283 break;
284 case FPR_BASE ... FPR_BASE + 31:
285 if (tsk_used_math(child)) {
286 fpureg_t *fregs = get_fpu_regs(child);
287
288#ifdef CONFIG_32BIT
289 /*
290 * The odd registers are actually the high
291 * order bits of the values stored in the even
292 * registers - unless we're using r2k_switch.S.
293 */
294 if (addr & 1)
295 tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
296 else
297 tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
298#endif
299#ifdef CONFIG_64BIT
300 tmp = fregs[addr - FPR_BASE];
301#endif
302 } else {
303 tmp = -1; /* FP not yet used */
304 }
305 break;
306 case PC:
307 tmp = regs->cp0_epc;
308 break;
309 case CAUSE:
310 tmp = regs->cp0_cause;
311 break;
312 case BADVADDR:
313 tmp = regs->cp0_badvaddr;
314 break;
315 case MMHI:
316 tmp = regs->hi;
317 break;
318 case MMLO:
319 tmp = regs->lo;
320 break;
321#ifdef CONFIG_CPU_HAS_SMARTMIPS
322 case ACX:
323 tmp = regs->acx;
324 break;
325#endif
326 case FPC_CSR:
327 tmp = child->thread.fpu.fcr31;
328 break;
329 case FPC_EIR: { /* implementation / version register */
330 unsigned int flags;
331#ifdef CONFIG_MIPS_MT_SMTC
332 unsigned long irqflags;
333 unsigned int mtflags;
334#endif /* CONFIG_MIPS_MT_SMTC */
335
336 preempt_disable();
337 if (!cpu_has_fpu) {
338 preempt_enable();
339 break;
340 }
341
342#ifdef CONFIG_MIPS_MT_SMTC
343 /* Read-modify-write of Status must be atomic */
344 local_irq_save(irqflags);
345 mtflags = dmt();
346#endif /* CONFIG_MIPS_MT_SMTC */
347 if (cpu_has_mipsmt) {
348 unsigned int vpflags = dvpe();
349 flags = read_c0_status();
350 __enable_fpu();
351 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
352 write_c0_status(flags);
353 evpe(vpflags);
354 } else {
355 flags = read_c0_status();
356 __enable_fpu();
357 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
358 write_c0_status(flags);
359 }
360#ifdef CONFIG_MIPS_MT_SMTC
361 emt(mtflags);
362 local_irq_restore(irqflags);
363#endif /* CONFIG_MIPS_MT_SMTC */
364 preempt_enable();
365 break;
366 }
367 case DSP_BASE ... DSP_BASE + 5: {
368 dspreg_t *dregs;
369
370 if (!cpu_has_dsp) {
371 tmp = 0;
372 ret = -EIO;
373 goto out;
374 }
375 dregs = __get_dsp_regs(child);
376 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
377 break;
378 }
379 case DSP_CONTROL:
380 if (!cpu_has_dsp) {
381 tmp = 0;
382 ret = -EIO;
383 goto out;
384 }
385 tmp = child->thread.dsp.dspcontrol;
386 break;
387 default:
388 tmp = 0;
389 ret = -EIO;
390 goto out;
391 }
392 ret = put_user(tmp, datalp);
393 break;
394 }
395
396 /* when I and D space are separate, this will have to be fixed. */
397 case PTRACE_POKETEXT: /* write the word at location addr. */
398 case PTRACE_POKEDATA:
399 ret = generic_ptrace_pokedata(child, addr, data);
400 break;
401
402 case PTRACE_POKEUSR: {
403 struct pt_regs *regs;
404 ret = 0;
405 regs = task_pt_regs(child);
406
407 switch (addr) {
408 case 0 ... 31:
409 regs->regs[addr] = data;
410 break;
411 case FPR_BASE ... FPR_BASE + 31: {
412 fpureg_t *fregs = get_fpu_regs(child);
413
414 if (!tsk_used_math(child)) {
415 /* FP not yet used */
416 memset(&child->thread.fpu, ~0,
417 sizeof(child->thread.fpu));
418 child->thread.fpu.fcr31 = 0;
419 }
420#ifdef CONFIG_32BIT
421 /*
422 * The odd registers are actually the high order bits
423 * of the values stored in the even registers - unless
424 * we're using r2k_switch.S.
425 */
426 if (addr & 1) {
427 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
428 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
429 } else {
430 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
431 fregs[addr - FPR_BASE] |= data;
432 }
433#endif
434#ifdef CONFIG_64BIT
435 fregs[addr - FPR_BASE] = data;
436#endif
437 break;
438 }
439 case PC:
440 regs->cp0_epc = data;
441 break;
442 case MMHI:
443 regs->hi = data;
444 break;
445 case MMLO:
446 regs->lo = data;
447 break;
448#ifdef CONFIG_CPU_HAS_SMARTMIPS
449 case ACX:
450 regs->acx = data;
451 break;
452#endif
453 case FPC_CSR:
454 child->thread.fpu.fcr31 = data;
455 break;
456 case DSP_BASE ... DSP_BASE + 5: {
457 dspreg_t *dregs;
458
459 if (!cpu_has_dsp) {
460 ret = -EIO;
461 break;
462 }
463
464 dregs = __get_dsp_regs(child);
465 dregs[addr - DSP_BASE] = data;
466 break;
467 }
468 case DSP_CONTROL:
469 if (!cpu_has_dsp) {
470 ret = -EIO;
471 break;
472 }
473 child->thread.dsp.dspcontrol = data;
474 break;
475 default:
476 /* The rest are not allowed. */
477 ret = -EIO;
478 break;
479 }
480 break;
481 }
482
483 case PTRACE_GETREGS:
484 ret = ptrace_getregs(child, datavp);
485 break;
486
487 case PTRACE_SETREGS:
488 ret = ptrace_setregs(child, datavp);
489 break;
490
491 case PTRACE_GETFPREGS:
492 ret = ptrace_getfpregs(child, datavp);
493 break;
494
495 case PTRACE_SETFPREGS:
496 ret = ptrace_setfpregs(child, datavp);
497 break;
498
499 case PTRACE_GET_THREAD_AREA:
500 ret = put_user(task_thread_info(child)->tp_value, datalp);
501 break;
502
503 case PTRACE_GET_WATCH_REGS:
504 ret = ptrace_get_watch_regs(child, addrp);
505 break;
506
507 case PTRACE_SET_WATCH_REGS:
508 ret = ptrace_set_watch_regs(child, addrp);
509 break;
510
511 default:
512 ret = ptrace_request(child, request, addr, data);
513 break;
514 }
515 out:
516 return ret;
517}
518
519static inline int audit_arch(void)
520{
521 int arch = EM_MIPS;
522#ifdef CONFIG_64BIT
523 arch |= __AUDIT_ARCH_64BIT;
524#endif
525#if defined(__LITTLE_ENDIAN)
526 arch |= __AUDIT_ARCH_LE;
527#endif
528 return arch;
529}
530
531/*
532 * Notification of system call entry/exit
533 * - triggered by current->work.syscall_trace
534 */
535asmlinkage void syscall_trace_enter(struct pt_regs *regs)
536{
537 /* do the secure computing check first */
538 secure_computing_strict(regs->regs[2]);
539
540 if (!(current->ptrace & PT_PTRACED))
541 goto out;
542
543 if (!test_thread_flag(TIF_SYSCALL_TRACE))
544 goto out;
545
546 /* The 0x80 provides a way for the tracing parent to distinguish
547 between a syscall stop and SIGTRAP delivery */
548 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
549 0x80 : 0));
550
551 /*
552 * this isn't the same as continuing with a signal, but it will do
553 * for normal use. strace only continues with a signal if the
554 * stopping signal is not SIGTRAP. -brl
555 */
556 if (current->exit_code) {
557 send_sig(current->exit_code, current, 1);
558 current->exit_code = 0;
559 }
560
561out:
562 audit_syscall_entry(audit_arch(), regs->regs[2],
563 regs->regs[4], regs->regs[5],
564 regs->regs[6], regs->regs[7]);
565}
566
567/*
568 * Notification of system call entry/exit
569 * - triggered by current->work.syscall_trace
570 */
571asmlinkage void syscall_trace_leave(struct pt_regs *regs)
572{
573 audit_syscall_exit(regs);
574
575 if (!(current->ptrace & PT_PTRACED))
576 return;
577
578 if (!test_thread_flag(TIF_SYSCALL_TRACE))
579 return;
580
581 /* The 0x80 provides a way for the tracing parent to distinguish
582 between a syscall stop and SIGTRAP delivery */
583 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
584 0x80 : 0));
585
586 /*
587 * this isn't the same as continuing with a signal, but it will do
588 * for normal use. strace only continues with a signal if the
589 * stopping signal is not SIGTRAP. -brl
590 */
591 if (current->exit_code) {
592 send_sig(current->exit_code, current, 1);
593 current->exit_code = 0;
594 }
595}
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Ross Biro
7 * Copyright (C) Linus Torvalds
8 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
9 * Copyright (C) 1996 David S. Miller
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 1999 MIPS Technologies, Inc.
12 * Copyright (C) 2000 Ulf Carlsson
13 *
14 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
15 * binaries.
16 */
17#include <linux/compiler.h>
18#include <linux/context_tracking.h>
19#include <linux/elf.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/mm.h>
23#include <linux/errno.h>
24#include <linux/ptrace.h>
25#include <linux/regset.h>
26#include <linux/smp.h>
27#include <linux/security.h>
28#include <linux/stddef.h>
29#include <linux/tracehook.h>
30#include <linux/audit.h>
31#include <linux/seccomp.h>
32#include <linux/ftrace.h>
33
34#include <asm/byteorder.h>
35#include <asm/cpu.h>
36#include <asm/cpu-info.h>
37#include <asm/dsp.h>
38#include <asm/fpu.h>
39#include <asm/mipsregs.h>
40#include <asm/mipsmtregs.h>
41#include <asm/pgtable.h>
42#include <asm/page.h>
43#include <asm/syscall.h>
44#include <linux/uaccess.h>
45#include <asm/bootinfo.h>
46#include <asm/reg.h>
47
48#define CREATE_TRACE_POINTS
49#include <trace/events/syscalls.h>
50
51static void init_fp_ctx(struct task_struct *target)
52{
53 /* If FP has been used then the target already has context */
54 if (tsk_used_math(target))
55 return;
56
57 /* Begin with data registers set to all 1s... */
58 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
59
60 /* FCSR has been preset by `mips_set_personality_nan'. */
61
62 /*
63 * Record that the target has "used" math, such that the context
64 * just initialised, and any modifications made by the caller,
65 * aren't discarded.
66 */
67 set_stopped_child_used_math(target);
68}
69
70/*
71 * Called by kernel/ptrace.c when detaching..
72 *
73 * Make sure single step bits etc are not set.
74 */
75void ptrace_disable(struct task_struct *child)
76{
77 /* Don't load the watchpoint registers for the ex-child. */
78 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
79}
80
81/*
82 * Poke at FCSR according to its mask. Set the Cause bits even
83 * if a corresponding Enable bit is set. This will be noticed at
84 * the time the thread is switched to and SIGFPE thrown accordingly.
85 */
86static void ptrace_setfcr31(struct task_struct *child, u32 value)
87{
88 u32 fcr31;
89 u32 mask;
90
91 fcr31 = child->thread.fpu.fcr31;
92 mask = boot_cpu_data.fpu_msk31;
93 child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
94}
95
96/*
97 * Read a general register set. We always use the 64-bit format, even
98 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
99 * Registers are sign extended to fill the available space.
100 */
101int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data)
102{
103 struct pt_regs *regs;
104 int i;
105
106 if (!access_ok(VERIFY_WRITE, data, 38 * 8))
107 return -EIO;
108
109 regs = task_pt_regs(child);
110
111 for (i = 0; i < 32; i++)
112 __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]);
113 __put_user((long)regs->lo, (__s64 __user *)&data->lo);
114 __put_user((long)regs->hi, (__s64 __user *)&data->hi);
115 __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
116 __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr);
117 __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status);
118 __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause);
119
120 return 0;
121}
122
123/*
124 * Write a general register set. As for PTRACE_GETREGS, we always use
125 * the 64-bit format. On a 32-bit kernel only the lower order half
126 * (according to endianness) will be used.
127 */
128int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
129{
130 struct pt_regs *regs;
131 int i;
132
133 if (!access_ok(VERIFY_READ, data, 38 * 8))
134 return -EIO;
135
136 regs = task_pt_regs(child);
137
138 for (i = 0; i < 32; i++)
139 __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]);
140 __get_user(regs->lo, (__s64 __user *)&data->lo);
141 __get_user(regs->hi, (__s64 __user *)&data->hi);
142 __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc);
143
144 /* badvaddr, status, and cause may not be written. */
145
146 return 0;
147}
148
149int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
150{
151 int i;
152
153 if (!access_ok(VERIFY_WRITE, data, 33 * 8))
154 return -EIO;
155
156 if (tsk_used_math(child)) {
157 union fpureg *fregs = get_fpu_regs(child);
158 for (i = 0; i < 32; i++)
159 __put_user(get_fpr64(&fregs[i], 0),
160 i + (__u64 __user *)data);
161 } else {
162 for (i = 0; i < 32; i++)
163 __put_user((__u64) -1, i + (__u64 __user *) data);
164 }
165
166 __put_user(child->thread.fpu.fcr31, data + 64);
167 __put_user(boot_cpu_data.fpu_id, data + 65);
168
169 return 0;
170}
171
172int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
173{
174 union fpureg *fregs;
175 u64 fpr_val;
176 u32 value;
177 int i;
178
179 if (!access_ok(VERIFY_READ, data, 33 * 8))
180 return -EIO;
181
182 init_fp_ctx(child);
183 fregs = get_fpu_regs(child);
184
185 for (i = 0; i < 32; i++) {
186 __get_user(fpr_val, i + (__u64 __user *)data);
187 set_fpr64(&fregs[i], 0, fpr_val);
188 }
189
190 __get_user(value, data + 64);
191 ptrace_setfcr31(child, value);
192
193 /* FIR may not be written. */
194
195 return 0;
196}
197
198int ptrace_get_watch_regs(struct task_struct *child,
199 struct pt_watch_regs __user *addr)
200{
201 enum pt_watch_style style;
202 int i;
203
204 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
205 return -EIO;
206 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
207 return -EIO;
208
209#ifdef CONFIG_32BIT
210 style = pt_watch_style_mips32;
211#define WATCH_STYLE mips32
212#else
213 style = pt_watch_style_mips64;
214#define WATCH_STYLE mips64
215#endif
216
217 __put_user(style, &addr->style);
218 __put_user(boot_cpu_data.watch_reg_use_cnt,
219 &addr->WATCH_STYLE.num_valid);
220 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
221 __put_user(child->thread.watch.mips3264.watchlo[i],
222 &addr->WATCH_STYLE.watchlo[i]);
223 __put_user(child->thread.watch.mips3264.watchhi[i] &
224 (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW),
225 &addr->WATCH_STYLE.watchhi[i]);
226 __put_user(boot_cpu_data.watch_reg_masks[i],
227 &addr->WATCH_STYLE.watch_masks[i]);
228 }
229 for (; i < 8; i++) {
230 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
231 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
232 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
233 }
234
235 return 0;
236}
237
238int ptrace_set_watch_regs(struct task_struct *child,
239 struct pt_watch_regs __user *addr)
240{
241 int i;
242 int watch_active = 0;
243 unsigned long lt[NUM_WATCH_REGS];
244 u16 ht[NUM_WATCH_REGS];
245
246 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
247 return -EIO;
248 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
249 return -EIO;
250 /* Check the values. */
251 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
252 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
253#ifdef CONFIG_32BIT
254 if (lt[i] & __UA_LIMIT)
255 return -EINVAL;
256#else
257 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
258 if (lt[i] & 0xffffffff80000000UL)
259 return -EINVAL;
260 } else {
261 if (lt[i] & __UA_LIMIT)
262 return -EINVAL;
263 }
264#endif
265 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
266 if (ht[i] & ~MIPS_WATCHHI_MASK)
267 return -EINVAL;
268 }
269 /* Install them. */
270 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
271 if (lt[i] & MIPS_WATCHLO_IRW)
272 watch_active = 1;
273 child->thread.watch.mips3264.watchlo[i] = lt[i];
274 /* Set the G bit. */
275 child->thread.watch.mips3264.watchhi[i] = ht[i];
276 }
277
278 if (watch_active)
279 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
280 else
281 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
282
283 return 0;
284}
285
286/* regset get/set implementations */
287
288#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
289
290static int gpr32_get(struct task_struct *target,
291 const struct user_regset *regset,
292 unsigned int pos, unsigned int count,
293 void *kbuf, void __user *ubuf)
294{
295 struct pt_regs *regs = task_pt_regs(target);
296 u32 uregs[ELF_NGREG] = {};
297 unsigned i;
298
299 for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
300 /* k0/k1 are copied as zero. */
301 if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
302 continue;
303
304 uregs[i] = regs->regs[i - MIPS32_EF_R0];
305 }
306
307 uregs[MIPS32_EF_LO] = regs->lo;
308 uregs[MIPS32_EF_HI] = regs->hi;
309 uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
310 uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
311 uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
312 uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
313
314 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
315 sizeof(uregs));
316}
317
318static int gpr32_set(struct task_struct *target,
319 const struct user_regset *regset,
320 unsigned int pos, unsigned int count,
321 const void *kbuf, const void __user *ubuf)
322{
323 struct pt_regs *regs = task_pt_regs(target);
324 u32 uregs[ELF_NGREG];
325 unsigned start, num_regs, i;
326 int err;
327
328 start = pos / sizeof(u32);
329 num_regs = count / sizeof(u32);
330
331 if (start + num_regs > ELF_NGREG)
332 return -EIO;
333
334 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
335 sizeof(uregs));
336 if (err)
337 return err;
338
339 for (i = start; i < num_regs; i++) {
340 /*
341 * Cast all values to signed here so that if this is a 64-bit
342 * kernel, the supplied 32-bit values will be sign extended.
343 */
344 switch (i) {
345 case MIPS32_EF_R1 ... MIPS32_EF_R25:
346 /* k0/k1 are ignored. */
347 case MIPS32_EF_R28 ... MIPS32_EF_R31:
348 regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i];
349 break;
350 case MIPS32_EF_LO:
351 regs->lo = (s32)uregs[i];
352 break;
353 case MIPS32_EF_HI:
354 regs->hi = (s32)uregs[i];
355 break;
356 case MIPS32_EF_CP0_EPC:
357 regs->cp0_epc = (s32)uregs[i];
358 break;
359 }
360 }
361
362 return 0;
363}
364
365#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
366
367#ifdef CONFIG_64BIT
368
369static int gpr64_get(struct task_struct *target,
370 const struct user_regset *regset,
371 unsigned int pos, unsigned int count,
372 void *kbuf, void __user *ubuf)
373{
374 struct pt_regs *regs = task_pt_regs(target);
375 u64 uregs[ELF_NGREG] = {};
376 unsigned i;
377
378 for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
379 /* k0/k1 are copied as zero. */
380 if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
381 continue;
382
383 uregs[i] = regs->regs[i - MIPS64_EF_R0];
384 }
385
386 uregs[MIPS64_EF_LO] = regs->lo;
387 uregs[MIPS64_EF_HI] = regs->hi;
388 uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
389 uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
390 uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
391 uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
392
393 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
394 sizeof(uregs));
395}
396
397static int gpr64_set(struct task_struct *target,
398 const struct user_regset *regset,
399 unsigned int pos, unsigned int count,
400 const void *kbuf, const void __user *ubuf)
401{
402 struct pt_regs *regs = task_pt_regs(target);
403 u64 uregs[ELF_NGREG];
404 unsigned start, num_regs, i;
405 int err;
406
407 start = pos / sizeof(u64);
408 num_regs = count / sizeof(u64);
409
410 if (start + num_regs > ELF_NGREG)
411 return -EIO;
412
413 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0,
414 sizeof(uregs));
415 if (err)
416 return err;
417
418 for (i = start; i < num_regs; i++) {
419 switch (i) {
420 case MIPS64_EF_R1 ... MIPS64_EF_R25:
421 /* k0/k1 are ignored. */
422 case MIPS64_EF_R28 ... MIPS64_EF_R31:
423 regs->regs[i - MIPS64_EF_R0] = uregs[i];
424 break;
425 case MIPS64_EF_LO:
426 regs->lo = uregs[i];
427 break;
428 case MIPS64_EF_HI:
429 regs->hi = uregs[i];
430 break;
431 case MIPS64_EF_CP0_EPC:
432 regs->cp0_epc = uregs[i];
433 break;
434 }
435 }
436
437 return 0;
438}
439
440#endif /* CONFIG_64BIT */
441
442static int fpr_get(struct task_struct *target,
443 const struct user_regset *regset,
444 unsigned int pos, unsigned int count,
445 void *kbuf, void __user *ubuf)
446{
447 unsigned i;
448 int err;
449 u64 fpr_val;
450
451 /* XXX fcr31 */
452
453 if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
454 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
455 &target->thread.fpu,
456 0, sizeof(elf_fpregset_t));
457
458 for (i = 0; i < NUM_FPU_REGS; i++) {
459 fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0);
460 err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
461 &fpr_val, i * sizeof(elf_fpreg_t),
462 (i + 1) * sizeof(elf_fpreg_t));
463 if (err)
464 return err;
465 }
466
467 return 0;
468}
469
470static int fpr_set(struct task_struct *target,
471 const struct user_regset *regset,
472 unsigned int pos, unsigned int count,
473 const void *kbuf, const void __user *ubuf)
474{
475 unsigned i;
476 int err;
477 u64 fpr_val;
478
479 /* XXX fcr31 */
480
481 init_fp_ctx(target);
482
483 if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t))
484 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
485 &target->thread.fpu,
486 0, sizeof(elf_fpregset_t));
487
488 BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t));
489 for (i = 0; i < NUM_FPU_REGS && count >= sizeof(elf_fpreg_t); i++) {
490 err = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
491 &fpr_val, i * sizeof(elf_fpreg_t),
492 (i + 1) * sizeof(elf_fpreg_t));
493 if (err)
494 return err;
495 set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val);
496 }
497
498 return 0;
499}
500
501enum mips_regset {
502 REGSET_GPR,
503 REGSET_FPR,
504};
505
506struct pt_regs_offset {
507 const char *name;
508 int offset;
509};
510
511#define REG_OFFSET_NAME(reg, r) { \
512 .name = #reg, \
513 .offset = offsetof(struct pt_regs, r) \
514}
515
516#define REG_OFFSET_END { \
517 .name = NULL, \
518 .offset = 0 \
519}
520
521static const struct pt_regs_offset regoffset_table[] = {
522 REG_OFFSET_NAME(r0, regs[0]),
523 REG_OFFSET_NAME(r1, regs[1]),
524 REG_OFFSET_NAME(r2, regs[2]),
525 REG_OFFSET_NAME(r3, regs[3]),
526 REG_OFFSET_NAME(r4, regs[4]),
527 REG_OFFSET_NAME(r5, regs[5]),
528 REG_OFFSET_NAME(r6, regs[6]),
529 REG_OFFSET_NAME(r7, regs[7]),
530 REG_OFFSET_NAME(r8, regs[8]),
531 REG_OFFSET_NAME(r9, regs[9]),
532 REG_OFFSET_NAME(r10, regs[10]),
533 REG_OFFSET_NAME(r11, regs[11]),
534 REG_OFFSET_NAME(r12, regs[12]),
535 REG_OFFSET_NAME(r13, regs[13]),
536 REG_OFFSET_NAME(r14, regs[14]),
537 REG_OFFSET_NAME(r15, regs[15]),
538 REG_OFFSET_NAME(r16, regs[16]),
539 REG_OFFSET_NAME(r17, regs[17]),
540 REG_OFFSET_NAME(r18, regs[18]),
541 REG_OFFSET_NAME(r19, regs[19]),
542 REG_OFFSET_NAME(r20, regs[20]),
543 REG_OFFSET_NAME(r21, regs[21]),
544 REG_OFFSET_NAME(r22, regs[22]),
545 REG_OFFSET_NAME(r23, regs[23]),
546 REG_OFFSET_NAME(r24, regs[24]),
547 REG_OFFSET_NAME(r25, regs[25]),
548 REG_OFFSET_NAME(r26, regs[26]),
549 REG_OFFSET_NAME(r27, regs[27]),
550 REG_OFFSET_NAME(r28, regs[28]),
551 REG_OFFSET_NAME(r29, regs[29]),
552 REG_OFFSET_NAME(r30, regs[30]),
553 REG_OFFSET_NAME(r31, regs[31]),
554 REG_OFFSET_NAME(c0_status, cp0_status),
555 REG_OFFSET_NAME(hi, hi),
556 REG_OFFSET_NAME(lo, lo),
557#ifdef CONFIG_CPU_HAS_SMARTMIPS
558 REG_OFFSET_NAME(acx, acx),
559#endif
560 REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr),
561 REG_OFFSET_NAME(c0_cause, cp0_cause),
562 REG_OFFSET_NAME(c0_epc, cp0_epc),
563#ifdef CONFIG_CPU_CAVIUM_OCTEON
564 REG_OFFSET_NAME(mpl0, mpl[0]),
565 REG_OFFSET_NAME(mpl1, mpl[1]),
566 REG_OFFSET_NAME(mpl2, mpl[2]),
567 REG_OFFSET_NAME(mtp0, mtp[0]),
568 REG_OFFSET_NAME(mtp1, mtp[1]),
569 REG_OFFSET_NAME(mtp2, mtp[2]),
570#endif
571 REG_OFFSET_END,
572};
573
574/**
575 * regs_query_register_offset() - query register offset from its name
576 * @name: the name of a register
577 *
578 * regs_query_register_offset() returns the offset of a register in struct
579 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
580 */
581int regs_query_register_offset(const char *name)
582{
583 const struct pt_regs_offset *roff;
584 for (roff = regoffset_table; roff->name != NULL; roff++)
585 if (!strcmp(roff->name, name))
586 return roff->offset;
587 return -EINVAL;
588}
589
590#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
591
592static const struct user_regset mips_regsets[] = {
593 [REGSET_GPR] = {
594 .core_note_type = NT_PRSTATUS,
595 .n = ELF_NGREG,
596 .size = sizeof(unsigned int),
597 .align = sizeof(unsigned int),
598 .get = gpr32_get,
599 .set = gpr32_set,
600 },
601 [REGSET_FPR] = {
602 .core_note_type = NT_PRFPREG,
603 .n = ELF_NFPREG,
604 .size = sizeof(elf_fpreg_t),
605 .align = sizeof(elf_fpreg_t),
606 .get = fpr_get,
607 .set = fpr_set,
608 },
609};
610
611static const struct user_regset_view user_mips_view = {
612 .name = "mips",
613 .e_machine = ELF_ARCH,
614 .ei_osabi = ELF_OSABI,
615 .regsets = mips_regsets,
616 .n = ARRAY_SIZE(mips_regsets),
617};
618
619#endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
620
621#ifdef CONFIG_64BIT
622
623static const struct user_regset mips64_regsets[] = {
624 [REGSET_GPR] = {
625 .core_note_type = NT_PRSTATUS,
626 .n = ELF_NGREG,
627 .size = sizeof(unsigned long),
628 .align = sizeof(unsigned long),
629 .get = gpr64_get,
630 .set = gpr64_set,
631 },
632 [REGSET_FPR] = {
633 .core_note_type = NT_PRFPREG,
634 .n = ELF_NFPREG,
635 .size = sizeof(elf_fpreg_t),
636 .align = sizeof(elf_fpreg_t),
637 .get = fpr_get,
638 .set = fpr_set,
639 },
640};
641
642static const struct user_regset_view user_mips64_view = {
643 .name = "mips64",
644 .e_machine = ELF_ARCH,
645 .ei_osabi = ELF_OSABI,
646 .regsets = mips64_regsets,
647 .n = ARRAY_SIZE(mips64_regsets),
648};
649
650#endif /* CONFIG_64BIT */
651
652const struct user_regset_view *task_user_regset_view(struct task_struct *task)
653{
654#ifdef CONFIG_32BIT
655 return &user_mips_view;
656#else
657#ifdef CONFIG_MIPS32_O32
658 if (test_tsk_thread_flag(task, TIF_32BIT_REGS))
659 return &user_mips_view;
660#endif
661 return &user_mips64_view;
662#endif
663}
664
665long arch_ptrace(struct task_struct *child, long request,
666 unsigned long addr, unsigned long data)
667{
668 int ret;
669 void __user *addrp = (void __user *) addr;
670 void __user *datavp = (void __user *) data;
671 unsigned long __user *datalp = (void __user *) data;
672
673 switch (request) {
674 /* when I and D space are separate, these will need to be fixed. */
675 case PTRACE_PEEKTEXT: /* read word at location addr. */
676 case PTRACE_PEEKDATA:
677 ret = generic_ptrace_peekdata(child, addr, data);
678 break;
679
680 /* Read the word at location addr in the USER area. */
681 case PTRACE_PEEKUSR: {
682 struct pt_regs *regs;
683 union fpureg *fregs;
684 unsigned long tmp = 0;
685
686 regs = task_pt_regs(child);
687 ret = 0; /* Default return value. */
688
689 switch (addr) {
690 case 0 ... 31:
691 tmp = regs->regs[addr];
692 break;
693 case FPR_BASE ... FPR_BASE + 31:
694 if (!tsk_used_math(child)) {
695 /* FP not yet used */
696 tmp = -1;
697 break;
698 }
699 fregs = get_fpu_regs(child);
700
701#ifdef CONFIG_32BIT
702 if (test_thread_flag(TIF_32BIT_FPREGS)) {
703 /*
704 * The odd registers are actually the high
705 * order bits of the values stored in the even
706 * registers - unless we're using r2k_switch.S.
707 */
708 tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
709 addr & 1);
710 break;
711 }
712#endif
713 tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
714 break;
715 case PC:
716 tmp = regs->cp0_epc;
717 break;
718 case CAUSE:
719 tmp = regs->cp0_cause;
720 break;
721 case BADVADDR:
722 tmp = regs->cp0_badvaddr;
723 break;
724 case MMHI:
725 tmp = regs->hi;
726 break;
727 case MMLO:
728 tmp = regs->lo;
729 break;
730#ifdef CONFIG_CPU_HAS_SMARTMIPS
731 case ACX:
732 tmp = regs->acx;
733 break;
734#endif
735 case FPC_CSR:
736 tmp = child->thread.fpu.fcr31;
737 break;
738 case FPC_EIR:
739 /* implementation / version register */
740 tmp = boot_cpu_data.fpu_id;
741 break;
742 case DSP_BASE ... DSP_BASE + 5: {
743 dspreg_t *dregs;
744
745 if (!cpu_has_dsp) {
746 tmp = 0;
747 ret = -EIO;
748 goto out;
749 }
750 dregs = __get_dsp_regs(child);
751 tmp = (unsigned long) (dregs[addr - DSP_BASE]);
752 break;
753 }
754 case DSP_CONTROL:
755 if (!cpu_has_dsp) {
756 tmp = 0;
757 ret = -EIO;
758 goto out;
759 }
760 tmp = child->thread.dsp.dspcontrol;
761 break;
762 default:
763 tmp = 0;
764 ret = -EIO;
765 goto out;
766 }
767 ret = put_user(tmp, datalp);
768 break;
769 }
770
771 /* when I and D space are separate, this will have to be fixed. */
772 case PTRACE_POKETEXT: /* write the word at location addr. */
773 case PTRACE_POKEDATA:
774 ret = generic_ptrace_pokedata(child, addr, data);
775 break;
776
777 case PTRACE_POKEUSR: {
778 struct pt_regs *regs;
779 ret = 0;
780 regs = task_pt_regs(child);
781
782 switch (addr) {
783 case 0 ... 31:
784 regs->regs[addr] = data;
785 break;
786 case FPR_BASE ... FPR_BASE + 31: {
787 union fpureg *fregs = get_fpu_regs(child);
788
789 init_fp_ctx(child);
790#ifdef CONFIG_32BIT
791 if (test_thread_flag(TIF_32BIT_FPREGS)) {
792 /*
793 * The odd registers are actually the high
794 * order bits of the values stored in the even
795 * registers - unless we're using r2k_switch.S.
796 */
797 set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
798 addr & 1, data);
799 break;
800 }
801#endif
802 set_fpr64(&fregs[addr - FPR_BASE], 0, data);
803 break;
804 }
805 case PC:
806 regs->cp0_epc = data;
807 break;
808 case MMHI:
809 regs->hi = data;
810 break;
811 case MMLO:
812 regs->lo = data;
813 break;
814#ifdef CONFIG_CPU_HAS_SMARTMIPS
815 case ACX:
816 regs->acx = data;
817 break;
818#endif
819 case FPC_CSR:
820 init_fp_ctx(child);
821 ptrace_setfcr31(child, data);
822 break;
823 case DSP_BASE ... DSP_BASE + 5: {
824 dspreg_t *dregs;
825
826 if (!cpu_has_dsp) {
827 ret = -EIO;
828 break;
829 }
830
831 dregs = __get_dsp_regs(child);
832 dregs[addr - DSP_BASE] = data;
833 break;
834 }
835 case DSP_CONTROL:
836 if (!cpu_has_dsp) {
837 ret = -EIO;
838 break;
839 }
840 child->thread.dsp.dspcontrol = data;
841 break;
842 default:
843 /* The rest are not allowed. */
844 ret = -EIO;
845 break;
846 }
847 break;
848 }
849
850 case PTRACE_GETREGS:
851 ret = ptrace_getregs(child, datavp);
852 break;
853
854 case PTRACE_SETREGS:
855 ret = ptrace_setregs(child, datavp);
856 break;
857
858 case PTRACE_GETFPREGS:
859 ret = ptrace_getfpregs(child, datavp);
860 break;
861
862 case PTRACE_SETFPREGS:
863 ret = ptrace_setfpregs(child, datavp);
864 break;
865
866 case PTRACE_GET_THREAD_AREA:
867 ret = put_user(task_thread_info(child)->tp_value, datalp);
868 break;
869
870 case PTRACE_GET_WATCH_REGS:
871 ret = ptrace_get_watch_regs(child, addrp);
872 break;
873
874 case PTRACE_SET_WATCH_REGS:
875 ret = ptrace_set_watch_regs(child, addrp);
876 break;
877
878 default:
879 ret = ptrace_request(child, request, addr, data);
880 break;
881 }
882 out:
883 return ret;
884}
885
886/*
887 * Notification of system call entry/exit
888 * - triggered by current->work.syscall_trace
889 */
890asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall)
891{
892 user_exit();
893
894 current_thread_info()->syscall = syscall;
895
896 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
897 tracehook_report_syscall_entry(regs))
898 return -1;
899
900 if (secure_computing(NULL) == -1)
901 return -1;
902
903 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
904 trace_sys_enter(regs, regs->regs[2]);
905
906 audit_syscall_entry(syscall, regs->regs[4], regs->regs[5],
907 regs->regs[6], regs->regs[7]);
908 return syscall;
909}
910
911/*
912 * Notification of system call entry/exit
913 * - triggered by current->work.syscall_trace
914 */
915asmlinkage void syscall_trace_leave(struct pt_regs *regs)
916{
917 /*
918 * We may come here right after calling schedule_user()
919 * or do_notify_resume(), in which case we can be in RCU
920 * user mode.
921 */
922 user_exit();
923
924 audit_syscall_exit(regs);
925
926 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
927 trace_sys_exit(regs, regs->regs[2]);
928
929 if (test_thread_flag(TIF_SYSCALL_TRACE))
930 tracehook_report_syscall_exit(regs, 0);
931
932 user_enter();
933}