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1/*
2 * Register map access API - MMIO support
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25
26struct regmap_mmio_context {
27 void __iomem *regs;
28 unsigned reg_bytes;
29 unsigned val_bytes;
30 unsigned pad_bytes;
31 struct clk *clk;
32};
33
34static inline void regmap_mmio_regsize_check(size_t reg_size)
35{
36 switch (reg_size) {
37 case 1:
38 case 2:
39 case 4:
40#ifdef CONFIG_64BIT
41 case 8:
42#endif
43 break;
44 default:
45 BUG();
46 }
47}
48
49static int regmap_mmio_regbits_check(size_t reg_bits)
50{
51 switch (reg_bits) {
52 case 8:
53 case 16:
54 case 32:
55#ifdef CONFIG_64BIT
56 case 64:
57#endif
58 return 0;
59 default:
60 return -EINVAL;
61 }
62}
63
64static inline void regmap_mmio_count_check(size_t count)
65{
66 BUG_ON(count % 2 != 0);
67}
68
69static int regmap_mmio_gather_write(void *context,
70 const void *reg, size_t reg_size,
71 const void *val, size_t val_size)
72{
73 struct regmap_mmio_context *ctx = context;
74 u32 offset;
75 int ret;
76
77 regmap_mmio_regsize_check(reg_size);
78
79 if (!IS_ERR(ctx->clk)) {
80 ret = clk_enable(ctx->clk);
81 if (ret < 0)
82 return ret;
83 }
84
85 offset = *(u32 *)reg;
86
87 while (val_size) {
88 switch (ctx->val_bytes) {
89 case 1:
90 writeb(*(u8 *)val, ctx->regs + offset);
91 break;
92 case 2:
93 writew(*(u16 *)val, ctx->regs + offset);
94 break;
95 case 4:
96 writel(*(u32 *)val, ctx->regs + offset);
97 break;
98#ifdef CONFIG_64BIT
99 case 8:
100 writeq(*(u64 *)val, ctx->regs + offset);
101 break;
102#endif
103 default:
104 /* Should be caught by regmap_mmio_check_config */
105 BUG();
106 }
107 val_size -= ctx->val_bytes;
108 val += ctx->val_bytes;
109 offset += ctx->val_bytes;
110 }
111
112 if (!IS_ERR(ctx->clk))
113 clk_disable(ctx->clk);
114
115 return 0;
116}
117
118static int regmap_mmio_write(void *context, const void *data, size_t count)
119{
120 struct regmap_mmio_context *ctx = context;
121 u32 offset = ctx->reg_bytes + ctx->pad_bytes;
122
123 regmap_mmio_count_check(count);
124
125 return regmap_mmio_gather_write(context, data, ctx->reg_bytes,
126 data + offset, count - offset);
127}
128
129static int regmap_mmio_read(void *context,
130 const void *reg, size_t reg_size,
131 void *val, size_t val_size)
132{
133 struct regmap_mmio_context *ctx = context;
134 u32 offset;
135 int ret;
136
137 regmap_mmio_regsize_check(reg_size);
138
139 if (!IS_ERR(ctx->clk)) {
140 ret = clk_enable(ctx->clk);
141 if (ret < 0)
142 return ret;
143 }
144
145 offset = *(u32 *)reg;
146
147 while (val_size) {
148 switch (ctx->val_bytes) {
149 case 1:
150 *(u8 *)val = readb(ctx->regs + offset);
151 break;
152 case 2:
153 *(u16 *)val = readw(ctx->regs + offset);
154 break;
155 case 4:
156 *(u32 *)val = readl(ctx->regs + offset);
157 break;
158#ifdef CONFIG_64BIT
159 case 8:
160 *(u64 *)val = readq(ctx->regs + offset);
161 break;
162#endif
163 default:
164 /* Should be caught by regmap_mmio_check_config */
165 BUG();
166 }
167 val_size -= ctx->val_bytes;
168 val += ctx->val_bytes;
169 offset += ctx->val_bytes;
170 }
171
172 if (!IS_ERR(ctx->clk))
173 clk_disable(ctx->clk);
174
175 return 0;
176}
177
178static void regmap_mmio_free_context(void *context)
179{
180 struct regmap_mmio_context *ctx = context;
181
182 if (!IS_ERR(ctx->clk)) {
183 clk_unprepare(ctx->clk);
184 clk_put(ctx->clk);
185 }
186 kfree(context);
187}
188
189static struct regmap_bus regmap_mmio = {
190 .fast_io = true,
191 .write = regmap_mmio_write,
192 .gather_write = regmap_mmio_gather_write,
193 .read = regmap_mmio_read,
194 .free_context = regmap_mmio_free_context,
195 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
196 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
197};
198
199static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
200 const char *clk_id,
201 void __iomem *regs,
202 const struct regmap_config *config)
203{
204 struct regmap_mmio_context *ctx;
205 int min_stride;
206 int ret;
207
208 ret = regmap_mmio_regbits_check(config->reg_bits);
209 if (ret)
210 return ERR_PTR(ret);
211
212 if (config->pad_bits)
213 return ERR_PTR(-EINVAL);
214
215 switch (config->val_bits) {
216 case 8:
217 /* The core treats 0 as 1 */
218 min_stride = 0;
219 break;
220 case 16:
221 min_stride = 2;
222 break;
223 case 32:
224 min_stride = 4;
225 break;
226#ifdef CONFIG_64BIT
227 case 64:
228 min_stride = 8;
229 break;
230#endif
231 break;
232 default:
233 return ERR_PTR(-EINVAL);
234 }
235
236 if (config->reg_stride < min_stride)
237 return ERR_PTR(-EINVAL);
238
239 switch (config->reg_format_endian) {
240 case REGMAP_ENDIAN_DEFAULT:
241 case REGMAP_ENDIAN_NATIVE:
242 break;
243 default:
244 return ERR_PTR(-EINVAL);
245 }
246
247 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
248 if (!ctx)
249 return ERR_PTR(-ENOMEM);
250
251 ctx->regs = regs;
252 ctx->val_bytes = config->val_bits / 8;
253 ctx->reg_bytes = config->reg_bits / 8;
254 ctx->pad_bytes = config->pad_bits / 8;
255 ctx->clk = ERR_PTR(-ENODEV);
256
257 if (clk_id == NULL)
258 return ctx;
259
260 ctx->clk = clk_get(dev, clk_id);
261 if (IS_ERR(ctx->clk)) {
262 ret = PTR_ERR(ctx->clk);
263 goto err_free;
264 }
265
266 ret = clk_prepare(ctx->clk);
267 if (ret < 0) {
268 clk_put(ctx->clk);
269 goto err_free;
270 }
271
272 return ctx;
273
274err_free:
275 kfree(ctx);
276
277 return ERR_PTR(ret);
278}
279
280/**
281 * regmap_init_mmio_clk(): Initialise register map with register clock
282 *
283 * @dev: Device that will be interacted with
284 * @clk_id: register clock consumer ID
285 * @regs: Pointer to memory-mapped IO region
286 * @config: Configuration for register map
287 *
288 * The return value will be an ERR_PTR() on error or a valid pointer to
289 * a struct regmap.
290 */
291struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
292 void __iomem *regs,
293 const struct regmap_config *config)
294{
295 struct regmap_mmio_context *ctx;
296
297 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
298 if (IS_ERR(ctx))
299 return ERR_CAST(ctx);
300
301 return regmap_init(dev, ®map_mmio, ctx, config);
302}
303EXPORT_SYMBOL_GPL(regmap_init_mmio_clk);
304
305/**
306 * devm_regmap_init_mmio_clk(): Initialise managed register map with clock
307 *
308 * @dev: Device that will be interacted with
309 * @clk_id: register clock consumer ID
310 * @regs: Pointer to memory-mapped IO region
311 * @config: Configuration for register map
312 *
313 * The return value will be an ERR_PTR() on error or a valid pointer
314 * to a struct regmap. The regmap will be automatically freed by the
315 * device management code.
316 */
317struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
318 void __iomem *regs,
319 const struct regmap_config *config)
320{
321 struct regmap_mmio_context *ctx;
322
323 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
324 if (IS_ERR(ctx))
325 return ERR_CAST(ctx);
326
327 return devm_regmap_init(dev, ®map_mmio, ctx, config);
328}
329EXPORT_SYMBOL_GPL(devm_regmap_init_mmio_clk);
330
331MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2//
3// Register map access API - MMIO support
4//
5// Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6
7#include <linux/clk.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include "internal.h"
15
16struct regmap_mmio_context {
17 void __iomem *regs;
18 unsigned val_bytes;
19
20 bool attached_clk;
21 struct clk *clk;
22
23 void (*reg_write)(struct regmap_mmio_context *ctx,
24 unsigned int reg, unsigned int val);
25 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
26 unsigned int reg);
27};
28
29static int regmap_mmio_regbits_check(size_t reg_bits)
30{
31 switch (reg_bits) {
32 case 8:
33 case 16:
34 case 32:
35#ifdef CONFIG_64BIT
36 case 64:
37#endif
38 return 0;
39 default:
40 return -EINVAL;
41 }
42}
43
44static int regmap_mmio_get_min_stride(size_t val_bits)
45{
46 int min_stride;
47
48 switch (val_bits) {
49 case 8:
50 /* The core treats 0 as 1 */
51 min_stride = 0;
52 return 0;
53 case 16:
54 min_stride = 2;
55 break;
56 case 32:
57 min_stride = 4;
58 break;
59#ifdef CONFIG_64BIT
60 case 64:
61 min_stride = 8;
62 break;
63#endif
64 default:
65 return -EINVAL;
66 }
67
68 return min_stride;
69}
70
71static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
72 unsigned int reg,
73 unsigned int val)
74{
75 writeb(val, ctx->regs + reg);
76}
77
78static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
79 unsigned int reg,
80 unsigned int val)
81{
82 writew(val, ctx->regs + reg);
83}
84
85static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
86 unsigned int reg,
87 unsigned int val)
88{
89 iowrite16be(val, ctx->regs + reg);
90}
91
92static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
93 unsigned int reg,
94 unsigned int val)
95{
96 writel(val, ctx->regs + reg);
97}
98
99static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
100 unsigned int reg,
101 unsigned int val)
102{
103 iowrite32be(val, ctx->regs + reg);
104}
105
106#ifdef CONFIG_64BIT
107static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
108 unsigned int reg,
109 unsigned int val)
110{
111 writeq(val, ctx->regs + reg);
112}
113#endif
114
115static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
116{
117 struct regmap_mmio_context *ctx = context;
118 int ret;
119
120 if (!IS_ERR(ctx->clk)) {
121 ret = clk_enable(ctx->clk);
122 if (ret < 0)
123 return ret;
124 }
125
126 ctx->reg_write(ctx, reg, val);
127
128 if (!IS_ERR(ctx->clk))
129 clk_disable(ctx->clk);
130
131 return 0;
132}
133
134static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
135 unsigned int reg)
136{
137 return readb(ctx->regs + reg);
138}
139
140static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
141 unsigned int reg)
142{
143 return readw(ctx->regs + reg);
144}
145
146static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
147 unsigned int reg)
148{
149 return ioread16be(ctx->regs + reg);
150}
151
152static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
153 unsigned int reg)
154{
155 return readl(ctx->regs + reg);
156}
157
158static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
159 unsigned int reg)
160{
161 return ioread32be(ctx->regs + reg);
162}
163
164#ifdef CONFIG_64BIT
165static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
166 unsigned int reg)
167{
168 return readq(ctx->regs + reg);
169}
170#endif
171
172static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
173{
174 struct regmap_mmio_context *ctx = context;
175 int ret;
176
177 if (!IS_ERR(ctx->clk)) {
178 ret = clk_enable(ctx->clk);
179 if (ret < 0)
180 return ret;
181 }
182
183 *val = ctx->reg_read(ctx, reg);
184
185 if (!IS_ERR(ctx->clk))
186 clk_disable(ctx->clk);
187
188 return 0;
189}
190
191static void regmap_mmio_free_context(void *context)
192{
193 struct regmap_mmio_context *ctx = context;
194
195 if (!IS_ERR(ctx->clk)) {
196 clk_unprepare(ctx->clk);
197 if (!ctx->attached_clk)
198 clk_put(ctx->clk);
199 }
200 kfree(context);
201}
202
203static const struct regmap_bus regmap_mmio = {
204 .fast_io = true,
205 .reg_write = regmap_mmio_write,
206 .reg_read = regmap_mmio_read,
207 .free_context = regmap_mmio_free_context,
208 .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
209};
210
211static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
212 const char *clk_id,
213 void __iomem *regs,
214 const struct regmap_config *config)
215{
216 struct regmap_mmio_context *ctx;
217 int min_stride;
218 int ret;
219
220 ret = regmap_mmio_regbits_check(config->reg_bits);
221 if (ret)
222 return ERR_PTR(ret);
223
224 if (config->pad_bits)
225 return ERR_PTR(-EINVAL);
226
227 min_stride = regmap_mmio_get_min_stride(config->val_bits);
228 if (min_stride < 0)
229 return ERR_PTR(min_stride);
230
231 if (config->reg_stride < min_stride)
232 return ERR_PTR(-EINVAL);
233
234 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
235 if (!ctx)
236 return ERR_PTR(-ENOMEM);
237
238 ctx->regs = regs;
239 ctx->val_bytes = config->val_bits / 8;
240 ctx->clk = ERR_PTR(-ENODEV);
241
242 switch (regmap_get_val_endian(dev, ®map_mmio, config)) {
243 case REGMAP_ENDIAN_DEFAULT:
244 case REGMAP_ENDIAN_LITTLE:
245#ifdef __LITTLE_ENDIAN
246 case REGMAP_ENDIAN_NATIVE:
247#endif
248 switch (config->val_bits) {
249 case 8:
250 ctx->reg_read = regmap_mmio_read8;
251 ctx->reg_write = regmap_mmio_write8;
252 break;
253 case 16:
254 ctx->reg_read = regmap_mmio_read16le;
255 ctx->reg_write = regmap_mmio_write16le;
256 break;
257 case 32:
258 ctx->reg_read = regmap_mmio_read32le;
259 ctx->reg_write = regmap_mmio_write32le;
260 break;
261#ifdef CONFIG_64BIT
262 case 64:
263 ctx->reg_read = regmap_mmio_read64le;
264 ctx->reg_write = regmap_mmio_write64le;
265 break;
266#endif
267 default:
268 ret = -EINVAL;
269 goto err_free;
270 }
271 break;
272 case REGMAP_ENDIAN_BIG:
273#ifdef __BIG_ENDIAN
274 case REGMAP_ENDIAN_NATIVE:
275#endif
276 switch (config->val_bits) {
277 case 8:
278 ctx->reg_read = regmap_mmio_read8;
279 ctx->reg_write = regmap_mmio_write8;
280 break;
281 case 16:
282 ctx->reg_read = regmap_mmio_read16be;
283 ctx->reg_write = regmap_mmio_write16be;
284 break;
285 case 32:
286 ctx->reg_read = regmap_mmio_read32be;
287 ctx->reg_write = regmap_mmio_write32be;
288 break;
289 default:
290 ret = -EINVAL;
291 goto err_free;
292 }
293 break;
294 default:
295 ret = -EINVAL;
296 goto err_free;
297 }
298
299 if (clk_id == NULL)
300 return ctx;
301
302 ctx->clk = clk_get(dev, clk_id);
303 if (IS_ERR(ctx->clk)) {
304 ret = PTR_ERR(ctx->clk);
305 goto err_free;
306 }
307
308 ret = clk_prepare(ctx->clk);
309 if (ret < 0) {
310 clk_put(ctx->clk);
311 goto err_free;
312 }
313
314 return ctx;
315
316err_free:
317 kfree(ctx);
318
319 return ERR_PTR(ret);
320}
321
322struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
323 void __iomem *regs,
324 const struct regmap_config *config,
325 struct lock_class_key *lock_key,
326 const char *lock_name)
327{
328 struct regmap_mmio_context *ctx;
329
330 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
331 if (IS_ERR(ctx))
332 return ERR_CAST(ctx);
333
334 return __regmap_init(dev, ®map_mmio, ctx, config,
335 lock_key, lock_name);
336}
337EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
338
339struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
340 const char *clk_id,
341 void __iomem *regs,
342 const struct regmap_config *config,
343 struct lock_class_key *lock_key,
344 const char *lock_name)
345{
346 struct regmap_mmio_context *ctx;
347
348 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
349 if (IS_ERR(ctx))
350 return ERR_CAST(ctx);
351
352 return __devm_regmap_init(dev, ®map_mmio, ctx, config,
353 lock_key, lock_name);
354}
355EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
356
357int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
358{
359 struct regmap_mmio_context *ctx = map->bus_context;
360
361 ctx->clk = clk;
362 ctx->attached_clk = true;
363
364 return clk_prepare(ctx->clk);
365}
366EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
367
368void regmap_mmio_detach_clk(struct regmap *map)
369{
370 struct regmap_mmio_context *ctx = map->bus_context;
371
372 clk_unprepare(ctx->clk);
373
374 ctx->attached_clk = false;
375 ctx->clk = NULL;
376}
377EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
378
379MODULE_LICENSE("GPL v2");