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1/*
2 * Register map access API - MMIO support
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25
26struct regmap_mmio_context {
27 void __iomem *regs;
28 unsigned reg_bytes;
29 unsigned val_bytes;
30 unsigned pad_bytes;
31 struct clk *clk;
32};
33
34static inline void regmap_mmio_regsize_check(size_t reg_size)
35{
36 switch (reg_size) {
37 case 1:
38 case 2:
39 case 4:
40#ifdef CONFIG_64BIT
41 case 8:
42#endif
43 break;
44 default:
45 BUG();
46 }
47}
48
49static int regmap_mmio_regbits_check(size_t reg_bits)
50{
51 switch (reg_bits) {
52 case 8:
53 case 16:
54 case 32:
55#ifdef CONFIG_64BIT
56 case 64:
57#endif
58 return 0;
59 default:
60 return -EINVAL;
61 }
62}
63
64static inline void regmap_mmio_count_check(size_t count)
65{
66 BUG_ON(count % 2 != 0);
67}
68
69static int regmap_mmio_gather_write(void *context,
70 const void *reg, size_t reg_size,
71 const void *val, size_t val_size)
72{
73 struct regmap_mmio_context *ctx = context;
74 u32 offset;
75 int ret;
76
77 regmap_mmio_regsize_check(reg_size);
78
79 if (!IS_ERR(ctx->clk)) {
80 ret = clk_enable(ctx->clk);
81 if (ret < 0)
82 return ret;
83 }
84
85 offset = *(u32 *)reg;
86
87 while (val_size) {
88 switch (ctx->val_bytes) {
89 case 1:
90 writeb(*(u8 *)val, ctx->regs + offset);
91 break;
92 case 2:
93 writew(*(u16 *)val, ctx->regs + offset);
94 break;
95 case 4:
96 writel(*(u32 *)val, ctx->regs + offset);
97 break;
98#ifdef CONFIG_64BIT
99 case 8:
100 writeq(*(u64 *)val, ctx->regs + offset);
101 break;
102#endif
103 default:
104 /* Should be caught by regmap_mmio_check_config */
105 BUG();
106 }
107 val_size -= ctx->val_bytes;
108 val += ctx->val_bytes;
109 offset += ctx->val_bytes;
110 }
111
112 if (!IS_ERR(ctx->clk))
113 clk_disable(ctx->clk);
114
115 return 0;
116}
117
118static int regmap_mmio_write(void *context, const void *data, size_t count)
119{
120 struct regmap_mmio_context *ctx = context;
121 u32 offset = ctx->reg_bytes + ctx->pad_bytes;
122
123 regmap_mmio_count_check(count);
124
125 return regmap_mmio_gather_write(context, data, ctx->reg_bytes,
126 data + offset, count - offset);
127}
128
129static int regmap_mmio_read(void *context,
130 const void *reg, size_t reg_size,
131 void *val, size_t val_size)
132{
133 struct regmap_mmio_context *ctx = context;
134 u32 offset;
135 int ret;
136
137 regmap_mmio_regsize_check(reg_size);
138
139 if (!IS_ERR(ctx->clk)) {
140 ret = clk_enable(ctx->clk);
141 if (ret < 0)
142 return ret;
143 }
144
145 offset = *(u32 *)reg;
146
147 while (val_size) {
148 switch (ctx->val_bytes) {
149 case 1:
150 *(u8 *)val = readb(ctx->regs + offset);
151 break;
152 case 2:
153 *(u16 *)val = readw(ctx->regs + offset);
154 break;
155 case 4:
156 *(u32 *)val = readl(ctx->regs + offset);
157 break;
158#ifdef CONFIG_64BIT
159 case 8:
160 *(u64 *)val = readq(ctx->regs + offset);
161 break;
162#endif
163 default:
164 /* Should be caught by regmap_mmio_check_config */
165 BUG();
166 }
167 val_size -= ctx->val_bytes;
168 val += ctx->val_bytes;
169 offset += ctx->val_bytes;
170 }
171
172 if (!IS_ERR(ctx->clk))
173 clk_disable(ctx->clk);
174
175 return 0;
176}
177
178static void regmap_mmio_free_context(void *context)
179{
180 struct regmap_mmio_context *ctx = context;
181
182 if (!IS_ERR(ctx->clk)) {
183 clk_unprepare(ctx->clk);
184 clk_put(ctx->clk);
185 }
186 kfree(context);
187}
188
189static struct regmap_bus regmap_mmio = {
190 .fast_io = true,
191 .write = regmap_mmio_write,
192 .gather_write = regmap_mmio_gather_write,
193 .read = regmap_mmio_read,
194 .free_context = regmap_mmio_free_context,
195 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
196 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
197};
198
199static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
200 const char *clk_id,
201 void __iomem *regs,
202 const struct regmap_config *config)
203{
204 struct regmap_mmio_context *ctx;
205 int min_stride;
206 int ret;
207
208 ret = regmap_mmio_regbits_check(config->reg_bits);
209 if (ret)
210 return ERR_PTR(ret);
211
212 if (config->pad_bits)
213 return ERR_PTR(-EINVAL);
214
215 switch (config->val_bits) {
216 case 8:
217 /* The core treats 0 as 1 */
218 min_stride = 0;
219 break;
220 case 16:
221 min_stride = 2;
222 break;
223 case 32:
224 min_stride = 4;
225 break;
226#ifdef CONFIG_64BIT
227 case 64:
228 min_stride = 8;
229 break;
230#endif
231 break;
232 default:
233 return ERR_PTR(-EINVAL);
234 }
235
236 if (config->reg_stride < min_stride)
237 return ERR_PTR(-EINVAL);
238
239 switch (config->reg_format_endian) {
240 case REGMAP_ENDIAN_DEFAULT:
241 case REGMAP_ENDIAN_NATIVE:
242 break;
243 default:
244 return ERR_PTR(-EINVAL);
245 }
246
247 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
248 if (!ctx)
249 return ERR_PTR(-ENOMEM);
250
251 ctx->regs = regs;
252 ctx->val_bytes = config->val_bits / 8;
253 ctx->reg_bytes = config->reg_bits / 8;
254 ctx->pad_bytes = config->pad_bits / 8;
255 ctx->clk = ERR_PTR(-ENODEV);
256
257 if (clk_id == NULL)
258 return ctx;
259
260 ctx->clk = clk_get(dev, clk_id);
261 if (IS_ERR(ctx->clk)) {
262 ret = PTR_ERR(ctx->clk);
263 goto err_free;
264 }
265
266 ret = clk_prepare(ctx->clk);
267 if (ret < 0) {
268 clk_put(ctx->clk);
269 goto err_free;
270 }
271
272 return ctx;
273
274err_free:
275 kfree(ctx);
276
277 return ERR_PTR(ret);
278}
279
280/**
281 * regmap_init_mmio_clk(): Initialise register map with register clock
282 *
283 * @dev: Device that will be interacted with
284 * @clk_id: register clock consumer ID
285 * @regs: Pointer to memory-mapped IO region
286 * @config: Configuration for register map
287 *
288 * The return value will be an ERR_PTR() on error or a valid pointer to
289 * a struct regmap.
290 */
291struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
292 void __iomem *regs,
293 const struct regmap_config *config)
294{
295 struct regmap_mmio_context *ctx;
296
297 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
298 if (IS_ERR(ctx))
299 return ERR_CAST(ctx);
300
301 return regmap_init(dev, ®map_mmio, ctx, config);
302}
303EXPORT_SYMBOL_GPL(regmap_init_mmio_clk);
304
305/**
306 * devm_regmap_init_mmio_clk(): Initialise managed register map with clock
307 *
308 * @dev: Device that will be interacted with
309 * @clk_id: register clock consumer ID
310 * @regs: Pointer to memory-mapped IO region
311 * @config: Configuration for register map
312 *
313 * The return value will be an ERR_PTR() on error or a valid pointer
314 * to a struct regmap. The regmap will be automatically freed by the
315 * device management code.
316 */
317struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
318 void __iomem *regs,
319 const struct regmap_config *config)
320{
321 struct regmap_mmio_context *ctx;
322
323 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
324 if (IS_ERR(ctx))
325 return ERR_CAST(ctx);
326
327 return devm_regmap_init(dev, ®map_mmio, ctx, config);
328}
329EXPORT_SYMBOL_GPL(devm_regmap_init_mmio_clk);
330
331MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2//
3// Register map access API - MMIO support
4//
5// Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6
7#include <linux/clk.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include "internal.h"
15
16struct regmap_mmio_context {
17 void __iomem *regs;
18 unsigned val_bytes;
19 bool relaxed_mmio;
20
21 bool attached_clk;
22 struct clk *clk;
23
24 void (*reg_write)(struct regmap_mmio_context *ctx,
25 unsigned int reg, unsigned int val);
26 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
27 unsigned int reg);
28};
29
30static int regmap_mmio_regbits_check(size_t reg_bits)
31{
32 switch (reg_bits) {
33 case 8:
34 case 16:
35 case 32:
36#ifdef CONFIG_64BIT
37 case 64:
38#endif
39 return 0;
40 default:
41 return -EINVAL;
42 }
43}
44
45static int regmap_mmio_get_min_stride(size_t val_bits)
46{
47 int min_stride;
48
49 switch (val_bits) {
50 case 8:
51 /* The core treats 0 as 1 */
52 min_stride = 0;
53 return 0;
54 case 16:
55 min_stride = 2;
56 break;
57 case 32:
58 min_stride = 4;
59 break;
60#ifdef CONFIG_64BIT
61 case 64:
62 min_stride = 8;
63 break;
64#endif
65 default:
66 return -EINVAL;
67 }
68
69 return min_stride;
70}
71
72static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
73 unsigned int reg,
74 unsigned int val)
75{
76 writeb(val, ctx->regs + reg);
77}
78
79static void regmap_mmio_write8_relaxed(struct regmap_mmio_context *ctx,
80 unsigned int reg,
81 unsigned int val)
82{
83 writeb_relaxed(val, ctx->regs + reg);
84}
85
86static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
87 unsigned int reg,
88 unsigned int val)
89{
90 writew(val, ctx->regs + reg);
91}
92
93static void regmap_mmio_write16le_relaxed(struct regmap_mmio_context *ctx,
94 unsigned int reg,
95 unsigned int val)
96{
97 writew_relaxed(val, ctx->regs + reg);
98}
99
100static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
101 unsigned int reg,
102 unsigned int val)
103{
104 iowrite16be(val, ctx->regs + reg);
105}
106
107static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
108 unsigned int reg,
109 unsigned int val)
110{
111 writel(val, ctx->regs + reg);
112}
113
114static void regmap_mmio_write32le_relaxed(struct regmap_mmio_context *ctx,
115 unsigned int reg,
116 unsigned int val)
117{
118 writel_relaxed(val, ctx->regs + reg);
119}
120
121static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
122 unsigned int reg,
123 unsigned int val)
124{
125 iowrite32be(val, ctx->regs + reg);
126}
127
128#ifdef CONFIG_64BIT
129static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
130 unsigned int reg,
131 unsigned int val)
132{
133 writeq(val, ctx->regs + reg);
134}
135
136static void regmap_mmio_write64le_relaxed(struct regmap_mmio_context *ctx,
137 unsigned int reg,
138 unsigned int val)
139{
140 writeq_relaxed(val, ctx->regs + reg);
141}
142#endif
143
144static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
145{
146 struct regmap_mmio_context *ctx = context;
147 int ret;
148
149 if (!IS_ERR(ctx->clk)) {
150 ret = clk_enable(ctx->clk);
151 if (ret < 0)
152 return ret;
153 }
154
155 ctx->reg_write(ctx, reg, val);
156
157 if (!IS_ERR(ctx->clk))
158 clk_disable(ctx->clk);
159
160 return 0;
161}
162
163static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
164 unsigned int reg)
165{
166 return readb(ctx->regs + reg);
167}
168
169static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx,
170 unsigned int reg)
171{
172 return readb_relaxed(ctx->regs + reg);
173}
174
175static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
176 unsigned int reg)
177{
178 return readw(ctx->regs + reg);
179}
180
181static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx,
182 unsigned int reg)
183{
184 return readw_relaxed(ctx->regs + reg);
185}
186
187static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
188 unsigned int reg)
189{
190 return ioread16be(ctx->regs + reg);
191}
192
193static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
194 unsigned int reg)
195{
196 return readl(ctx->regs + reg);
197}
198
199static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx,
200 unsigned int reg)
201{
202 return readl_relaxed(ctx->regs + reg);
203}
204
205static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
206 unsigned int reg)
207{
208 return ioread32be(ctx->regs + reg);
209}
210
211#ifdef CONFIG_64BIT
212static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
213 unsigned int reg)
214{
215 return readq(ctx->regs + reg);
216}
217
218static unsigned int regmap_mmio_read64le_relaxed(struct regmap_mmio_context *ctx,
219 unsigned int reg)
220{
221 return readq_relaxed(ctx->regs + reg);
222}
223#endif
224
225static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
226{
227 struct regmap_mmio_context *ctx = context;
228 int ret;
229
230 if (!IS_ERR(ctx->clk)) {
231 ret = clk_enable(ctx->clk);
232 if (ret < 0)
233 return ret;
234 }
235
236 *val = ctx->reg_read(ctx, reg);
237
238 if (!IS_ERR(ctx->clk))
239 clk_disable(ctx->clk);
240
241 return 0;
242}
243
244static void regmap_mmio_free_context(void *context)
245{
246 struct regmap_mmio_context *ctx = context;
247
248 if (!IS_ERR(ctx->clk)) {
249 clk_unprepare(ctx->clk);
250 if (!ctx->attached_clk)
251 clk_put(ctx->clk);
252 }
253 kfree(context);
254}
255
256static const struct regmap_bus regmap_mmio = {
257 .fast_io = true,
258 .reg_write = regmap_mmio_write,
259 .reg_read = regmap_mmio_read,
260 .free_context = regmap_mmio_free_context,
261 .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
262};
263
264static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
265 const char *clk_id,
266 void __iomem *regs,
267 const struct regmap_config *config)
268{
269 struct regmap_mmio_context *ctx;
270 int min_stride;
271 int ret;
272
273 ret = regmap_mmio_regbits_check(config->reg_bits);
274 if (ret)
275 return ERR_PTR(ret);
276
277 if (config->pad_bits)
278 return ERR_PTR(-EINVAL);
279
280 min_stride = regmap_mmio_get_min_stride(config->val_bits);
281 if (min_stride < 0)
282 return ERR_PTR(min_stride);
283
284 if (config->reg_stride < min_stride)
285 return ERR_PTR(-EINVAL);
286
287 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
288 if (!ctx)
289 return ERR_PTR(-ENOMEM);
290
291 ctx->regs = regs;
292 ctx->val_bytes = config->val_bits / 8;
293 ctx->relaxed_mmio = config->use_relaxed_mmio;
294 ctx->clk = ERR_PTR(-ENODEV);
295
296 switch (regmap_get_val_endian(dev, ®map_mmio, config)) {
297 case REGMAP_ENDIAN_DEFAULT:
298 case REGMAP_ENDIAN_LITTLE:
299#ifdef __LITTLE_ENDIAN
300 case REGMAP_ENDIAN_NATIVE:
301#endif
302 switch (config->val_bits) {
303 case 8:
304 if (ctx->relaxed_mmio) {
305 ctx->reg_read = regmap_mmio_read8_relaxed;
306 ctx->reg_write = regmap_mmio_write8_relaxed;
307 } else {
308 ctx->reg_read = regmap_mmio_read8;
309 ctx->reg_write = regmap_mmio_write8;
310 }
311 break;
312 case 16:
313 if (ctx->relaxed_mmio) {
314 ctx->reg_read = regmap_mmio_read16le_relaxed;
315 ctx->reg_write = regmap_mmio_write16le_relaxed;
316 } else {
317 ctx->reg_read = regmap_mmio_read16le;
318 ctx->reg_write = regmap_mmio_write16le;
319 }
320 break;
321 case 32:
322 if (ctx->relaxed_mmio) {
323 ctx->reg_read = regmap_mmio_read32le_relaxed;
324 ctx->reg_write = regmap_mmio_write32le_relaxed;
325 } else {
326 ctx->reg_read = regmap_mmio_read32le;
327 ctx->reg_write = regmap_mmio_write32le;
328 }
329 break;
330#ifdef CONFIG_64BIT
331 case 64:
332 if (ctx->relaxed_mmio) {
333 ctx->reg_read = regmap_mmio_read64le_relaxed;
334 ctx->reg_write = regmap_mmio_write64le_relaxed;
335 } else {
336 ctx->reg_read = regmap_mmio_read64le;
337 ctx->reg_write = regmap_mmio_write64le;
338 }
339 break;
340#endif
341 default:
342 ret = -EINVAL;
343 goto err_free;
344 }
345 break;
346 case REGMAP_ENDIAN_BIG:
347#ifdef __BIG_ENDIAN
348 case REGMAP_ENDIAN_NATIVE:
349#endif
350 switch (config->val_bits) {
351 case 8:
352 ctx->reg_read = regmap_mmio_read8;
353 ctx->reg_write = regmap_mmio_write8;
354 break;
355 case 16:
356 ctx->reg_read = regmap_mmio_read16be;
357 ctx->reg_write = regmap_mmio_write16be;
358 break;
359 case 32:
360 ctx->reg_read = regmap_mmio_read32be;
361 ctx->reg_write = regmap_mmio_write32be;
362 break;
363 default:
364 ret = -EINVAL;
365 goto err_free;
366 }
367 break;
368 default:
369 ret = -EINVAL;
370 goto err_free;
371 }
372
373 if (clk_id == NULL)
374 return ctx;
375
376 ctx->clk = clk_get(dev, clk_id);
377 if (IS_ERR(ctx->clk)) {
378 ret = PTR_ERR(ctx->clk);
379 goto err_free;
380 }
381
382 ret = clk_prepare(ctx->clk);
383 if (ret < 0) {
384 clk_put(ctx->clk);
385 goto err_free;
386 }
387
388 return ctx;
389
390err_free:
391 kfree(ctx);
392
393 return ERR_PTR(ret);
394}
395
396struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
397 void __iomem *regs,
398 const struct regmap_config *config,
399 struct lock_class_key *lock_key,
400 const char *lock_name)
401{
402 struct regmap_mmio_context *ctx;
403
404 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
405 if (IS_ERR(ctx))
406 return ERR_CAST(ctx);
407
408 return __regmap_init(dev, ®map_mmio, ctx, config,
409 lock_key, lock_name);
410}
411EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
412
413struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
414 const char *clk_id,
415 void __iomem *regs,
416 const struct regmap_config *config,
417 struct lock_class_key *lock_key,
418 const char *lock_name)
419{
420 struct regmap_mmio_context *ctx;
421
422 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
423 if (IS_ERR(ctx))
424 return ERR_CAST(ctx);
425
426 return __devm_regmap_init(dev, ®map_mmio, ctx, config,
427 lock_key, lock_name);
428}
429EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
430
431int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
432{
433 struct regmap_mmio_context *ctx = map->bus_context;
434
435 ctx->clk = clk;
436 ctx->attached_clk = true;
437
438 return clk_prepare(ctx->clk);
439}
440EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
441
442void regmap_mmio_detach_clk(struct regmap *map)
443{
444 struct regmap_mmio_context *ctx = map->bus_context;
445
446 clk_unprepare(ctx->clk);
447
448 ctx->attached_clk = false;
449 ctx->clk = NULL;
450}
451EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
452
453MODULE_LICENSE("GPL v2");