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1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/export.h>
11#include <linux/kernel.h>
12#include <linux/stddef.h>
13#include <linux/ioport.h>
14#include <linux/delay.h>
15#include <linux/utsname.h>
16#include <linux/initrd.h>
17#include <linux/console.h>
18#include <linux/bootmem.h>
19#include <linux/seq_file.h>
20#include <linux/screen_info.h>
21#include <linux/of_platform.h>
22#include <linux/init.h>
23#include <linux/kexec.h>
24#include <linux/of_fdt.h>
25#include <linux/cpu.h>
26#include <linux/interrupt.h>
27#include <linux/smp.h>
28#include <linux/proc_fs.h>
29#include <linux/memblock.h>
30#include <linux/bug.h>
31#include <linux/compiler.h>
32#include <linux/sort.h>
33
34#include <asm/unified.h>
35#include <asm/cp15.h>
36#include <asm/cpu.h>
37#include <asm/cputype.h>
38#include <asm/elf.h>
39#include <asm/procinfo.h>
40#include <asm/psci.h>
41#include <asm/sections.h>
42#include <asm/setup.h>
43#include <asm/smp_plat.h>
44#include <asm/mach-types.h>
45#include <asm/cacheflush.h>
46#include <asm/cachetype.h>
47#include <asm/tlbflush.h>
48
49#include <asm/prom.h>
50#include <asm/mach/arch.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53#include <asm/system_info.h>
54#include <asm/system_misc.h>
55#include <asm/traps.h>
56#include <asm/unwind.h>
57#include <asm/memblock.h>
58#include <asm/virt.h>
59
60#include "atags.h"
61
62
63#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
64char fpe_type[8];
65
66static int __init fpe_setup(char *line)
67{
68 memcpy(fpe_type, line, 8);
69 return 1;
70}
71
72__setup("fpe=", fpe_setup);
73#endif
74
75extern void paging_init(const struct machine_desc *desc);
76extern void early_paging_init(const struct machine_desc *,
77 struct proc_info_list *);
78extern void sanity_check_meminfo(void);
79extern enum reboot_mode reboot_mode;
80extern void setup_dma_zone(const struct machine_desc *desc);
81
82unsigned int processor_id;
83EXPORT_SYMBOL(processor_id);
84unsigned int __machine_arch_type __read_mostly;
85EXPORT_SYMBOL(__machine_arch_type);
86unsigned int cacheid __read_mostly;
87EXPORT_SYMBOL(cacheid);
88
89unsigned int __atags_pointer __initdata;
90
91unsigned int system_rev;
92EXPORT_SYMBOL(system_rev);
93
94unsigned int system_serial_low;
95EXPORT_SYMBOL(system_serial_low);
96
97unsigned int system_serial_high;
98EXPORT_SYMBOL(system_serial_high);
99
100unsigned int elf_hwcap __read_mostly;
101EXPORT_SYMBOL(elf_hwcap);
102
103unsigned int elf_hwcap2 __read_mostly;
104EXPORT_SYMBOL(elf_hwcap2);
105
106
107#ifdef MULTI_CPU
108struct processor processor __read_mostly;
109#endif
110#ifdef MULTI_TLB
111struct cpu_tlb_fns cpu_tlb __read_mostly;
112#endif
113#ifdef MULTI_USER
114struct cpu_user_fns cpu_user __read_mostly;
115#endif
116#ifdef MULTI_CACHE
117struct cpu_cache_fns cpu_cache __read_mostly;
118#endif
119#ifdef CONFIG_OUTER_CACHE
120struct outer_cache_fns outer_cache __read_mostly;
121EXPORT_SYMBOL(outer_cache);
122#endif
123
124/*
125 * Cached cpu_architecture() result for use by assembler code.
126 * C code should use the cpu_architecture() function instead of accessing this
127 * variable directly.
128 */
129int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
130
131struct stack {
132 u32 irq[3];
133 u32 abt[3];
134 u32 und[3];
135} ____cacheline_aligned;
136
137#ifndef CONFIG_CPU_V7M
138static struct stack stacks[NR_CPUS];
139#endif
140
141char elf_platform[ELF_PLATFORM_SIZE];
142EXPORT_SYMBOL(elf_platform);
143
144static const char *cpu_name;
145static const char *machine_name;
146static char __initdata cmd_line[COMMAND_LINE_SIZE];
147const struct machine_desc *machine_desc __initdata;
148
149static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
150#define ENDIANNESS ((char)endian_test.l)
151
152DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
153
154/*
155 * Standard memory resources
156 */
157static struct resource mem_res[] = {
158 {
159 .name = "Video RAM",
160 .start = 0,
161 .end = 0,
162 .flags = IORESOURCE_MEM
163 },
164 {
165 .name = "Kernel code",
166 .start = 0,
167 .end = 0,
168 .flags = IORESOURCE_MEM
169 },
170 {
171 .name = "Kernel data",
172 .start = 0,
173 .end = 0,
174 .flags = IORESOURCE_MEM
175 }
176};
177
178#define video_ram mem_res[0]
179#define kernel_code mem_res[1]
180#define kernel_data mem_res[2]
181
182static struct resource io_res[] = {
183 {
184 .name = "reserved",
185 .start = 0x3bc,
186 .end = 0x3be,
187 .flags = IORESOURCE_IO | IORESOURCE_BUSY
188 },
189 {
190 .name = "reserved",
191 .start = 0x378,
192 .end = 0x37f,
193 .flags = IORESOURCE_IO | IORESOURCE_BUSY
194 },
195 {
196 .name = "reserved",
197 .start = 0x278,
198 .end = 0x27f,
199 .flags = IORESOURCE_IO | IORESOURCE_BUSY
200 }
201};
202
203#define lp0 io_res[0]
204#define lp1 io_res[1]
205#define lp2 io_res[2]
206
207static const char *proc_arch[] = {
208 "undefined/unknown",
209 "3",
210 "4",
211 "4T",
212 "5",
213 "5T",
214 "5TE",
215 "5TEJ",
216 "6TEJ",
217 "7",
218 "7M",
219 "?(12)",
220 "?(13)",
221 "?(14)",
222 "?(15)",
223 "?(16)",
224 "?(17)",
225};
226
227#ifdef CONFIG_CPU_V7M
228static int __get_cpu_architecture(void)
229{
230 return CPU_ARCH_ARMv7M;
231}
232#else
233static int __get_cpu_architecture(void)
234{
235 int cpu_arch;
236
237 if ((read_cpuid_id() & 0x0008f000) == 0) {
238 cpu_arch = CPU_ARCH_UNKNOWN;
239 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
240 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
241 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
242 cpu_arch = (read_cpuid_id() >> 16) & 7;
243 if (cpu_arch)
244 cpu_arch += CPU_ARCH_ARMv3;
245 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
246 unsigned int mmfr0;
247
248 /* Revised CPUID format. Read the Memory Model Feature
249 * Register 0 and check for VMSAv7 or PMSAv7 */
250 asm("mrc p15, 0, %0, c0, c1, 4"
251 : "=r" (mmfr0));
252 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
253 (mmfr0 & 0x000000f0) >= 0x00000030)
254 cpu_arch = CPU_ARCH_ARMv7;
255 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
256 (mmfr0 & 0x000000f0) == 0x00000020)
257 cpu_arch = CPU_ARCH_ARMv6;
258 else
259 cpu_arch = CPU_ARCH_UNKNOWN;
260 } else
261 cpu_arch = CPU_ARCH_UNKNOWN;
262
263 return cpu_arch;
264}
265#endif
266
267int __pure cpu_architecture(void)
268{
269 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
270
271 return __cpu_architecture;
272}
273
274static int cpu_has_aliasing_icache(unsigned int arch)
275{
276 int aliasing_icache;
277 unsigned int id_reg, num_sets, line_size;
278
279 /* PIPT caches never alias. */
280 if (icache_is_pipt())
281 return 0;
282
283 /* arch specifies the register format */
284 switch (arch) {
285 case CPU_ARCH_ARMv7:
286 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
287 : /* No output operands */
288 : "r" (1));
289 isb();
290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
291 : "=r" (id_reg));
292 line_size = 4 << ((id_reg & 0x7) + 2);
293 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
294 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
295 break;
296 case CPU_ARCH_ARMv6:
297 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
298 break;
299 default:
300 /* I-cache aliases will be handled by D-cache aliasing code */
301 aliasing_icache = 0;
302 }
303
304 return aliasing_icache;
305}
306
307static void __init cacheid_init(void)
308{
309 unsigned int arch = cpu_architecture();
310
311 if (arch == CPU_ARCH_ARMv7M) {
312 cacheid = 0;
313 } else if (arch >= CPU_ARCH_ARMv6) {
314 unsigned int cachetype = read_cpuid_cachetype();
315 if ((cachetype & (7 << 29)) == 4 << 29) {
316 /* ARMv7 register format */
317 arch = CPU_ARCH_ARMv7;
318 cacheid = CACHEID_VIPT_NONALIASING;
319 switch (cachetype & (3 << 14)) {
320 case (1 << 14):
321 cacheid |= CACHEID_ASID_TAGGED;
322 break;
323 case (3 << 14):
324 cacheid |= CACHEID_PIPT;
325 break;
326 }
327 } else {
328 arch = CPU_ARCH_ARMv6;
329 if (cachetype & (1 << 23))
330 cacheid = CACHEID_VIPT_ALIASING;
331 else
332 cacheid = CACHEID_VIPT_NONALIASING;
333 }
334 if (cpu_has_aliasing_icache(arch))
335 cacheid |= CACHEID_VIPT_I_ALIASING;
336 } else {
337 cacheid = CACHEID_VIVT;
338 }
339
340 pr_info("CPU: %s data cache, %s instruction cache\n",
341 cache_is_vivt() ? "VIVT" :
342 cache_is_vipt_aliasing() ? "VIPT aliasing" :
343 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
344 cache_is_vivt() ? "VIVT" :
345 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
346 icache_is_vipt_aliasing() ? "VIPT aliasing" :
347 icache_is_pipt() ? "PIPT" :
348 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
349}
350
351/*
352 * These functions re-use the assembly code in head.S, which
353 * already provide the required functionality.
354 */
355extern struct proc_info_list *lookup_processor_type(unsigned int);
356
357void __init early_print(const char *str, ...)
358{
359 extern void printascii(const char *);
360 char buf[256];
361 va_list ap;
362
363 va_start(ap, str);
364 vsnprintf(buf, sizeof(buf), str, ap);
365 va_end(ap);
366
367#ifdef CONFIG_DEBUG_LL
368 printascii(buf);
369#endif
370 printk("%s", buf);
371}
372
373static void __init cpuid_init_hwcaps(void)
374{
375 unsigned int divide_instrs, vmsa;
376
377 if (cpu_architecture() < CPU_ARCH_ARMv7)
378 return;
379
380 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
381
382 switch (divide_instrs) {
383 case 2:
384 elf_hwcap |= HWCAP_IDIVA;
385 case 1:
386 elf_hwcap |= HWCAP_IDIVT;
387 }
388
389 /* LPAE implies atomic ldrd/strd instructions */
390 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
391 if (vmsa >= 5)
392 elf_hwcap |= HWCAP_LPAE;
393}
394
395static void __init feat_v6_fixup(void)
396{
397 int id = read_cpuid_id();
398
399 if ((id & 0xff0f0000) != 0x41070000)
400 return;
401
402 /*
403 * HWCAP_TLS is available only on 1136 r1p0 and later,
404 * see also kuser_get_tls_init.
405 */
406 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
407 elf_hwcap &= ~HWCAP_TLS;
408}
409
410/*
411 * cpu_init - initialise one CPU.
412 *
413 * cpu_init sets up the per-CPU stacks.
414 */
415void notrace cpu_init(void)
416{
417#ifndef CONFIG_CPU_V7M
418 unsigned int cpu = smp_processor_id();
419 struct stack *stk = &stacks[cpu];
420
421 if (cpu >= NR_CPUS) {
422 pr_crit("CPU%u: bad primary CPU number\n", cpu);
423 BUG();
424 }
425
426 /*
427 * This only works on resume and secondary cores. For booting on the
428 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
429 */
430 set_my_cpu_offset(per_cpu_offset(cpu));
431
432 cpu_proc_init();
433
434 /*
435 * Define the placement constraint for the inline asm directive below.
436 * In Thumb-2, msr with an immediate value is not allowed.
437 */
438#ifdef CONFIG_THUMB2_KERNEL
439#define PLC "r"
440#else
441#define PLC "I"
442#endif
443
444 /*
445 * setup stacks for re-entrant exception handlers
446 */
447 __asm__ (
448 "msr cpsr_c, %1\n\t"
449 "add r14, %0, %2\n\t"
450 "mov sp, r14\n\t"
451 "msr cpsr_c, %3\n\t"
452 "add r14, %0, %4\n\t"
453 "mov sp, r14\n\t"
454 "msr cpsr_c, %5\n\t"
455 "add r14, %0, %6\n\t"
456 "mov sp, r14\n\t"
457 "msr cpsr_c, %7"
458 :
459 : "r" (stk),
460 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
461 "I" (offsetof(struct stack, irq[0])),
462 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
463 "I" (offsetof(struct stack, abt[0])),
464 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
465 "I" (offsetof(struct stack, und[0])),
466 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
467 : "r14");
468#endif
469}
470
471u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
472
473void __init smp_setup_processor_id(void)
474{
475 int i;
476 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
477 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
478
479 cpu_logical_map(0) = cpu;
480 for (i = 1; i < nr_cpu_ids; ++i)
481 cpu_logical_map(i) = i == cpu ? 0 : i;
482
483 /*
484 * clear __my_cpu_offset on boot CPU to avoid hang caused by
485 * using percpu variable early, for example, lockdep will
486 * access percpu variable inside lock_release
487 */
488 set_my_cpu_offset(0);
489
490 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
491}
492
493struct mpidr_hash mpidr_hash;
494#ifdef CONFIG_SMP
495/**
496 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
497 * level in order to build a linear index from an
498 * MPIDR value. Resulting algorithm is a collision
499 * free hash carried out through shifting and ORing
500 */
501static void __init smp_build_mpidr_hash(void)
502{
503 u32 i, affinity;
504 u32 fs[3], bits[3], ls, mask = 0;
505 /*
506 * Pre-scan the list of MPIDRS and filter out bits that do
507 * not contribute to affinity levels, ie they never toggle.
508 */
509 for_each_possible_cpu(i)
510 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
511 pr_debug("mask of set bits 0x%x\n", mask);
512 /*
513 * Find and stash the last and first bit set at all affinity levels to
514 * check how many bits are required to represent them.
515 */
516 for (i = 0; i < 3; i++) {
517 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
518 /*
519 * Find the MSB bit and LSB bits position
520 * to determine how many bits are required
521 * to express the affinity level.
522 */
523 ls = fls(affinity);
524 fs[i] = affinity ? ffs(affinity) - 1 : 0;
525 bits[i] = ls - fs[i];
526 }
527 /*
528 * An index can be created from the MPIDR by isolating the
529 * significant bits at each affinity level and by shifting
530 * them in order to compress the 24 bits values space to a
531 * compressed set of values. This is equivalent to hashing
532 * the MPIDR through shifting and ORing. It is a collision free
533 * hash though not minimal since some levels might contain a number
534 * of CPUs that is not an exact power of 2 and their bit
535 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
536 */
537 mpidr_hash.shift_aff[0] = fs[0];
538 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
539 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
540 (bits[1] + bits[0]);
541 mpidr_hash.mask = mask;
542 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
543 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
544 mpidr_hash.shift_aff[0],
545 mpidr_hash.shift_aff[1],
546 mpidr_hash.shift_aff[2],
547 mpidr_hash.mask,
548 mpidr_hash.bits);
549 /*
550 * 4x is an arbitrary value used to warn on a hash table much bigger
551 * than expected on most systems.
552 */
553 if (mpidr_hash_size() > 4 * num_possible_cpus())
554 pr_warn("Large number of MPIDR hash buckets detected\n");
555 sync_cache_w(&mpidr_hash);
556}
557#endif
558
559static void __init setup_processor(void)
560{
561 struct proc_info_list *list;
562
563 /*
564 * locate processor in the list of supported processor
565 * types. The linker builds this table for us from the
566 * entries in arch/arm/mm/proc-*.S
567 */
568 list = lookup_processor_type(read_cpuid_id());
569 if (!list) {
570 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
571 read_cpuid_id());
572 while (1);
573 }
574
575 cpu_name = list->cpu_name;
576 __cpu_architecture = __get_cpu_architecture();
577
578#ifdef MULTI_CPU
579 processor = *list->proc;
580#endif
581#ifdef MULTI_TLB
582 cpu_tlb = *list->tlb;
583#endif
584#ifdef MULTI_USER
585 cpu_user = *list->user;
586#endif
587#ifdef MULTI_CACHE
588 cpu_cache = *list->cache;
589#endif
590
591 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
592 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
593 proc_arch[cpu_architecture()], cr_alignment);
594
595 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
596 list->arch_name, ENDIANNESS);
597 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
598 list->elf_name, ENDIANNESS);
599 elf_hwcap = list->elf_hwcap;
600
601 cpuid_init_hwcaps();
602
603#ifndef CONFIG_ARM_THUMB
604 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
605#endif
606
607 erratum_a15_798181_init();
608
609 feat_v6_fixup();
610
611 cacheid_init();
612 cpu_init();
613}
614
615void __init dump_machine_table(void)
616{
617 const struct machine_desc *p;
618
619 early_print("Available machine support:\n\nID (hex)\tNAME\n");
620 for_each_machine_desc(p)
621 early_print("%08x\t%s\n", p->nr, p->name);
622
623 early_print("\nPlease check your kernel config and/or bootloader.\n");
624
625 while (true)
626 /* can't use cpu_relax() here as it may require MMU setup */;
627}
628
629int __init arm_add_memory(u64 start, u64 size)
630{
631 struct membank *bank = &meminfo.bank[meminfo.nr_banks];
632 u64 aligned_start;
633
634 if (meminfo.nr_banks >= NR_BANKS) {
635 pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
636 (long long)start);
637 return -EINVAL;
638 }
639
640 /*
641 * Ensure that start/size are aligned to a page boundary.
642 * Size is appropriately rounded down, start is rounded up.
643 */
644 size -= start & ~PAGE_MASK;
645 aligned_start = PAGE_ALIGN(start);
646
647#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
648 if (aligned_start > ULONG_MAX) {
649 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
650 (long long)start);
651 return -EINVAL;
652 }
653
654 if (aligned_start + size > ULONG_MAX) {
655 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
656 (long long)start);
657 /*
658 * To ensure bank->start + bank->size is representable in
659 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
660 * This means we lose a page after masking.
661 */
662 size = ULONG_MAX - aligned_start;
663 }
664#endif
665
666 if (aligned_start < PHYS_OFFSET) {
667 if (aligned_start + size <= PHYS_OFFSET) {
668 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
669 aligned_start, aligned_start + size);
670 return -EINVAL;
671 }
672
673 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
674 aligned_start, (u64)PHYS_OFFSET);
675
676 size -= PHYS_OFFSET - aligned_start;
677 aligned_start = PHYS_OFFSET;
678 }
679
680 bank->start = aligned_start;
681 bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
682
683 /*
684 * Check whether this memory region has non-zero size or
685 * invalid node number.
686 */
687 if (bank->size == 0)
688 return -EINVAL;
689
690 meminfo.nr_banks++;
691 return 0;
692}
693
694/*
695 * Pick out the memory size. We look for mem=size@start,
696 * where start and size are "size[KkMm]"
697 */
698static int __init early_mem(char *p)
699{
700 static int usermem __initdata = 0;
701 u64 size;
702 u64 start;
703 char *endp;
704
705 /*
706 * If the user specifies memory size, we
707 * blow away any automatically generated
708 * size.
709 */
710 if (usermem == 0) {
711 usermem = 1;
712 meminfo.nr_banks = 0;
713 }
714
715 start = PHYS_OFFSET;
716 size = memparse(p, &endp);
717 if (*endp == '@')
718 start = memparse(endp + 1, NULL);
719
720 arm_add_memory(start, size);
721
722 return 0;
723}
724early_param("mem", early_mem);
725
726static void __init request_standard_resources(const struct machine_desc *mdesc)
727{
728 struct memblock_region *region;
729 struct resource *res;
730
731 kernel_code.start = virt_to_phys(_text);
732 kernel_code.end = virt_to_phys(_etext - 1);
733 kernel_data.start = virt_to_phys(_sdata);
734 kernel_data.end = virt_to_phys(_end - 1);
735
736 for_each_memblock(memory, region) {
737 res = memblock_virt_alloc(sizeof(*res), 0);
738 res->name = "System RAM";
739 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
740 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
741 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
742
743 request_resource(&iomem_resource, res);
744
745 if (kernel_code.start >= res->start &&
746 kernel_code.end <= res->end)
747 request_resource(res, &kernel_code);
748 if (kernel_data.start >= res->start &&
749 kernel_data.end <= res->end)
750 request_resource(res, &kernel_data);
751 }
752
753 if (mdesc->video_start) {
754 video_ram.start = mdesc->video_start;
755 video_ram.end = mdesc->video_end;
756 request_resource(&iomem_resource, &video_ram);
757 }
758
759 /*
760 * Some machines don't have the possibility of ever
761 * possessing lp0, lp1 or lp2
762 */
763 if (mdesc->reserve_lp0)
764 request_resource(&ioport_resource, &lp0);
765 if (mdesc->reserve_lp1)
766 request_resource(&ioport_resource, &lp1);
767 if (mdesc->reserve_lp2)
768 request_resource(&ioport_resource, &lp2);
769}
770
771#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
772struct screen_info screen_info = {
773 .orig_video_lines = 30,
774 .orig_video_cols = 80,
775 .orig_video_mode = 0,
776 .orig_video_ega_bx = 0,
777 .orig_video_isVGA = 1,
778 .orig_video_points = 8
779};
780#endif
781
782static int __init customize_machine(void)
783{
784 /*
785 * customizes platform devices, or adds new ones
786 * On DT based machines, we fall back to populating the
787 * machine from the device tree, if no callback is provided,
788 * otherwise we would always need an init_machine callback.
789 */
790 if (machine_desc->init_machine)
791 machine_desc->init_machine();
792#ifdef CONFIG_OF
793 else
794 of_platform_populate(NULL, of_default_bus_match_table,
795 NULL, NULL);
796#endif
797 return 0;
798}
799arch_initcall(customize_machine);
800
801static int __init init_machine_late(void)
802{
803 if (machine_desc->init_late)
804 machine_desc->init_late();
805 return 0;
806}
807late_initcall(init_machine_late);
808
809#ifdef CONFIG_KEXEC
810static inline unsigned long long get_total_mem(void)
811{
812 unsigned long total;
813
814 total = max_low_pfn - min_low_pfn;
815 return total << PAGE_SHIFT;
816}
817
818/**
819 * reserve_crashkernel() - reserves memory are for crash kernel
820 *
821 * This function reserves memory area given in "crashkernel=" kernel command
822 * line parameter. The memory reserved is used by a dump capture kernel when
823 * primary kernel is crashing.
824 */
825static void __init reserve_crashkernel(void)
826{
827 unsigned long long crash_size, crash_base;
828 unsigned long long total_mem;
829 int ret;
830
831 total_mem = get_total_mem();
832 ret = parse_crashkernel(boot_command_line, total_mem,
833 &crash_size, &crash_base);
834 if (ret)
835 return;
836
837 ret = memblock_reserve(crash_base, crash_size);
838 if (ret < 0) {
839 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
840 (unsigned long)crash_base);
841 return;
842 }
843
844 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
845 (unsigned long)(crash_size >> 20),
846 (unsigned long)(crash_base >> 20),
847 (unsigned long)(total_mem >> 20));
848
849 crashk_res.start = crash_base;
850 crashk_res.end = crash_base + crash_size - 1;
851 insert_resource(&iomem_resource, &crashk_res);
852}
853#else
854static inline void reserve_crashkernel(void) {}
855#endif /* CONFIG_KEXEC */
856
857static int __init meminfo_cmp(const void *_a, const void *_b)
858{
859 const struct membank *a = _a, *b = _b;
860 long cmp = bank_pfn_start(a) - bank_pfn_start(b);
861 return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
862}
863
864void __init hyp_mode_check(void)
865{
866#ifdef CONFIG_ARM_VIRT_EXT
867 sync_boot_mode();
868
869 if (is_hyp_mode_available()) {
870 pr_info("CPU: All CPU(s) started in HYP mode.\n");
871 pr_info("CPU: Virtualization extensions available.\n");
872 } else if (is_hyp_mode_mismatched()) {
873 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
874 __boot_cpu_mode & MODE_MASK);
875 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
876 } else
877 pr_info("CPU: All CPU(s) started in SVC mode.\n");
878#endif
879}
880
881void __init setup_arch(char **cmdline_p)
882{
883 const struct machine_desc *mdesc;
884
885 setup_processor();
886 mdesc = setup_machine_fdt(__atags_pointer);
887 if (!mdesc)
888 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
889 machine_desc = mdesc;
890 machine_name = mdesc->name;
891
892 if (mdesc->reboot_mode != REBOOT_HARD)
893 reboot_mode = mdesc->reboot_mode;
894
895 init_mm.start_code = (unsigned long) _text;
896 init_mm.end_code = (unsigned long) _etext;
897 init_mm.end_data = (unsigned long) _edata;
898 init_mm.brk = (unsigned long) _end;
899
900 /* populate cmd_line too for later use, preserving boot_command_line */
901 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
902 *cmdline_p = cmd_line;
903
904 parse_early_param();
905
906 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
907
908 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
909 setup_dma_zone(mdesc);
910 sanity_check_meminfo();
911 arm_memblock_init(&meminfo, mdesc);
912
913 paging_init(mdesc);
914 request_standard_resources(mdesc);
915
916 if (mdesc->restart)
917 arm_pm_restart = mdesc->restart;
918
919 unflatten_device_tree();
920
921 arm_dt_init_cpu_maps();
922 psci_init();
923#ifdef CONFIG_SMP
924 if (is_smp()) {
925 if (!mdesc->smp_init || !mdesc->smp_init()) {
926 if (psci_smp_available())
927 smp_set_ops(&psci_smp_ops);
928 else if (mdesc->smp)
929 smp_set_ops(mdesc->smp);
930 }
931 smp_init_cpus();
932 smp_build_mpidr_hash();
933 }
934#endif
935
936 if (!is_smp())
937 hyp_mode_check();
938
939 reserve_crashkernel();
940
941#ifdef CONFIG_MULTI_IRQ_HANDLER
942 handle_arch_irq = mdesc->handle_irq;
943#endif
944
945#ifdef CONFIG_VT
946#if defined(CONFIG_VGA_CONSOLE)
947 conswitchp = &vga_con;
948#elif defined(CONFIG_DUMMY_CONSOLE)
949 conswitchp = &dummy_con;
950#endif
951#endif
952
953 if (mdesc->init_early)
954 mdesc->init_early();
955}
956
957
958static int __init topology_init(void)
959{
960 int cpu;
961
962 for_each_possible_cpu(cpu) {
963 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
964 cpuinfo->cpu.hotpluggable = 1;
965 register_cpu(&cpuinfo->cpu, cpu);
966 }
967
968 return 0;
969}
970subsys_initcall(topology_init);
971
972#ifdef CONFIG_HAVE_PROC_CPU
973static int __init proc_cpu_init(void)
974{
975 struct proc_dir_entry *res;
976
977 res = proc_mkdir("cpu", NULL);
978 if (!res)
979 return -ENOMEM;
980 return 0;
981}
982fs_initcall(proc_cpu_init);
983#endif
984
985static const char *hwcap_str[] = {
986 "swp",
987 "half",
988 "thumb",
989 "26bit",
990 "fastmult",
991 "fpa",
992 "vfp",
993 "edsp",
994 "java",
995 "iwmmxt",
996 "crunch",
997 "thumbee",
998 "neon",
999 "vfpv3",
1000 "vfpv3d16",
1001 "tls",
1002 "vfpv4",
1003 "idiva",
1004 "idivt",
1005 "vfpd32",
1006 "lpae",
1007 "evtstrm",
1008 NULL
1009};
1010
1011static const char *hwcap2_str[] = {
1012 "aes",
1013 "pmull",
1014 "sha1",
1015 "sha2",
1016 "crc32",
1017 NULL
1018};
1019
1020static int c_show(struct seq_file *m, void *v)
1021{
1022 int i, j;
1023 u32 cpuid;
1024
1025 for_each_online_cpu(i) {
1026 /*
1027 * glibc reads /proc/cpuinfo to determine the number of
1028 * online processors, looking for lines beginning with
1029 * "processor". Give glibc what it expects.
1030 */
1031 seq_printf(m, "processor\t: %d\n", i);
1032 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1033 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1034 cpu_name, cpuid & 15, elf_platform);
1035
1036 /* dump out the processor features */
1037 seq_puts(m, "Features\t: ");
1038
1039 for (j = 0; hwcap_str[j]; j++)
1040 if (elf_hwcap & (1 << j))
1041 seq_printf(m, "%s ", hwcap_str[j]);
1042
1043 for (j = 0; hwcap2_str[j]; j++)
1044 if (elf_hwcap2 & (1 << j))
1045 seq_printf(m, "%s ", hwcap2_str[j]);
1046
1047 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1048 seq_printf(m, "CPU architecture: %s\n",
1049 proc_arch[cpu_architecture()]);
1050
1051 if ((cpuid & 0x0008f000) == 0x00000000) {
1052 /* pre-ARM7 */
1053 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1054 } else {
1055 if ((cpuid & 0x0008f000) == 0x00007000) {
1056 /* ARM7 */
1057 seq_printf(m, "CPU variant\t: 0x%02x\n",
1058 (cpuid >> 16) & 127);
1059 } else {
1060 /* post-ARM7 */
1061 seq_printf(m, "CPU variant\t: 0x%x\n",
1062 (cpuid >> 20) & 15);
1063 }
1064 seq_printf(m, "CPU part\t: 0x%03x\n",
1065 (cpuid >> 4) & 0xfff);
1066 }
1067 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1068 }
1069
1070 seq_printf(m, "Hardware\t: %s\n", machine_name);
1071 seq_printf(m, "Revision\t: %04x\n", system_rev);
1072 seq_printf(m, "Serial\t\t: %08x%08x\n",
1073 system_serial_high, system_serial_low);
1074
1075 return 0;
1076}
1077
1078static void *c_start(struct seq_file *m, loff_t *pos)
1079{
1080 return *pos < 1 ? (void *)1 : NULL;
1081}
1082
1083static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1084{
1085 ++*pos;
1086 return NULL;
1087}
1088
1089static void c_stop(struct seq_file *m, void *v)
1090{
1091}
1092
1093const struct seq_operations cpuinfo_op = {
1094 .start = c_start,
1095 .next = c_next,
1096 .stop = c_stop,
1097 .show = c_show
1098};
1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/export.h>
11#include <linux/kernel.h>
12#include <linux/stddef.h>
13#include <linux/ioport.h>
14#include <linux/delay.h>
15#include <linux/utsname.h>
16#include <linux/initrd.h>
17#include <linux/console.h>
18#include <linux/bootmem.h>
19#include <linux/seq_file.h>
20#include <linux/screen_info.h>
21#include <linux/init.h>
22#include <linux/kexec.h>
23#include <linux/of_fdt.h>
24#include <linux/root_dev.h>
25#include <linux/cpu.h>
26#include <linux/interrupt.h>
27#include <linux/smp.h>
28#include <linux/fs.h>
29#include <linux/proc_fs.h>
30#include <linux/memblock.h>
31#include <linux/bug.h>
32#include <linux/compiler.h>
33#include <linux/sort.h>
34
35#include <asm/unified.h>
36#include <asm/cp15.h>
37#include <asm/cpu.h>
38#include <asm/cputype.h>
39#include <asm/elf.h>
40#include <asm/procinfo.h>
41#include <asm/sections.h>
42#include <asm/setup.h>
43#include <asm/smp_plat.h>
44#include <asm/mach-types.h>
45#include <asm/cacheflush.h>
46#include <asm/cachetype.h>
47#include <asm/tlbflush.h>
48
49#include <asm/prom.h>
50#include <asm/mach/arch.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53#include <asm/system_info.h>
54#include <asm/system_misc.h>
55#include <asm/traps.h>
56#include <asm/unwind.h>
57#include <asm/memblock.h>
58
59#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
60#include "compat.h"
61#endif
62#include "atags.h"
63#include "tcm.h"
64
65#ifndef MEM_SIZE
66#define MEM_SIZE (16*1024*1024)
67#endif
68
69#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
70char fpe_type[8];
71
72static int __init fpe_setup(char *line)
73{
74 memcpy(fpe_type, line, 8);
75 return 1;
76}
77
78__setup("fpe=", fpe_setup);
79#endif
80
81extern void paging_init(struct machine_desc *desc);
82extern void sanity_check_meminfo(void);
83extern void reboot_setup(char *str);
84extern void setup_dma_zone(struct machine_desc *desc);
85
86unsigned int processor_id;
87EXPORT_SYMBOL(processor_id);
88unsigned int __machine_arch_type __read_mostly;
89EXPORT_SYMBOL(__machine_arch_type);
90unsigned int cacheid __read_mostly;
91EXPORT_SYMBOL(cacheid);
92
93unsigned int __atags_pointer __initdata;
94
95unsigned int system_rev;
96EXPORT_SYMBOL(system_rev);
97
98unsigned int system_serial_low;
99EXPORT_SYMBOL(system_serial_low);
100
101unsigned int system_serial_high;
102EXPORT_SYMBOL(system_serial_high);
103
104unsigned int elf_hwcap __read_mostly;
105EXPORT_SYMBOL(elf_hwcap);
106
107
108#ifdef MULTI_CPU
109struct processor processor __read_mostly;
110#endif
111#ifdef MULTI_TLB
112struct cpu_tlb_fns cpu_tlb __read_mostly;
113#endif
114#ifdef MULTI_USER
115struct cpu_user_fns cpu_user __read_mostly;
116#endif
117#ifdef MULTI_CACHE
118struct cpu_cache_fns cpu_cache __read_mostly;
119#endif
120#ifdef CONFIG_OUTER_CACHE
121struct outer_cache_fns outer_cache __read_mostly;
122EXPORT_SYMBOL(outer_cache);
123#endif
124
125/*
126 * Cached cpu_architecture() result for use by assembler code.
127 * C code should use the cpu_architecture() function instead of accessing this
128 * variable directly.
129 */
130int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
131
132struct stack {
133 u32 irq[3];
134 u32 abt[3];
135 u32 und[3];
136} ____cacheline_aligned;
137
138static struct stack stacks[NR_CPUS];
139
140char elf_platform[ELF_PLATFORM_SIZE];
141EXPORT_SYMBOL(elf_platform);
142
143static const char *cpu_name;
144static const char *machine_name;
145static char __initdata cmd_line[COMMAND_LINE_SIZE];
146struct machine_desc *machine_desc __initdata;
147
148static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
149static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
150#define ENDIANNESS ((char)endian_test.l)
151
152DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
153
154/*
155 * Standard memory resources
156 */
157static struct resource mem_res[] = {
158 {
159 .name = "Video RAM",
160 .start = 0,
161 .end = 0,
162 .flags = IORESOURCE_MEM
163 },
164 {
165 .name = "Kernel code",
166 .start = 0,
167 .end = 0,
168 .flags = IORESOURCE_MEM
169 },
170 {
171 .name = "Kernel data",
172 .start = 0,
173 .end = 0,
174 .flags = IORESOURCE_MEM
175 }
176};
177
178#define video_ram mem_res[0]
179#define kernel_code mem_res[1]
180#define kernel_data mem_res[2]
181
182static struct resource io_res[] = {
183 {
184 .name = "reserved",
185 .start = 0x3bc,
186 .end = 0x3be,
187 .flags = IORESOURCE_IO | IORESOURCE_BUSY
188 },
189 {
190 .name = "reserved",
191 .start = 0x378,
192 .end = 0x37f,
193 .flags = IORESOURCE_IO | IORESOURCE_BUSY
194 },
195 {
196 .name = "reserved",
197 .start = 0x278,
198 .end = 0x27f,
199 .flags = IORESOURCE_IO | IORESOURCE_BUSY
200 }
201};
202
203#define lp0 io_res[0]
204#define lp1 io_res[1]
205#define lp2 io_res[2]
206
207static const char *proc_arch[] = {
208 "undefined/unknown",
209 "3",
210 "4",
211 "4T",
212 "5",
213 "5T",
214 "5TE",
215 "5TEJ",
216 "6TEJ",
217 "7",
218 "?(11)",
219 "?(12)",
220 "?(13)",
221 "?(14)",
222 "?(15)",
223 "?(16)",
224 "?(17)",
225};
226
227static int __get_cpu_architecture(void)
228{
229 int cpu_arch;
230
231 if ((read_cpuid_id() & 0x0008f000) == 0) {
232 cpu_arch = CPU_ARCH_UNKNOWN;
233 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
234 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
235 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
236 cpu_arch = (read_cpuid_id() >> 16) & 7;
237 if (cpu_arch)
238 cpu_arch += CPU_ARCH_ARMv3;
239 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
240 unsigned int mmfr0;
241
242 /* Revised CPUID format. Read the Memory Model Feature
243 * Register 0 and check for VMSAv7 or PMSAv7 */
244 asm("mrc p15, 0, %0, c0, c1, 4"
245 : "=r" (mmfr0));
246 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
247 (mmfr0 & 0x000000f0) >= 0x00000030)
248 cpu_arch = CPU_ARCH_ARMv7;
249 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
250 (mmfr0 & 0x000000f0) == 0x00000020)
251 cpu_arch = CPU_ARCH_ARMv6;
252 else
253 cpu_arch = CPU_ARCH_UNKNOWN;
254 } else
255 cpu_arch = CPU_ARCH_UNKNOWN;
256
257 return cpu_arch;
258}
259
260int __pure cpu_architecture(void)
261{
262 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
263
264 return __cpu_architecture;
265}
266
267static int cpu_has_aliasing_icache(unsigned int arch)
268{
269 int aliasing_icache;
270 unsigned int id_reg, num_sets, line_size;
271
272 /* PIPT caches never alias. */
273 if (icache_is_pipt())
274 return 0;
275
276 /* arch specifies the register format */
277 switch (arch) {
278 case CPU_ARCH_ARMv7:
279 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
280 : /* No output operands */
281 : "r" (1));
282 isb();
283 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
284 : "=r" (id_reg));
285 line_size = 4 << ((id_reg & 0x7) + 2);
286 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
287 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
288 break;
289 case CPU_ARCH_ARMv6:
290 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
291 break;
292 default:
293 /* I-cache aliases will be handled by D-cache aliasing code */
294 aliasing_icache = 0;
295 }
296
297 return aliasing_icache;
298}
299
300static void __init cacheid_init(void)
301{
302 unsigned int cachetype = read_cpuid_cachetype();
303 unsigned int arch = cpu_architecture();
304
305 if (arch >= CPU_ARCH_ARMv6) {
306 if ((cachetype & (7 << 29)) == 4 << 29) {
307 /* ARMv7 register format */
308 arch = CPU_ARCH_ARMv7;
309 cacheid = CACHEID_VIPT_NONALIASING;
310 switch (cachetype & (3 << 14)) {
311 case (1 << 14):
312 cacheid |= CACHEID_ASID_TAGGED;
313 break;
314 case (3 << 14):
315 cacheid |= CACHEID_PIPT;
316 break;
317 }
318 } else {
319 arch = CPU_ARCH_ARMv6;
320 if (cachetype & (1 << 23))
321 cacheid = CACHEID_VIPT_ALIASING;
322 else
323 cacheid = CACHEID_VIPT_NONALIASING;
324 }
325 if (cpu_has_aliasing_icache(arch))
326 cacheid |= CACHEID_VIPT_I_ALIASING;
327 } else {
328 cacheid = CACHEID_VIVT;
329 }
330
331 printk("CPU: %s data cache, %s instruction cache\n",
332 cache_is_vivt() ? "VIVT" :
333 cache_is_vipt_aliasing() ? "VIPT aliasing" :
334 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
335 cache_is_vivt() ? "VIVT" :
336 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
337 icache_is_vipt_aliasing() ? "VIPT aliasing" :
338 icache_is_pipt() ? "PIPT" :
339 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
340}
341
342/*
343 * These functions re-use the assembly code in head.S, which
344 * already provide the required functionality.
345 */
346extern struct proc_info_list *lookup_processor_type(unsigned int);
347
348void __init early_print(const char *str, ...)
349{
350 extern void printascii(const char *);
351 char buf[256];
352 va_list ap;
353
354 va_start(ap, str);
355 vsnprintf(buf, sizeof(buf), str, ap);
356 va_end(ap);
357
358#ifdef CONFIG_DEBUG_LL
359 printascii(buf);
360#endif
361 printk("%s", buf);
362}
363
364static void __init feat_v6_fixup(void)
365{
366 int id = read_cpuid_id();
367
368 if ((id & 0xff0f0000) != 0x41070000)
369 return;
370
371 /*
372 * HWCAP_TLS is available only on 1136 r1p0 and later,
373 * see also kuser_get_tls_init.
374 */
375 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
376 elf_hwcap &= ~HWCAP_TLS;
377}
378
379/*
380 * cpu_init - initialise one CPU.
381 *
382 * cpu_init sets up the per-CPU stacks.
383 */
384void cpu_init(void)
385{
386 unsigned int cpu = smp_processor_id();
387 struct stack *stk = &stacks[cpu];
388
389 if (cpu >= NR_CPUS) {
390 printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
391 BUG();
392 }
393
394 cpu_proc_init();
395
396 /*
397 * Define the placement constraint for the inline asm directive below.
398 * In Thumb-2, msr with an immediate value is not allowed.
399 */
400#ifdef CONFIG_THUMB2_KERNEL
401#define PLC "r"
402#else
403#define PLC "I"
404#endif
405
406 /*
407 * setup stacks for re-entrant exception handlers
408 */
409 __asm__ (
410 "msr cpsr_c, %1\n\t"
411 "add r14, %0, %2\n\t"
412 "mov sp, r14\n\t"
413 "msr cpsr_c, %3\n\t"
414 "add r14, %0, %4\n\t"
415 "mov sp, r14\n\t"
416 "msr cpsr_c, %5\n\t"
417 "add r14, %0, %6\n\t"
418 "mov sp, r14\n\t"
419 "msr cpsr_c, %7"
420 :
421 : "r" (stk),
422 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
423 "I" (offsetof(struct stack, irq[0])),
424 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
425 "I" (offsetof(struct stack, abt[0])),
426 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
427 "I" (offsetof(struct stack, und[0])),
428 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
429 : "r14");
430}
431
432int __cpu_logical_map[NR_CPUS];
433
434void __init smp_setup_processor_id(void)
435{
436 int i;
437 u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
438
439 cpu_logical_map(0) = cpu;
440 for (i = 1; i < NR_CPUS; ++i)
441 cpu_logical_map(i) = i == cpu ? 0 : i;
442
443 printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
444}
445
446static void __init setup_processor(void)
447{
448 struct proc_info_list *list;
449
450 /*
451 * locate processor in the list of supported processor
452 * types. The linker builds this table for us from the
453 * entries in arch/arm/mm/proc-*.S
454 */
455 list = lookup_processor_type(read_cpuid_id());
456 if (!list) {
457 printk("CPU configuration botched (ID %08x), unable "
458 "to continue.\n", read_cpuid_id());
459 while (1);
460 }
461
462 cpu_name = list->cpu_name;
463 __cpu_architecture = __get_cpu_architecture();
464
465#ifdef MULTI_CPU
466 processor = *list->proc;
467#endif
468#ifdef MULTI_TLB
469 cpu_tlb = *list->tlb;
470#endif
471#ifdef MULTI_USER
472 cpu_user = *list->user;
473#endif
474#ifdef MULTI_CACHE
475 cpu_cache = *list->cache;
476#endif
477
478 printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
479 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
480 proc_arch[cpu_architecture()], cr_alignment);
481
482 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
483 list->arch_name, ENDIANNESS);
484 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
485 list->elf_name, ENDIANNESS);
486 elf_hwcap = list->elf_hwcap;
487#ifndef CONFIG_ARM_THUMB
488 elf_hwcap &= ~HWCAP_THUMB;
489#endif
490
491 feat_v6_fixup();
492
493 cacheid_init();
494 cpu_init();
495}
496
497void __init dump_machine_table(void)
498{
499 struct machine_desc *p;
500
501 early_print("Available machine support:\n\nID (hex)\tNAME\n");
502 for_each_machine_desc(p)
503 early_print("%08x\t%s\n", p->nr, p->name);
504
505 early_print("\nPlease check your kernel config and/or bootloader.\n");
506
507 while (true)
508 /* can't use cpu_relax() here as it may require MMU setup */;
509}
510
511int __init arm_add_memory(phys_addr_t start, unsigned long size)
512{
513 struct membank *bank = &meminfo.bank[meminfo.nr_banks];
514
515 if (meminfo.nr_banks >= NR_BANKS) {
516 printk(KERN_CRIT "NR_BANKS too low, "
517 "ignoring memory at 0x%08llx\n", (long long)start);
518 return -EINVAL;
519 }
520
521 /*
522 * Ensure that start/size are aligned to a page boundary.
523 * Size is appropriately rounded down, start is rounded up.
524 */
525 size -= start & ~PAGE_MASK;
526 bank->start = PAGE_ALIGN(start);
527
528#ifndef CONFIG_LPAE
529 if (bank->start + size < bank->start) {
530 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
531 "32-bit physical address space\n", (long long)start);
532 /*
533 * To ensure bank->start + bank->size is representable in
534 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
535 * This means we lose a page after masking.
536 */
537 size = ULONG_MAX - bank->start;
538 }
539#endif
540
541 bank->size = size & PAGE_MASK;
542
543 /*
544 * Check whether this memory region has non-zero size or
545 * invalid node number.
546 */
547 if (bank->size == 0)
548 return -EINVAL;
549
550 meminfo.nr_banks++;
551 return 0;
552}
553
554/*
555 * Pick out the memory size. We look for mem=size@start,
556 * where start and size are "size[KkMm]"
557 */
558static int __init early_mem(char *p)
559{
560 static int usermem __initdata = 0;
561 unsigned long size;
562 phys_addr_t start;
563 char *endp;
564
565 /*
566 * If the user specifies memory size, we
567 * blow away any automatically generated
568 * size.
569 */
570 if (usermem == 0) {
571 usermem = 1;
572 meminfo.nr_banks = 0;
573 }
574
575 start = PHYS_OFFSET;
576 size = memparse(p, &endp);
577 if (*endp == '@')
578 start = memparse(endp + 1, NULL);
579
580 arm_add_memory(start, size);
581
582 return 0;
583}
584early_param("mem", early_mem);
585
586static void __init
587setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
588{
589#ifdef CONFIG_BLK_DEV_RAM
590 extern int rd_size, rd_image_start, rd_prompt, rd_doload;
591
592 rd_image_start = image_start;
593 rd_prompt = prompt;
594 rd_doload = doload;
595
596 if (rd_sz)
597 rd_size = rd_sz;
598#endif
599}
600
601static void __init request_standard_resources(struct machine_desc *mdesc)
602{
603 struct memblock_region *region;
604 struct resource *res;
605
606 kernel_code.start = virt_to_phys(_text);
607 kernel_code.end = virt_to_phys(_etext - 1);
608 kernel_data.start = virt_to_phys(_sdata);
609 kernel_data.end = virt_to_phys(_end - 1);
610
611 for_each_memblock(memory, region) {
612 res = alloc_bootmem_low(sizeof(*res));
613 res->name = "System RAM";
614 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
615 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
616 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
617
618 request_resource(&iomem_resource, res);
619
620 if (kernel_code.start >= res->start &&
621 kernel_code.end <= res->end)
622 request_resource(res, &kernel_code);
623 if (kernel_data.start >= res->start &&
624 kernel_data.end <= res->end)
625 request_resource(res, &kernel_data);
626 }
627
628 if (mdesc->video_start) {
629 video_ram.start = mdesc->video_start;
630 video_ram.end = mdesc->video_end;
631 request_resource(&iomem_resource, &video_ram);
632 }
633
634 /*
635 * Some machines don't have the possibility of ever
636 * possessing lp0, lp1 or lp2
637 */
638 if (mdesc->reserve_lp0)
639 request_resource(&ioport_resource, &lp0);
640 if (mdesc->reserve_lp1)
641 request_resource(&ioport_resource, &lp1);
642 if (mdesc->reserve_lp2)
643 request_resource(&ioport_resource, &lp2);
644}
645
646/*
647 * Tag parsing.
648 *
649 * This is the new way of passing data to the kernel at boot time. Rather
650 * than passing a fixed inflexible structure to the kernel, we pass a list
651 * of variable-sized tags to the kernel. The first tag must be a ATAG_CORE
652 * tag for the list to be recognised (to distinguish the tagged list from
653 * a param_struct). The list is terminated with a zero-length tag (this tag
654 * is not parsed in any way).
655 */
656static int __init parse_tag_core(const struct tag *tag)
657{
658 if (tag->hdr.size > 2) {
659 if ((tag->u.core.flags & 1) == 0)
660 root_mountflags &= ~MS_RDONLY;
661 ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
662 }
663 return 0;
664}
665
666__tagtable(ATAG_CORE, parse_tag_core);
667
668static int __init parse_tag_mem32(const struct tag *tag)
669{
670 return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
671}
672
673__tagtable(ATAG_MEM, parse_tag_mem32);
674
675#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
676struct screen_info screen_info = {
677 .orig_video_lines = 30,
678 .orig_video_cols = 80,
679 .orig_video_mode = 0,
680 .orig_video_ega_bx = 0,
681 .orig_video_isVGA = 1,
682 .orig_video_points = 8
683};
684
685static int __init parse_tag_videotext(const struct tag *tag)
686{
687 screen_info.orig_x = tag->u.videotext.x;
688 screen_info.orig_y = tag->u.videotext.y;
689 screen_info.orig_video_page = tag->u.videotext.video_page;
690 screen_info.orig_video_mode = tag->u.videotext.video_mode;
691 screen_info.orig_video_cols = tag->u.videotext.video_cols;
692 screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
693 screen_info.orig_video_lines = tag->u.videotext.video_lines;
694 screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
695 screen_info.orig_video_points = tag->u.videotext.video_points;
696 return 0;
697}
698
699__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
700#endif
701
702static int __init parse_tag_ramdisk(const struct tag *tag)
703{
704 setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
705 (tag->u.ramdisk.flags & 2) == 0,
706 tag->u.ramdisk.start, tag->u.ramdisk.size);
707 return 0;
708}
709
710__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
711
712static int __init parse_tag_serialnr(const struct tag *tag)
713{
714 system_serial_low = tag->u.serialnr.low;
715 system_serial_high = tag->u.serialnr.high;
716 return 0;
717}
718
719__tagtable(ATAG_SERIAL, parse_tag_serialnr);
720
721static int __init parse_tag_revision(const struct tag *tag)
722{
723 system_rev = tag->u.revision.rev;
724 return 0;
725}
726
727__tagtable(ATAG_REVISION, parse_tag_revision);
728
729static int __init parse_tag_cmdline(const struct tag *tag)
730{
731#if defined(CONFIG_CMDLINE_EXTEND)
732 strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
733 strlcat(default_command_line, tag->u.cmdline.cmdline,
734 COMMAND_LINE_SIZE);
735#elif defined(CONFIG_CMDLINE_FORCE)
736 pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
737#else
738 strlcpy(default_command_line, tag->u.cmdline.cmdline,
739 COMMAND_LINE_SIZE);
740#endif
741 return 0;
742}
743
744__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
745
746/*
747 * Scan the tag table for this tag, and call its parse function.
748 * The tag table is built by the linker from all the __tagtable
749 * declarations.
750 */
751static int __init parse_tag(const struct tag *tag)
752{
753 extern struct tagtable __tagtable_begin, __tagtable_end;
754 struct tagtable *t;
755
756 for (t = &__tagtable_begin; t < &__tagtable_end; t++)
757 if (tag->hdr.tag == t->tag) {
758 t->parse(tag);
759 break;
760 }
761
762 return t < &__tagtable_end;
763}
764
765/*
766 * Parse all tags in the list, checking both the global and architecture
767 * specific tag tables.
768 */
769static void __init parse_tags(const struct tag *t)
770{
771 for (; t->hdr.size; t = tag_next(t))
772 if (!parse_tag(t))
773 printk(KERN_WARNING
774 "Ignoring unrecognised tag 0x%08x\n",
775 t->hdr.tag);
776}
777
778/*
779 * This holds our defaults.
780 */
781static struct init_tags {
782 struct tag_header hdr1;
783 struct tag_core core;
784 struct tag_header hdr2;
785 struct tag_mem32 mem;
786 struct tag_header hdr3;
787} init_tags __initdata = {
788 { tag_size(tag_core), ATAG_CORE },
789 { 1, PAGE_SIZE, 0xff },
790 { tag_size(tag_mem32), ATAG_MEM },
791 { MEM_SIZE },
792 { 0, ATAG_NONE }
793};
794
795static int __init customize_machine(void)
796{
797 /* customizes platform devices, or adds new ones */
798 if (machine_desc->init_machine)
799 machine_desc->init_machine();
800 return 0;
801}
802arch_initcall(customize_machine);
803
804static int __init init_machine_late(void)
805{
806 if (machine_desc->init_late)
807 machine_desc->init_late();
808 return 0;
809}
810late_initcall(init_machine_late);
811
812#ifdef CONFIG_KEXEC
813static inline unsigned long long get_total_mem(void)
814{
815 unsigned long total;
816
817 total = max_low_pfn - min_low_pfn;
818 return total << PAGE_SHIFT;
819}
820
821/**
822 * reserve_crashkernel() - reserves memory are for crash kernel
823 *
824 * This function reserves memory area given in "crashkernel=" kernel command
825 * line parameter. The memory reserved is used by a dump capture kernel when
826 * primary kernel is crashing.
827 */
828static void __init reserve_crashkernel(void)
829{
830 unsigned long long crash_size, crash_base;
831 unsigned long long total_mem;
832 int ret;
833
834 total_mem = get_total_mem();
835 ret = parse_crashkernel(boot_command_line, total_mem,
836 &crash_size, &crash_base);
837 if (ret)
838 return;
839
840 ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
841 if (ret < 0) {
842 printk(KERN_WARNING "crashkernel reservation failed - "
843 "memory is in use (0x%lx)\n", (unsigned long)crash_base);
844 return;
845 }
846
847 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
848 "for crashkernel (System RAM: %ldMB)\n",
849 (unsigned long)(crash_size >> 20),
850 (unsigned long)(crash_base >> 20),
851 (unsigned long)(total_mem >> 20));
852
853 crashk_res.start = crash_base;
854 crashk_res.end = crash_base + crash_size - 1;
855 insert_resource(&iomem_resource, &crashk_res);
856}
857#else
858static inline void reserve_crashkernel(void) {}
859#endif /* CONFIG_KEXEC */
860
861static void __init squash_mem_tags(struct tag *tag)
862{
863 for (; tag->hdr.size; tag = tag_next(tag))
864 if (tag->hdr.tag == ATAG_MEM)
865 tag->hdr.tag = ATAG_NONE;
866}
867
868static struct machine_desc * __init setup_machine_tags(unsigned int nr)
869{
870 struct tag *tags = (struct tag *)&init_tags;
871 struct machine_desc *mdesc = NULL, *p;
872 char *from = default_command_line;
873
874 init_tags.mem.start = PHYS_OFFSET;
875
876 /*
877 * locate machine in the list of supported machines.
878 */
879 for_each_machine_desc(p)
880 if (nr == p->nr) {
881 printk("Machine: %s\n", p->name);
882 mdesc = p;
883 break;
884 }
885
886 if (!mdesc) {
887 early_print("\nError: unrecognized/unsupported machine ID"
888 " (r1 = 0x%08x).\n\n", nr);
889 dump_machine_table(); /* does not return */
890 }
891
892 if (__atags_pointer)
893 tags = phys_to_virt(__atags_pointer);
894 else if (mdesc->atag_offset)
895 tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
896
897#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
898 /*
899 * If we have the old style parameters, convert them to
900 * a tag list.
901 */
902 if (tags->hdr.tag != ATAG_CORE)
903 convert_to_tag_list(tags);
904#endif
905
906 if (tags->hdr.tag != ATAG_CORE) {
907#if defined(CONFIG_OF)
908 /*
909 * If CONFIG_OF is set, then assume this is a reasonably
910 * modern system that should pass boot parameters
911 */
912 early_print("Warning: Neither atags nor dtb found\n");
913#endif
914 tags = (struct tag *)&init_tags;
915 }
916
917 if (mdesc->fixup)
918 mdesc->fixup(tags, &from, &meminfo);
919
920 if (tags->hdr.tag == ATAG_CORE) {
921 if (meminfo.nr_banks != 0)
922 squash_mem_tags(tags);
923 save_atags(tags);
924 parse_tags(tags);
925 }
926
927 /* parse_early_param needs a boot_command_line */
928 strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
929
930 return mdesc;
931}
932
933static int __init meminfo_cmp(const void *_a, const void *_b)
934{
935 const struct membank *a = _a, *b = _b;
936 long cmp = bank_pfn_start(a) - bank_pfn_start(b);
937 return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
938}
939
940void __init setup_arch(char **cmdline_p)
941{
942 struct machine_desc *mdesc;
943
944 setup_processor();
945 mdesc = setup_machine_fdt(__atags_pointer);
946 if (!mdesc)
947 mdesc = setup_machine_tags(machine_arch_type);
948 machine_desc = mdesc;
949 machine_name = mdesc->name;
950
951 setup_dma_zone(mdesc);
952
953 if (mdesc->restart_mode)
954 reboot_setup(&mdesc->restart_mode);
955
956 init_mm.start_code = (unsigned long) _text;
957 init_mm.end_code = (unsigned long) _etext;
958 init_mm.end_data = (unsigned long) _edata;
959 init_mm.brk = (unsigned long) _end;
960
961 /* populate cmd_line too for later use, preserving boot_command_line */
962 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
963 *cmdline_p = cmd_line;
964
965 parse_early_param();
966
967 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
968 sanity_check_meminfo();
969 arm_memblock_init(&meminfo, mdesc);
970
971 paging_init(mdesc);
972 request_standard_resources(mdesc);
973
974 if (mdesc->restart)
975 arm_pm_restart = mdesc->restart;
976
977 unflatten_device_tree();
978
979#ifdef CONFIG_SMP
980 if (is_smp())
981 smp_init_cpus();
982#endif
983 reserve_crashkernel();
984
985 tcm_init();
986
987#ifdef CONFIG_MULTI_IRQ_HANDLER
988 handle_arch_irq = mdesc->handle_irq;
989#endif
990
991#ifdef CONFIG_VT
992#if defined(CONFIG_VGA_CONSOLE)
993 conswitchp = &vga_con;
994#elif defined(CONFIG_DUMMY_CONSOLE)
995 conswitchp = &dummy_con;
996#endif
997#endif
998
999 if (mdesc->init_early)
1000 mdesc->init_early();
1001}
1002
1003
1004static int __init topology_init(void)
1005{
1006 int cpu;
1007
1008 for_each_possible_cpu(cpu) {
1009 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
1010 cpuinfo->cpu.hotpluggable = 1;
1011 register_cpu(&cpuinfo->cpu, cpu);
1012 }
1013
1014 return 0;
1015}
1016subsys_initcall(topology_init);
1017
1018#ifdef CONFIG_HAVE_PROC_CPU
1019static int __init proc_cpu_init(void)
1020{
1021 struct proc_dir_entry *res;
1022
1023 res = proc_mkdir("cpu", NULL);
1024 if (!res)
1025 return -ENOMEM;
1026 return 0;
1027}
1028fs_initcall(proc_cpu_init);
1029#endif
1030
1031static const char *hwcap_str[] = {
1032 "swp",
1033 "half",
1034 "thumb",
1035 "26bit",
1036 "fastmult",
1037 "fpa",
1038 "vfp",
1039 "edsp",
1040 "java",
1041 "iwmmxt",
1042 "crunch",
1043 "thumbee",
1044 "neon",
1045 "vfpv3",
1046 "vfpv3d16",
1047 "tls",
1048 "vfpv4",
1049 "idiva",
1050 "idivt",
1051 NULL
1052};
1053
1054static int c_show(struct seq_file *m, void *v)
1055{
1056 int i;
1057
1058 seq_printf(m, "Processor\t: %s rev %d (%s)\n",
1059 cpu_name, read_cpuid_id() & 15, elf_platform);
1060
1061#if defined(CONFIG_SMP)
1062 for_each_online_cpu(i) {
1063 /*
1064 * glibc reads /proc/cpuinfo to determine the number of
1065 * online processors, looking for lines beginning with
1066 * "processor". Give glibc what it expects.
1067 */
1068 seq_printf(m, "processor\t: %d\n", i);
1069 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
1070 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1071 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1072 }
1073#else /* CONFIG_SMP */
1074 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1075 loops_per_jiffy / (500000/HZ),
1076 (loops_per_jiffy / (5000/HZ)) % 100);
1077#endif
1078
1079 /* dump out the processor features */
1080 seq_puts(m, "Features\t: ");
1081
1082 for (i = 0; hwcap_str[i]; i++)
1083 if (elf_hwcap & (1 << i))
1084 seq_printf(m, "%s ", hwcap_str[i]);
1085
1086 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
1087 seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
1088
1089 if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
1090 /* pre-ARM7 */
1091 seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
1092 } else {
1093 if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
1094 /* ARM7 */
1095 seq_printf(m, "CPU variant\t: 0x%02x\n",
1096 (read_cpuid_id() >> 16) & 127);
1097 } else {
1098 /* post-ARM7 */
1099 seq_printf(m, "CPU variant\t: 0x%x\n",
1100 (read_cpuid_id() >> 20) & 15);
1101 }
1102 seq_printf(m, "CPU part\t: 0x%03x\n",
1103 (read_cpuid_id() >> 4) & 0xfff);
1104 }
1105 seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
1106
1107 seq_puts(m, "\n");
1108
1109 seq_printf(m, "Hardware\t: %s\n", machine_name);
1110 seq_printf(m, "Revision\t: %04x\n", system_rev);
1111 seq_printf(m, "Serial\t\t: %08x%08x\n",
1112 system_serial_high, system_serial_low);
1113
1114 return 0;
1115}
1116
1117static void *c_start(struct seq_file *m, loff_t *pos)
1118{
1119 return *pos < 1 ? (void *)1 : NULL;
1120}
1121
1122static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1123{
1124 ++*pos;
1125 return NULL;
1126}
1127
1128static void c_stop(struct seq_file *m, void *v)
1129{
1130}
1131
1132const struct seq_operations cpuinfo_op = {
1133 .start = c_start,
1134 .next = c_next,
1135 .stop = c_stop,
1136 .show = c_show
1137};