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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 */
5
6/**
7 * DOC: VC4 DSI0/DSI1 module
8 *
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
11 * controller.
12 *
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
15 *
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
18 * hopefully present.
19 */
20
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23#include <linux/completion.h>
24#include <linux/component.h>
25#include <linux/dma-mapping.h>
26#include <linux/dmaengine.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_simple_kms_helper.h>
41
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45#define DSI_CMD_FIFO_DEPTH 16
46#define DSI_PIX_FIFO_DEPTH 256
47#define DSI_PIX_FIFO_WIDTH 4
48
49#define DSI0_CTRL 0x00
50
51/* Command packet control. */
52#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
53#define DSI1_TXPKT1C 0x04
54# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
55# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
56# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
57# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
58
59# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
60# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
61/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
63/* Primary display where cmdfifo provides part of the payload and
64 * pixelvalve the rest.
65 */
66# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
67/* Secondary display where cmdfifo provides part of the payload and
68 * pixfifo the rest.
69 */
70# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
71
72# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
73# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
74
75# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
76# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
77/* Command only. Uses TXPKT1H and DISPLAY_NO */
78# define DSI_TXPKT1C_CMD_CTRL_TX 0
79/* Command with BTA for either ack or read data. */
80# define DSI_TXPKT1C_CMD_CTRL_RX 1
81/* Trigger according to TRIG_CMD */
82# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
83/* BTA alone for getting error status after a command, or a TE trigger
84 * without a previous command.
85 */
86# define DSI_TXPKT1C_CMD_CTRL_BTA 3
87
88# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91# define DSI_TXPKT1C_CMD_EN BIT(0)
92
93/* Command packet header. */
94#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
95#define DSI1_TXPKT1H 0x08
96# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
97# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
98# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
99# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
100# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
101# define DSI_TXPKT1H_BC_DT_SHIFT 0
102
103#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
104#define DSI1_RXPKT1H 0x14
105# define DSI_RXPKT1H_CRC_ERR BIT(31)
106# define DSI_RXPKT1H_DET_ERR BIT(30)
107# define DSI_RXPKT1H_ECC_ERR BIT(29)
108# define DSI_RXPKT1H_COR_ERR BIT(28)
109# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
111/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
113# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
114/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
116# define DSI_RXPKT1H_SHORT_1_SHIFT 16
117# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
118# define DSI_RXPKT1H_SHORT_0_SHIFT 8
119# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
120# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
121
122#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
123#define DSI1_RXPKT2H 0x18
124# define DSI_RXPKT1H_DET_ERR BIT(30)
125# define DSI_RXPKT1H_ECC_ERR BIT(29)
126# define DSI_RXPKT1H_COR_ERR BIT(28)
127# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
128# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
129# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
130# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
131# define DSI_RXPKT1H_DT_SHIFT 0
132
133#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
134#define DSI1_TXPKT_CMD_FIFO 0x1c
135
136#define DSI0_DISP0_CTRL 0x18
137# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
138# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
139# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
140# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
141# define DSI_DISP0_LP_STOP_DISABLE 0
142# define DSI_DISP0_LP_STOP_PERLINE 1
143# define DSI_DISP0_LP_STOP_PERFRAME 2
144
145/* Transmit RGB pixels and null packets only during HACTIVE, instead
146 * of going to LP-STOP.
147 */
148# define DSI_DISP_HACTIVE_NULL BIT(10)
149/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150# define DSI_DISP_VBLP_CTRL BIT(9)
151/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152# define DSI_DISP_HFP_CTRL BIT(8)
153/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154# define DSI_DISP_HBP_CTRL BIT(7)
155# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
156# define DSI_DISP0_CHANNEL_SHIFT 5
157/* Enables end events for HSYNC/VSYNC, not just start events. */
158# define DSI_DISP0_ST_END BIT(4)
159# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
160# define DSI_DISP0_PFORMAT_SHIFT 2
161# define DSI_PFORMAT_RGB565 0
162# define DSI_PFORMAT_RGB666_PACKED 1
163# define DSI_PFORMAT_RGB666 2
164# define DSI_PFORMAT_RGB888 3
165/* Default is VIDEO mode. */
166# define DSI_DISP0_COMMAND_MODE BIT(1)
167# define DSI_DISP0_ENABLE BIT(0)
168
169#define DSI0_DISP1_CTRL 0x1c
170#define DSI1_DISP1_CTRL 0x2c
171/* Format of the data written to TXPKT_PIX_FIFO. */
172# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
173# define DSI_DISP1_PFORMAT_SHIFT 1
174# define DSI_DISP1_PFORMAT_16BIT 0
175# define DSI_DISP1_PFORMAT_24BIT 1
176# define DSI_DISP1_PFORMAT_32BIT_LE 2
177# define DSI_DISP1_PFORMAT_32BIT_BE 3
178
179/* DISP1 is always command mode. */
180# define DSI_DISP1_ENABLE BIT(0)
181
182#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
183
184#define DSI0_INT_STAT 0x24
185#define DSI0_INT_EN 0x28
186# define DSI0_INT_FIFO_ERR BIT(25)
187# define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)
188# define DSI0_INT_CMDC_DONE_SHIFT 23
189# define DSI0_INT_CMDC_DONE_NO_REPEAT 1
190# define DSI0_INT_CMDC_DONE_REPEAT 3
191# define DSI0_INT_PHY_DIR_RTF BIT(22)
192# define DSI0_INT_PHY_D1_ULPS BIT(21)
193# define DSI0_INT_PHY_D1_STOP BIT(20)
194# define DSI0_INT_PHY_RXLPDT BIT(19)
195# define DSI0_INT_PHY_RXTRIG BIT(18)
196# define DSI0_INT_PHY_D0_ULPS BIT(17)
197# define DSI0_INT_PHY_D0_LPDT BIT(16)
198# define DSI0_INT_PHY_D0_FTR BIT(15)
199# define DSI0_INT_PHY_D0_STOP BIT(14)
200/* Signaled when the clock lane enters the given state. */
201# define DSI0_INT_PHY_CLK_ULPS BIT(13)
202# define DSI0_INT_PHY_CLK_HS BIT(12)
203# define DSI0_INT_PHY_CLK_FTR BIT(11)
204/* Signaled on timeouts */
205# define DSI0_INT_PR_TO BIT(10)
206# define DSI0_INT_TA_TO BIT(9)
207# define DSI0_INT_LPRX_TO BIT(8)
208# define DSI0_INT_HSTX_TO BIT(7)
209/* Contention on a line when trying to drive the line low */
210# define DSI0_INT_ERR_CONT_LP1 BIT(6)
211# define DSI0_INT_ERR_CONT_LP0 BIT(5)
212/* Control error: incorrect line state sequence on data lane 0. */
213# define DSI0_INT_ERR_CONTROL BIT(4)
214# define DSI0_INT_ERR_SYNC_ESC BIT(3)
215# define DSI0_INT_RX2_PKT BIT(2)
216# define DSI0_INT_RX1_PKT BIT(1)
217# define DSI0_INT_CMD_PKT BIT(0)
218
219#define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \
220 DSI0_INT_ERR_CONTROL | \
221 DSI0_INT_ERR_CONT_LP0 | \
222 DSI0_INT_ERR_CONT_LP1 | \
223 DSI0_INT_HSTX_TO | \
224 DSI0_INT_LPRX_TO | \
225 DSI0_INT_TA_TO | \
226 DSI0_INT_PR_TO)
227
228# define DSI1_INT_PHY_D3_ULPS BIT(30)
229# define DSI1_INT_PHY_D3_STOP BIT(29)
230# define DSI1_INT_PHY_D2_ULPS BIT(28)
231# define DSI1_INT_PHY_D2_STOP BIT(27)
232# define DSI1_INT_PHY_D1_ULPS BIT(26)
233# define DSI1_INT_PHY_D1_STOP BIT(25)
234# define DSI1_INT_PHY_D0_ULPS BIT(24)
235# define DSI1_INT_PHY_D0_STOP BIT(23)
236# define DSI1_INT_FIFO_ERR BIT(22)
237# define DSI1_INT_PHY_DIR_RTF BIT(21)
238# define DSI1_INT_PHY_RXLPDT BIT(20)
239# define DSI1_INT_PHY_RXTRIG BIT(19)
240# define DSI1_INT_PHY_D0_LPDT BIT(18)
241# define DSI1_INT_PHY_DIR_FTR BIT(17)
242
243/* Signaled when the clock lane enters the given state. */
244# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
245# define DSI1_INT_PHY_CLOCK_HS BIT(15)
246# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
247
248/* Signaled on timeouts */
249# define DSI1_INT_PR_TO BIT(13)
250# define DSI1_INT_TA_TO BIT(12)
251# define DSI1_INT_LPRX_TO BIT(11)
252# define DSI1_INT_HSTX_TO BIT(10)
253
254/* Contention on a line when trying to drive the line low */
255# define DSI1_INT_ERR_CONT_LP1 BIT(9)
256# define DSI1_INT_ERR_CONT_LP0 BIT(8)
257
258/* Control error: incorrect line state sequence on data lane 0. */
259# define DSI1_INT_ERR_CONTROL BIT(7)
260/* LPDT synchronization error (bits received not a multiple of 8. */
261
262# define DSI1_INT_ERR_SYNC_ESC BIT(6)
263/* Signaled after receiving an error packet from the display in
264 * response to a read.
265 */
266# define DSI1_INT_RXPKT2 BIT(5)
267/* Signaled after receiving a packet. The header and optional short
268 * response will be in RXPKT1H, and a long response will be in the
269 * RXPKT_FIFO.
270 */
271# define DSI1_INT_RXPKT1 BIT(4)
272# define DSI1_INT_TXPKT2_DONE BIT(3)
273# define DSI1_INT_TXPKT2_END BIT(2)
274/* Signaled after all repeats of TXPKT1 are transferred. */
275# define DSI1_INT_TXPKT1_DONE BIT(1)
276/* Signaled after each TXPKT1 repeat is scheduled. */
277# define DSI1_INT_TXPKT1_END BIT(0)
278
279#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
280 DSI1_INT_ERR_CONTROL | \
281 DSI1_INT_ERR_CONT_LP0 | \
282 DSI1_INT_ERR_CONT_LP1 | \
283 DSI1_INT_HSTX_TO | \
284 DSI1_INT_LPRX_TO | \
285 DSI1_INT_TA_TO | \
286 DSI1_INT_PR_TO)
287
288#define DSI0_STAT 0x2c
289#define DSI0_HSTX_TO_CNT 0x30
290#define DSI0_LPRX_TO_CNT 0x34
291#define DSI0_TA_TO_CNT 0x38
292#define DSI0_PR_TO_CNT 0x3c
293#define DSI0_PHYC 0x40
294# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
295# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
296# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
297# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
298# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
299# define DSI1_PHYC_CLANE_ULPS BIT(17)
300# define DSI1_PHYC_CLANE_ENABLE BIT(16)
301# define DSI_PHYC_DLANE3_ULPS BIT(13)
302# define DSI_PHYC_DLANE3_ENABLE BIT(12)
303# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
304# define DSI0_PHYC_CLANE_ULPS BIT(9)
305# define DSI_PHYC_DLANE2_ULPS BIT(9)
306# define DSI0_PHYC_CLANE_ENABLE BIT(8)
307# define DSI_PHYC_DLANE2_ENABLE BIT(8)
308# define DSI_PHYC_DLANE1_ULPS BIT(5)
309# define DSI_PHYC_DLANE1_ENABLE BIT(4)
310# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
311# define DSI_PHYC_DLANE0_ULPS BIT(1)
312# define DSI_PHYC_DLANE0_ENABLE BIT(0)
313
314#define DSI0_HS_CLT0 0x44
315#define DSI0_HS_CLT1 0x48
316#define DSI0_HS_CLT2 0x4c
317#define DSI0_HS_DLT3 0x50
318#define DSI0_HS_DLT4 0x54
319#define DSI0_HS_DLT5 0x58
320#define DSI0_HS_DLT6 0x5c
321#define DSI0_HS_DLT7 0x60
322
323#define DSI0_PHY_AFEC0 0x64
324# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
325# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
326# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
327# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
328# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
329# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
330# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
331# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
332# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
333# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
334# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
335# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
336# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
337# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
338# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
339# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
340# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
341# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
342# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
343# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
344# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
345# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
346# define DSI1_PHY_AFEC0_RESET BIT(13)
347# define DSI1_PHY_AFEC0_PD BIT(12)
348# define DSI0_PHY_AFEC0_RESET BIT(11)
349# define DSI1_PHY_AFEC0_PD_BG BIT(11)
350# define DSI0_PHY_AFEC0_PD BIT(10)
351# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
352# define DSI0_PHY_AFEC0_PD_BG BIT(9)
353# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
354# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
355# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
356# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
357# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
358# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
359# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
360
361#define DSI0_PHY_AFEC1 0x68
362# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
363# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
364# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
365# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
366# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
367# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
368
369#define DSI0_TST_SEL 0x6c
370#define DSI0_TST_MON 0x70
371#define DSI0_ID 0x74
372# define DSI_ID_VALUE 0x00647369
373
374#define DSI1_CTRL 0x00
375# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
376# define DSI_CTRL_HS_CLKC_SHIFT 14
377# define DSI_CTRL_HS_CLKC_BYTE 0
378# define DSI_CTRL_HS_CLKC_DDR2 1
379# define DSI_CTRL_HS_CLKC_DDR 2
380
381# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
382# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
383# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
384# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
385# define DSI_CTRL_CAL_BYTE BIT(9)
386# define DSI_CTRL_INV_BYTE BIT(8)
387# define DSI_CTRL_CLR_LDF BIT(7)
388# define DSI0_CTRL_CLR_PBCF BIT(6)
389# define DSI1_CTRL_CLR_RXF BIT(6)
390# define DSI0_CTRL_CLR_CPBCF BIT(5)
391# define DSI1_CTRL_CLR_PDF BIT(5)
392# define DSI0_CTRL_CLR_PDF BIT(4)
393# define DSI1_CTRL_CLR_CDF BIT(4)
394# define DSI0_CTRL_CLR_CDF BIT(3)
395# define DSI0_CTRL_CTRL2 BIT(2)
396# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
397# define DSI0_CTRL_CTRL1 BIT(1)
398# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
399# define DSI0_CTRL_CTRL0 BIT(0)
400# define DSI1_CTRL_EN BIT(0)
401# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
402 DSI0_CTRL_CLR_PBCF | \
403 DSI0_CTRL_CLR_CPBCF | \
404 DSI0_CTRL_CLR_PDF | \
405 DSI0_CTRL_CLR_CDF)
406# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
407 DSI1_CTRL_CLR_RXF | \
408 DSI1_CTRL_CLR_PDF | \
409 DSI1_CTRL_CLR_CDF)
410
411#define DSI1_TXPKT2C 0x0c
412#define DSI1_TXPKT2H 0x10
413#define DSI1_TXPKT_PIX_FIFO 0x20
414#define DSI1_RXPKT_FIFO 0x24
415#define DSI1_DISP0_CTRL 0x28
416#define DSI1_INT_STAT 0x30
417#define DSI1_INT_EN 0x34
418/* State reporting bits. These mostly behave like INT_STAT, where
419 * writing a 1 clears the bit.
420 */
421#define DSI1_STAT 0x38
422# define DSI1_STAT_PHY_D3_ULPS BIT(31)
423# define DSI1_STAT_PHY_D3_STOP BIT(30)
424# define DSI1_STAT_PHY_D2_ULPS BIT(29)
425# define DSI1_STAT_PHY_D2_STOP BIT(28)
426# define DSI1_STAT_PHY_D1_ULPS BIT(27)
427# define DSI1_STAT_PHY_D1_STOP BIT(26)
428# define DSI1_STAT_PHY_D0_ULPS BIT(25)
429# define DSI1_STAT_PHY_D0_STOP BIT(24)
430# define DSI1_STAT_FIFO_ERR BIT(23)
431# define DSI1_STAT_PHY_RXLPDT BIT(22)
432# define DSI1_STAT_PHY_RXTRIG BIT(21)
433# define DSI1_STAT_PHY_D0_LPDT BIT(20)
434/* Set when in forward direction */
435# define DSI1_STAT_PHY_DIR BIT(19)
436# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
437# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
438# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
439# define DSI1_STAT_PR_TO BIT(15)
440# define DSI1_STAT_TA_TO BIT(14)
441# define DSI1_STAT_LPRX_TO BIT(13)
442# define DSI1_STAT_HSTX_TO BIT(12)
443# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
444# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
445# define DSI1_STAT_ERR_CONTROL BIT(9)
446# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
447# define DSI1_STAT_RXPKT2 BIT(7)
448# define DSI1_STAT_RXPKT1 BIT(6)
449# define DSI1_STAT_TXPKT2_BUSY BIT(5)
450# define DSI1_STAT_TXPKT2_DONE BIT(4)
451# define DSI1_STAT_TXPKT2_END BIT(3)
452# define DSI1_STAT_TXPKT1_BUSY BIT(2)
453# define DSI1_STAT_TXPKT1_DONE BIT(1)
454# define DSI1_STAT_TXPKT1_END BIT(0)
455
456#define DSI1_HSTX_TO_CNT 0x3c
457#define DSI1_LPRX_TO_CNT 0x40
458#define DSI1_TA_TO_CNT 0x44
459#define DSI1_PR_TO_CNT 0x48
460#define DSI1_PHYC 0x4c
461
462#define DSI1_HS_CLT0 0x50
463# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
464# define DSI_HS_CLT0_CZERO_SHIFT 18
465# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
466# define DSI_HS_CLT0_CPRE_SHIFT 9
467# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
468# define DSI_HS_CLT0_CPREP_SHIFT 0
469
470#define DSI1_HS_CLT1 0x54
471# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
472# define DSI_HS_CLT1_CTRAIL_SHIFT 9
473# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
474# define DSI_HS_CLT1_CPOST_SHIFT 0
475
476#define DSI1_HS_CLT2 0x58
477# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
478# define DSI_HS_CLT2_WUP_SHIFT 0
479
480#define DSI1_HS_DLT3 0x5c
481# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
482# define DSI_HS_DLT3_EXIT_SHIFT 18
483# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
484# define DSI_HS_DLT3_ZERO_SHIFT 9
485# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
486# define DSI_HS_DLT3_PRE_SHIFT 0
487
488#define DSI1_HS_DLT4 0x60
489# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
490# define DSI_HS_DLT4_ANLAT_SHIFT 18
491# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
492# define DSI_HS_DLT4_TRAIL_SHIFT 9
493# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
494# define DSI_HS_DLT4_LPX_SHIFT 0
495
496#define DSI1_HS_DLT5 0x64
497# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
498# define DSI_HS_DLT5_INIT_SHIFT 0
499
500#define DSI1_HS_DLT6 0x68
501# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
502# define DSI_HS_DLT6_TA_GET_SHIFT 24
503# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
504# define DSI_HS_DLT6_TA_SURE_SHIFT 16
505# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
506# define DSI_HS_DLT6_TA_GO_SHIFT 8
507# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
508# define DSI_HS_DLT6_LP_LPX_SHIFT 0
509
510#define DSI1_HS_DLT7 0x6c
511# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
512# define DSI_HS_DLT7_LP_WUP_SHIFT 0
513
514#define DSI1_PHY_AFEC0 0x70
515
516#define DSI1_PHY_AFEC1 0x74
517# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
518# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
519# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
520# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
521# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
522# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
523# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
524# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
525# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
526# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
527
528#define DSI1_TST_SEL 0x78
529#define DSI1_TST_MON 0x7c
530#define DSI1_PHY_TST1 0x80
531#define DSI1_PHY_TST2 0x84
532#define DSI1_PHY_FIFO_STAT 0x88
533/* Actually, all registers in the range that aren't otherwise claimed
534 * will return the ID.
535 */
536#define DSI1_ID 0x8c
537
538struct vc4_dsi_variant {
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
540 unsigned int port;
541
542 bool broken_axi_workaround;
543
544 const char *debugfs_name;
545 const struct debugfs_reg32 *regs;
546 size_t nregs;
547
548};
549
550/* General DSI hardware state. */
551struct vc4_dsi {
552 struct vc4_encoder encoder;
553 struct mipi_dsi_host dsi_host;
554
555 struct kref kref;
556
557 struct platform_device *pdev;
558
559 struct drm_bridge *out_bridge;
560 struct drm_bridge bridge;
561
562 void __iomem *regs;
563
564 struct dma_chan *reg_dma_chan;
565 dma_addr_t reg_dma_paddr;
566 u32 *reg_dma_mem;
567 dma_addr_t reg_paddr;
568
569 const struct vc4_dsi_variant *variant;
570
571 /* DSI channel for the panel we're connected to. */
572 u32 channel;
573 u32 lanes;
574 u32 format;
575 u32 divider;
576 u32 mode_flags;
577
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
579 * escape clock.
580 */
581 struct clk *escape_clock;
582
583 /* Input clock to the analog PHY, used to generate the DSI bit
584 * clock.
585 */
586 struct clk *pll_phy_clock;
587
588 /* HS Clocks generated within the DSI analog PHY. */
589 struct clk_fixed_factor phy_clocks[3];
590
591 struct clk_hw_onecell_data *clk_onecell;
592
593 /* Pixel clock output to the pixelvalve, generated from the HS
594 * clock.
595 */
596 struct clk *pixel_clock;
597
598 struct completion xfer_completion;
599 int xfer_result;
600
601 struct debugfs_regset32 regset;
602};
603
604#define host_to_dsi(host) \
605 container_of_const(host, struct vc4_dsi, dsi_host)
606
607#define to_vc4_dsi(_encoder) \
608 container_of_const(_encoder, struct vc4_dsi, encoder.base)
609
610#define bridge_to_vc4_dsi(_bridge) \
611 container_of_const(_bridge, struct vc4_dsi, bridge)
612
613static inline void
614dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
615{
616 struct dma_chan *chan = dsi->reg_dma_chan;
617 struct dma_async_tx_descriptor *tx;
618 dma_cookie_t cookie;
619 int ret;
620
621 kunit_fail_current_test("Accessing a register in a unit test!\n");
622
623 /* DSI0 should be able to write normally. */
624 if (!chan) {
625 writel(val, dsi->regs + offset);
626 return;
627 }
628
629 *dsi->reg_dma_mem = val;
630
631 tx = chan->device->device_prep_dma_memcpy(chan,
632 dsi->reg_paddr + offset,
633 dsi->reg_dma_paddr,
634 4, 0);
635 if (!tx) {
636 DRM_ERROR("Failed to set up DMA register write\n");
637 return;
638 }
639
640 cookie = tx->tx_submit(tx);
641 ret = dma_submit_error(cookie);
642 if (ret) {
643 DRM_ERROR("Failed to submit DMA: %d\n", ret);
644 return;
645 }
646 ret = dma_sync_wait(chan, cookie);
647 if (ret)
648 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
649}
650
651#define DSI_READ(offset) \
652 ({ \
653 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
654 readl(dsi->regs + (offset)); \
655 })
656
657#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
658#define DSI_PORT_READ(offset) \
659 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
660#define DSI_PORT_WRITE(offset, val) \
661 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
662#define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
663
664static const struct debugfs_reg32 dsi0_regs[] = {
665 VC4_REG32(DSI0_CTRL),
666 VC4_REG32(DSI0_STAT),
667 VC4_REG32(DSI0_HSTX_TO_CNT),
668 VC4_REG32(DSI0_LPRX_TO_CNT),
669 VC4_REG32(DSI0_TA_TO_CNT),
670 VC4_REG32(DSI0_PR_TO_CNT),
671 VC4_REG32(DSI0_DISP0_CTRL),
672 VC4_REG32(DSI0_DISP1_CTRL),
673 VC4_REG32(DSI0_INT_STAT),
674 VC4_REG32(DSI0_INT_EN),
675 VC4_REG32(DSI0_PHYC),
676 VC4_REG32(DSI0_HS_CLT0),
677 VC4_REG32(DSI0_HS_CLT1),
678 VC4_REG32(DSI0_HS_CLT2),
679 VC4_REG32(DSI0_HS_DLT3),
680 VC4_REG32(DSI0_HS_DLT4),
681 VC4_REG32(DSI0_HS_DLT5),
682 VC4_REG32(DSI0_HS_DLT6),
683 VC4_REG32(DSI0_HS_DLT7),
684 VC4_REG32(DSI0_PHY_AFEC0),
685 VC4_REG32(DSI0_PHY_AFEC1),
686 VC4_REG32(DSI0_ID),
687};
688
689static const struct debugfs_reg32 dsi1_regs[] = {
690 VC4_REG32(DSI1_CTRL),
691 VC4_REG32(DSI1_STAT),
692 VC4_REG32(DSI1_HSTX_TO_CNT),
693 VC4_REG32(DSI1_LPRX_TO_CNT),
694 VC4_REG32(DSI1_TA_TO_CNT),
695 VC4_REG32(DSI1_PR_TO_CNT),
696 VC4_REG32(DSI1_DISP0_CTRL),
697 VC4_REG32(DSI1_DISP1_CTRL),
698 VC4_REG32(DSI1_INT_STAT),
699 VC4_REG32(DSI1_INT_EN),
700 VC4_REG32(DSI1_PHYC),
701 VC4_REG32(DSI1_HS_CLT0),
702 VC4_REG32(DSI1_HS_CLT1),
703 VC4_REG32(DSI1_HS_CLT2),
704 VC4_REG32(DSI1_HS_DLT3),
705 VC4_REG32(DSI1_HS_DLT4),
706 VC4_REG32(DSI1_HS_DLT5),
707 VC4_REG32(DSI1_HS_DLT6),
708 VC4_REG32(DSI1_HS_DLT7),
709 VC4_REG32(DSI1_PHY_AFEC0),
710 VC4_REG32(DSI1_PHY_AFEC1),
711 VC4_REG32(DSI1_ID),
712};
713
714static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
715{
716 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
717
718 if (latch)
719 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
720 else
721 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
722
723 DSI_PORT_WRITE(PHY_AFEC0, afec0);
724}
725
726/* Enters or exits Ultra Low Power State. */
727static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
728{
729 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
730 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
731 DSI_PHYC_DLANE0_ULPS |
732 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
733 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
734 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
735 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
736 DSI1_STAT_PHY_D0_ULPS |
737 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
738 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
739 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
740 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
741 DSI1_STAT_PHY_D0_STOP |
742 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
743 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
744 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
745 int ret;
746 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
747 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
748
749 if (ulps == ulps_currently_enabled)
750 return;
751
752 DSI_PORT_WRITE(STAT, stat_ulps);
753 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
754 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
755 if (ret) {
756 dev_warn(&dsi->pdev->dev,
757 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
758 DSI_PORT_READ(STAT));
759 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
760 vc4_dsi_latch_ulps(dsi, false);
761 return;
762 }
763
764 /* The DSI module can't be disabled while the module is
765 * generating ULPS state. So, to be able to disable the
766 * module, we have the AFE latch the ULPS state and continue
767 * on to having the module enter STOP.
768 */
769 vc4_dsi_latch_ulps(dsi, ulps);
770
771 DSI_PORT_WRITE(STAT, stat_stop);
772 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
773 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
774 if (ret) {
775 dev_warn(&dsi->pdev->dev,
776 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
777 DSI_PORT_READ(STAT));
778 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
779 return;
780 }
781}
782
783static u32
784dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
785{
786 /* The HS timings have to be rounded up to a multiple of 8
787 * because we're using the byte clock.
788 */
789 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
790}
791
792/* ESC always runs at 100Mhz. */
793#define ESC_TIME_NS 10
794
795static u32
796dsi_esc_timing(u32 ns)
797{
798 return DIV_ROUND_UP(ns, ESC_TIME_NS);
799}
800
801static void vc4_dsi_bridge_disable(struct drm_bridge *bridge,
802 struct drm_bridge_state *state)
803{
804 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
805 u32 disp0_ctrl;
806
807 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
808 disp0_ctrl &= ~DSI_DISP0_ENABLE;
809 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
810}
811
812static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge,
813 struct drm_bridge_state *state)
814{
815 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
816 struct device *dev = &dsi->pdev->dev;
817
818 clk_disable_unprepare(dsi->pll_phy_clock);
819 clk_disable_unprepare(dsi->escape_clock);
820 clk_disable_unprepare(dsi->pixel_clock);
821
822 pm_runtime_put(dev);
823}
824
825/* Extends the mode's blank intervals to handle BCM2835's integer-only
826 * DSI PLL divider.
827 *
828 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
829 * driver since most peripherals are hanging off of the PLLD_PER
830 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
831 * the pixel clock), only has an integer divider off of DSI.
832 *
833 * To get our panel mode to refresh at the expected 60Hz, we need to
834 * extend the horizontal blank time. This means we drive a
835 * higher-than-expected clock rate to the panel, but that's what the
836 * firmware does too.
837 */
838static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
839 const struct drm_display_mode *mode,
840 struct drm_display_mode *adjusted_mode)
841{
842 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
843 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
844 unsigned long parent_rate = clk_get_rate(phy_parent);
845 unsigned long pixel_clock_hz = mode->clock * 1000;
846 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
847 int divider;
848
849 /* Find what divider gets us a faster clock than the requested
850 * pixel clock.
851 */
852 for (divider = 1; divider < 255; divider++) {
853 if (parent_rate / (divider + 1) < pll_clock)
854 break;
855 }
856
857 /* Now that we've picked a PLL divider, calculate back to its
858 * pixel clock.
859 */
860 pll_clock = parent_rate / divider;
861 pixel_clock_hz = pll_clock / dsi->divider;
862
863 adjusted_mode->clock = pixel_clock_hz / 1000;
864
865 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
866 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
867 mode->clock;
868 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
869 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
870
871 return true;
872}
873
874static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge,
875 struct drm_bridge_state *old_state)
876{
877 struct drm_atomic_state *state = old_state->base.state;
878 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
879 const struct drm_crtc_state *crtc_state;
880 struct device *dev = &dsi->pdev->dev;
881 const struct drm_display_mode *mode;
882 struct drm_connector *connector;
883 bool debug_dump_regs = false;
884 unsigned long hs_clock;
885 struct drm_crtc *crtc;
886 u32 ui_ns;
887 /* Minimum LP state duration in escape clock cycles. */
888 u32 lpx = dsi_esc_timing(60);
889 unsigned long pixel_clock_hz;
890 unsigned long dsip_clock;
891 unsigned long phy_clock;
892 int ret;
893
894 ret = pm_runtime_resume_and_get(dev);
895 if (ret) {
896 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
897 return;
898 }
899
900 if (debug_dump_regs) {
901 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
902 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
903 drm_print_regset32(&p, &dsi->regset);
904 }
905
906 /*
907 * Retrieve the CRTC adjusted mode. This requires a little dance to go
908 * from the bridge to the encoder, to the connector and to the CRTC.
909 */
910 connector = drm_atomic_get_new_connector_for_encoder(state,
911 bridge->encoder);
912 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
913 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
914 mode = &crtc_state->adjusted_mode;
915
916 pixel_clock_hz = mode->clock * 1000;
917
918 /* Round up the clk_set_rate() request slightly, since
919 * PLLD_DSI1 is an integer divider and its rate selection will
920 * never round up.
921 */
922 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
923 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
924 if (ret) {
925 dev_err(&dsi->pdev->dev,
926 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
927 }
928
929 /* Reset the DSI and all its fifos. */
930 DSI_PORT_WRITE(CTRL,
931 DSI_CTRL_SOFT_RESET_CFG |
932 DSI_PORT_BIT(CTRL_RESET_FIFOS));
933
934 DSI_PORT_WRITE(CTRL,
935 DSI_CTRL_HSDT_EOT_DISABLE |
936 DSI_CTRL_RX_LPDT_EOT_DISABLE);
937
938 /* Clear all stat bits so we see what has happened during enable. */
939 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
940
941 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
942 if (dsi->variant->port == 0) {
943 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
944 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
945
946 if (dsi->lanes < 2)
947 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
948
949 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
950 afec0 |= DSI0_PHY_AFEC0_RESET;
951
952 DSI_PORT_WRITE(PHY_AFEC0, afec0);
953
954 /* AFEC reset hold time */
955 mdelay(1);
956
957 DSI_PORT_WRITE(PHY_AFEC1,
958 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
959 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
960 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
961 } else {
962 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
963 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
964 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
965 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
966 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
967 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
968 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
969
970 if (dsi->lanes < 4)
971 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
972 if (dsi->lanes < 3)
973 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
974 if (dsi->lanes < 2)
975 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
976
977 afec0 |= DSI1_PHY_AFEC0_RESET;
978
979 DSI_PORT_WRITE(PHY_AFEC0, afec0);
980
981 DSI_PORT_WRITE(PHY_AFEC1, 0);
982
983 /* AFEC reset hold time */
984 mdelay(1);
985 }
986
987 ret = clk_prepare_enable(dsi->escape_clock);
988 if (ret) {
989 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
990 return;
991 }
992
993 ret = clk_prepare_enable(dsi->pll_phy_clock);
994 if (ret) {
995 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
996 return;
997 }
998
999 hs_clock = clk_get_rate(dsi->pll_phy_clock);
1000
1001 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
1002 * not the pixel clock rate. DSIxP take from the APHY's byte,
1003 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
1004 * that rate. Separately, a value derived from PIX_CLK_DIV
1005 * and HS_CLKC is fed into the PV to divide down to the actual
1006 * pixel clock for pushing pixels into DSI.
1007 */
1008 dsip_clock = phy_clock / 8;
1009 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1010 if (ret) {
1011 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
1012 dsip_clock, ret);
1013 }
1014
1015 ret = clk_prepare_enable(dsi->pixel_clock);
1016 if (ret) {
1017 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1018 return;
1019 }
1020
1021 /* How many ns one DSI unit interval is. Note that the clock
1022 * is DDR, so there's an extra divide by 2.
1023 */
1024 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1025
1026 DSI_PORT_WRITE(HS_CLT0,
1027 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1028 DSI_HS_CLT0_CZERO) |
1029 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1030 DSI_HS_CLT0_CPRE) |
1031 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1032 DSI_HS_CLT0_CPREP));
1033
1034 DSI_PORT_WRITE(HS_CLT1,
1035 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1036 DSI_HS_CLT1_CTRAIL) |
1037 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1038 DSI_HS_CLT1_CPOST));
1039
1040 DSI_PORT_WRITE(HS_CLT2,
1041 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1042 DSI_HS_CLT2_WUP));
1043
1044 DSI_PORT_WRITE(HS_DLT3,
1045 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1046 DSI_HS_DLT3_EXIT) |
1047 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1048 DSI_HS_DLT3_ZERO) |
1049 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1050 DSI_HS_DLT3_PRE));
1051
1052 DSI_PORT_WRITE(HS_DLT4,
1053 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1054 DSI_HS_DLT4_LPX) |
1055 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1056 dsi_hs_timing(ui_ns, 60, 4)),
1057 DSI_HS_DLT4_TRAIL) |
1058 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1059
1060 /* T_INIT is how long STOP is driven after power-up to
1061 * indicate to the slave (also coming out of power-up) that
1062 * master init is complete, and should be greater than the
1063 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1064 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1065 * T_INIT,SLAVE, while allowing protocols on top of it to give
1066 * greater minimums. The vc4 firmware uses an extremely
1067 * conservative 5ms, and we maintain that here.
1068 */
1069 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1070 5 * 1000 * 1000, 0),
1071 DSI_HS_DLT5_INIT));
1072
1073 DSI_PORT_WRITE(HS_DLT6,
1074 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1075 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1076 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1077 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1078
1079 DSI_PORT_WRITE(HS_DLT7,
1080 VC4_SET_FIELD(dsi_esc_timing(1000000),
1081 DSI_HS_DLT7_LP_WUP));
1082
1083 DSI_PORT_WRITE(PHYC,
1084 DSI_PHYC_DLANE0_ENABLE |
1085 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1086 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1087 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1088 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1089 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1090 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1091 (dsi->variant->port == 0 ?
1092 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1093 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1094
1095 DSI_PORT_WRITE(CTRL,
1096 DSI_PORT_READ(CTRL) |
1097 DSI_CTRL_CAL_BYTE);
1098
1099 /* HS timeout in HS clock cycles: disabled. */
1100 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1101 /* LP receive timeout in HS clocks. */
1102 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1103 /* Bus turnaround timeout */
1104 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1105 /* Display reset sequence timeout */
1106 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1107
1108 /* Set up DISP1 for transferring long command payloads through
1109 * the pixfifo.
1110 */
1111 DSI_PORT_WRITE(DISP1_CTRL,
1112 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1113 DSI_DISP1_PFORMAT) |
1114 DSI_DISP1_ENABLE);
1115
1116 /* Ungate the block. */
1117 if (dsi->variant->port == 0)
1118 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1119 else
1120 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1121
1122 /* Bring AFE out of reset. */
1123 DSI_PORT_WRITE(PHY_AFEC0,
1124 DSI_PORT_READ(PHY_AFEC0) &
1125 ~DSI_PORT_BIT(PHY_AFEC0_RESET));
1126
1127 vc4_dsi_ulps(dsi, false);
1128
1129 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1130 DSI_PORT_WRITE(DISP0_CTRL,
1131 VC4_SET_FIELD(dsi->divider,
1132 DSI_DISP0_PIX_CLK_DIV) |
1133 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1134 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1135 DSI_DISP0_LP_STOP_CTRL) |
1136 DSI_DISP0_ST_END);
1137 } else {
1138 DSI_PORT_WRITE(DISP0_CTRL,
1139 DSI_DISP0_COMMAND_MODE);
1140 }
1141}
1142
1143static void vc4_dsi_bridge_enable(struct drm_bridge *bridge,
1144 struct drm_bridge_state *old_state)
1145{
1146 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1147 bool debug_dump_regs = false;
1148 u32 disp0_ctrl;
1149
1150 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
1151 disp0_ctrl |= DSI_DISP0_ENABLE;
1152 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
1153
1154 if (debug_dump_regs) {
1155 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1156 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1157 drm_print_regset32(&p, &dsi->regset);
1158 }
1159}
1160
1161static int vc4_dsi_bridge_attach(struct drm_bridge *bridge,
1162 enum drm_bridge_attach_flags flags)
1163{
1164 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1165
1166 /* Attach the panel or bridge to the dsi bridge */
1167 return drm_bridge_attach(bridge->encoder, dsi->out_bridge,
1168 &dsi->bridge, flags);
1169}
1170
1171static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1172 const struct mipi_dsi_msg *msg)
1173{
1174 struct vc4_dsi *dsi = host_to_dsi(host);
1175 struct mipi_dsi_packet packet;
1176 u32 pkth = 0, pktc = 0;
1177 int i, ret;
1178 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1179 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1180
1181 mipi_dsi_create_packet(&packet, msg);
1182
1183 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1184 pkth |= VC4_SET_FIELD(packet.header[1] |
1185 (packet.header[2] << 8),
1186 DSI_TXPKT1H_BC_PARAM);
1187 if (is_long) {
1188 /* Divide data across the various FIFOs we have available.
1189 * The command FIFO takes byte-oriented data, but is of
1190 * limited size. The pixel FIFO (never actually used for
1191 * pixel data in reality) is word oriented, and substantially
1192 * larger. So, we use the pixel FIFO for most of the data,
1193 * sending the residual bytes in the command FIFO at the start.
1194 *
1195 * With this arrangement, the command FIFO will never get full.
1196 */
1197 if (packet.payload_length <= 16) {
1198 cmd_fifo_len = packet.payload_length;
1199 pix_fifo_len = 0;
1200 } else {
1201 cmd_fifo_len = (packet.payload_length %
1202 DSI_PIX_FIFO_WIDTH);
1203 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1204 DSI_PIX_FIFO_WIDTH);
1205 }
1206
1207 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1208
1209 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1210 }
1211
1212 if (msg->rx_len) {
1213 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1214 DSI_TXPKT1C_CMD_CTRL);
1215 } else {
1216 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1217 DSI_TXPKT1C_CMD_CTRL);
1218 }
1219
1220 for (i = 0; i < cmd_fifo_len; i++)
1221 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1222 for (i = 0; i < pix_fifo_len; i++) {
1223 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1224
1225 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1226 pix[0] |
1227 pix[1] << 8 |
1228 pix[2] << 16 |
1229 pix[3] << 24);
1230 }
1231
1232 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1233 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1234 if (is_long)
1235 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1236
1237 /* Send one copy of the packet. Larger repeats are used for pixel
1238 * data in command mode.
1239 */
1240 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1241
1242 pktc |= DSI_TXPKT1C_CMD_EN;
1243 if (pix_fifo_len) {
1244 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1245 DSI_TXPKT1C_DISPLAY_NO);
1246 } else {
1247 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1248 DSI_TXPKT1C_DISPLAY_NO);
1249 }
1250
1251 /* Enable the appropriate interrupt for the transfer completion. */
1252 dsi->xfer_result = 0;
1253 reinit_completion(&dsi->xfer_completion);
1254 if (dsi->variant->port == 0) {
1255 DSI_PORT_WRITE(INT_STAT,
1256 DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
1257 if (msg->rx_len) {
1258 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1259 DSI0_INT_PHY_DIR_RTF));
1260 } else {
1261 DSI_PORT_WRITE(INT_EN,
1262 (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1263 VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
1264 DSI0_INT_CMDC_DONE)));
1265 }
1266 } else {
1267 DSI_PORT_WRITE(INT_STAT,
1268 DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1269 if (msg->rx_len) {
1270 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1271 DSI1_INT_PHY_DIR_RTF));
1272 } else {
1273 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1274 DSI1_INT_TXPKT1_DONE));
1275 }
1276 }
1277
1278 /* Send the packet. */
1279 DSI_PORT_WRITE(TXPKT1H, pkth);
1280 DSI_PORT_WRITE(TXPKT1C, pktc);
1281
1282 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1283 msecs_to_jiffies(1000))) {
1284 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1285 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1286 DSI_PORT_READ(INT_STAT));
1287 ret = -ETIMEDOUT;
1288 } else {
1289 ret = dsi->xfer_result;
1290 }
1291
1292 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1293
1294 if (ret)
1295 goto reset_fifo_and_return;
1296
1297 if (ret == 0 && msg->rx_len) {
1298 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1299 u8 *msg_rx = msg->rx_buf;
1300
1301 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1302 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1303 DSI_RXPKT1H_BC_PARAM);
1304
1305 if (rxlen != msg->rx_len) {
1306 DRM_ERROR("DSI returned %db, expecting %db\n",
1307 rxlen, (int)msg->rx_len);
1308 ret = -ENXIO;
1309 goto reset_fifo_and_return;
1310 }
1311
1312 for (i = 0; i < msg->rx_len; i++)
1313 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1314 } else {
1315 /* FINISHME: Handle AWER */
1316
1317 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1318 DSI_RXPKT1H_SHORT_0);
1319 if (msg->rx_len > 1) {
1320 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1321 DSI_RXPKT1H_SHORT_1);
1322 }
1323 }
1324 }
1325
1326 return ret;
1327
1328reset_fifo_and_return:
1329 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1330
1331 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1332 udelay(1);
1333 DSI_PORT_WRITE(CTRL,
1334 DSI_PORT_READ(CTRL) |
1335 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1336
1337 DSI_PORT_WRITE(TXPKT1C, 0);
1338 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1339 return ret;
1340}
1341
1342static const struct component_ops vc4_dsi_ops;
1343static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1344 struct mipi_dsi_device *device)
1345{
1346 struct vc4_dsi *dsi = host_to_dsi(host);
1347 int ret;
1348
1349 dsi->lanes = device->lanes;
1350 dsi->channel = device->channel;
1351 dsi->mode_flags = device->mode_flags;
1352
1353 switch (device->format) {
1354 case MIPI_DSI_FMT_RGB888:
1355 dsi->format = DSI_PFORMAT_RGB888;
1356 dsi->divider = 24 / dsi->lanes;
1357 break;
1358 case MIPI_DSI_FMT_RGB666:
1359 dsi->format = DSI_PFORMAT_RGB666;
1360 dsi->divider = 24 / dsi->lanes;
1361 break;
1362 case MIPI_DSI_FMT_RGB666_PACKED:
1363 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1364 dsi->divider = 18 / dsi->lanes;
1365 break;
1366 case MIPI_DSI_FMT_RGB565:
1367 dsi->format = DSI_PFORMAT_RGB565;
1368 dsi->divider = 16 / dsi->lanes;
1369 break;
1370 default:
1371 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1372 dsi->format);
1373 return 0;
1374 }
1375
1376 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1377 dev_err(&dsi->pdev->dev,
1378 "Only VIDEO mode panels supported currently.\n");
1379 return 0;
1380 }
1381
1382 drm_bridge_add(&dsi->bridge);
1383
1384 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1385 if (ret) {
1386 drm_bridge_remove(&dsi->bridge);
1387 return ret;
1388 }
1389
1390 return 0;
1391}
1392
1393static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1394 struct mipi_dsi_device *device)
1395{
1396 struct vc4_dsi *dsi = host_to_dsi(host);
1397
1398 component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1399 drm_bridge_remove(&dsi->bridge);
1400 return 0;
1401}
1402
1403static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1404 .attach = vc4_dsi_host_attach,
1405 .detach = vc4_dsi_host_detach,
1406 .transfer = vc4_dsi_host_transfer,
1407};
1408
1409static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = {
1410 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1411 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1412 .atomic_reset = drm_atomic_helper_bridge_reset,
1413 .atomic_pre_enable = vc4_dsi_bridge_pre_enable,
1414 .atomic_enable = vc4_dsi_bridge_enable,
1415 .atomic_disable = vc4_dsi_bridge_disable,
1416 .atomic_post_disable = vc4_dsi_bridge_post_disable,
1417 .attach = vc4_dsi_bridge_attach,
1418 .mode_fixup = vc4_dsi_bridge_mode_fixup,
1419};
1420
1421static int vc4_dsi_late_register(struct drm_encoder *encoder)
1422{
1423 struct drm_device *drm = encoder->dev;
1424 struct vc4_dsi *dsi = to_vc4_dsi(encoder);
1425
1426 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);
1427
1428 return 0;
1429}
1430
1431static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
1432 .late_register = vc4_dsi_late_register,
1433};
1434
1435static const struct vc4_dsi_variant bcm2711_dsi1_variant = {
1436 .port = 1,
1437 .debugfs_name = "dsi1_regs",
1438 .regs = dsi1_regs,
1439 .nregs = ARRAY_SIZE(dsi1_regs),
1440};
1441
1442static const struct vc4_dsi_variant bcm2835_dsi0_variant = {
1443 .port = 0,
1444 .debugfs_name = "dsi0_regs",
1445 .regs = dsi0_regs,
1446 .nregs = ARRAY_SIZE(dsi0_regs),
1447};
1448
1449static const struct vc4_dsi_variant bcm2835_dsi1_variant = {
1450 .port = 1,
1451 .broken_axi_workaround = true,
1452 .debugfs_name = "dsi1_regs",
1453 .regs = dsi1_regs,
1454 .nregs = ARRAY_SIZE(dsi1_regs),
1455};
1456
1457static const struct of_device_id vc4_dsi_dt_match[] = {
1458 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1459 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1460 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1461 {}
1462};
1463
1464static void dsi_handle_error(struct vc4_dsi *dsi,
1465 irqreturn_t *ret, u32 stat, u32 bit,
1466 const char *type)
1467{
1468 if (!(stat & bit))
1469 return;
1470
1471 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1472 *ret = IRQ_HANDLED;
1473}
1474
1475/*
1476 * Initial handler for port 1 where we need the reg_dma workaround.
1477 * The register DMA writes sleep, so we can't do it in the top half.
1478 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1479 * parent interrupt contrller until our interrupt thread is done.
1480 */
1481static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1482{
1483 struct vc4_dsi *dsi = data;
1484 u32 stat = DSI_PORT_READ(INT_STAT);
1485
1486 if (!stat)
1487 return IRQ_NONE;
1488
1489 return IRQ_WAKE_THREAD;
1490}
1491
1492/*
1493 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1494 * 1 where we need the reg_dma workaround.
1495 */
1496static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1497{
1498 struct vc4_dsi *dsi = data;
1499 u32 stat = DSI_PORT_READ(INT_STAT);
1500 irqreturn_t ret = IRQ_NONE;
1501
1502 DSI_PORT_WRITE(INT_STAT, stat);
1503
1504 dsi_handle_error(dsi, &ret, stat,
1505 DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
1506 dsi_handle_error(dsi, &ret, stat,
1507 DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
1508 dsi_handle_error(dsi, &ret, stat,
1509 DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
1510 dsi_handle_error(dsi, &ret, stat,
1511 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
1512 dsi_handle_error(dsi, &ret, stat,
1513 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
1514 dsi_handle_error(dsi, &ret, stat,
1515 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
1516 dsi_handle_error(dsi, &ret, stat,
1517 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
1518 dsi_handle_error(dsi, &ret, stat,
1519 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
1520
1521 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1522 DSI0_INT_CMDC_DONE_MASK) |
1523 DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
1524 complete(&dsi->xfer_completion);
1525 ret = IRQ_HANDLED;
1526 } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
1527 complete(&dsi->xfer_completion);
1528 dsi->xfer_result = -ETIMEDOUT;
1529 ret = IRQ_HANDLED;
1530 }
1531
1532 return ret;
1533}
1534
1535/**
1536 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1537 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1538 * @dsi: DSI encoder
1539 */
1540static int
1541vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1542{
1543 struct device *dev = &dsi->pdev->dev;
1544 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1545 static const struct {
1546 const char *name;
1547 int div;
1548 } phy_clocks[] = {
1549 { "byte", 8 },
1550 { "ddr2", 4 },
1551 { "ddr", 2 },
1552 };
1553 int i;
1554
1555 dsi->clk_onecell = devm_kzalloc(dev,
1556 sizeof(*dsi->clk_onecell) +
1557 ARRAY_SIZE(phy_clocks) *
1558 sizeof(struct clk_hw *),
1559 GFP_KERNEL);
1560 if (!dsi->clk_onecell)
1561 return -ENOMEM;
1562 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1563
1564 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1565 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1566 struct clk_init_data init;
1567 char clk_name[16];
1568 int ret;
1569
1570 snprintf(clk_name, sizeof(clk_name),
1571 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1572
1573 /* We just use core fixed factor clock ops for the PHY
1574 * clocks. The clocks are actually gated by the
1575 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1576 * setting if we use the DDR/DDR2 clocks. However,
1577 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1578 * setting both our parent DSI PLL's rate and this
1579 * clock's rate, so it knows if DDR/DDR2 are going to
1580 * be used and could enable the gates itself.
1581 */
1582 fix->mult = 1;
1583 fix->div = phy_clocks[i].div;
1584 fix->hw.init = &init;
1585
1586 memset(&init, 0, sizeof(init));
1587 init.parent_names = &parent_name;
1588 init.num_parents = 1;
1589 init.name = clk_name;
1590 init.ops = &clk_fixed_factor_ops;
1591
1592 ret = devm_clk_hw_register(dev, &fix->hw);
1593 if (ret)
1594 return ret;
1595
1596 dsi->clk_onecell->hws[i] = &fix->hw;
1597 }
1598
1599 return of_clk_add_hw_provider(dev->of_node,
1600 of_clk_hw_onecell_get,
1601 dsi->clk_onecell);
1602}
1603
1604static void vc4_dsi_dma_mem_release(void *ptr)
1605{
1606 struct vc4_dsi *dsi = ptr;
1607 struct device *dev = &dsi->pdev->dev;
1608
1609 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1610 dsi->reg_dma_mem = NULL;
1611}
1612
1613static void vc4_dsi_dma_chan_release(void *ptr)
1614{
1615 struct vc4_dsi *dsi = ptr;
1616
1617 dma_release_channel(dsi->reg_dma_chan);
1618 dsi->reg_dma_chan = NULL;
1619}
1620
1621static void vc4_dsi_release(struct kref *kref)
1622{
1623 struct vc4_dsi *dsi =
1624 container_of(kref, struct vc4_dsi, kref);
1625
1626 kfree(dsi);
1627}
1628
1629static void vc4_dsi_get(struct vc4_dsi *dsi)
1630{
1631 kref_get(&dsi->kref);
1632}
1633
1634static void vc4_dsi_put(struct vc4_dsi *dsi)
1635{
1636 kref_put(&dsi->kref, &vc4_dsi_release);
1637}
1638
1639static void vc4_dsi_release_action(struct drm_device *drm, void *ptr)
1640{
1641 struct vc4_dsi *dsi = ptr;
1642
1643 vc4_dsi_put(dsi);
1644}
1645
1646static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1647{
1648 struct platform_device *pdev = to_platform_device(dev);
1649 struct drm_device *drm = dev_get_drvdata(master);
1650 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1651 struct drm_encoder *encoder = &dsi->encoder.base;
1652 int ret;
1653
1654 vc4_dsi_get(dsi);
1655
1656 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
1657 if (ret)
1658 return ret;
1659
1660 dsi->variant = of_device_get_match_data(dev);
1661
1662 dsi->encoder.type = dsi->variant->port ?
1663 VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0;
1664
1665 dsi->regs = vc4_ioremap_regs(pdev, 0);
1666 if (IS_ERR(dsi->regs))
1667 return PTR_ERR(dsi->regs);
1668
1669 dsi->regset.base = dsi->regs;
1670 dsi->regset.regs = dsi->variant->regs;
1671 dsi->regset.nregs = dsi->variant->nregs;
1672
1673 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1674 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1675 DSI_PORT_READ(ID), DSI_ID_VALUE);
1676 return -ENODEV;
1677 }
1678
1679 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to
1680 * writes from the ARM. It does handle writes from the DMA engine,
1681 * so set up a channel for talking to it.
1682 */
1683 if (dsi->variant->broken_axi_workaround) {
1684 dma_cap_mask_t dma_mask;
1685
1686 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1687 &dsi->reg_dma_paddr,
1688 GFP_KERNEL);
1689 if (!dsi->reg_dma_mem) {
1690 DRM_ERROR("Failed to get DMA memory\n");
1691 return -ENOMEM;
1692 }
1693
1694 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi);
1695 if (ret)
1696 return ret;
1697
1698 dma_cap_zero(dma_mask);
1699 dma_cap_set(DMA_MEMCPY, dma_mask);
1700
1701 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1702 if (IS_ERR(dsi->reg_dma_chan)) {
1703 ret = PTR_ERR(dsi->reg_dma_chan);
1704 if (ret != -EPROBE_DEFER)
1705 DRM_ERROR("Failed to get DMA channel: %d\n",
1706 ret);
1707 return ret;
1708 }
1709
1710 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi);
1711 if (ret)
1712 return ret;
1713
1714 /* Get the physical address of the device's registers. The
1715 * struct resource for the regs gives us the bus address
1716 * instead.
1717 */
1718 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1719 0, NULL, NULL));
1720 }
1721
1722 init_completion(&dsi->xfer_completion);
1723 /* At startup enable error-reporting interrupts and nothing else. */
1724 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1725 /* Clear any existing interrupt state. */
1726 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1727
1728 if (dsi->reg_dma_mem)
1729 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1730 vc4_dsi_irq_defer_to_thread_handler,
1731 vc4_dsi_irq_handler,
1732 IRQF_ONESHOT,
1733 "vc4 dsi", dsi);
1734 else
1735 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1736 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1737 if (ret) {
1738 if (ret != -EPROBE_DEFER)
1739 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1740 return ret;
1741 }
1742
1743 dsi->escape_clock = devm_clk_get(dev, "escape");
1744 if (IS_ERR(dsi->escape_clock)) {
1745 ret = PTR_ERR(dsi->escape_clock);
1746 if (ret != -EPROBE_DEFER)
1747 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1748 return ret;
1749 }
1750
1751 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1752 if (IS_ERR(dsi->pll_phy_clock)) {
1753 ret = PTR_ERR(dsi->pll_phy_clock);
1754 if (ret != -EPROBE_DEFER)
1755 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1756 return ret;
1757 }
1758
1759 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1760 if (IS_ERR(dsi->pixel_clock)) {
1761 ret = PTR_ERR(dsi->pixel_clock);
1762 if (ret != -EPROBE_DEFER)
1763 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1764 return ret;
1765 }
1766
1767 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1768 if (IS_ERR(dsi->out_bridge))
1769 return PTR_ERR(dsi->out_bridge);
1770
1771 /* The esc clock rate is supposed to always be 100Mhz. */
1772 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1773 if (ret) {
1774 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1775 return ret;
1776 }
1777
1778 ret = vc4_dsi_init_phy_clocks(dsi);
1779 if (ret)
1780 return ret;
1781
1782 ret = drmm_encoder_init(drm, encoder,
1783 &vc4_dsi_encoder_funcs,
1784 DRM_MODE_ENCODER_DSI,
1785 NULL);
1786 if (ret)
1787 return ret;
1788
1789 ret = devm_pm_runtime_enable(dev);
1790 if (ret)
1791 return ret;
1792
1793 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1794 if (ret)
1795 return ret;
1796
1797 return 0;
1798}
1799
1800static const struct component_ops vc4_dsi_ops = {
1801 .bind = vc4_dsi_bind,
1802};
1803
1804static int vc4_dsi_dev_probe(struct platform_device *pdev)
1805{
1806 struct device *dev = &pdev->dev;
1807 struct vc4_dsi *dsi;
1808
1809 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1810 if (!dsi)
1811 return -ENOMEM;
1812 dev_set_drvdata(dev, dsi);
1813
1814 kref_init(&dsi->kref);
1815
1816 dsi->pdev = pdev;
1817 dsi->bridge.funcs = &vc4_dsi_bridge_funcs;
1818#ifdef CONFIG_OF
1819 dsi->bridge.of_node = dev->of_node;
1820#endif
1821 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1822 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1823 dsi->dsi_host.dev = dev;
1824 mipi_dsi_host_register(&dsi->dsi_host);
1825
1826 return 0;
1827}
1828
1829static void vc4_dsi_dev_remove(struct platform_device *pdev)
1830{
1831 struct device *dev = &pdev->dev;
1832 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1833
1834 mipi_dsi_host_unregister(&dsi->dsi_host);
1835 vc4_dsi_put(dsi);
1836}
1837
1838struct platform_driver vc4_dsi_driver = {
1839 .probe = vc4_dsi_dev_probe,
1840 .remove_new = vc4_dsi_dev_remove,
1841 .driver = {
1842 .name = "vc4_dsi",
1843 .of_match_table = vc4_dsi_dt_match,
1844 },
1845};