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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 */
5
6/**
7 * DOC: VC4 DSI0/DSI1 module
8 *
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
11 * controller.
12 *
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
15 *
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
18 * hopefully present.
19 */
20
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23#include <linux/completion.h>
24#include <linux/component.h>
25#include <linux/dma-mapping.h>
26#include <linux/dmaengine.h>
27#include <linux/i2c.h>
28#include <linux/io.h>
29#include <linux/of_address.h>
30#include <linux/of_platform.h>
31#include <linux/pm_runtime.h>
32
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_simple_kms_helper.h>
41
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45#define DSI_CMD_FIFO_DEPTH 16
46#define DSI_PIX_FIFO_DEPTH 256
47#define DSI_PIX_FIFO_WIDTH 4
48
49#define DSI0_CTRL 0x00
50
51/* Command packet control. */
52#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
53#define DSI1_TXPKT1C 0x04
54# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
55# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
56# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
57# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
58
59# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
60# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
61/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
63/* Primary display where cmdfifo provides part of the payload and
64 * pixelvalve the rest.
65 */
66# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
67/* Secondary display where cmdfifo provides part of the payload and
68 * pixfifo the rest.
69 */
70# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
71
72# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
73# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
74
75# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
76# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
77/* Command only. Uses TXPKT1H and DISPLAY_NO */
78# define DSI_TXPKT1C_CMD_CTRL_TX 0
79/* Command with BTA for either ack or read data. */
80# define DSI_TXPKT1C_CMD_CTRL_RX 1
81/* Trigger according to TRIG_CMD */
82# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
83/* BTA alone for getting error status after a command, or a TE trigger
84 * without a previous command.
85 */
86# define DSI_TXPKT1C_CMD_CTRL_BTA 3
87
88# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91# define DSI_TXPKT1C_CMD_EN BIT(0)
92
93/* Command packet header. */
94#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
95#define DSI1_TXPKT1H 0x08
96# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
97# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
98# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
99# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
100# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
101# define DSI_TXPKT1H_BC_DT_SHIFT 0
102
103#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
104#define DSI1_RXPKT1H 0x14
105# define DSI_RXPKT1H_CRC_ERR BIT(31)
106# define DSI_RXPKT1H_DET_ERR BIT(30)
107# define DSI_RXPKT1H_ECC_ERR BIT(29)
108# define DSI_RXPKT1H_COR_ERR BIT(28)
109# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
111/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
113# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
114/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
116# define DSI_RXPKT1H_SHORT_1_SHIFT 16
117# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
118# define DSI_RXPKT1H_SHORT_0_SHIFT 8
119# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
120# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
121
122#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
123#define DSI1_RXPKT2H 0x18
124# define DSI_RXPKT1H_DET_ERR BIT(30)
125# define DSI_RXPKT1H_ECC_ERR BIT(29)
126# define DSI_RXPKT1H_COR_ERR BIT(28)
127# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
128# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
129# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
130# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
131# define DSI_RXPKT1H_DT_SHIFT 0
132
133#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
134#define DSI1_TXPKT_CMD_FIFO 0x1c
135
136#define DSI0_DISP0_CTRL 0x18
137# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
138# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
139# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
140# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
141# define DSI_DISP0_LP_STOP_DISABLE 0
142# define DSI_DISP0_LP_STOP_PERLINE 1
143# define DSI_DISP0_LP_STOP_PERFRAME 2
144
145/* Transmit RGB pixels and null packets only during HACTIVE, instead
146 * of going to LP-STOP.
147 */
148# define DSI_DISP_HACTIVE_NULL BIT(10)
149/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150# define DSI_DISP_VBLP_CTRL BIT(9)
151/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152# define DSI_DISP_HFP_CTRL BIT(8)
153/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154# define DSI_DISP_HBP_CTRL BIT(7)
155# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
156# define DSI_DISP0_CHANNEL_SHIFT 5
157/* Enables end events for HSYNC/VSYNC, not just start events. */
158# define DSI_DISP0_ST_END BIT(4)
159# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
160# define DSI_DISP0_PFORMAT_SHIFT 2
161# define DSI_PFORMAT_RGB565 0
162# define DSI_PFORMAT_RGB666_PACKED 1
163# define DSI_PFORMAT_RGB666 2
164# define DSI_PFORMAT_RGB888 3
165/* Default is VIDEO mode. */
166# define DSI_DISP0_COMMAND_MODE BIT(1)
167# define DSI_DISP0_ENABLE BIT(0)
168
169#define DSI0_DISP1_CTRL 0x1c
170#define DSI1_DISP1_CTRL 0x2c
171/* Format of the data written to TXPKT_PIX_FIFO. */
172# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
173# define DSI_DISP1_PFORMAT_SHIFT 1
174# define DSI_DISP1_PFORMAT_16BIT 0
175# define DSI_DISP1_PFORMAT_24BIT 1
176# define DSI_DISP1_PFORMAT_32BIT_LE 2
177# define DSI_DISP1_PFORMAT_32BIT_BE 3
178
179/* DISP1 is always command mode. */
180# define DSI_DISP1_ENABLE BIT(0)
181
182#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
183
184#define DSI0_INT_STAT 0x24
185#define DSI0_INT_EN 0x28
186# define DSI1_INT_PHY_D3_ULPS BIT(30)
187# define DSI1_INT_PHY_D3_STOP BIT(29)
188# define DSI1_INT_PHY_D2_ULPS BIT(28)
189# define DSI1_INT_PHY_D2_STOP BIT(27)
190# define DSI1_INT_PHY_D1_ULPS BIT(26)
191# define DSI1_INT_PHY_D1_STOP BIT(25)
192# define DSI1_INT_PHY_D0_ULPS BIT(24)
193# define DSI1_INT_PHY_D0_STOP BIT(23)
194# define DSI1_INT_FIFO_ERR BIT(22)
195# define DSI1_INT_PHY_DIR_RTF BIT(21)
196# define DSI1_INT_PHY_RXLPDT BIT(20)
197# define DSI1_INT_PHY_RXTRIG BIT(19)
198# define DSI1_INT_PHY_D0_LPDT BIT(18)
199# define DSI1_INT_PHY_DIR_FTR BIT(17)
200
201/* Signaled when the clock lane enters the given state. */
202# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
203# define DSI1_INT_PHY_CLOCK_HS BIT(15)
204# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
205
206/* Signaled on timeouts */
207# define DSI1_INT_PR_TO BIT(13)
208# define DSI1_INT_TA_TO BIT(12)
209# define DSI1_INT_LPRX_TO BIT(11)
210# define DSI1_INT_HSTX_TO BIT(10)
211
212/* Contention on a line when trying to drive the line low */
213# define DSI1_INT_ERR_CONT_LP1 BIT(9)
214# define DSI1_INT_ERR_CONT_LP0 BIT(8)
215
216/* Control error: incorrect line state sequence on data lane 0. */
217# define DSI1_INT_ERR_CONTROL BIT(7)
218/* LPDT synchronization error (bits received not a multiple of 8. */
219
220# define DSI1_INT_ERR_SYNC_ESC BIT(6)
221/* Signaled after receiving an error packet from the display in
222 * response to a read.
223 */
224# define DSI1_INT_RXPKT2 BIT(5)
225/* Signaled after receiving a packet. The header and optional short
226 * response will be in RXPKT1H, and a long response will be in the
227 * RXPKT_FIFO.
228 */
229# define DSI1_INT_RXPKT1 BIT(4)
230# define DSI1_INT_TXPKT2_DONE BIT(3)
231# define DSI1_INT_TXPKT2_END BIT(2)
232/* Signaled after all repeats of TXPKT1 are transferred. */
233# define DSI1_INT_TXPKT1_DONE BIT(1)
234/* Signaled after each TXPKT1 repeat is scheduled. */
235# define DSI1_INT_TXPKT1_END BIT(0)
236
237#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
238 DSI1_INT_ERR_CONTROL | \
239 DSI1_INT_ERR_CONT_LP0 | \
240 DSI1_INT_ERR_CONT_LP1 | \
241 DSI1_INT_HSTX_TO | \
242 DSI1_INT_LPRX_TO | \
243 DSI1_INT_TA_TO | \
244 DSI1_INT_PR_TO)
245
246#define DSI0_STAT 0x2c
247#define DSI0_HSTX_TO_CNT 0x30
248#define DSI0_LPRX_TO_CNT 0x34
249#define DSI0_TA_TO_CNT 0x38
250#define DSI0_PR_TO_CNT 0x3c
251#define DSI0_PHYC 0x40
252# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
253# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
254# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
255# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
256# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
257# define DSI1_PHYC_CLANE_ULPS BIT(17)
258# define DSI1_PHYC_CLANE_ENABLE BIT(16)
259# define DSI_PHYC_DLANE3_ULPS BIT(13)
260# define DSI_PHYC_DLANE3_ENABLE BIT(12)
261# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
262# define DSI0_PHYC_CLANE_ULPS BIT(9)
263# define DSI_PHYC_DLANE2_ULPS BIT(9)
264# define DSI0_PHYC_CLANE_ENABLE BIT(8)
265# define DSI_PHYC_DLANE2_ENABLE BIT(8)
266# define DSI_PHYC_DLANE1_ULPS BIT(5)
267# define DSI_PHYC_DLANE1_ENABLE BIT(4)
268# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
269# define DSI_PHYC_DLANE0_ULPS BIT(1)
270# define DSI_PHYC_DLANE0_ENABLE BIT(0)
271
272#define DSI0_HS_CLT0 0x44
273#define DSI0_HS_CLT1 0x48
274#define DSI0_HS_CLT2 0x4c
275#define DSI0_HS_DLT3 0x50
276#define DSI0_HS_DLT4 0x54
277#define DSI0_HS_DLT5 0x58
278#define DSI0_HS_DLT6 0x5c
279#define DSI0_HS_DLT7 0x60
280
281#define DSI0_PHY_AFEC0 0x64
282# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
283# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
284# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
285# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
286# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
287# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
288# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
289# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
290# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
291# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
292# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
293# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
294# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
295# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
296# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
297# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
298# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
299# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
300# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
301# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
302# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
303# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
304# define DSI1_PHY_AFEC0_RESET BIT(13)
305# define DSI1_PHY_AFEC0_PD BIT(12)
306# define DSI0_PHY_AFEC0_RESET BIT(11)
307# define DSI1_PHY_AFEC0_PD_BG BIT(11)
308# define DSI0_PHY_AFEC0_PD BIT(10)
309# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
310# define DSI0_PHY_AFEC0_PD_BG BIT(9)
311# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
312# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
313# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
314# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
315# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
316# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
317# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
318
319#define DSI0_PHY_AFEC1 0x68
320# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
321# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
322# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
323# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
324# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
325# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
326
327#define DSI0_TST_SEL 0x6c
328#define DSI0_TST_MON 0x70
329#define DSI0_ID 0x74
330# define DSI_ID_VALUE 0x00647369
331
332#define DSI1_CTRL 0x00
333# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
334# define DSI_CTRL_HS_CLKC_SHIFT 14
335# define DSI_CTRL_HS_CLKC_BYTE 0
336# define DSI_CTRL_HS_CLKC_DDR2 1
337# define DSI_CTRL_HS_CLKC_DDR 2
338
339# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
340# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
341# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
342# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
343# define DSI_CTRL_CAL_BYTE BIT(9)
344# define DSI_CTRL_INV_BYTE BIT(8)
345# define DSI_CTRL_CLR_LDF BIT(7)
346# define DSI0_CTRL_CLR_PBCF BIT(6)
347# define DSI1_CTRL_CLR_RXF BIT(6)
348# define DSI0_CTRL_CLR_CPBCF BIT(5)
349# define DSI1_CTRL_CLR_PDF BIT(5)
350# define DSI0_CTRL_CLR_PDF BIT(4)
351# define DSI1_CTRL_CLR_CDF BIT(4)
352# define DSI0_CTRL_CLR_CDF BIT(3)
353# define DSI0_CTRL_CTRL2 BIT(2)
354# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
355# define DSI0_CTRL_CTRL1 BIT(1)
356# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
357# define DSI0_CTRL_CTRL0 BIT(0)
358# define DSI1_CTRL_EN BIT(0)
359# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
360 DSI0_CTRL_CLR_PBCF | \
361 DSI0_CTRL_CLR_CPBCF | \
362 DSI0_CTRL_CLR_PDF | \
363 DSI0_CTRL_CLR_CDF)
364# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
365 DSI1_CTRL_CLR_RXF | \
366 DSI1_CTRL_CLR_PDF | \
367 DSI1_CTRL_CLR_CDF)
368
369#define DSI1_TXPKT2C 0x0c
370#define DSI1_TXPKT2H 0x10
371#define DSI1_TXPKT_PIX_FIFO 0x20
372#define DSI1_RXPKT_FIFO 0x24
373#define DSI1_DISP0_CTRL 0x28
374#define DSI1_INT_STAT 0x30
375#define DSI1_INT_EN 0x34
376/* State reporting bits. These mostly behave like INT_STAT, where
377 * writing a 1 clears the bit.
378 */
379#define DSI1_STAT 0x38
380# define DSI1_STAT_PHY_D3_ULPS BIT(31)
381# define DSI1_STAT_PHY_D3_STOP BIT(30)
382# define DSI1_STAT_PHY_D2_ULPS BIT(29)
383# define DSI1_STAT_PHY_D2_STOP BIT(28)
384# define DSI1_STAT_PHY_D1_ULPS BIT(27)
385# define DSI1_STAT_PHY_D1_STOP BIT(26)
386# define DSI1_STAT_PHY_D0_ULPS BIT(25)
387# define DSI1_STAT_PHY_D0_STOP BIT(24)
388# define DSI1_STAT_FIFO_ERR BIT(23)
389# define DSI1_STAT_PHY_RXLPDT BIT(22)
390# define DSI1_STAT_PHY_RXTRIG BIT(21)
391# define DSI1_STAT_PHY_D0_LPDT BIT(20)
392/* Set when in forward direction */
393# define DSI1_STAT_PHY_DIR BIT(19)
394# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
395# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
396# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
397# define DSI1_STAT_PR_TO BIT(15)
398# define DSI1_STAT_TA_TO BIT(14)
399# define DSI1_STAT_LPRX_TO BIT(13)
400# define DSI1_STAT_HSTX_TO BIT(12)
401# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
402# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
403# define DSI1_STAT_ERR_CONTROL BIT(9)
404# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
405# define DSI1_STAT_RXPKT2 BIT(7)
406# define DSI1_STAT_RXPKT1 BIT(6)
407# define DSI1_STAT_TXPKT2_BUSY BIT(5)
408# define DSI1_STAT_TXPKT2_DONE BIT(4)
409# define DSI1_STAT_TXPKT2_END BIT(3)
410# define DSI1_STAT_TXPKT1_BUSY BIT(2)
411# define DSI1_STAT_TXPKT1_DONE BIT(1)
412# define DSI1_STAT_TXPKT1_END BIT(0)
413
414#define DSI1_HSTX_TO_CNT 0x3c
415#define DSI1_LPRX_TO_CNT 0x40
416#define DSI1_TA_TO_CNT 0x44
417#define DSI1_PR_TO_CNT 0x48
418#define DSI1_PHYC 0x4c
419
420#define DSI1_HS_CLT0 0x50
421# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
422# define DSI_HS_CLT0_CZERO_SHIFT 18
423# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
424# define DSI_HS_CLT0_CPRE_SHIFT 9
425# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
426# define DSI_HS_CLT0_CPREP_SHIFT 0
427
428#define DSI1_HS_CLT1 0x54
429# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
430# define DSI_HS_CLT1_CTRAIL_SHIFT 9
431# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
432# define DSI_HS_CLT1_CPOST_SHIFT 0
433
434#define DSI1_HS_CLT2 0x58
435# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
436# define DSI_HS_CLT2_WUP_SHIFT 0
437
438#define DSI1_HS_DLT3 0x5c
439# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
440# define DSI_HS_DLT3_EXIT_SHIFT 18
441# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
442# define DSI_HS_DLT3_ZERO_SHIFT 9
443# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
444# define DSI_HS_DLT3_PRE_SHIFT 0
445
446#define DSI1_HS_DLT4 0x60
447# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
448# define DSI_HS_DLT4_ANLAT_SHIFT 18
449# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
450# define DSI_HS_DLT4_TRAIL_SHIFT 9
451# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
452# define DSI_HS_DLT4_LPX_SHIFT 0
453
454#define DSI1_HS_DLT5 0x64
455# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
456# define DSI_HS_DLT5_INIT_SHIFT 0
457
458#define DSI1_HS_DLT6 0x68
459# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
460# define DSI_HS_DLT6_TA_GET_SHIFT 24
461# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
462# define DSI_HS_DLT6_TA_SURE_SHIFT 16
463# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
464# define DSI_HS_DLT6_TA_GO_SHIFT 8
465# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
466# define DSI_HS_DLT6_LP_LPX_SHIFT 0
467
468#define DSI1_HS_DLT7 0x6c
469# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
470# define DSI_HS_DLT7_LP_WUP_SHIFT 0
471
472#define DSI1_PHY_AFEC0 0x70
473
474#define DSI1_PHY_AFEC1 0x74
475# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
476# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
477# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
478# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
479# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
480# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
481# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
482# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
483# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
484# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
485
486#define DSI1_TST_SEL 0x78
487#define DSI1_TST_MON 0x7c
488#define DSI1_PHY_TST1 0x80
489#define DSI1_PHY_TST2 0x84
490#define DSI1_PHY_FIFO_STAT 0x88
491/* Actually, all registers in the range that aren't otherwise claimed
492 * will return the ID.
493 */
494#define DSI1_ID 0x8c
495
496struct vc4_dsi_variant {
497 /* Whether we're on bcm2835's DSI0 or DSI1. */
498 unsigned int port;
499
500 bool broken_axi_workaround;
501
502 const char *debugfs_name;
503 const struct debugfs_reg32 *regs;
504 size_t nregs;
505
506};
507
508/* General DSI hardware state. */
509struct vc4_dsi {
510 struct platform_device *pdev;
511
512 struct mipi_dsi_host dsi_host;
513 struct drm_encoder *encoder;
514 struct drm_bridge *bridge;
515 struct list_head bridge_chain;
516
517 void __iomem *regs;
518
519 struct dma_chan *reg_dma_chan;
520 dma_addr_t reg_dma_paddr;
521 u32 *reg_dma_mem;
522 dma_addr_t reg_paddr;
523
524 const struct vc4_dsi_variant *variant;
525
526 /* DSI channel for the panel we're connected to. */
527 u32 channel;
528 u32 lanes;
529 u32 format;
530 u32 divider;
531 u32 mode_flags;
532
533 /* Input clock from CPRMAN to the digital PHY, for the DSI
534 * escape clock.
535 */
536 struct clk *escape_clock;
537
538 /* Input clock to the analog PHY, used to generate the DSI bit
539 * clock.
540 */
541 struct clk *pll_phy_clock;
542
543 /* HS Clocks generated within the DSI analog PHY. */
544 struct clk_fixed_factor phy_clocks[3];
545
546 struct clk_hw_onecell_data *clk_onecell;
547
548 /* Pixel clock output to the pixelvalve, generated from the HS
549 * clock.
550 */
551 struct clk *pixel_clock;
552
553 struct completion xfer_completion;
554 int xfer_result;
555
556 struct debugfs_regset32 regset;
557};
558
559#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
560
561static inline void
562dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
563{
564 struct dma_chan *chan = dsi->reg_dma_chan;
565 struct dma_async_tx_descriptor *tx;
566 dma_cookie_t cookie;
567 int ret;
568
569 /* DSI0 should be able to write normally. */
570 if (!chan) {
571 writel(val, dsi->regs + offset);
572 return;
573 }
574
575 *dsi->reg_dma_mem = val;
576
577 tx = chan->device->device_prep_dma_memcpy(chan,
578 dsi->reg_paddr + offset,
579 dsi->reg_dma_paddr,
580 4, 0);
581 if (!tx) {
582 DRM_ERROR("Failed to set up DMA register write\n");
583 return;
584 }
585
586 cookie = tx->tx_submit(tx);
587 ret = dma_submit_error(cookie);
588 if (ret) {
589 DRM_ERROR("Failed to submit DMA: %d\n", ret);
590 return;
591 }
592 ret = dma_sync_wait(chan, cookie);
593 if (ret)
594 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
595}
596
597#define DSI_READ(offset) readl(dsi->regs + (offset))
598#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
599#define DSI_PORT_READ(offset) \
600 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
601#define DSI_PORT_WRITE(offset, val) \
602 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
603#define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
604
605/* VC4 DSI encoder KMS struct */
606struct vc4_dsi_encoder {
607 struct vc4_encoder base;
608 struct vc4_dsi *dsi;
609};
610
611static inline struct vc4_dsi_encoder *
612to_vc4_dsi_encoder(struct drm_encoder *encoder)
613{
614 return container_of(encoder, struct vc4_dsi_encoder, base.base);
615}
616
617static const struct debugfs_reg32 dsi0_regs[] = {
618 VC4_REG32(DSI0_CTRL),
619 VC4_REG32(DSI0_STAT),
620 VC4_REG32(DSI0_HSTX_TO_CNT),
621 VC4_REG32(DSI0_LPRX_TO_CNT),
622 VC4_REG32(DSI0_TA_TO_CNT),
623 VC4_REG32(DSI0_PR_TO_CNT),
624 VC4_REG32(DSI0_DISP0_CTRL),
625 VC4_REG32(DSI0_DISP1_CTRL),
626 VC4_REG32(DSI0_INT_STAT),
627 VC4_REG32(DSI0_INT_EN),
628 VC4_REG32(DSI0_PHYC),
629 VC4_REG32(DSI0_HS_CLT0),
630 VC4_REG32(DSI0_HS_CLT1),
631 VC4_REG32(DSI0_HS_CLT2),
632 VC4_REG32(DSI0_HS_DLT3),
633 VC4_REG32(DSI0_HS_DLT4),
634 VC4_REG32(DSI0_HS_DLT5),
635 VC4_REG32(DSI0_HS_DLT6),
636 VC4_REG32(DSI0_HS_DLT7),
637 VC4_REG32(DSI0_PHY_AFEC0),
638 VC4_REG32(DSI0_PHY_AFEC1),
639 VC4_REG32(DSI0_ID),
640};
641
642static const struct debugfs_reg32 dsi1_regs[] = {
643 VC4_REG32(DSI1_CTRL),
644 VC4_REG32(DSI1_STAT),
645 VC4_REG32(DSI1_HSTX_TO_CNT),
646 VC4_REG32(DSI1_LPRX_TO_CNT),
647 VC4_REG32(DSI1_TA_TO_CNT),
648 VC4_REG32(DSI1_PR_TO_CNT),
649 VC4_REG32(DSI1_DISP0_CTRL),
650 VC4_REG32(DSI1_DISP1_CTRL),
651 VC4_REG32(DSI1_INT_STAT),
652 VC4_REG32(DSI1_INT_EN),
653 VC4_REG32(DSI1_PHYC),
654 VC4_REG32(DSI1_HS_CLT0),
655 VC4_REG32(DSI1_HS_CLT1),
656 VC4_REG32(DSI1_HS_CLT2),
657 VC4_REG32(DSI1_HS_DLT3),
658 VC4_REG32(DSI1_HS_DLT4),
659 VC4_REG32(DSI1_HS_DLT5),
660 VC4_REG32(DSI1_HS_DLT6),
661 VC4_REG32(DSI1_HS_DLT7),
662 VC4_REG32(DSI1_PHY_AFEC0),
663 VC4_REG32(DSI1_PHY_AFEC1),
664 VC4_REG32(DSI1_ID),
665};
666
667static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
668{
669 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
670
671 if (latch)
672 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
673 else
674 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
675
676 DSI_PORT_WRITE(PHY_AFEC0, afec0);
677}
678
679/* Enters or exits Ultra Low Power State. */
680static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
681{
682 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
683 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
684 DSI_PHYC_DLANE0_ULPS |
685 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
686 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
687 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
688 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
689 DSI1_STAT_PHY_D0_ULPS |
690 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
691 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
692 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
693 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
694 DSI1_STAT_PHY_D0_STOP |
695 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
696 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
697 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
698 int ret;
699 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
700 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
701
702 if (ulps == ulps_currently_enabled)
703 return;
704
705 DSI_PORT_WRITE(STAT, stat_ulps);
706 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
707 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
708 if (ret) {
709 dev_warn(&dsi->pdev->dev,
710 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
711 DSI_PORT_READ(STAT));
712 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
713 vc4_dsi_latch_ulps(dsi, false);
714 return;
715 }
716
717 /* The DSI module can't be disabled while the module is
718 * generating ULPS state. So, to be able to disable the
719 * module, we have the AFE latch the ULPS state and continue
720 * on to having the module enter STOP.
721 */
722 vc4_dsi_latch_ulps(dsi, ulps);
723
724 DSI_PORT_WRITE(STAT, stat_stop);
725 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
726 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
727 if (ret) {
728 dev_warn(&dsi->pdev->dev,
729 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
730 DSI_PORT_READ(STAT));
731 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
732 return;
733 }
734}
735
736static u32
737dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
738{
739 /* The HS timings have to be rounded up to a multiple of 8
740 * because we're using the byte clock.
741 */
742 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
743}
744
745/* ESC always runs at 100Mhz. */
746#define ESC_TIME_NS 10
747
748static u32
749dsi_esc_timing(u32 ns)
750{
751 return DIV_ROUND_UP(ns, ESC_TIME_NS);
752}
753
754static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
755{
756 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
757 struct vc4_dsi *dsi = vc4_encoder->dsi;
758 struct device *dev = &dsi->pdev->dev;
759 struct drm_bridge *iter;
760
761 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
762 if (iter->funcs->disable)
763 iter->funcs->disable(iter);
764 }
765
766 vc4_dsi_ulps(dsi, true);
767
768 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) {
769 if (iter->funcs->post_disable)
770 iter->funcs->post_disable(iter);
771 }
772
773 clk_disable_unprepare(dsi->pll_phy_clock);
774 clk_disable_unprepare(dsi->escape_clock);
775 clk_disable_unprepare(dsi->pixel_clock);
776
777 pm_runtime_put(dev);
778}
779
780/* Extends the mode's blank intervals to handle BCM2835's integer-only
781 * DSI PLL divider.
782 *
783 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
784 * driver since most peripherals are hanging off of the PLLD_PER
785 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
786 * the pixel clock), only has an integer divider off of DSI.
787 *
788 * To get our panel mode to refresh at the expected 60Hz, we need to
789 * extend the horizontal blank time. This means we drive a
790 * higher-than-expected clock rate to the panel, but that's what the
791 * firmware does too.
792 */
793static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
794 const struct drm_display_mode *mode,
795 struct drm_display_mode *adjusted_mode)
796{
797 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
798 struct vc4_dsi *dsi = vc4_encoder->dsi;
799 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
800 unsigned long parent_rate = clk_get_rate(phy_parent);
801 unsigned long pixel_clock_hz = mode->clock * 1000;
802 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
803 int divider;
804
805 /* Find what divider gets us a faster clock than the requested
806 * pixel clock.
807 */
808 for (divider = 1; divider < 8; divider++) {
809 if (parent_rate / divider < pll_clock) {
810 divider--;
811 break;
812 }
813 }
814
815 /* Now that we've picked a PLL divider, calculate back to its
816 * pixel clock.
817 */
818 pll_clock = parent_rate / divider;
819 pixel_clock_hz = pll_clock / dsi->divider;
820
821 adjusted_mode->clock = pixel_clock_hz / 1000;
822
823 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
824 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
825 mode->clock;
826 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
827 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
828
829 return true;
830}
831
832static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
833{
834 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
835 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
836 struct vc4_dsi *dsi = vc4_encoder->dsi;
837 struct device *dev = &dsi->pdev->dev;
838 bool debug_dump_regs = false;
839 struct drm_bridge *iter;
840 unsigned long hs_clock;
841 u32 ui_ns;
842 /* Minimum LP state duration in escape clock cycles. */
843 u32 lpx = dsi_esc_timing(60);
844 unsigned long pixel_clock_hz = mode->clock * 1000;
845 unsigned long dsip_clock;
846 unsigned long phy_clock;
847 int ret;
848
849 ret = pm_runtime_get_sync(dev);
850 if (ret) {
851 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
852 return;
853 }
854
855 if (debug_dump_regs) {
856 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
857 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
858 drm_print_regset32(&p, &dsi->regset);
859 }
860
861 /* Round up the clk_set_rate() request slightly, since
862 * PLLD_DSI1 is an integer divider and its rate selection will
863 * never round up.
864 */
865 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
866 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
867 if (ret) {
868 dev_err(&dsi->pdev->dev,
869 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
870 }
871
872 /* Reset the DSI and all its fifos. */
873 DSI_PORT_WRITE(CTRL,
874 DSI_CTRL_SOFT_RESET_CFG |
875 DSI_PORT_BIT(CTRL_RESET_FIFOS));
876
877 DSI_PORT_WRITE(CTRL,
878 DSI_CTRL_HSDT_EOT_DISABLE |
879 DSI_CTRL_RX_LPDT_EOT_DISABLE);
880
881 /* Clear all stat bits so we see what has happened during enable. */
882 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
883
884 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
885 if (dsi->variant->port == 0) {
886 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
887 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
888
889 if (dsi->lanes < 2)
890 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
891
892 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
893 afec0 |= DSI0_PHY_AFEC0_RESET;
894
895 DSI_PORT_WRITE(PHY_AFEC0, afec0);
896
897 DSI_PORT_WRITE(PHY_AFEC1,
898 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
899 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
900 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
901 } else {
902 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
903 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
904 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
905 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
906 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
907 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
908 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
909
910 if (dsi->lanes < 4)
911 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
912 if (dsi->lanes < 3)
913 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
914 if (dsi->lanes < 2)
915 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
916
917 afec0 |= DSI1_PHY_AFEC0_RESET;
918
919 DSI_PORT_WRITE(PHY_AFEC0, afec0);
920
921 DSI_PORT_WRITE(PHY_AFEC1, 0);
922
923 /* AFEC reset hold time */
924 mdelay(1);
925 }
926
927 ret = clk_prepare_enable(dsi->escape_clock);
928 if (ret) {
929 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
930 return;
931 }
932
933 ret = clk_prepare_enable(dsi->pll_phy_clock);
934 if (ret) {
935 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
936 return;
937 }
938
939 hs_clock = clk_get_rate(dsi->pll_phy_clock);
940
941 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
942 * not the pixel clock rate. DSIxP take from the APHY's byte,
943 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
944 * that rate. Separately, a value derived from PIX_CLK_DIV
945 * and HS_CLKC is fed into the PV to divide down to the actual
946 * pixel clock for pushing pixels into DSI.
947 */
948 dsip_clock = phy_clock / 8;
949 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
950 if (ret) {
951 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
952 dsip_clock, ret);
953 }
954
955 ret = clk_prepare_enable(dsi->pixel_clock);
956 if (ret) {
957 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
958 return;
959 }
960
961 /* How many ns one DSI unit interval is. Note that the clock
962 * is DDR, so there's an extra divide by 2.
963 */
964 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
965
966 DSI_PORT_WRITE(HS_CLT0,
967 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
968 DSI_HS_CLT0_CZERO) |
969 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
970 DSI_HS_CLT0_CPRE) |
971 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
972 DSI_HS_CLT0_CPREP));
973
974 DSI_PORT_WRITE(HS_CLT1,
975 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
976 DSI_HS_CLT1_CTRAIL) |
977 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
978 DSI_HS_CLT1_CPOST));
979
980 DSI_PORT_WRITE(HS_CLT2,
981 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
982 DSI_HS_CLT2_WUP));
983
984 DSI_PORT_WRITE(HS_DLT3,
985 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
986 DSI_HS_DLT3_EXIT) |
987 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
988 DSI_HS_DLT3_ZERO) |
989 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
990 DSI_HS_DLT3_PRE));
991
992 DSI_PORT_WRITE(HS_DLT4,
993 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
994 DSI_HS_DLT4_LPX) |
995 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
996 dsi_hs_timing(ui_ns, 60, 4)),
997 DSI_HS_DLT4_TRAIL) |
998 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
999
1000 /* T_INIT is how long STOP is driven after power-up to
1001 * indicate to the slave (also coming out of power-up) that
1002 * master init is complete, and should be greater than the
1003 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1004 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1005 * T_INIT,SLAVE, while allowing protocols on top of it to give
1006 * greater minimums. The vc4 firmware uses an extremely
1007 * conservative 5ms, and we maintain that here.
1008 */
1009 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1010 5 * 1000 * 1000, 0),
1011 DSI_HS_DLT5_INIT));
1012
1013 DSI_PORT_WRITE(HS_DLT6,
1014 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1015 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1016 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1017 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1018
1019 DSI_PORT_WRITE(HS_DLT7,
1020 VC4_SET_FIELD(dsi_esc_timing(1000000),
1021 DSI_HS_DLT7_LP_WUP));
1022
1023 DSI_PORT_WRITE(PHYC,
1024 DSI_PHYC_DLANE0_ENABLE |
1025 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1026 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1027 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1028 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1029 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1030 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1031 (dsi->variant->port == 0 ?
1032 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1033 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1034
1035 DSI_PORT_WRITE(CTRL,
1036 DSI_PORT_READ(CTRL) |
1037 DSI_CTRL_CAL_BYTE);
1038
1039 /* HS timeout in HS clock cycles: disabled. */
1040 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1041 /* LP receive timeout in HS clocks. */
1042 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1043 /* Bus turnaround timeout */
1044 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1045 /* Display reset sequence timeout */
1046 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1047
1048 /* Set up DISP1 for transferring long command payloads through
1049 * the pixfifo.
1050 */
1051 DSI_PORT_WRITE(DISP1_CTRL,
1052 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1053 DSI_DISP1_PFORMAT) |
1054 DSI_DISP1_ENABLE);
1055
1056 /* Ungate the block. */
1057 if (dsi->variant->port == 0)
1058 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1059 else
1060 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1061
1062 /* Bring AFE out of reset. */
1063 if (dsi->variant->port == 0) {
1064 } else {
1065 DSI_PORT_WRITE(PHY_AFEC0,
1066 DSI_PORT_READ(PHY_AFEC0) &
1067 ~DSI1_PHY_AFEC0_RESET);
1068 }
1069
1070 vc4_dsi_ulps(dsi, false);
1071
1072 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1073 if (iter->funcs->pre_enable)
1074 iter->funcs->pre_enable(iter);
1075 }
1076
1077 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1078 DSI_PORT_WRITE(DISP0_CTRL,
1079 VC4_SET_FIELD(dsi->divider,
1080 DSI_DISP0_PIX_CLK_DIV) |
1081 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1082 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1083 DSI_DISP0_LP_STOP_CTRL) |
1084 DSI_DISP0_ST_END |
1085 DSI_DISP0_ENABLE);
1086 } else {
1087 DSI_PORT_WRITE(DISP0_CTRL,
1088 DSI_DISP0_COMMAND_MODE |
1089 DSI_DISP0_ENABLE);
1090 }
1091
1092 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1093 if (iter->funcs->enable)
1094 iter->funcs->enable(iter);
1095 }
1096
1097 if (debug_dump_regs) {
1098 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1099 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1100 drm_print_regset32(&p, &dsi->regset);
1101 }
1102}
1103
1104static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1105 const struct mipi_dsi_msg *msg)
1106{
1107 struct vc4_dsi *dsi = host_to_dsi(host);
1108 struct mipi_dsi_packet packet;
1109 u32 pkth = 0, pktc = 0;
1110 int i, ret;
1111 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1112 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1113
1114 mipi_dsi_create_packet(&packet, msg);
1115
1116 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1117 pkth |= VC4_SET_FIELD(packet.header[1] |
1118 (packet.header[2] << 8),
1119 DSI_TXPKT1H_BC_PARAM);
1120 if (is_long) {
1121 /* Divide data across the various FIFOs we have available.
1122 * The command FIFO takes byte-oriented data, but is of
1123 * limited size. The pixel FIFO (never actually used for
1124 * pixel data in reality) is word oriented, and substantially
1125 * larger. So, we use the pixel FIFO for most of the data,
1126 * sending the residual bytes in the command FIFO at the start.
1127 *
1128 * With this arrangement, the command FIFO will never get full.
1129 */
1130 if (packet.payload_length <= 16) {
1131 cmd_fifo_len = packet.payload_length;
1132 pix_fifo_len = 0;
1133 } else {
1134 cmd_fifo_len = (packet.payload_length %
1135 DSI_PIX_FIFO_WIDTH);
1136 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1137 DSI_PIX_FIFO_WIDTH);
1138 }
1139
1140 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1141
1142 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1143 }
1144
1145 if (msg->rx_len) {
1146 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1147 DSI_TXPKT1C_CMD_CTRL);
1148 } else {
1149 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1150 DSI_TXPKT1C_CMD_CTRL);
1151 }
1152
1153 for (i = 0; i < cmd_fifo_len; i++)
1154 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1155 for (i = 0; i < pix_fifo_len; i++) {
1156 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1157
1158 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1159 pix[0] |
1160 pix[1] << 8 |
1161 pix[2] << 16 |
1162 pix[3] << 24);
1163 }
1164
1165 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1166 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1167 if (is_long)
1168 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1169
1170 /* Send one copy of the packet. Larger repeats are used for pixel
1171 * data in command mode.
1172 */
1173 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1174
1175 pktc |= DSI_TXPKT1C_CMD_EN;
1176 if (pix_fifo_len) {
1177 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1178 DSI_TXPKT1C_DISPLAY_NO);
1179 } else {
1180 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1181 DSI_TXPKT1C_DISPLAY_NO);
1182 }
1183
1184 /* Enable the appropriate interrupt for the transfer completion. */
1185 dsi->xfer_result = 0;
1186 reinit_completion(&dsi->xfer_completion);
1187 DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1188 if (msg->rx_len) {
1189 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1190 DSI1_INT_PHY_DIR_RTF));
1191 } else {
1192 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1193 DSI1_INT_TXPKT1_DONE));
1194 }
1195
1196 /* Send the packet. */
1197 DSI_PORT_WRITE(TXPKT1H, pkth);
1198 DSI_PORT_WRITE(TXPKT1C, pktc);
1199
1200 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1201 msecs_to_jiffies(1000))) {
1202 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1203 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1204 DSI_PORT_READ(INT_STAT));
1205 ret = -ETIMEDOUT;
1206 } else {
1207 ret = dsi->xfer_result;
1208 }
1209
1210 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1211
1212 if (ret)
1213 goto reset_fifo_and_return;
1214
1215 if (ret == 0 && msg->rx_len) {
1216 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1217 u8 *msg_rx = msg->rx_buf;
1218
1219 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1220 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1221 DSI_RXPKT1H_BC_PARAM);
1222
1223 if (rxlen != msg->rx_len) {
1224 DRM_ERROR("DSI returned %db, expecting %db\n",
1225 rxlen, (int)msg->rx_len);
1226 ret = -ENXIO;
1227 goto reset_fifo_and_return;
1228 }
1229
1230 for (i = 0; i < msg->rx_len; i++)
1231 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1232 } else {
1233 /* FINISHME: Handle AWER */
1234
1235 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1236 DSI_RXPKT1H_SHORT_0);
1237 if (msg->rx_len > 1) {
1238 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1239 DSI_RXPKT1H_SHORT_1);
1240 }
1241 }
1242 }
1243
1244 return ret;
1245
1246reset_fifo_and_return:
1247 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1248
1249 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1250 udelay(1);
1251 DSI_PORT_WRITE(CTRL,
1252 DSI_PORT_READ(CTRL) |
1253 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1254
1255 DSI_PORT_WRITE(TXPKT1C, 0);
1256 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1257 return ret;
1258}
1259
1260static const struct component_ops vc4_dsi_ops;
1261static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1262 struct mipi_dsi_device *device)
1263{
1264 struct vc4_dsi *dsi = host_to_dsi(host);
1265 int ret;
1266
1267 dsi->lanes = device->lanes;
1268 dsi->channel = device->channel;
1269 dsi->mode_flags = device->mode_flags;
1270
1271 switch (device->format) {
1272 case MIPI_DSI_FMT_RGB888:
1273 dsi->format = DSI_PFORMAT_RGB888;
1274 dsi->divider = 24 / dsi->lanes;
1275 break;
1276 case MIPI_DSI_FMT_RGB666:
1277 dsi->format = DSI_PFORMAT_RGB666;
1278 dsi->divider = 24 / dsi->lanes;
1279 break;
1280 case MIPI_DSI_FMT_RGB666_PACKED:
1281 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1282 dsi->divider = 18 / dsi->lanes;
1283 break;
1284 case MIPI_DSI_FMT_RGB565:
1285 dsi->format = DSI_PFORMAT_RGB565;
1286 dsi->divider = 16 / dsi->lanes;
1287 break;
1288 default:
1289 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1290 dsi->format);
1291 return 0;
1292 }
1293
1294 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1295 dev_err(&dsi->pdev->dev,
1296 "Only VIDEO mode panels supported currently.\n");
1297 return 0;
1298 }
1299
1300 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1301 if (ret) {
1302 mipi_dsi_host_unregister(&dsi->dsi_host);
1303 return ret;
1304 }
1305
1306 return 0;
1307}
1308
1309static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1310 struct mipi_dsi_device *device)
1311{
1312 return 0;
1313}
1314
1315static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1316 .attach = vc4_dsi_host_attach,
1317 .detach = vc4_dsi_host_detach,
1318 .transfer = vc4_dsi_host_transfer,
1319};
1320
1321static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1322 .disable = vc4_dsi_encoder_disable,
1323 .enable = vc4_dsi_encoder_enable,
1324 .mode_fixup = vc4_dsi_encoder_mode_fixup,
1325};
1326
1327static const struct vc4_dsi_variant bcm2711_dsi1_variant = {
1328 .port = 1,
1329 .debugfs_name = "dsi1_regs",
1330 .regs = dsi1_regs,
1331 .nregs = ARRAY_SIZE(dsi1_regs),
1332};
1333
1334static const struct vc4_dsi_variant bcm2835_dsi0_variant = {
1335 .port = 0,
1336 .debugfs_name = "dsi0_regs",
1337 .regs = dsi0_regs,
1338 .nregs = ARRAY_SIZE(dsi0_regs),
1339};
1340
1341static const struct vc4_dsi_variant bcm2835_dsi1_variant = {
1342 .port = 1,
1343 .broken_axi_workaround = true,
1344 .debugfs_name = "dsi1_regs",
1345 .regs = dsi1_regs,
1346 .nregs = ARRAY_SIZE(dsi1_regs),
1347};
1348
1349static const struct of_device_id vc4_dsi_dt_match[] = {
1350 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1351 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1352 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1353 {}
1354};
1355
1356static void dsi_handle_error(struct vc4_dsi *dsi,
1357 irqreturn_t *ret, u32 stat, u32 bit,
1358 const char *type)
1359{
1360 if (!(stat & bit))
1361 return;
1362
1363 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1364 *ret = IRQ_HANDLED;
1365}
1366
1367/*
1368 * Initial handler for port 1 where we need the reg_dma workaround.
1369 * The register DMA writes sleep, so we can't do it in the top half.
1370 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1371 * parent interrupt contrller until our interrupt thread is done.
1372 */
1373static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1374{
1375 struct vc4_dsi *dsi = data;
1376 u32 stat = DSI_PORT_READ(INT_STAT);
1377
1378 if (!stat)
1379 return IRQ_NONE;
1380
1381 return IRQ_WAKE_THREAD;
1382}
1383
1384/*
1385 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1386 * 1 where we need the reg_dma workaround.
1387 */
1388static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1389{
1390 struct vc4_dsi *dsi = data;
1391 u32 stat = DSI_PORT_READ(INT_STAT);
1392 irqreturn_t ret = IRQ_NONE;
1393
1394 DSI_PORT_WRITE(INT_STAT, stat);
1395
1396 dsi_handle_error(dsi, &ret, stat,
1397 DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1398 dsi_handle_error(dsi, &ret, stat,
1399 DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1400 dsi_handle_error(dsi, &ret, stat,
1401 DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1402 dsi_handle_error(dsi, &ret, stat,
1403 DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1404 dsi_handle_error(dsi, &ret, stat,
1405 DSI1_INT_HSTX_TO, "HSTX timeout");
1406 dsi_handle_error(dsi, &ret, stat,
1407 DSI1_INT_LPRX_TO, "LPRX timeout");
1408 dsi_handle_error(dsi, &ret, stat,
1409 DSI1_INT_TA_TO, "turnaround timeout");
1410 dsi_handle_error(dsi, &ret, stat,
1411 DSI1_INT_PR_TO, "peripheral reset timeout");
1412
1413 if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1414 complete(&dsi->xfer_completion);
1415 ret = IRQ_HANDLED;
1416 } else if (stat & DSI1_INT_HSTX_TO) {
1417 complete(&dsi->xfer_completion);
1418 dsi->xfer_result = -ETIMEDOUT;
1419 ret = IRQ_HANDLED;
1420 }
1421
1422 return ret;
1423}
1424
1425/**
1426 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1427 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1428 * @dsi: DSI encoder
1429 */
1430static int
1431vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1432{
1433 struct device *dev = &dsi->pdev->dev;
1434 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1435 static const struct {
1436 const char *name;
1437 int div;
1438 } phy_clocks[] = {
1439 { "byte", 8 },
1440 { "ddr2", 4 },
1441 { "ddr", 2 },
1442 };
1443 int i;
1444
1445 dsi->clk_onecell = devm_kzalloc(dev,
1446 sizeof(*dsi->clk_onecell) +
1447 ARRAY_SIZE(phy_clocks) *
1448 sizeof(struct clk_hw *),
1449 GFP_KERNEL);
1450 if (!dsi->clk_onecell)
1451 return -ENOMEM;
1452 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1453
1454 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1455 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1456 struct clk_init_data init;
1457 char clk_name[16];
1458 int ret;
1459
1460 snprintf(clk_name, sizeof(clk_name),
1461 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1462
1463 /* We just use core fixed factor clock ops for the PHY
1464 * clocks. The clocks are actually gated by the
1465 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1466 * setting if we use the DDR/DDR2 clocks. However,
1467 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1468 * setting both our parent DSI PLL's rate and this
1469 * clock's rate, so it knows if DDR/DDR2 are going to
1470 * be used and could enable the gates itself.
1471 */
1472 fix->mult = 1;
1473 fix->div = phy_clocks[i].div;
1474 fix->hw.init = &init;
1475
1476 memset(&init, 0, sizeof(init));
1477 init.parent_names = &parent_name;
1478 init.num_parents = 1;
1479 init.name = clk_name;
1480 init.ops = &clk_fixed_factor_ops;
1481
1482 ret = devm_clk_hw_register(dev, &fix->hw);
1483 if (ret)
1484 return ret;
1485
1486 dsi->clk_onecell->hws[i] = &fix->hw;
1487 }
1488
1489 return of_clk_add_hw_provider(dev->of_node,
1490 of_clk_hw_onecell_get,
1491 dsi->clk_onecell);
1492}
1493
1494static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1495{
1496 struct platform_device *pdev = to_platform_device(dev);
1497 struct drm_device *drm = dev_get_drvdata(master);
1498 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1499 struct vc4_dsi_encoder *vc4_dsi_encoder;
1500 struct drm_panel *panel;
1501 const struct of_device_id *match;
1502 dma_cap_mask_t dma_mask;
1503 int ret;
1504
1505 match = of_match_device(vc4_dsi_dt_match, dev);
1506 if (!match)
1507 return -ENODEV;
1508
1509 dsi->variant = match->data;
1510
1511 vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1512 GFP_KERNEL);
1513 if (!vc4_dsi_encoder)
1514 return -ENOMEM;
1515
1516 INIT_LIST_HEAD(&dsi->bridge_chain);
1517 vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1518 vc4_dsi_encoder->dsi = dsi;
1519 dsi->encoder = &vc4_dsi_encoder->base.base;
1520
1521 dsi->regs = vc4_ioremap_regs(pdev, 0);
1522 if (IS_ERR(dsi->regs))
1523 return PTR_ERR(dsi->regs);
1524
1525 dsi->regset.base = dsi->regs;
1526 dsi->regset.regs = dsi->variant->regs;
1527 dsi->regset.nregs = dsi->variant->nregs;
1528
1529 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1530 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1531 DSI_PORT_READ(ID), DSI_ID_VALUE);
1532 return -ENODEV;
1533 }
1534
1535 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to
1536 * writes from the ARM. It does handle writes from the DMA engine,
1537 * so set up a channel for talking to it.
1538 */
1539 if (dsi->variant->broken_axi_workaround) {
1540 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1541 &dsi->reg_dma_paddr,
1542 GFP_KERNEL);
1543 if (!dsi->reg_dma_mem) {
1544 DRM_ERROR("Failed to get DMA memory\n");
1545 return -ENOMEM;
1546 }
1547
1548 dma_cap_zero(dma_mask);
1549 dma_cap_set(DMA_MEMCPY, dma_mask);
1550 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1551 if (IS_ERR(dsi->reg_dma_chan)) {
1552 ret = PTR_ERR(dsi->reg_dma_chan);
1553 if (ret != -EPROBE_DEFER)
1554 DRM_ERROR("Failed to get DMA channel: %d\n",
1555 ret);
1556 return ret;
1557 }
1558
1559 /* Get the physical address of the device's registers. The
1560 * struct resource for the regs gives us the bus address
1561 * instead.
1562 */
1563 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1564 0, NULL, NULL));
1565 }
1566
1567 init_completion(&dsi->xfer_completion);
1568 /* At startup enable error-reporting interrupts and nothing else. */
1569 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1570 /* Clear any existing interrupt state. */
1571 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1572
1573 if (dsi->reg_dma_mem)
1574 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1575 vc4_dsi_irq_defer_to_thread_handler,
1576 vc4_dsi_irq_handler,
1577 IRQF_ONESHOT,
1578 "vc4 dsi", dsi);
1579 else
1580 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1581 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1582 if (ret) {
1583 if (ret != -EPROBE_DEFER)
1584 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1585 return ret;
1586 }
1587
1588 dsi->escape_clock = devm_clk_get(dev, "escape");
1589 if (IS_ERR(dsi->escape_clock)) {
1590 ret = PTR_ERR(dsi->escape_clock);
1591 if (ret != -EPROBE_DEFER)
1592 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1593 return ret;
1594 }
1595
1596 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1597 if (IS_ERR(dsi->pll_phy_clock)) {
1598 ret = PTR_ERR(dsi->pll_phy_clock);
1599 if (ret != -EPROBE_DEFER)
1600 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1601 return ret;
1602 }
1603
1604 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1605 if (IS_ERR(dsi->pixel_clock)) {
1606 ret = PTR_ERR(dsi->pixel_clock);
1607 if (ret != -EPROBE_DEFER)
1608 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1609 return ret;
1610 }
1611
1612 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1613 &panel, &dsi->bridge);
1614 if (ret) {
1615 /* If the bridge or panel pointed by dev->of_node is not
1616 * enabled, just return 0 here so that we don't prevent the DRM
1617 * dev from being registered. Of course that means the DSI
1618 * encoder won't be exposed, but that's not a problem since
1619 * nothing is connected to it.
1620 */
1621 if (ret == -ENODEV)
1622 return 0;
1623
1624 return ret;
1625 }
1626
1627 if (panel) {
1628 dsi->bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1629 DRM_MODE_CONNECTOR_DSI);
1630 if (IS_ERR(dsi->bridge))
1631 return PTR_ERR(dsi->bridge);
1632 }
1633
1634 /* The esc clock rate is supposed to always be 100Mhz. */
1635 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1636 if (ret) {
1637 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1638 return ret;
1639 }
1640
1641 ret = vc4_dsi_init_phy_clocks(dsi);
1642 if (ret)
1643 return ret;
1644
1645 drm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI);
1646 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1647
1648 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL, 0);
1649 if (ret) {
1650 dev_err(dev, "bridge attach failed: %d\n", ret);
1651 return ret;
1652 }
1653 /* Disable the atomic helper calls into the bridge. We
1654 * manually call the bridge pre_enable / enable / etc. calls
1655 * from our driver, since we need to sequence them within the
1656 * encoder's enable/disable paths.
1657 */
1658 list_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain);
1659
1660 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);
1661
1662 pm_runtime_enable(dev);
1663
1664 return 0;
1665}
1666
1667static void vc4_dsi_unbind(struct device *dev, struct device *master,
1668 void *data)
1669{
1670 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1671
1672 if (dsi->bridge)
1673 pm_runtime_disable(dev);
1674
1675 /*
1676 * Restore the bridge_chain so the bridge detach procedure can happen
1677 * normally.
1678 */
1679 list_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain);
1680 drm_encoder_cleanup(dsi->encoder);
1681}
1682
1683static const struct component_ops vc4_dsi_ops = {
1684 .bind = vc4_dsi_bind,
1685 .unbind = vc4_dsi_unbind,
1686};
1687
1688static int vc4_dsi_dev_probe(struct platform_device *pdev)
1689{
1690 struct device *dev = &pdev->dev;
1691 struct vc4_dsi *dsi;
1692
1693 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1694 if (!dsi)
1695 return -ENOMEM;
1696 dev_set_drvdata(dev, dsi);
1697
1698 dsi->pdev = pdev;
1699 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1700 dsi->dsi_host.dev = dev;
1701 mipi_dsi_host_register(&dsi->dsi_host);
1702
1703 return 0;
1704}
1705
1706static int vc4_dsi_dev_remove(struct platform_device *pdev)
1707{
1708 struct device *dev = &pdev->dev;
1709 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1710
1711 component_del(&pdev->dev, &vc4_dsi_ops);
1712 mipi_dsi_host_unregister(&dsi->dsi_host);
1713
1714 return 0;
1715}
1716
1717struct platform_driver vc4_dsi_driver = {
1718 .probe = vc4_dsi_dev_probe,
1719 .remove = vc4_dsi_dev_remove,
1720 .driver = {
1721 .name = "vc4_dsi",
1722 .of_match_table = vc4_dsi_dt_match,
1723 },
1724};