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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103/* RADEON_IB_POOL_SIZE must be a power of 2 */
104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
107#define RADEON_BIOS_NUM_SCRATCH 8
108
109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
125#define ATRM_BIOS_PAGE 4096
126
127#if defined(CONFIG_VGA_SWITCHEROO)
128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
140bool radeon_get_bios(struct radeon_device *rdev);
141
142
143/*
144 * Dummy page
145 */
146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
153
154/*
155 * Clocks
156 */
157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
168 uint32_t max_pixel_clock;
169};
170
171/*
172 * Power management
173 */
174int radeon_pm_init(struct radeon_device *rdev);
175void radeon_pm_fini(struct radeon_device *rdev);
176void radeon_pm_compute_clocks(struct radeon_device *rdev);
177void radeon_pm_suspend(struct radeon_device *rdev);
178void radeon_pm_resume(struct radeon_device *rdev);
179void radeon_combios_get_power_modes(struct radeon_device *rdev);
180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
183void rs690_pm_info(struct radeon_device *rdev);
184extern int rv6xx_get_temp(struct radeon_device *rdev);
185extern int rv770_get_temp(struct radeon_device *rdev);
186extern int evergreen_get_temp(struct radeon_device *rdev);
187extern int sumo_get_temp(struct radeon_device *rdev);
188
189/*
190 * Fences.
191 */
192struct radeon_fence_driver {
193 uint32_t scratch_reg;
194 atomic_t seq;
195 uint32_t last_seq;
196 unsigned long last_jiffies;
197 unsigned long last_timeout;
198 wait_queue_head_t queue;
199 rwlock_t lock;
200 struct list_head created;
201 struct list_head emited;
202 struct list_head signaled;
203 bool initialized;
204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
212 bool emited;
213 bool signaled;
214};
215
216int radeon_fence_driver_init(struct radeon_device *rdev);
217void radeon_fence_driver_fini(struct radeon_device *rdev);
218int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
219int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
220void radeon_fence_process(struct radeon_device *rdev);
221bool radeon_fence_signaled(struct radeon_fence *fence);
222int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
223int radeon_fence_wait_next(struct radeon_device *rdev);
224int radeon_fence_wait_last(struct radeon_device *rdev);
225struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
226void radeon_fence_unref(struct radeon_fence **fence);
227
228/*
229 * Tiling registers
230 */
231struct radeon_surface_reg {
232 struct radeon_bo *bo;
233};
234
235#define RADEON_GEM_MAX_SURFACES 8
236
237/*
238 * TTM.
239 */
240struct radeon_mman {
241 struct ttm_bo_global_ref bo_global_ref;
242 struct drm_global_reference mem_global_ref;
243 struct ttm_bo_device bdev;
244 bool mem_global_referenced;
245 bool initialized;
246};
247
248struct radeon_bo {
249 /* Protected by gem.mutex */
250 struct list_head list;
251 /* Protected by tbo.reserved */
252 u32 placements[3];
253 struct ttm_placement placement;
254 struct ttm_buffer_object tbo;
255 struct ttm_bo_kmap_obj kmap;
256 unsigned pin_count;
257 void *kptr;
258 u32 tiling_flags;
259 u32 pitch;
260 int surface_reg;
261 /* Constant after initialization */
262 struct radeon_device *rdev;
263 struct drm_gem_object gem_base;
264};
265#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
266
267struct radeon_bo_list {
268 struct ttm_validate_buffer tv;
269 struct radeon_bo *bo;
270 uint64_t gpu_offset;
271 unsigned rdomain;
272 unsigned wdomain;
273 u32 tiling_flags;
274};
275
276/*
277 * GEM objects.
278 */
279struct radeon_gem {
280 struct mutex mutex;
281 struct list_head objects;
282};
283
284int radeon_gem_init(struct radeon_device *rdev);
285void radeon_gem_fini(struct radeon_device *rdev);
286int radeon_gem_object_create(struct radeon_device *rdev, int size,
287 int alignment, int initial_domain,
288 bool discardable, bool kernel,
289 struct drm_gem_object **obj);
290int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
291 uint64_t *gpu_addr);
292void radeon_gem_object_unpin(struct drm_gem_object *obj);
293
294int radeon_mode_dumb_create(struct drm_file *file_priv,
295 struct drm_device *dev,
296 struct drm_mode_create_dumb *args);
297int radeon_mode_dumb_mmap(struct drm_file *filp,
298 struct drm_device *dev,
299 uint32_t handle, uint64_t *offset_p);
300int radeon_mode_dumb_destroy(struct drm_file *file_priv,
301 struct drm_device *dev,
302 uint32_t handle);
303
304/*
305 * GART structures, functions & helpers
306 */
307struct radeon_mc;
308
309struct radeon_gart_table_ram {
310 volatile uint32_t *ptr;
311};
312
313struct radeon_gart_table_vram {
314 struct radeon_bo *robj;
315 volatile uint32_t *ptr;
316};
317
318union radeon_gart_table {
319 struct radeon_gart_table_ram ram;
320 struct radeon_gart_table_vram vram;
321};
322
323#define RADEON_GPU_PAGE_SIZE 4096
324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
325#define RADEON_GPU_PAGE_SHIFT 12
326
327struct radeon_gart {
328 dma_addr_t table_addr;
329 unsigned num_gpu_pages;
330 unsigned num_cpu_pages;
331 unsigned table_size;
332 union radeon_gart_table table;
333 struct page **pages;
334 dma_addr_t *pages_addr;
335 bool *ttm_alloced;
336 bool ready;
337};
338
339int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
340void radeon_gart_table_ram_free(struct radeon_device *rdev);
341int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
342void radeon_gart_table_vram_free(struct radeon_device *rdev);
343int radeon_gart_init(struct radeon_device *rdev);
344void radeon_gart_fini(struct radeon_device *rdev);
345void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
346 int pages);
347int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
348 int pages, struct page **pagelist,
349 dma_addr_t *dma_addr);
350
351
352/*
353 * GPU MC structures, functions & helpers
354 */
355struct radeon_mc {
356 resource_size_t aper_size;
357 resource_size_t aper_base;
358 resource_size_t agp_base;
359 /* for some chips with <= 32MB we need to lie
360 * about vram size near mc fb location */
361 u64 mc_vram_size;
362 u64 visible_vram_size;
363 u64 gtt_size;
364 u64 gtt_start;
365 u64 gtt_end;
366 u64 vram_start;
367 u64 vram_end;
368 unsigned vram_width;
369 u64 real_vram_size;
370 int vram_mtrr;
371 bool vram_is_ddr;
372 bool igp_sideport_enabled;
373 u64 gtt_base_align;
374};
375
376bool radeon_combios_sideport_present(struct radeon_device *rdev);
377bool radeon_atombios_sideport_present(struct radeon_device *rdev);
378
379/*
380 * GPU scratch registers structures, functions & helpers
381 */
382struct radeon_scratch {
383 unsigned num_reg;
384 uint32_t reg_base;
385 bool free[32];
386 uint32_t reg[32];
387};
388
389int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
390void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
391
392
393/*
394 * IRQS.
395 */
396
397struct radeon_unpin_work {
398 struct work_struct work;
399 struct radeon_device *rdev;
400 int crtc_id;
401 struct radeon_fence *fence;
402 struct drm_pending_vblank_event *event;
403 struct radeon_bo *old_rbo;
404 u64 new_crtc_base;
405};
406
407struct r500_irq_stat_regs {
408 u32 disp_int;
409};
410
411struct r600_irq_stat_regs {
412 u32 disp_int;
413 u32 disp_int_cont;
414 u32 disp_int_cont2;
415 u32 d1grph_int;
416 u32 d2grph_int;
417};
418
419struct evergreen_irq_stat_regs {
420 u32 disp_int;
421 u32 disp_int_cont;
422 u32 disp_int_cont2;
423 u32 disp_int_cont3;
424 u32 disp_int_cont4;
425 u32 disp_int_cont5;
426 u32 d1grph_int;
427 u32 d2grph_int;
428 u32 d3grph_int;
429 u32 d4grph_int;
430 u32 d5grph_int;
431 u32 d6grph_int;
432};
433
434union radeon_irq_stat_regs {
435 struct r500_irq_stat_regs r500;
436 struct r600_irq_stat_regs r600;
437 struct evergreen_irq_stat_regs evergreen;
438};
439
440struct radeon_irq {
441 bool installed;
442 bool sw_int;
443 /* FIXME: use a define max crtc rather than hardcode it */
444 bool crtc_vblank_int[6];
445 bool pflip[6];
446 wait_queue_head_t vblank_queue;
447 /* FIXME: use defines for max hpd/dacs */
448 bool hpd[6];
449 bool gui_idle;
450 bool gui_idle_acked;
451 wait_queue_head_t idle_queue;
452 /* FIXME: use defines for max HDMI blocks */
453 bool hdmi[2];
454 spinlock_t sw_lock;
455 int sw_refcount;
456 union radeon_irq_stat_regs stat_regs;
457 spinlock_t pflip_lock[6];
458 int pflip_refcount[6];
459};
460
461int radeon_irq_kms_init(struct radeon_device *rdev);
462void radeon_irq_kms_fini(struct radeon_device *rdev);
463void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
464void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
465void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
466void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
467
468/*
469 * CP & ring.
470 */
471struct radeon_ib {
472 struct list_head list;
473 unsigned idx;
474 uint64_t gpu_addr;
475 struct radeon_fence *fence;
476 uint32_t *ptr;
477 uint32_t length_dw;
478 bool free;
479};
480
481/*
482 * locking -
483 * mutex protects scheduled_ibs, ready, alloc_bm
484 */
485struct radeon_ib_pool {
486 struct mutex mutex;
487 struct radeon_bo *robj;
488 struct list_head bogus_ib;
489 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
490 bool ready;
491 unsigned head_id;
492};
493
494struct radeon_cp {
495 struct radeon_bo *ring_obj;
496 volatile uint32_t *ring;
497 unsigned rptr;
498 unsigned wptr;
499 unsigned wptr_old;
500 unsigned ring_size;
501 unsigned ring_free_dw;
502 int count_dw;
503 uint64_t gpu_addr;
504 uint32_t align_mask;
505 uint32_t ptr_mask;
506 struct mutex mutex;
507 bool ready;
508};
509
510/*
511 * R6xx+ IH ring
512 */
513struct r600_ih {
514 struct radeon_bo *ring_obj;
515 volatile uint32_t *ring;
516 unsigned rptr;
517 unsigned wptr;
518 unsigned wptr_old;
519 unsigned ring_size;
520 uint64_t gpu_addr;
521 uint32_t ptr_mask;
522 spinlock_t lock;
523 bool enabled;
524};
525
526struct r600_blit {
527 struct mutex mutex;
528 struct radeon_bo *shader_obj;
529 u64 shader_gpu_addr;
530 u32 vs_offset, ps_offset;
531 u32 state_offset;
532 u32 state_len;
533 u32 vb_used, vb_total;
534 struct radeon_ib *vb_ib;
535};
536
537int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
538void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
539int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
540int radeon_ib_pool_init(struct radeon_device *rdev);
541void radeon_ib_pool_fini(struct radeon_device *rdev);
542int radeon_ib_test(struct radeon_device *rdev);
543extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
544/* Ring access between begin & end cannot sleep */
545void radeon_ring_free_size(struct radeon_device *rdev);
546int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
547int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
548void radeon_ring_commit(struct radeon_device *rdev);
549void radeon_ring_unlock_commit(struct radeon_device *rdev);
550void radeon_ring_unlock_undo(struct radeon_device *rdev);
551int radeon_ring_test(struct radeon_device *rdev);
552int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
553void radeon_ring_fini(struct radeon_device *rdev);
554
555
556/*
557 * CS.
558 */
559struct radeon_cs_reloc {
560 struct drm_gem_object *gobj;
561 struct radeon_bo *robj;
562 struct radeon_bo_list lobj;
563 uint32_t handle;
564 uint32_t flags;
565};
566
567struct radeon_cs_chunk {
568 uint32_t chunk_id;
569 uint32_t length_dw;
570 int kpage_idx[2];
571 uint32_t *kpage[2];
572 uint32_t *kdata;
573 void __user *user_ptr;
574 int last_copied_page;
575 int last_page_index;
576};
577
578struct radeon_cs_parser {
579 struct device *dev;
580 struct radeon_device *rdev;
581 struct drm_file *filp;
582 /* chunks */
583 unsigned nchunks;
584 struct radeon_cs_chunk *chunks;
585 uint64_t *chunks_array;
586 /* IB */
587 unsigned idx;
588 /* relocations */
589 unsigned nrelocs;
590 struct radeon_cs_reloc *relocs;
591 struct radeon_cs_reloc **relocs_ptr;
592 struct list_head validated;
593 /* indices of various chunks */
594 int chunk_ib_idx;
595 int chunk_relocs_idx;
596 struct radeon_ib *ib;
597 void *track;
598 unsigned family;
599 int parser_error;
600};
601
602extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
603extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
604
605
606static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
607{
608 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 u32 pg_idx, pg_offset;
610 u32 idx_value = 0;
611 int new_page;
612
613 pg_idx = (idx * 4) / PAGE_SIZE;
614 pg_offset = (idx * 4) % PAGE_SIZE;
615
616 if (ibc->kpage_idx[0] == pg_idx)
617 return ibc->kpage[0][pg_offset/4];
618 if (ibc->kpage_idx[1] == pg_idx)
619 return ibc->kpage[1][pg_offset/4];
620
621 new_page = radeon_cs_update_pages(p, pg_idx);
622 if (new_page < 0) {
623 p->parser_error = new_page;
624 return 0;
625 }
626
627 idx_value = ibc->kpage[new_page][pg_offset/4];
628 return idx_value;
629}
630
631struct radeon_cs_packet {
632 unsigned idx;
633 unsigned type;
634 unsigned reg;
635 unsigned opcode;
636 int count;
637 unsigned one_reg_wr;
638};
639
640typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt,
642 unsigned idx, unsigned reg);
643typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
644 struct radeon_cs_packet *pkt);
645
646
647/*
648 * AGP
649 */
650int radeon_agp_init(struct radeon_device *rdev);
651void radeon_agp_resume(struct radeon_device *rdev);
652void radeon_agp_suspend(struct radeon_device *rdev);
653void radeon_agp_fini(struct radeon_device *rdev);
654
655
656/*
657 * Writeback
658 */
659struct radeon_wb {
660 struct radeon_bo *wb_obj;
661 volatile uint32_t *wb;
662 uint64_t gpu_addr;
663 bool enabled;
664 bool use_event;
665};
666
667#define RADEON_WB_SCRATCH_OFFSET 0
668#define RADEON_WB_CP_RPTR_OFFSET 1024
669#define RADEON_WB_CP1_RPTR_OFFSET 1280
670#define RADEON_WB_CP2_RPTR_OFFSET 1536
671#define R600_WB_IH_WPTR_OFFSET 2048
672#define R600_WB_EVENT_OFFSET 3072
673
674/**
675 * struct radeon_pm - power management datas
676 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
677 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
678 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
679 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
680 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
681 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
682 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
683 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
684 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
685 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
686 * @needed_bandwidth: current bandwidth needs
687 *
688 * It keeps track of various data needed to take powermanagement decision.
689 * Bandwidth need is used to determine minimun clock of the GPU and memory.
690 * Equation between gpu/memory clock and available bandwidth is hw dependent
691 * (type of memory, bus size, efficiency, ...)
692 */
693
694enum radeon_pm_method {
695 PM_METHOD_PROFILE,
696 PM_METHOD_DYNPM,
697};
698
699enum radeon_dynpm_state {
700 DYNPM_STATE_DISABLED,
701 DYNPM_STATE_MINIMUM,
702 DYNPM_STATE_PAUSED,
703 DYNPM_STATE_ACTIVE,
704 DYNPM_STATE_SUSPENDED,
705};
706enum radeon_dynpm_action {
707 DYNPM_ACTION_NONE,
708 DYNPM_ACTION_MINIMUM,
709 DYNPM_ACTION_DOWNCLOCK,
710 DYNPM_ACTION_UPCLOCK,
711 DYNPM_ACTION_DEFAULT
712};
713
714enum radeon_voltage_type {
715 VOLTAGE_NONE = 0,
716 VOLTAGE_GPIO,
717 VOLTAGE_VDDC,
718 VOLTAGE_SW
719};
720
721enum radeon_pm_state_type {
722 POWER_STATE_TYPE_DEFAULT,
723 POWER_STATE_TYPE_POWERSAVE,
724 POWER_STATE_TYPE_BATTERY,
725 POWER_STATE_TYPE_BALANCED,
726 POWER_STATE_TYPE_PERFORMANCE,
727};
728
729enum radeon_pm_profile_type {
730 PM_PROFILE_DEFAULT,
731 PM_PROFILE_AUTO,
732 PM_PROFILE_LOW,
733 PM_PROFILE_MID,
734 PM_PROFILE_HIGH,
735};
736
737#define PM_PROFILE_DEFAULT_IDX 0
738#define PM_PROFILE_LOW_SH_IDX 1
739#define PM_PROFILE_MID_SH_IDX 2
740#define PM_PROFILE_HIGH_SH_IDX 3
741#define PM_PROFILE_LOW_MH_IDX 4
742#define PM_PROFILE_MID_MH_IDX 5
743#define PM_PROFILE_HIGH_MH_IDX 6
744#define PM_PROFILE_MAX 7
745
746struct radeon_pm_profile {
747 int dpms_off_ps_idx;
748 int dpms_on_ps_idx;
749 int dpms_off_cm_idx;
750 int dpms_on_cm_idx;
751};
752
753enum radeon_int_thermal_type {
754 THERMAL_TYPE_NONE,
755 THERMAL_TYPE_RV6XX,
756 THERMAL_TYPE_RV770,
757 THERMAL_TYPE_EVERGREEN,
758 THERMAL_TYPE_SUMO,
759 THERMAL_TYPE_NI,
760};
761
762struct radeon_voltage {
763 enum radeon_voltage_type type;
764 /* gpio voltage */
765 struct radeon_gpio_rec gpio;
766 u32 delay; /* delay in usec from voltage drop to sclk change */
767 bool active_high; /* voltage drop is active when bit is high */
768 /* VDDC voltage */
769 u8 vddc_id; /* index into vddc voltage table */
770 u8 vddci_id; /* index into vddci voltage table */
771 bool vddci_enabled;
772 /* r6xx+ sw */
773 u16 voltage;
774 /* evergreen+ vddci */
775 u16 vddci;
776};
777
778/* clock mode flags */
779#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
780
781struct radeon_pm_clock_info {
782 /* memory clock */
783 u32 mclk;
784 /* engine clock */
785 u32 sclk;
786 /* voltage info */
787 struct radeon_voltage voltage;
788 /* standardized clock flags */
789 u32 flags;
790};
791
792/* state flags */
793#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
794
795struct radeon_power_state {
796 enum radeon_pm_state_type type;
797 /* XXX: use a define for num clock modes */
798 struct radeon_pm_clock_info clock_info[8];
799 /* number of valid clock modes in this power state */
800 int num_clock_modes;
801 struct radeon_pm_clock_info *default_clock_mode;
802 /* standardized state flags */
803 u32 flags;
804 u32 misc; /* vbios specific flags */
805 u32 misc2; /* vbios specific flags */
806 int pcie_lanes; /* pcie lanes */
807};
808
809/*
810 * Some modes are overclocked by very low value, accept them
811 */
812#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
813
814struct radeon_pm {
815 struct mutex mutex;
816 u32 active_crtcs;
817 int active_crtc_count;
818 int req_vblank;
819 bool vblank_sync;
820 bool gui_idle;
821 fixed20_12 max_bandwidth;
822 fixed20_12 igp_sideport_mclk;
823 fixed20_12 igp_system_mclk;
824 fixed20_12 igp_ht_link_clk;
825 fixed20_12 igp_ht_link_width;
826 fixed20_12 k8_bandwidth;
827 fixed20_12 sideport_bandwidth;
828 fixed20_12 ht_bandwidth;
829 fixed20_12 core_bandwidth;
830 fixed20_12 sclk;
831 fixed20_12 mclk;
832 fixed20_12 needed_bandwidth;
833 struct radeon_power_state *power_state;
834 /* number of valid power states */
835 int num_power_states;
836 int current_power_state_index;
837 int current_clock_mode_index;
838 int requested_power_state_index;
839 int requested_clock_mode_index;
840 int default_power_state_index;
841 u32 current_sclk;
842 u32 current_mclk;
843 u16 current_vddc;
844 u16 current_vddci;
845 u32 default_sclk;
846 u32 default_mclk;
847 u16 default_vddc;
848 u16 default_vddci;
849 struct radeon_i2c_chan *i2c_bus;
850 /* selected pm method */
851 enum radeon_pm_method pm_method;
852 /* dynpm power management */
853 struct delayed_work dynpm_idle_work;
854 enum radeon_dynpm_state dynpm_state;
855 enum radeon_dynpm_action dynpm_planned_action;
856 unsigned long dynpm_action_timeout;
857 bool dynpm_can_upclock;
858 bool dynpm_can_downclock;
859 /* profile-based power management */
860 enum radeon_pm_profile_type profile;
861 int profile_index;
862 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
863 /* internal thermal controller on rv6xx+ */
864 enum radeon_int_thermal_type int_thermal_type;
865 struct device *int_hwmon_dev;
866};
867
868
869/*
870 * Benchmarking
871 */
872void radeon_benchmark(struct radeon_device *rdev);
873
874
875/*
876 * Testing
877 */
878void radeon_test_moves(struct radeon_device *rdev);
879
880
881/*
882 * Debugfs
883 */
884int radeon_debugfs_add_files(struct radeon_device *rdev,
885 struct drm_info_list *files,
886 unsigned nfiles);
887int radeon_debugfs_fence_init(struct radeon_device *rdev);
888
889
890/*
891 * ASIC specific functions.
892 */
893struct radeon_asic {
894 int (*init)(struct radeon_device *rdev);
895 void (*fini)(struct radeon_device *rdev);
896 int (*resume)(struct radeon_device *rdev);
897 int (*suspend)(struct radeon_device *rdev);
898 void (*vga_set_state)(struct radeon_device *rdev, bool state);
899 bool (*gpu_is_lockup)(struct radeon_device *rdev);
900 int (*asic_reset)(struct radeon_device *rdev);
901 void (*gart_tlb_flush)(struct radeon_device *rdev);
902 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
903 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
904 void (*cp_fini)(struct radeon_device *rdev);
905 void (*cp_disable)(struct radeon_device *rdev);
906 void (*cp_commit)(struct radeon_device *rdev);
907 void (*ring_start)(struct radeon_device *rdev);
908 int (*ring_test)(struct radeon_device *rdev);
909 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
910 int (*irq_set)(struct radeon_device *rdev);
911 int (*irq_process)(struct radeon_device *rdev);
912 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
913 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
914 int (*cs_parse)(struct radeon_cs_parser *p);
915 int (*copy_blit)(struct radeon_device *rdev,
916 uint64_t src_offset,
917 uint64_t dst_offset,
918 unsigned num_gpu_pages,
919 struct radeon_fence *fence);
920 int (*copy_dma)(struct radeon_device *rdev,
921 uint64_t src_offset,
922 uint64_t dst_offset,
923 unsigned num_gpu_pages,
924 struct radeon_fence *fence);
925 int (*copy)(struct radeon_device *rdev,
926 uint64_t src_offset,
927 uint64_t dst_offset,
928 unsigned num_gpu_pages,
929 struct radeon_fence *fence);
930 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
931 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
932 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
933 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
934 int (*get_pcie_lanes)(struct radeon_device *rdev);
935 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
936 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
937 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
938 uint32_t tiling_flags, uint32_t pitch,
939 uint32_t offset, uint32_t obj_size);
940 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
941 void (*bandwidth_update)(struct radeon_device *rdev);
942 void (*hpd_init)(struct radeon_device *rdev);
943 void (*hpd_fini)(struct radeon_device *rdev);
944 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
945 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
946 /* ioctl hw specific callback. Some hw might want to perform special
947 * operation on specific ioctl. For instance on wait idle some hw
948 * might want to perform and HDP flush through MMIO as it seems that
949 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
950 * through ring.
951 */
952 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
953 bool (*gui_idle)(struct radeon_device *rdev);
954 /* power management */
955 void (*pm_misc)(struct radeon_device *rdev);
956 void (*pm_prepare)(struct radeon_device *rdev);
957 void (*pm_finish)(struct radeon_device *rdev);
958 void (*pm_init_profile)(struct radeon_device *rdev);
959 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
960 /* pageflipping */
961 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
962 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
963 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
964};
965
966/*
967 * Asic structures
968 */
969struct r100_gpu_lockup {
970 unsigned long last_jiffies;
971 u32 last_cp_rptr;
972};
973
974struct r100_asic {
975 const unsigned *reg_safe_bm;
976 unsigned reg_safe_bm_size;
977 u32 hdp_cntl;
978 struct r100_gpu_lockup lockup;
979};
980
981struct r300_asic {
982 const unsigned *reg_safe_bm;
983 unsigned reg_safe_bm_size;
984 u32 resync_scratch;
985 u32 hdp_cntl;
986 struct r100_gpu_lockup lockup;
987};
988
989struct r600_asic {
990 unsigned max_pipes;
991 unsigned max_tile_pipes;
992 unsigned max_simds;
993 unsigned max_backends;
994 unsigned max_gprs;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned tiling_nbanks;
1004 unsigned tiling_npipes;
1005 unsigned tiling_group_size;
1006 unsigned tile_config;
1007 unsigned backend_map;
1008 struct r100_gpu_lockup lockup;
1009};
1010
1011struct rv770_asic {
1012 unsigned max_pipes;
1013 unsigned max_tile_pipes;
1014 unsigned max_simds;
1015 unsigned max_backends;
1016 unsigned max_gprs;
1017 unsigned max_threads;
1018 unsigned max_stack_entries;
1019 unsigned max_hw_contexts;
1020 unsigned max_gs_threads;
1021 unsigned sx_max_export_size;
1022 unsigned sx_max_export_pos_size;
1023 unsigned sx_max_export_smx_size;
1024 unsigned sq_num_cf_insts;
1025 unsigned sx_num_of_sets;
1026 unsigned sc_prim_fifo_size;
1027 unsigned sc_hiz_tile_fifo_size;
1028 unsigned sc_earlyz_tile_fifo_fize;
1029 unsigned tiling_nbanks;
1030 unsigned tiling_npipes;
1031 unsigned tiling_group_size;
1032 unsigned tile_config;
1033 unsigned backend_map;
1034 struct r100_gpu_lockup lockup;
1035};
1036
1037struct evergreen_asic {
1038 unsigned num_ses;
1039 unsigned max_pipes;
1040 unsigned max_tile_pipes;
1041 unsigned max_simds;
1042 unsigned max_backends;
1043 unsigned max_gprs;
1044 unsigned max_threads;
1045 unsigned max_stack_entries;
1046 unsigned max_hw_contexts;
1047 unsigned max_gs_threads;
1048 unsigned sx_max_export_size;
1049 unsigned sx_max_export_pos_size;
1050 unsigned sx_max_export_smx_size;
1051 unsigned sq_num_cf_insts;
1052 unsigned sx_num_of_sets;
1053 unsigned sc_prim_fifo_size;
1054 unsigned sc_hiz_tile_fifo_size;
1055 unsigned sc_earlyz_tile_fifo_size;
1056 unsigned tiling_nbanks;
1057 unsigned tiling_npipes;
1058 unsigned tiling_group_size;
1059 unsigned tile_config;
1060 unsigned backend_map;
1061 struct r100_gpu_lockup lockup;
1062};
1063
1064struct cayman_asic {
1065 unsigned max_shader_engines;
1066 unsigned max_pipes_per_simd;
1067 unsigned max_tile_pipes;
1068 unsigned max_simds_per_se;
1069 unsigned max_backends_per_se;
1070 unsigned max_texture_channel_caches;
1071 unsigned max_gprs;
1072 unsigned max_threads;
1073 unsigned max_gs_threads;
1074 unsigned max_stack_entries;
1075 unsigned sx_num_of_sets;
1076 unsigned sx_max_export_size;
1077 unsigned sx_max_export_pos_size;
1078 unsigned sx_max_export_smx_size;
1079 unsigned max_hw_contexts;
1080 unsigned sq_num_cf_insts;
1081 unsigned sc_prim_fifo_size;
1082 unsigned sc_hiz_tile_fifo_size;
1083 unsigned sc_earlyz_tile_fifo_size;
1084
1085 unsigned num_shader_engines;
1086 unsigned num_shader_pipes_per_simd;
1087 unsigned num_tile_pipes;
1088 unsigned num_simds_per_se;
1089 unsigned num_backends_per_se;
1090 unsigned backend_disable_mask_per_asic;
1091 unsigned backend_map;
1092 unsigned num_texture_channel_caches;
1093 unsigned mem_max_burst_length_bytes;
1094 unsigned mem_row_size_in_kb;
1095 unsigned shader_engine_tile_size;
1096 unsigned num_gpus;
1097 unsigned multi_gpu_tile_size;
1098
1099 unsigned tile_config;
1100 struct r100_gpu_lockup lockup;
1101};
1102
1103union radeon_asic_config {
1104 struct r300_asic r300;
1105 struct r100_asic r100;
1106 struct r600_asic r600;
1107 struct rv770_asic rv770;
1108 struct evergreen_asic evergreen;
1109 struct cayman_asic cayman;
1110};
1111
1112/*
1113 * asic initizalization from radeon_asic.c
1114 */
1115void radeon_agp_disable(struct radeon_device *rdev);
1116int radeon_asic_init(struct radeon_device *rdev);
1117
1118
1119/*
1120 * IOCTL.
1121 */
1122int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *filp);
1124int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *filp);
1126int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
1138int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1139 struct drm_file *filp);
1140int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1141 struct drm_file *filp);
1142int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1143int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *filp);
1145int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1146 struct drm_file *filp);
1147
1148/* VRAM scratch page for HDP bug */
1149struct r700_vram_scratch {
1150 struct radeon_bo *robj;
1151 volatile uint32_t *ptr;
1152};
1153
1154/*
1155 * Core structure, functions and helpers.
1156 */
1157typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1158typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1159
1160struct radeon_device {
1161 struct device *dev;
1162 struct drm_device *ddev;
1163 struct pci_dev *pdev;
1164 /* ASIC */
1165 union radeon_asic_config config;
1166 enum radeon_family family;
1167 unsigned long flags;
1168 int usec_timeout;
1169 enum radeon_pll_errata pll_errata;
1170 int num_gb_pipes;
1171 int num_z_pipes;
1172 int disp_priority;
1173 /* BIOS */
1174 uint8_t *bios;
1175 bool is_atom_bios;
1176 uint16_t bios_header_start;
1177 struct radeon_bo *stollen_vga_memory;
1178 /* Register mmio */
1179 resource_size_t rmmio_base;
1180 resource_size_t rmmio_size;
1181 void __iomem *rmmio;
1182 radeon_rreg_t mc_rreg;
1183 radeon_wreg_t mc_wreg;
1184 radeon_rreg_t pll_rreg;
1185 radeon_wreg_t pll_wreg;
1186 uint32_t pcie_reg_mask;
1187 radeon_rreg_t pciep_rreg;
1188 radeon_wreg_t pciep_wreg;
1189 /* io port */
1190 void __iomem *rio_mem;
1191 resource_size_t rio_mem_size;
1192 struct radeon_clock clock;
1193 struct radeon_mc mc;
1194 struct radeon_gart gart;
1195 struct radeon_mode_info mode_info;
1196 struct radeon_scratch scratch;
1197 struct radeon_mman mman;
1198 struct radeon_fence_driver fence_drv;
1199 struct radeon_cp cp;
1200 /* cayman compute rings */
1201 struct radeon_cp cp1;
1202 struct radeon_cp cp2;
1203 struct radeon_ib_pool ib_pool;
1204 struct radeon_irq irq;
1205 struct radeon_asic *asic;
1206 struct radeon_gem gem;
1207 struct radeon_pm pm;
1208 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1209 struct mutex cs_mutex;
1210 struct radeon_wb wb;
1211 struct radeon_dummy_page dummy_page;
1212 bool gpu_lockup;
1213 bool shutdown;
1214 bool suspend;
1215 bool need_dma32;
1216 bool accel_working;
1217 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1218 const struct firmware *me_fw; /* all family ME firmware */
1219 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1220 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1221 const struct firmware *mc_fw; /* NI MC firmware */
1222 struct r600_blit r600_blit;
1223 struct r700_vram_scratch vram_scratch;
1224 int msi_enabled; /* msi enabled */
1225 struct r600_ih ih; /* r6/700 interrupt ring */
1226 struct work_struct hotplug_work;
1227 int num_crtc; /* number of crtcs */
1228 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1229 struct mutex vram_mutex;
1230
1231 /* audio stuff */
1232 bool audio_enabled;
1233 struct timer_list audio_timer;
1234 int audio_channels;
1235 int audio_rate;
1236 int audio_bits_per_sample;
1237 uint8_t audio_status_bits;
1238 uint8_t audio_category_code;
1239
1240 struct notifier_block acpi_nb;
1241 /* only one userspace can use Hyperz features or CMASK at a time */
1242 struct drm_file *hyperz_filp;
1243 struct drm_file *cmask_filp;
1244 /* i2c buses */
1245 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1246};
1247
1248int radeon_device_init(struct radeon_device *rdev,
1249 struct drm_device *ddev,
1250 struct pci_dev *pdev,
1251 uint32_t flags);
1252void radeon_device_fini(struct radeon_device *rdev);
1253int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254
1255static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1256{
1257 if (reg < rdev->rmmio_size)
1258 return readl((rdev->rmmio) + reg);
1259 else {
1260 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261 return readl((rdev->rmmio) + RADEON_MM_DATA);
1262 }
1263}
1264
1265static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266{
1267 if (reg < rdev->rmmio_size)
1268 writel(v, (rdev->rmmio) + reg);
1269 else {
1270 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1272 }
1273}
1274
1275static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276{
1277 if (reg < rdev->rio_mem_size)
1278 return ioread32(rdev->rio_mem + reg);
1279 else {
1280 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282 }
1283}
1284
1285static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286{
1287 if (reg < rdev->rio_mem_size)
1288 iowrite32(v, rdev->rio_mem + reg);
1289 else {
1290 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292 }
1293}
1294
1295/*
1296 * Cast helper
1297 */
1298#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1299
1300/*
1301 * Registers read & write functions.
1302 */
1303#define RREG8(reg) readb((rdev->rmmio) + (reg))
1304#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305#define RREG16(reg) readw((rdev->rmmio) + (reg))
1306#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1307#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1308#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1309#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1310#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1316#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1318#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1320#define WREG32_P(reg, val, mask) \
1321 do { \
1322 uint32_t tmp_ = RREG32(reg); \
1323 tmp_ &= (mask); \
1324 tmp_ |= ((val) & ~(mask)); \
1325 WREG32(reg, tmp_); \
1326 } while (0)
1327#define WREG32_PLL_P(reg, val, mask) \
1328 do { \
1329 uint32_t tmp_ = RREG32_PLL(reg); \
1330 tmp_ &= (mask); \
1331 tmp_ |= ((val) & ~(mask)); \
1332 WREG32_PLL(reg, tmp_); \
1333 } while (0)
1334#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1335#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1337
1338/*
1339 * Indirect registers accessor
1340 */
1341static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342{
1343 uint32_t r;
1344
1345 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346 r = RREG32(RADEON_PCIE_DATA);
1347 return r;
1348}
1349
1350static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351{
1352 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353 WREG32(RADEON_PCIE_DATA, (v));
1354}
1355
1356void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359/*
1360 * ASICs helpers.
1361 */
1362#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363 (rdev->pdev->device == 0x5969))
1364#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365 (rdev->family == CHIP_RV200) || \
1366 (rdev->family == CHIP_RS100) || \
1367 (rdev->family == CHIP_RS200) || \
1368 (rdev->family == CHIP_RV250) || \
1369 (rdev->family == CHIP_RV280) || \
1370 (rdev->family == CHIP_RS300))
1371#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1372 (rdev->family == CHIP_RV350) || \
1373 (rdev->family == CHIP_R350) || \
1374 (rdev->family == CHIP_RV380) || \
1375 (rdev->family == CHIP_R420) || \
1376 (rdev->family == CHIP_R423) || \
1377 (rdev->family == CHIP_RV410) || \
1378 (rdev->family == CHIP_RS400) || \
1379 (rdev->family == CHIP_RS480))
1380#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381 (rdev->ddev->pdev->device == 0x9443) || \
1382 (rdev->ddev->pdev->device == 0x944B) || \
1383 (rdev->ddev->pdev->device == 0x9506) || \
1384 (rdev->ddev->pdev->device == 0x9509) || \
1385 (rdev->ddev->pdev->device == 0x950F) || \
1386 (rdev->ddev->pdev->device == 0x689C) || \
1387 (rdev->ddev->pdev->device == 0x689D))
1388#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1389#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1390 (rdev->family == CHIP_RS690) || \
1391 (rdev->family == CHIP_RS740) || \
1392 (rdev->family >= CHIP_R600))
1393#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1395#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1396#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397 (rdev->flags & RADEON_IS_IGP))
1398#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1399
1400/*
1401 * BIOS helpers.
1402 */
1403#define RBIOS8(i) (rdev->bios[i])
1404#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407int radeon_combios_init(struct radeon_device *rdev);
1408void radeon_combios_fini(struct radeon_device *rdev);
1409int radeon_atombios_init(struct radeon_device *rdev);
1410void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413/*
1414 * RING helpers.
1415 */
1416static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417{
1418#if DRM_DEBUG_CODE
1419 if (rdev->cp.count_dw <= 0) {
1420 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 }
1422#endif
1423 rdev->cp.ring[rdev->cp.wptr++] = v;
1424 rdev->cp.wptr &= rdev->cp.ptr_mask;
1425 rdev->cp.count_dw--;
1426 rdev->cp.ring_free_dw--;
1427}
1428
1429
1430/*
1431 * ASICs macro.
1432 */
1433#define radeon_init(rdev) (rdev)->asic->init((rdev))
1434#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1437#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1438#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1439#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1440#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1441#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1443#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1444#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1445#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1447#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1449#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1450#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1454#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1455#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1456#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1457#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1458#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1459#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1461#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1463#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1464#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1468#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1469#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1472#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1474#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1477
1478/* Common functions */
1479/* AGP */
1480extern int radeon_gpu_reset(struct radeon_device *rdev);
1481extern void radeon_agp_disable(struct radeon_device *rdev);
1482extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1483extern void radeon_gart_restore(struct radeon_device *rdev);
1484extern int radeon_modeset_init(struct radeon_device *rdev);
1485extern void radeon_modeset_fini(struct radeon_device *rdev);
1486extern bool radeon_card_posted(struct radeon_device *rdev);
1487extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1488extern void radeon_update_display_priority(struct radeon_device *rdev);
1489extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1490extern void radeon_scratch_init(struct radeon_device *rdev);
1491extern void radeon_wb_fini(struct radeon_device *rdev);
1492extern int radeon_wb_init(struct radeon_device *rdev);
1493extern void radeon_wb_disable(struct radeon_device *rdev);
1494extern void radeon_surface_init(struct radeon_device *rdev);
1495extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1496extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1497extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1498extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1499extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1500extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1501extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1502extern int radeon_resume_kms(struct drm_device *dev);
1503extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1504extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1505
1506/*
1507 * r600 functions used by radeon_encoder.c
1508 */
1509extern void r600_hdmi_enable(struct drm_encoder *encoder);
1510extern void r600_hdmi_disable(struct drm_encoder *encoder);
1511extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1512
1513extern int ni_init_microcode(struct radeon_device *rdev);
1514extern int ni_mc_load_microcode(struct radeon_device *rdev);
1515
1516/* radeon_acpi.c */
1517#if defined(CONFIG_ACPI)
1518extern int radeon_acpi_init(struct radeon_device *rdev);
1519#else
1520static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521#endif
1522
1523#include "radeon_object.h"
1524
1525#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/agp_backend.h>
64#include <linux/atomic.h>
65#include <linux/wait.h>
66#include <linux/list.h>
67#include <linux/kref.h>
68#include <linux/interval_tree.h>
69#include <linux/hashtable.h>
70#include <linux/dma-fence.h>
71
72#ifdef CONFIG_MMU_NOTIFIER
73#include <linux/mmu_notifier.h>
74#endif
75
76#include <drm/ttm/ttm_bo.h>
77#include <drm/ttm/ttm_placement.h>
78#include <drm/ttm/ttm_execbuf_util.h>
79
80#include <drm/drm_gem.h>
81#include <drm/drm_audio_component.h>
82#include <drm/drm_suballoc.h>
83
84#include "radeon_family.h"
85#include "radeon_mode.h"
86#include "radeon_reg.h"
87
88/*
89 * Modules parameters.
90 */
91extern int radeon_no_wb;
92extern int radeon_modeset;
93extern int radeon_dynclks;
94extern int radeon_r4xx_atom;
95extern int radeon_agpmode;
96extern int radeon_vram_limit;
97extern int radeon_gart_size;
98extern int radeon_benchmarking;
99extern int radeon_testing;
100extern int radeon_connector_table;
101extern int radeon_tv;
102extern int radeon_audio;
103extern int radeon_disp_priority;
104extern int radeon_hw_i2c;
105extern int radeon_pcie_gen2;
106extern int radeon_msi;
107extern int radeon_lockup_timeout;
108extern int radeon_fastfb;
109extern int radeon_dpm;
110extern int radeon_aspm;
111extern int radeon_runtime_pm;
112extern int radeon_hard_reset;
113extern int radeon_vm_size;
114extern int radeon_vm_block_size;
115extern int radeon_deep_color;
116extern int radeon_use_pflipirq;
117extern int radeon_bapm;
118extern int radeon_backlight;
119extern int radeon_auxch;
120extern int radeon_uvd;
121extern int radeon_vce;
122extern int radeon_si_support;
123extern int radeon_cik_support;
124
125/*
126 * Copy from radeon_drv.h so we don't have to include both and have conflicting
127 * symbol;
128 */
129#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
130#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
131#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
132/* RADEON_IB_POOL_SIZE must be a power of 2 */
133#define RADEON_IB_POOL_SIZE 16
134#define RADEON_DEBUGFS_MAX_COMPONENTS 32
135#define RADEONFB_CONN_LIMIT 4
136#define RADEON_BIOS_NUM_SCRATCH 8
137
138/* internal ring indices */
139/* r1xx+ has gfx CP ring */
140#define RADEON_RING_TYPE_GFX_INDEX 0
141
142/* cayman has 2 compute CP rings */
143#define CAYMAN_RING_TYPE_CP1_INDEX 1
144#define CAYMAN_RING_TYPE_CP2_INDEX 2
145
146/* R600+ has an async dma ring */
147#define R600_RING_TYPE_DMA_INDEX 3
148/* cayman add a second async dma ring */
149#define CAYMAN_RING_TYPE_DMA1_INDEX 4
150
151/* R600+ */
152#define R600_RING_TYPE_UVD_INDEX 5
153
154/* TN+ */
155#define TN_RING_TYPE_VCE1_INDEX 6
156#define TN_RING_TYPE_VCE2_INDEX 7
157
158/* max number of rings */
159#define RADEON_NUM_RINGS 8
160
161/* number of hw syncs before falling back on blocking */
162#define RADEON_NUM_SYNCS 4
163
164/* hardcode those limit for now */
165#define RADEON_VA_IB_OFFSET (1 << 20)
166#define RADEON_VA_RESERVED_SIZE (8 << 20)
167#define RADEON_IB_VM_MAX_SIZE (64 << 10)
168
169/* hard reset data */
170#define RADEON_ASIC_RESET_DATA 0x39d5e86b
171
172/* reset flags */
173#define RADEON_RESET_GFX (1 << 0)
174#define RADEON_RESET_COMPUTE (1 << 1)
175#define RADEON_RESET_DMA (1 << 2)
176#define RADEON_RESET_CP (1 << 3)
177#define RADEON_RESET_GRBM (1 << 4)
178#define RADEON_RESET_DMA1 (1 << 5)
179#define RADEON_RESET_RLC (1 << 6)
180#define RADEON_RESET_SEM (1 << 7)
181#define RADEON_RESET_IH (1 << 8)
182#define RADEON_RESET_VMC (1 << 9)
183#define RADEON_RESET_MC (1 << 10)
184#define RADEON_RESET_DISPLAY (1 << 11)
185
186/* CG block flags */
187#define RADEON_CG_BLOCK_GFX (1 << 0)
188#define RADEON_CG_BLOCK_MC (1 << 1)
189#define RADEON_CG_BLOCK_SDMA (1 << 2)
190#define RADEON_CG_BLOCK_UVD (1 << 3)
191#define RADEON_CG_BLOCK_VCE (1 << 4)
192#define RADEON_CG_BLOCK_HDP (1 << 5)
193#define RADEON_CG_BLOCK_BIF (1 << 6)
194
195/* CG flags */
196#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
197#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
198#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
199#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
200#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
201#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
202#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
203#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
204#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
205#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
206#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
207#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
208#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
209#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
210#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
211#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
212#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
213
214/* PG flags */
215#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
216#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
217#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
218#define RADEON_PG_SUPPORT_UVD (1 << 3)
219#define RADEON_PG_SUPPORT_VCE (1 << 4)
220#define RADEON_PG_SUPPORT_CP (1 << 5)
221#define RADEON_PG_SUPPORT_GDS (1 << 6)
222#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
223#define RADEON_PG_SUPPORT_SDMA (1 << 8)
224#define RADEON_PG_SUPPORT_ACP (1 << 9)
225#define RADEON_PG_SUPPORT_SAMU (1 << 10)
226
227/* max cursor sizes (in pixels) */
228#define CURSOR_WIDTH 64
229#define CURSOR_HEIGHT 64
230
231#define CIK_CURSOR_WIDTH 128
232#define CIK_CURSOR_HEIGHT 128
233
234/*
235 * Errata workarounds.
236 */
237enum radeon_pll_errata {
238 CHIP_ERRATA_R300_CG = 0x00000001,
239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
240 CHIP_ERRATA_PLL_DELAY = 0x00000004
241};
242
243
244struct radeon_device;
245
246
247/*
248 * BIOS.
249 */
250bool radeon_get_bios(struct radeon_device *rdev);
251
252/*
253 * Dummy page
254 */
255struct radeon_dummy_page {
256 uint64_t entry;
257 struct page *page;
258 dma_addr_t addr;
259};
260int radeon_dummy_page_init(struct radeon_device *rdev);
261void radeon_dummy_page_fini(struct radeon_device *rdev);
262
263
264/*
265 * Clocks
266 */
267struct radeon_clock {
268 struct radeon_pll p1pll;
269 struct radeon_pll p2pll;
270 struct radeon_pll dcpll;
271 struct radeon_pll spll;
272 struct radeon_pll mpll;
273 /* 10 Khz units */
274 uint32_t default_mclk;
275 uint32_t default_sclk;
276 uint32_t default_dispclk;
277 uint32_t current_dispclk;
278 uint32_t dp_extclk;
279 uint32_t max_pixel_clock;
280 uint32_t vco_freq;
281};
282
283/*
284 * Power management
285 */
286int radeon_pm_init(struct radeon_device *rdev);
287int radeon_pm_late_init(struct radeon_device *rdev);
288void radeon_pm_fini(struct radeon_device *rdev);
289void radeon_pm_compute_clocks(struct radeon_device *rdev);
290void radeon_pm_suspend(struct radeon_device *rdev);
291void radeon_pm_resume(struct radeon_device *rdev);
292void radeon_combios_get_power_modes(struct radeon_device *rdev);
293void radeon_atombios_get_power_modes(struct radeon_device *rdev);
294int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
295 u8 clock_type,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_clock_dividers *dividers);
299int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
300 u32 clock,
301 bool strobe_mode,
302 struct atom_mpll_param *mpll_param);
303void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
304int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
305 u16 voltage_level, u8 voltage_type,
306 u32 *gpio_value, u32 *gpio_mask);
307void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
308 u32 eng_clock, u32 mem_clock);
309int radeon_atom_get_voltage_step(struct radeon_device *rdev,
310 u8 voltage_type, u16 *voltage_step);
311int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
312 u16 voltage_id, u16 *voltage);
313int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
314 u16 *voltage,
315 u16 leakage_idx);
316int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
317 u16 *leakage_id);
318int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
319 u16 *vddc, u16 *vddci,
320 u16 virtual_voltage_id,
321 u16 vbios_voltage_id);
322int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
323 u16 virtual_voltage_id,
324 u16 *voltage);
325int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
326 u8 voltage_type,
327 u16 nominal_voltage,
328 u16 *true_voltage);
329int radeon_atom_get_min_voltage(struct radeon_device *rdev,
330 u8 voltage_type, u16 *min_voltage);
331int radeon_atom_get_max_voltage(struct radeon_device *rdev,
332 u8 voltage_type, u16 *max_voltage);
333int radeon_atom_get_voltage_table(struct radeon_device *rdev,
334 u8 voltage_type, u8 voltage_mode,
335 struct atom_voltage_table *voltage_table);
336bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
337 u8 voltage_type, u8 voltage_mode);
338int radeon_atom_get_svi2_info(struct radeon_device *rdev,
339 u8 voltage_type,
340 u8 *svd_gpio_id, u8 *svc_gpio_id);
341void radeon_atom_update_memory_dll(struct radeon_device *rdev,
342 u32 mem_clock);
343void radeon_atom_set_ac_timing(struct radeon_device *rdev,
344 u32 mem_clock);
345int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
346 u8 module_index,
347 struct atom_mc_reg_table *reg_table);
348int radeon_atom_get_memory_info(struct radeon_device *rdev,
349 u8 module_index, struct atom_memory_info *mem_info);
350int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
351 bool gddr5, u8 module_index,
352 struct atom_memory_clock_range_table *mclk_range_table);
353int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
354 u16 voltage_id, u16 *voltage);
355void rs690_pm_info(struct radeon_device *rdev);
356extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
357 unsigned *bankh, unsigned *mtaspect,
358 unsigned *tile_split);
359
360/*
361 * Fences.
362 */
363struct radeon_fence_driver {
364 struct radeon_device *rdev;
365 uint32_t scratch_reg;
366 uint64_t gpu_addr;
367 volatile uint32_t *cpu_addr;
368 /* sync_seq is protected by ring emission lock */
369 uint64_t sync_seq[RADEON_NUM_RINGS];
370 atomic64_t last_seq;
371 bool initialized, delayed_irq;
372 struct delayed_work lockup_work;
373};
374
375struct radeon_fence {
376 struct dma_fence base;
377
378 struct radeon_device *rdev;
379 uint64_t seq;
380 /* RB, DMA, etc. */
381 unsigned ring;
382 bool is_vm_update;
383
384 wait_queue_entry_t fence_wake;
385};
386
387int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
388void radeon_fence_driver_init(struct radeon_device *rdev);
389void radeon_fence_driver_fini(struct radeon_device *rdev);
390void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
391int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
392void radeon_fence_process(struct radeon_device *rdev, int ring);
393bool radeon_fence_signaled(struct radeon_fence *fence);
394long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
395int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
396int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
397int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
398int radeon_fence_wait_any(struct radeon_device *rdev,
399 struct radeon_fence **fences,
400 bool intr);
401struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
402void radeon_fence_unref(struct radeon_fence **fence);
403unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
404bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
405void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
406static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
407 struct radeon_fence *b)
408{
409 if (!a) {
410 return b;
411 }
412
413 if (!b) {
414 return a;
415 }
416
417 BUG_ON(a->ring != b->ring);
418
419 if (a->seq > b->seq) {
420 return a;
421 } else {
422 return b;
423 }
424}
425
426static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
427 struct radeon_fence *b)
428{
429 if (!a) {
430 return false;
431 }
432
433 if (!b) {
434 return true;
435 }
436
437 BUG_ON(a->ring != b->ring);
438
439 return a->seq < b->seq;
440}
441
442/*
443 * Tiling registers
444 */
445struct radeon_surface_reg {
446 struct radeon_bo *bo;
447};
448
449#define RADEON_GEM_MAX_SURFACES 8
450
451/*
452 * TTM.
453 */
454struct radeon_mman {
455 struct ttm_device bdev;
456 bool initialized;
457};
458
459struct radeon_bo_list {
460 struct radeon_bo *robj;
461 struct ttm_validate_buffer tv;
462 uint64_t gpu_offset;
463 unsigned preferred_domains;
464 unsigned allowed_domains;
465 uint32_t tiling_flags;
466};
467
468/* bo virtual address in a specific vm */
469struct radeon_bo_va {
470 /* protected by bo being reserved */
471 struct list_head bo_list;
472 uint32_t flags;
473 struct radeon_fence *last_pt_update;
474 unsigned ref_count;
475
476 /* protected by vm mutex */
477 struct interval_tree_node it;
478 struct list_head vm_status;
479
480 /* constant after initialization */
481 struct radeon_vm *vm;
482 struct radeon_bo *bo;
483};
484
485struct radeon_bo {
486 /* Protected by gem.mutex */
487 struct list_head list;
488 /* Protected by tbo.reserved */
489 u32 initial_domain;
490 struct ttm_place placements[4];
491 struct ttm_placement placement;
492 struct ttm_buffer_object tbo;
493 struct ttm_bo_kmap_obj kmap;
494 u32 flags;
495 void *kptr;
496 u32 tiling_flags;
497 u32 pitch;
498 int surface_reg;
499 unsigned prime_shared_count;
500 /* list of all virtual address to which this bo
501 * is associated to
502 */
503 struct list_head va;
504 /* Constant after initialization */
505 struct radeon_device *rdev;
506
507 pid_t pid;
508
509#ifdef CONFIG_MMU_NOTIFIER
510 struct mmu_interval_notifier notifier;
511#endif
512};
513#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
514
515struct radeon_sa_manager {
516 struct drm_suballoc_manager base;
517 struct radeon_bo *bo;
518 uint64_t gpu_addr;
519 void *cpu_ptr;
520 u32 domain;
521};
522
523/*
524 * GEM objects.
525 */
526struct radeon_gem {
527 struct mutex mutex;
528 struct list_head objects;
529};
530
531extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
532
533int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled);
534
535int radeon_gem_init(struct radeon_device *rdev);
536void radeon_gem_fini(struct radeon_device *rdev);
537int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
538 int alignment, int initial_domain,
539 u32 flags, bool kernel,
540 struct drm_gem_object **obj);
541
542int radeon_mode_dumb_create(struct drm_file *file_priv,
543 struct drm_device *dev,
544 struct drm_mode_create_dumb *args);
545int radeon_mode_dumb_mmap(struct drm_file *filp,
546 struct drm_device *dev,
547 uint32_t handle, uint64_t *offset_p);
548
549/*
550 * Semaphores.
551 */
552struct radeon_semaphore {
553 struct drm_suballoc *sa_bo;
554 signed waiters;
555 uint64_t gpu_addr;
556};
557
558int radeon_semaphore_create(struct radeon_device *rdev,
559 struct radeon_semaphore **semaphore);
560bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
561 struct radeon_semaphore *semaphore);
562bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
563 struct radeon_semaphore *semaphore);
564void radeon_semaphore_free(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore,
566 struct radeon_fence *fence);
567
568/*
569 * Synchronization
570 */
571struct radeon_sync {
572 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
573 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
574 struct radeon_fence *last_vm_update;
575};
576
577void radeon_sync_create(struct radeon_sync *sync);
578void radeon_sync_fence(struct radeon_sync *sync,
579 struct radeon_fence *fence);
580int radeon_sync_resv(struct radeon_device *rdev,
581 struct radeon_sync *sync,
582 struct dma_resv *resv,
583 bool shared);
584int radeon_sync_rings(struct radeon_device *rdev,
585 struct radeon_sync *sync,
586 int waiting_ring);
587void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
588 struct radeon_fence *fence);
589
590/*
591 * GART structures, functions & helpers
592 */
593struct radeon_mc;
594
595#define RADEON_GPU_PAGE_SIZE 4096
596#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
597#define RADEON_GPU_PAGE_SHIFT 12
598#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
599
600#define RADEON_GART_PAGE_DUMMY 0
601#define RADEON_GART_PAGE_VALID (1 << 0)
602#define RADEON_GART_PAGE_READ (1 << 1)
603#define RADEON_GART_PAGE_WRITE (1 << 2)
604#define RADEON_GART_PAGE_SNOOP (1 << 3)
605
606struct radeon_gart {
607 dma_addr_t table_addr;
608 struct radeon_bo *robj;
609 void *ptr;
610 unsigned num_gpu_pages;
611 unsigned num_cpu_pages;
612 unsigned table_size;
613 struct page **pages;
614 uint64_t *pages_entry;
615 bool ready;
616};
617
618int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
619void radeon_gart_table_ram_free(struct radeon_device *rdev);
620int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
621void radeon_gart_table_vram_free(struct radeon_device *rdev);
622int radeon_gart_table_vram_pin(struct radeon_device *rdev);
623void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
624int radeon_gart_init(struct radeon_device *rdev);
625void radeon_gart_fini(struct radeon_device *rdev);
626void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
627 int pages);
628int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
629 int pages, struct page **pagelist,
630 dma_addr_t *dma_addr, uint32_t flags);
631
632
633/*
634 * GPU MC structures, functions & helpers
635 */
636struct radeon_mc {
637 resource_size_t aper_size;
638 resource_size_t aper_base;
639 resource_size_t agp_base;
640 /* for some chips with <= 32MB we need to lie
641 * about vram size near mc fb location */
642 u64 mc_vram_size;
643 u64 visible_vram_size;
644 u64 gtt_size;
645 u64 gtt_start;
646 u64 gtt_end;
647 u64 vram_start;
648 u64 vram_end;
649 unsigned vram_width;
650 u64 real_vram_size;
651 int vram_mtrr;
652 bool vram_is_ddr;
653 bool igp_sideport_enabled;
654 u64 gtt_base_align;
655 u64 mc_mask;
656};
657
658bool radeon_combios_sideport_present(struct radeon_device *rdev);
659bool radeon_atombios_sideport_present(struct radeon_device *rdev);
660
661/*
662 * GPU scratch registers structures, functions & helpers
663 */
664struct radeon_scratch {
665 unsigned num_reg;
666 uint32_t reg_base;
667 bool free[32];
668 uint32_t reg[32];
669};
670
671int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
672void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
673
674/*
675 * GPU doorbell structures, functions & helpers
676 */
677#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
678
679struct radeon_doorbell {
680 /* doorbell mmio */
681 resource_size_t base;
682 resource_size_t size;
683 u32 __iomem *ptr;
684 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
685 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
686};
687
688int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
689void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
690
691/*
692 * IRQS.
693 */
694
695struct radeon_flip_work {
696 struct work_struct flip_work;
697 struct work_struct unpin_work;
698 struct radeon_device *rdev;
699 int crtc_id;
700 u32 target_vblank;
701 uint64_t base;
702 struct drm_pending_vblank_event *event;
703 struct radeon_bo *old_rbo;
704 struct dma_fence *fence;
705 bool async;
706};
707
708struct r500_irq_stat_regs {
709 u32 disp_int;
710 u32 hdmi0_status;
711};
712
713struct r600_irq_stat_regs {
714 u32 disp_int;
715 u32 disp_int_cont;
716 u32 disp_int_cont2;
717 u32 d1grph_int;
718 u32 d2grph_int;
719 u32 hdmi0_status;
720 u32 hdmi1_status;
721};
722
723struct evergreen_irq_stat_regs {
724 u32 disp_int[6];
725 u32 grph_int[6];
726 u32 afmt_status[6];
727};
728
729struct cik_irq_stat_regs {
730 u32 disp_int;
731 u32 disp_int_cont;
732 u32 disp_int_cont2;
733 u32 disp_int_cont3;
734 u32 disp_int_cont4;
735 u32 disp_int_cont5;
736 u32 disp_int_cont6;
737 u32 d1grph_int;
738 u32 d2grph_int;
739 u32 d3grph_int;
740 u32 d4grph_int;
741 u32 d5grph_int;
742 u32 d6grph_int;
743};
744
745union radeon_irq_stat_regs {
746 struct r500_irq_stat_regs r500;
747 struct r600_irq_stat_regs r600;
748 struct evergreen_irq_stat_regs evergreen;
749 struct cik_irq_stat_regs cik;
750};
751
752struct radeon_irq {
753 bool installed;
754 spinlock_t lock;
755 atomic_t ring_int[RADEON_NUM_RINGS];
756 bool crtc_vblank_int[RADEON_MAX_CRTCS];
757 atomic_t pflip[RADEON_MAX_CRTCS];
758 wait_queue_head_t vblank_queue;
759 bool hpd[RADEON_MAX_HPD_PINS];
760 bool afmt[RADEON_MAX_AFMT_BLOCKS];
761 union radeon_irq_stat_regs stat_regs;
762 bool dpm_thermal;
763};
764
765int radeon_irq_kms_init(struct radeon_device *rdev);
766void radeon_irq_kms_fini(struct radeon_device *rdev);
767void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
768bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
770void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
772void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
776
777/*
778 * CP & rings.
779 */
780
781struct radeon_ib {
782 struct drm_suballoc *sa_bo;
783 uint32_t length_dw;
784 uint64_t gpu_addr;
785 uint32_t *ptr;
786 int ring;
787 struct radeon_fence *fence;
788 struct radeon_vm *vm;
789 bool is_const_ib;
790 struct radeon_sync sync;
791};
792
793struct radeon_ring {
794 struct radeon_device *rdev;
795 struct radeon_bo *ring_obj;
796 volatile uint32_t *ring;
797 unsigned rptr_offs;
798 unsigned rptr_save_reg;
799 u64 next_rptr_gpu_addr;
800 volatile u32 *next_rptr_cpu_addr;
801 unsigned wptr;
802 unsigned wptr_old;
803 unsigned ring_size;
804 unsigned ring_free_dw;
805 int count_dw;
806 atomic_t last_rptr;
807 atomic64_t last_activity;
808 uint64_t gpu_addr;
809 uint32_t align_mask;
810 uint32_t ptr_mask;
811 bool ready;
812 u32 nop;
813 u32 idx;
814 u64 last_semaphore_signal_addr;
815 u64 last_semaphore_wait_addr;
816 /* for CIK queues */
817 u32 me;
818 u32 pipe;
819 u32 queue;
820 struct radeon_bo *mqd_obj;
821 u32 doorbell_index;
822 unsigned wptr_offs;
823};
824
825struct radeon_mec {
826 struct radeon_bo *hpd_eop_obj;
827 u64 hpd_eop_gpu_addr;
828 u32 num_pipe;
829 u32 num_mec;
830 u32 num_queue;
831};
832
833/*
834 * VM
835 */
836
837/* maximum number of VMIDs */
838#define RADEON_NUM_VM 16
839
840/* number of entries in page table */
841#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
842
843/* PTBs (Page Table Blocks) need to be aligned to 32K */
844#define RADEON_VM_PTB_ALIGN_SIZE 32768
845#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
846#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
847
848#define R600_PTE_VALID (1 << 0)
849#define R600_PTE_SYSTEM (1 << 1)
850#define R600_PTE_SNOOPED (1 << 2)
851#define R600_PTE_READABLE (1 << 5)
852#define R600_PTE_WRITEABLE (1 << 6)
853
854/* PTE (Page Table Entry) fragment field for different page sizes */
855#define R600_PTE_FRAG_4KB (0 << 7)
856#define R600_PTE_FRAG_64KB (4 << 7)
857#define R600_PTE_FRAG_256KB (6 << 7)
858
859/* flags needed to be set so we can copy directly from the GART table */
860#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
861 R600_PTE_SYSTEM | R600_PTE_VALID )
862
863struct radeon_vm_pt {
864 struct radeon_bo *bo;
865 uint64_t addr;
866};
867
868struct radeon_vm_id {
869 unsigned id;
870 uint64_t pd_gpu_addr;
871 /* last flushed PD/PT update */
872 struct radeon_fence *flushed_updates;
873 /* last use of vmid */
874 struct radeon_fence *last_id_use;
875};
876
877struct radeon_vm {
878 struct mutex mutex;
879
880 struct rb_root_cached va;
881
882 /* protecting invalidated and freed */
883 spinlock_t status_lock;
884
885 /* BOs moved, but not yet updated in the PT */
886 struct list_head invalidated;
887
888 /* BOs freed, but not yet updated in the PT */
889 struct list_head freed;
890
891 /* BOs cleared in the PT */
892 struct list_head cleared;
893
894 /* contains the page directory */
895 struct radeon_bo *page_directory;
896 unsigned max_pde_used;
897
898 /* array of page tables, one for each page directory entry */
899 struct radeon_vm_pt *page_tables;
900
901 struct radeon_bo_va *ib_bo_va;
902
903 /* for id and flush management per ring */
904 struct radeon_vm_id ids[RADEON_NUM_RINGS];
905};
906
907struct radeon_vm_manager {
908 struct radeon_fence *active[RADEON_NUM_VM];
909 uint32_t max_pfn;
910 /* number of VMIDs */
911 unsigned nvm;
912 /* vram base address for page table entry */
913 u64 vram_base_offset;
914 /* is vm enabled? */
915 bool enabled;
916 /* for hw to save the PD addr on suspend/resume */
917 uint32_t saved_table_addr[RADEON_NUM_VM];
918};
919
920/*
921 * file private structure
922 */
923struct radeon_fpriv {
924 struct radeon_vm vm;
925};
926
927/*
928 * R6xx+ IH ring
929 */
930struct r600_ih {
931 struct radeon_bo *ring_obj;
932 volatile uint32_t *ring;
933 unsigned rptr;
934 unsigned ring_size;
935 uint64_t gpu_addr;
936 uint32_t ptr_mask;
937 atomic_t lock;
938 bool enabled;
939};
940
941/*
942 * RLC stuff
943 */
944#include "clearstate_defs.h"
945
946struct radeon_rlc {
947 /* for power gating */
948 struct radeon_bo *save_restore_obj;
949 uint64_t save_restore_gpu_addr;
950 volatile uint32_t *sr_ptr;
951 const u32 *reg_list;
952 u32 reg_list_size;
953 /* for clear state */
954 struct radeon_bo *clear_state_obj;
955 uint64_t clear_state_gpu_addr;
956 volatile uint32_t *cs_ptr;
957 const struct cs_section_def *cs_data;
958 u32 clear_state_size;
959 /* for cp tables */
960 struct radeon_bo *cp_table_obj;
961 uint64_t cp_table_gpu_addr;
962 volatile uint32_t *cp_table_ptr;
963 u32 cp_table_size;
964};
965
966int radeon_ib_get(struct radeon_device *rdev, int ring,
967 struct radeon_ib *ib, struct radeon_vm *vm,
968 unsigned size);
969void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
970int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
971 struct radeon_ib *const_ib, bool hdp_flush);
972int radeon_ib_pool_init(struct radeon_device *rdev);
973void radeon_ib_pool_fini(struct radeon_device *rdev);
974int radeon_ib_ring_tests(struct radeon_device *rdev);
975/* Ring access between begin & end cannot sleep */
976bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
977 struct radeon_ring *ring);
978void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
979int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
980int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
981void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
982 bool hdp_flush);
983void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
984 bool hdp_flush);
985void radeon_ring_undo(struct radeon_ring *ring);
986void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
987int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
988void radeon_ring_lockup_update(struct radeon_device *rdev,
989 struct radeon_ring *ring);
990bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
991unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
992 uint32_t **data);
993int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
994 unsigned size, uint32_t *data);
995int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
996 unsigned rptr_offs, u32 nop);
997void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
998
999
1000/* r600 async dma */
1001void r600_dma_stop(struct radeon_device *rdev);
1002int r600_dma_resume(struct radeon_device *rdev);
1003void r600_dma_fini(struct radeon_device *rdev);
1004
1005void cayman_dma_stop(struct radeon_device *rdev);
1006int cayman_dma_resume(struct radeon_device *rdev);
1007void cayman_dma_fini(struct radeon_device *rdev);
1008
1009/*
1010 * CS.
1011 */
1012struct radeon_cs_chunk {
1013 uint32_t length_dw;
1014 uint32_t *kdata;
1015 void __user *user_ptr;
1016};
1017
1018struct radeon_cs_parser {
1019 struct device *dev;
1020 struct radeon_device *rdev;
1021 struct drm_file *filp;
1022 /* chunks */
1023 unsigned nchunks;
1024 struct radeon_cs_chunk *chunks;
1025 uint64_t *chunks_array;
1026 /* IB */
1027 unsigned idx;
1028 /* relocations */
1029 unsigned nrelocs;
1030 struct radeon_bo_list *relocs;
1031 struct radeon_bo_list *vm_bos;
1032 struct list_head validated;
1033 unsigned dma_reloc_idx;
1034 /* indices of various chunks */
1035 struct radeon_cs_chunk *chunk_ib;
1036 struct radeon_cs_chunk *chunk_relocs;
1037 struct radeon_cs_chunk *chunk_flags;
1038 struct radeon_cs_chunk *chunk_const_ib;
1039 struct radeon_ib ib;
1040 struct radeon_ib const_ib;
1041 void *track;
1042 unsigned family;
1043 int parser_error;
1044 u32 cs_flags;
1045 u32 ring;
1046 s32 priority;
1047 struct ww_acquire_ctx ticket;
1048};
1049
1050static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1051{
1052 struct radeon_cs_chunk *ibc = p->chunk_ib;
1053
1054 if (ibc->kdata)
1055 return ibc->kdata[idx];
1056 return p->ib.ptr[idx];
1057}
1058
1059
1060struct radeon_cs_packet {
1061 unsigned idx;
1062 unsigned type;
1063 unsigned reg;
1064 unsigned opcode;
1065 int count;
1066 unsigned one_reg_wr;
1067};
1068
1069typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1070 struct radeon_cs_packet *pkt,
1071 unsigned idx, unsigned reg);
1072
1073/*
1074 * AGP
1075 */
1076
1077struct radeon_agp_mode {
1078 unsigned long mode; /**< AGP mode */
1079};
1080
1081struct radeon_agp_info {
1082 int agp_version_major;
1083 int agp_version_minor;
1084 unsigned long mode;
1085 unsigned long aperture_base; /* physical address */
1086 unsigned long aperture_size; /* bytes */
1087 unsigned long memory_allowed; /* bytes */
1088 unsigned long memory_used;
1089
1090 /* PCI information */
1091 unsigned short id_vendor;
1092 unsigned short id_device;
1093};
1094
1095struct radeon_agp_head {
1096 struct agp_kern_info agp_info;
1097 struct list_head memory;
1098 unsigned long mode;
1099 struct agp_bridge_data *bridge;
1100 int enabled;
1101 int acquired;
1102 unsigned long base;
1103 int agp_mtrr;
1104 int cant_use_aperture;
1105 unsigned long page_mask;
1106};
1107
1108#if IS_ENABLED(CONFIG_AGP)
1109struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1110#else
1111static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1112{
1113 return NULL;
1114}
1115#endif
1116int radeon_agp_init(struct radeon_device *rdev);
1117void radeon_agp_resume(struct radeon_device *rdev);
1118void radeon_agp_suspend(struct radeon_device *rdev);
1119void radeon_agp_fini(struct radeon_device *rdev);
1120
1121
1122/*
1123 * Writeback
1124 */
1125struct radeon_wb {
1126 struct radeon_bo *wb_obj;
1127 volatile uint32_t *wb;
1128 uint64_t gpu_addr;
1129 bool enabled;
1130 bool use_event;
1131};
1132
1133#define RADEON_WB_SCRATCH_OFFSET 0
1134#define RADEON_WB_RING0_NEXT_RPTR 256
1135#define RADEON_WB_CP_RPTR_OFFSET 1024
1136#define RADEON_WB_CP1_RPTR_OFFSET 1280
1137#define RADEON_WB_CP2_RPTR_OFFSET 1536
1138#define R600_WB_DMA_RPTR_OFFSET 1792
1139#define R600_WB_IH_WPTR_OFFSET 2048
1140#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1141#define R600_WB_EVENT_OFFSET 3072
1142#define CIK_WB_CP1_WPTR_OFFSET 3328
1143#define CIK_WB_CP2_WPTR_OFFSET 3584
1144#define R600_WB_DMA_RING_TEST_OFFSET 3588
1145#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1146
1147/**
1148 * struct radeon_pm - power management datas
1149 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1150 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1151 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1152 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1153 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1154 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1155 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1156 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1157 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1158 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1159 * @needed_bandwidth: current bandwidth needs
1160 *
1161 * It keeps track of various data needed to take powermanagement decision.
1162 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1163 * Equation between gpu/memory clock and available bandwidth is hw dependent
1164 * (type of memory, bus size, efficiency, ...)
1165 */
1166
1167enum radeon_pm_method {
1168 PM_METHOD_PROFILE,
1169 PM_METHOD_DYNPM,
1170 PM_METHOD_DPM,
1171};
1172
1173enum radeon_dynpm_state {
1174 DYNPM_STATE_DISABLED,
1175 DYNPM_STATE_MINIMUM,
1176 DYNPM_STATE_PAUSED,
1177 DYNPM_STATE_ACTIVE,
1178 DYNPM_STATE_SUSPENDED,
1179};
1180enum radeon_dynpm_action {
1181 DYNPM_ACTION_NONE,
1182 DYNPM_ACTION_MINIMUM,
1183 DYNPM_ACTION_DOWNCLOCK,
1184 DYNPM_ACTION_UPCLOCK,
1185 DYNPM_ACTION_DEFAULT
1186};
1187
1188enum radeon_voltage_type {
1189 VOLTAGE_NONE = 0,
1190 VOLTAGE_GPIO,
1191 VOLTAGE_VDDC,
1192 VOLTAGE_SW
1193};
1194
1195enum radeon_pm_state_type {
1196 /* not used for dpm */
1197 POWER_STATE_TYPE_DEFAULT,
1198 POWER_STATE_TYPE_POWERSAVE,
1199 /* user selectable states */
1200 POWER_STATE_TYPE_BATTERY,
1201 POWER_STATE_TYPE_BALANCED,
1202 POWER_STATE_TYPE_PERFORMANCE,
1203 /* internal states */
1204 POWER_STATE_TYPE_INTERNAL_UVD,
1205 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1206 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1207 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1208 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1209 POWER_STATE_TYPE_INTERNAL_BOOT,
1210 POWER_STATE_TYPE_INTERNAL_THERMAL,
1211 POWER_STATE_TYPE_INTERNAL_ACPI,
1212 POWER_STATE_TYPE_INTERNAL_ULV,
1213 POWER_STATE_TYPE_INTERNAL_3DPERF,
1214};
1215
1216enum radeon_pm_profile_type {
1217 PM_PROFILE_DEFAULT,
1218 PM_PROFILE_AUTO,
1219 PM_PROFILE_LOW,
1220 PM_PROFILE_MID,
1221 PM_PROFILE_HIGH,
1222};
1223
1224#define PM_PROFILE_DEFAULT_IDX 0
1225#define PM_PROFILE_LOW_SH_IDX 1
1226#define PM_PROFILE_MID_SH_IDX 2
1227#define PM_PROFILE_HIGH_SH_IDX 3
1228#define PM_PROFILE_LOW_MH_IDX 4
1229#define PM_PROFILE_MID_MH_IDX 5
1230#define PM_PROFILE_HIGH_MH_IDX 6
1231#define PM_PROFILE_MAX 7
1232
1233struct radeon_pm_profile {
1234 int dpms_off_ps_idx;
1235 int dpms_on_ps_idx;
1236 int dpms_off_cm_idx;
1237 int dpms_on_cm_idx;
1238};
1239
1240enum radeon_int_thermal_type {
1241 THERMAL_TYPE_NONE,
1242 THERMAL_TYPE_EXTERNAL,
1243 THERMAL_TYPE_EXTERNAL_GPIO,
1244 THERMAL_TYPE_RV6XX,
1245 THERMAL_TYPE_RV770,
1246 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1247 THERMAL_TYPE_EVERGREEN,
1248 THERMAL_TYPE_SUMO,
1249 THERMAL_TYPE_NI,
1250 THERMAL_TYPE_SI,
1251 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1252 THERMAL_TYPE_CI,
1253 THERMAL_TYPE_KV,
1254};
1255
1256struct radeon_voltage {
1257 enum radeon_voltage_type type;
1258 /* gpio voltage */
1259 struct radeon_gpio_rec gpio;
1260 u32 delay; /* delay in usec from voltage drop to sclk change */
1261 bool active_high; /* voltage drop is active when bit is high */
1262 /* VDDC voltage */
1263 u8 vddc_id; /* index into vddc voltage table */
1264 u8 vddci_id; /* index into vddci voltage table */
1265 bool vddci_enabled;
1266 /* r6xx+ sw */
1267 u16 voltage;
1268 /* evergreen+ vddci */
1269 u16 vddci;
1270};
1271
1272/* clock mode flags */
1273#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1274
1275struct radeon_pm_clock_info {
1276 /* memory clock */
1277 u32 mclk;
1278 /* engine clock */
1279 u32 sclk;
1280 /* voltage info */
1281 struct radeon_voltage voltage;
1282 /* standardized clock flags */
1283 u32 flags;
1284};
1285
1286/* state flags */
1287#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1288
1289struct radeon_power_state {
1290 enum radeon_pm_state_type type;
1291 struct radeon_pm_clock_info *clock_info;
1292 /* number of valid clock modes in this power state */
1293 int num_clock_modes;
1294 struct radeon_pm_clock_info *default_clock_mode;
1295 /* standardized state flags */
1296 u32 flags;
1297 u32 misc; /* vbios specific flags */
1298 u32 misc2; /* vbios specific flags */
1299 int pcie_lanes; /* pcie lanes */
1300};
1301
1302/*
1303 * Some modes are overclocked by very low value, accept them
1304 */
1305#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1306
1307enum radeon_dpm_auto_throttle_src {
1308 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1309 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1310};
1311
1312enum radeon_dpm_event_src {
1313 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1314 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1315 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1316 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1317 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1318};
1319
1320#define RADEON_MAX_VCE_LEVELS 6
1321
1322enum radeon_vce_level {
1323 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1324 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1325 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1326 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1327 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1328 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1329};
1330
1331struct radeon_ps {
1332 u32 caps; /* vbios flags */
1333 u32 class; /* vbios flags */
1334 u32 class2; /* vbios flags */
1335 /* UVD clocks */
1336 u32 vclk;
1337 u32 dclk;
1338 /* VCE clocks */
1339 u32 evclk;
1340 u32 ecclk;
1341 bool vce_active;
1342 enum radeon_vce_level vce_level;
1343 /* asic priv */
1344 void *ps_priv;
1345};
1346
1347struct radeon_dpm_thermal {
1348 /* thermal interrupt work */
1349 struct work_struct work;
1350 /* low temperature threshold */
1351 int min_temp;
1352 /* high temperature threshold */
1353 int max_temp;
1354 /* was interrupt low to high or high to low */
1355 bool high_to_low;
1356};
1357
1358enum radeon_clk_action
1359{
1360 RADEON_SCLK_UP = 1,
1361 RADEON_SCLK_DOWN
1362};
1363
1364struct radeon_blacklist_clocks
1365{
1366 u32 sclk;
1367 u32 mclk;
1368 enum radeon_clk_action action;
1369};
1370
1371struct radeon_clock_and_voltage_limits {
1372 u32 sclk;
1373 u32 mclk;
1374 u16 vddc;
1375 u16 vddci;
1376};
1377
1378struct radeon_clock_array {
1379 u32 count;
1380 u32 *values;
1381};
1382
1383struct radeon_clock_voltage_dependency_entry {
1384 u32 clk;
1385 u16 v;
1386};
1387
1388struct radeon_clock_voltage_dependency_table {
1389 u32 count;
1390 struct radeon_clock_voltage_dependency_entry *entries;
1391};
1392
1393union radeon_cac_leakage_entry {
1394 struct {
1395 u16 vddc;
1396 u32 leakage;
1397 };
1398 struct {
1399 u16 vddc1;
1400 u16 vddc2;
1401 u16 vddc3;
1402 };
1403};
1404
1405struct radeon_cac_leakage_table {
1406 u32 count;
1407 union radeon_cac_leakage_entry *entries;
1408};
1409
1410struct radeon_phase_shedding_limits_entry {
1411 u16 voltage;
1412 u32 sclk;
1413 u32 mclk;
1414};
1415
1416struct radeon_phase_shedding_limits_table {
1417 u32 count;
1418 struct radeon_phase_shedding_limits_entry *entries;
1419};
1420
1421struct radeon_uvd_clock_voltage_dependency_entry {
1422 u32 vclk;
1423 u32 dclk;
1424 u16 v;
1425};
1426
1427struct radeon_uvd_clock_voltage_dependency_table {
1428 u8 count;
1429 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1430};
1431
1432struct radeon_vce_clock_voltage_dependency_entry {
1433 u32 ecclk;
1434 u32 evclk;
1435 u16 v;
1436};
1437
1438struct radeon_vce_clock_voltage_dependency_table {
1439 u8 count;
1440 struct radeon_vce_clock_voltage_dependency_entry *entries;
1441};
1442
1443struct radeon_ppm_table {
1444 u8 ppm_design;
1445 u16 cpu_core_number;
1446 u32 platform_tdp;
1447 u32 small_ac_platform_tdp;
1448 u32 platform_tdc;
1449 u32 small_ac_platform_tdc;
1450 u32 apu_tdp;
1451 u32 dgpu_tdp;
1452 u32 dgpu_ulv_power;
1453 u32 tj_max;
1454};
1455
1456struct radeon_cac_tdp_table {
1457 u16 tdp;
1458 u16 configurable_tdp;
1459 u16 tdc;
1460 u16 battery_power_limit;
1461 u16 small_power_limit;
1462 u16 low_cac_leakage;
1463 u16 high_cac_leakage;
1464 u16 maximum_power_delivery_limit;
1465};
1466
1467struct radeon_dpm_dynamic_state {
1468 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1469 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1470 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1471 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1472 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1473 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1474 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1475 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1476 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1477 struct radeon_clock_array valid_sclk_values;
1478 struct radeon_clock_array valid_mclk_values;
1479 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1480 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1481 u32 mclk_sclk_ratio;
1482 u32 sclk_mclk_delta;
1483 u16 vddc_vddci_delta;
1484 u16 min_vddc_for_pcie_gen2;
1485 struct radeon_cac_leakage_table cac_leakage_table;
1486 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1487 struct radeon_ppm_table *ppm_table;
1488 struct radeon_cac_tdp_table *cac_tdp_table;
1489};
1490
1491struct radeon_dpm_fan {
1492 u16 t_min;
1493 u16 t_med;
1494 u16 t_high;
1495 u16 pwm_min;
1496 u16 pwm_med;
1497 u16 pwm_high;
1498 u8 t_hyst;
1499 u32 cycle_delay;
1500 u16 t_max;
1501 u8 control_mode;
1502 u16 default_max_fan_pwm;
1503 u16 default_fan_output_sensitivity;
1504 u16 fan_output_sensitivity;
1505 bool ucode_fan_control;
1506};
1507
1508enum radeon_pcie_gen {
1509 RADEON_PCIE_GEN1 = 0,
1510 RADEON_PCIE_GEN2 = 1,
1511 RADEON_PCIE_GEN3 = 2,
1512 RADEON_PCIE_GEN_INVALID = 0xffff
1513};
1514
1515enum radeon_dpm_forced_level {
1516 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1517 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1518 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1519};
1520
1521struct radeon_vce_state {
1522 /* vce clocks */
1523 u32 evclk;
1524 u32 ecclk;
1525 /* gpu clocks */
1526 u32 sclk;
1527 u32 mclk;
1528 u8 clk_idx;
1529 u8 pstate;
1530};
1531
1532struct radeon_dpm {
1533 struct radeon_ps *ps;
1534 /* number of valid power states */
1535 int num_ps;
1536 /* current power state that is active */
1537 struct radeon_ps *current_ps;
1538 /* requested power state */
1539 struct radeon_ps *requested_ps;
1540 /* boot up power state */
1541 struct radeon_ps *boot_ps;
1542 /* default uvd power state */
1543 struct radeon_ps *uvd_ps;
1544 /* vce requirements */
1545 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1546 enum radeon_vce_level vce_level;
1547 enum radeon_pm_state_type state;
1548 enum radeon_pm_state_type user_state;
1549 u32 platform_caps;
1550 u32 voltage_response_time;
1551 u32 backbias_response_time;
1552 void *priv;
1553 u32 new_active_crtcs;
1554 int new_active_crtc_count;
1555 int high_pixelclock_count;
1556 u32 current_active_crtcs;
1557 int current_active_crtc_count;
1558 bool single_display;
1559 struct radeon_dpm_dynamic_state dyn_state;
1560 struct radeon_dpm_fan fan;
1561 u32 tdp_limit;
1562 u32 near_tdp_limit;
1563 u32 near_tdp_limit_adjusted;
1564 u32 sq_ramping_threshold;
1565 u32 cac_leakage;
1566 u16 tdp_od_limit;
1567 u32 tdp_adjustment;
1568 u16 load_line_slope;
1569 bool power_control;
1570 bool ac_power;
1571 /* special states active */
1572 bool thermal_active;
1573 bool uvd_active;
1574 bool vce_active;
1575 /* thermal handling */
1576 struct radeon_dpm_thermal thermal;
1577 /* forced levels */
1578 enum radeon_dpm_forced_level forced_level;
1579 /* track UVD streams */
1580 unsigned sd;
1581 unsigned hd;
1582};
1583
1584void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1585void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1586
1587struct radeon_pm {
1588 struct mutex mutex;
1589 /* write locked while reprogramming mclk */
1590 struct rw_semaphore mclk_lock;
1591 u32 active_crtcs;
1592 int active_crtc_count;
1593 int req_vblank;
1594 bool vblank_sync;
1595 fixed20_12 max_bandwidth;
1596 fixed20_12 igp_sideport_mclk;
1597 fixed20_12 igp_system_mclk;
1598 fixed20_12 igp_ht_link_clk;
1599 fixed20_12 igp_ht_link_width;
1600 fixed20_12 k8_bandwidth;
1601 fixed20_12 sideport_bandwidth;
1602 fixed20_12 ht_bandwidth;
1603 fixed20_12 core_bandwidth;
1604 fixed20_12 sclk;
1605 fixed20_12 mclk;
1606 fixed20_12 needed_bandwidth;
1607 struct radeon_power_state *power_state;
1608 /* number of valid power states */
1609 int num_power_states;
1610 int current_power_state_index;
1611 int current_clock_mode_index;
1612 int requested_power_state_index;
1613 int requested_clock_mode_index;
1614 int default_power_state_index;
1615 u32 current_sclk;
1616 u32 current_mclk;
1617 u16 current_vddc;
1618 u16 current_vddci;
1619 u32 default_sclk;
1620 u32 default_mclk;
1621 u16 default_vddc;
1622 u16 default_vddci;
1623 struct radeon_i2c_chan *i2c_bus;
1624 /* selected pm method */
1625 enum radeon_pm_method pm_method;
1626 /* dynpm power management */
1627 struct delayed_work dynpm_idle_work;
1628 enum radeon_dynpm_state dynpm_state;
1629 enum radeon_dynpm_action dynpm_planned_action;
1630 unsigned long dynpm_action_timeout;
1631 bool dynpm_can_upclock;
1632 bool dynpm_can_downclock;
1633 /* profile-based power management */
1634 enum radeon_pm_profile_type profile;
1635 int profile_index;
1636 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1637 /* internal thermal controller on rv6xx+ */
1638 enum radeon_int_thermal_type int_thermal_type;
1639 struct device *int_hwmon_dev;
1640 /* fan control parameters */
1641 bool no_fan;
1642 u8 fan_pulses_per_revolution;
1643 u8 fan_min_rpm;
1644 u8 fan_max_rpm;
1645 /* dpm */
1646 bool dpm_enabled;
1647 bool sysfs_initialized;
1648 struct radeon_dpm dpm;
1649};
1650
1651#define RADEON_PCIE_SPEED_25 1
1652#define RADEON_PCIE_SPEED_50 2
1653#define RADEON_PCIE_SPEED_80 4
1654
1655int radeon_pm_get_type_index(struct radeon_device *rdev,
1656 enum radeon_pm_state_type ps_type,
1657 int instance);
1658/*
1659 * UVD
1660 */
1661#define RADEON_DEFAULT_UVD_HANDLES 10
1662#define RADEON_MAX_UVD_HANDLES 30
1663#define RADEON_UVD_STACK_SIZE (200*1024)
1664#define RADEON_UVD_HEAP_SIZE (256*1024)
1665#define RADEON_UVD_SESSION_SIZE (50*1024)
1666
1667struct radeon_uvd {
1668 bool fw_header_present;
1669 struct radeon_bo *vcpu_bo;
1670 void *cpu_addr;
1671 uint64_t gpu_addr;
1672 unsigned max_handles;
1673 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1674 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1675 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1676 struct delayed_work idle_work;
1677};
1678
1679int radeon_uvd_init(struct radeon_device *rdev);
1680void radeon_uvd_fini(struct radeon_device *rdev);
1681int radeon_uvd_suspend(struct radeon_device *rdev);
1682int radeon_uvd_resume(struct radeon_device *rdev);
1683int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1684 uint32_t handle, struct radeon_fence **fence);
1685int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1686 uint32_t handle, struct radeon_fence **fence);
1687void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1688 uint32_t allowed_domains);
1689void radeon_uvd_free_handles(struct radeon_device *rdev,
1690 struct drm_file *filp);
1691int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1692void radeon_uvd_note_usage(struct radeon_device *rdev);
1693int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1694 unsigned vclk, unsigned dclk,
1695 unsigned vco_min, unsigned vco_max,
1696 unsigned fb_factor, unsigned fb_mask,
1697 unsigned pd_min, unsigned pd_max,
1698 unsigned pd_even,
1699 unsigned *optimal_fb_div,
1700 unsigned *optimal_vclk_div,
1701 unsigned *optimal_dclk_div);
1702int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1703 unsigned cg_upll_func_cntl);
1704
1705/*
1706 * VCE
1707 */
1708#define RADEON_MAX_VCE_HANDLES 16
1709
1710struct radeon_vce {
1711 struct radeon_bo *vcpu_bo;
1712 uint64_t gpu_addr;
1713 unsigned fw_version;
1714 unsigned fb_version;
1715 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1716 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1717 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1718 struct delayed_work idle_work;
1719 uint32_t keyselect;
1720};
1721
1722int radeon_vce_init(struct radeon_device *rdev);
1723void radeon_vce_fini(struct radeon_device *rdev);
1724int radeon_vce_suspend(struct radeon_device *rdev);
1725int radeon_vce_resume(struct radeon_device *rdev);
1726int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1727 uint32_t handle, struct radeon_fence **fence);
1728int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1729 uint32_t handle, struct radeon_fence **fence);
1730void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1731void radeon_vce_note_usage(struct radeon_device *rdev);
1732int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1733int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1734bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1735 struct radeon_ring *ring,
1736 struct radeon_semaphore *semaphore,
1737 bool emit_wait);
1738void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1739void radeon_vce_fence_emit(struct radeon_device *rdev,
1740 struct radeon_fence *fence);
1741int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1742int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1743
1744struct r600_audio_pin {
1745 int channels;
1746 int rate;
1747 int bits_per_sample;
1748 u8 status_bits;
1749 u8 category_code;
1750 u32 offset;
1751 bool connected;
1752 u32 id;
1753};
1754
1755struct r600_audio {
1756 bool enabled;
1757 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1758 int num_pins;
1759 struct radeon_audio_funcs *hdmi_funcs;
1760 struct radeon_audio_funcs *dp_funcs;
1761 struct radeon_audio_basic_funcs *funcs;
1762 struct drm_audio_component *component;
1763 bool component_registered;
1764 struct mutex component_mutex;
1765};
1766
1767/*
1768 * Benchmarking
1769 */
1770void radeon_benchmark(struct radeon_device *rdev, int test_number);
1771
1772
1773/*
1774 * Testing
1775 */
1776void radeon_test_moves(struct radeon_device *rdev);
1777void radeon_test_ring_sync(struct radeon_device *rdev,
1778 struct radeon_ring *cpA,
1779 struct radeon_ring *cpB);
1780void radeon_test_syncing(struct radeon_device *rdev);
1781
1782/*
1783 * MMU Notifier
1784 */
1785#if defined(CONFIG_MMU_NOTIFIER)
1786int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1787void radeon_mn_unregister(struct radeon_bo *bo);
1788#else
1789static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1790{
1791 return -ENODEV;
1792}
1793static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1794#endif
1795
1796/*
1797 * Debugfs
1798 */
1799void radeon_debugfs_fence_init(struct radeon_device *rdev);
1800void radeon_gem_debugfs_init(struct radeon_device *rdev);
1801
1802/*
1803 * ASIC ring specific functions.
1804 */
1805struct radeon_asic_ring {
1806 /* ring read/write ptr handling */
1807 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1808 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1809 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1810
1811 /* validating and patching of IBs */
1812 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1813 int (*cs_parse)(struct radeon_cs_parser *p);
1814
1815 /* command emmit functions */
1816 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1817 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1818 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1819 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1820 struct radeon_semaphore *semaphore, bool emit_wait);
1821 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1822 unsigned vm_id, uint64_t pd_addr);
1823
1824 /* testing functions */
1825 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1826 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1827 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1828
1829 /* deprecated */
1830 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1831};
1832
1833/*
1834 * ASIC specific functions.
1835 */
1836struct radeon_asic {
1837 int (*init)(struct radeon_device *rdev);
1838 void (*fini)(struct radeon_device *rdev);
1839 int (*resume)(struct radeon_device *rdev);
1840 int (*suspend)(struct radeon_device *rdev);
1841 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1842 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1843 /* Flush the HDP cache via MMIO */
1844 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1845 /* check if 3D engine is idle */
1846 bool (*gui_idle)(struct radeon_device *rdev);
1847 /* wait for mc_idle */
1848 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1849 /* get the reference clock */
1850 u32 (*get_xclk)(struct radeon_device *rdev);
1851 /* get the gpu clock counter */
1852 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1853 /* get register for info ioctl */
1854 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1855 /* gart */
1856 struct {
1857 void (*tlb_flush)(struct radeon_device *rdev);
1858 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1859 void (*set_page)(struct radeon_device *rdev, unsigned i,
1860 uint64_t entry);
1861 } gart;
1862 struct {
1863 int (*init)(struct radeon_device *rdev);
1864 void (*fini)(struct radeon_device *rdev);
1865 void (*copy_pages)(struct radeon_device *rdev,
1866 struct radeon_ib *ib,
1867 uint64_t pe, uint64_t src,
1868 unsigned count);
1869 void (*write_pages)(struct radeon_device *rdev,
1870 struct radeon_ib *ib,
1871 uint64_t pe,
1872 uint64_t addr, unsigned count,
1873 uint32_t incr, uint32_t flags);
1874 void (*set_pages)(struct radeon_device *rdev,
1875 struct radeon_ib *ib,
1876 uint64_t pe,
1877 uint64_t addr, unsigned count,
1878 uint32_t incr, uint32_t flags);
1879 void (*pad_ib)(struct radeon_ib *ib);
1880 } vm;
1881 /* ring specific callbacks */
1882 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1883 /* irqs */
1884 struct {
1885 int (*set)(struct radeon_device *rdev);
1886 int (*process)(struct radeon_device *rdev);
1887 } irq;
1888 /* displays */
1889 struct {
1890 /* display watermarks */
1891 void (*bandwidth_update)(struct radeon_device *rdev);
1892 /* get frame count */
1893 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1894 /* wait for vblank */
1895 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1896 /* set backlight level */
1897 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1898 /* get backlight level */
1899 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1900 /* audio callbacks */
1901 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1902 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1903 } display;
1904 /* copy functions for bo handling */
1905 struct {
1906 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1907 uint64_t src_offset,
1908 uint64_t dst_offset,
1909 unsigned num_gpu_pages,
1910 struct dma_resv *resv);
1911 u32 blit_ring_index;
1912 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1913 uint64_t src_offset,
1914 uint64_t dst_offset,
1915 unsigned num_gpu_pages,
1916 struct dma_resv *resv);
1917 u32 dma_ring_index;
1918 /* method used for bo copy */
1919 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 unsigned num_gpu_pages,
1923 struct dma_resv *resv);
1924 /* ring used for bo copies */
1925 u32 copy_ring_index;
1926 } copy;
1927 /* surfaces */
1928 struct {
1929 int (*set_reg)(struct radeon_device *rdev, int reg,
1930 uint32_t tiling_flags, uint32_t pitch,
1931 uint32_t offset, uint32_t obj_size);
1932 void (*clear_reg)(struct radeon_device *rdev, int reg);
1933 } surface;
1934 /* hotplug detect */
1935 struct {
1936 void (*init)(struct radeon_device *rdev);
1937 void (*fini)(struct radeon_device *rdev);
1938 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1939 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1940 } hpd;
1941 /* static power management */
1942 struct {
1943 void (*misc)(struct radeon_device *rdev);
1944 void (*prepare)(struct radeon_device *rdev);
1945 void (*finish)(struct radeon_device *rdev);
1946 void (*init_profile)(struct radeon_device *rdev);
1947 void (*get_dynpm_state)(struct radeon_device *rdev);
1948 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1949 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1950 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1951 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1952 int (*get_pcie_lanes)(struct radeon_device *rdev);
1953 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1954 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1955 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1956 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1957 int (*get_temperature)(struct radeon_device *rdev);
1958 } pm;
1959 /* dynamic power management */
1960 struct {
1961 int (*init)(struct radeon_device *rdev);
1962 void (*setup_asic)(struct radeon_device *rdev);
1963 int (*enable)(struct radeon_device *rdev);
1964 int (*late_enable)(struct radeon_device *rdev);
1965 void (*disable)(struct radeon_device *rdev);
1966 int (*pre_set_power_state)(struct radeon_device *rdev);
1967 int (*set_power_state)(struct radeon_device *rdev);
1968 void (*post_set_power_state)(struct radeon_device *rdev);
1969 void (*display_configuration_changed)(struct radeon_device *rdev);
1970 void (*fini)(struct radeon_device *rdev);
1971 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1972 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1973 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1974 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1975 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1976 bool (*vblank_too_short)(struct radeon_device *rdev);
1977 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1978 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1979 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1980 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1981 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1982 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1983 u32 (*get_current_sclk)(struct radeon_device *rdev);
1984 u32 (*get_current_mclk)(struct radeon_device *rdev);
1985 u16 (*get_current_vddc)(struct radeon_device *rdev);
1986 } dpm;
1987 /* pageflipping */
1988 struct {
1989 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1990 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1991 } pflip;
1992};
1993
1994/*
1995 * Asic structures
1996 */
1997struct r100_asic {
1998 const unsigned *reg_safe_bm;
1999 unsigned reg_safe_bm_size;
2000 u32 hdp_cntl;
2001};
2002
2003struct r300_asic {
2004 const unsigned *reg_safe_bm;
2005 unsigned reg_safe_bm_size;
2006 u32 resync_scratch;
2007 u32 hdp_cntl;
2008};
2009
2010struct r600_asic {
2011 unsigned max_pipes;
2012 unsigned max_tile_pipes;
2013 unsigned max_simds;
2014 unsigned max_backends;
2015 unsigned max_gprs;
2016 unsigned max_threads;
2017 unsigned max_stack_entries;
2018 unsigned max_hw_contexts;
2019 unsigned max_gs_threads;
2020 unsigned sx_max_export_size;
2021 unsigned sx_max_export_pos_size;
2022 unsigned sx_max_export_smx_size;
2023 unsigned sq_num_cf_insts;
2024 unsigned tiling_nbanks;
2025 unsigned tiling_npipes;
2026 unsigned tiling_group_size;
2027 unsigned tile_config;
2028 unsigned backend_map;
2029 unsigned active_simds;
2030};
2031
2032struct rv770_asic {
2033 unsigned max_pipes;
2034 unsigned max_tile_pipes;
2035 unsigned max_simds;
2036 unsigned max_backends;
2037 unsigned max_gprs;
2038 unsigned max_threads;
2039 unsigned max_stack_entries;
2040 unsigned max_hw_contexts;
2041 unsigned max_gs_threads;
2042 unsigned sx_max_export_size;
2043 unsigned sx_max_export_pos_size;
2044 unsigned sx_max_export_smx_size;
2045 unsigned sq_num_cf_insts;
2046 unsigned sx_num_of_sets;
2047 unsigned sc_prim_fifo_size;
2048 unsigned sc_hiz_tile_fifo_size;
2049 unsigned sc_earlyz_tile_fifo_fize;
2050 unsigned tiling_nbanks;
2051 unsigned tiling_npipes;
2052 unsigned tiling_group_size;
2053 unsigned tile_config;
2054 unsigned backend_map;
2055 unsigned active_simds;
2056};
2057
2058struct evergreen_asic {
2059 unsigned num_ses;
2060 unsigned max_pipes;
2061 unsigned max_tile_pipes;
2062 unsigned max_simds;
2063 unsigned max_backends;
2064 unsigned max_gprs;
2065 unsigned max_threads;
2066 unsigned max_stack_entries;
2067 unsigned max_hw_contexts;
2068 unsigned max_gs_threads;
2069 unsigned sx_max_export_size;
2070 unsigned sx_max_export_pos_size;
2071 unsigned sx_max_export_smx_size;
2072 unsigned sq_num_cf_insts;
2073 unsigned sx_num_of_sets;
2074 unsigned sc_prim_fifo_size;
2075 unsigned sc_hiz_tile_fifo_size;
2076 unsigned sc_earlyz_tile_fifo_size;
2077 unsigned tiling_nbanks;
2078 unsigned tiling_npipes;
2079 unsigned tiling_group_size;
2080 unsigned tile_config;
2081 unsigned backend_map;
2082 unsigned active_simds;
2083};
2084
2085struct cayman_asic {
2086 unsigned max_shader_engines;
2087 unsigned max_pipes_per_simd;
2088 unsigned max_tile_pipes;
2089 unsigned max_simds_per_se;
2090 unsigned max_backends_per_se;
2091 unsigned max_texture_channel_caches;
2092 unsigned max_gprs;
2093 unsigned max_threads;
2094 unsigned max_gs_threads;
2095 unsigned max_stack_entries;
2096 unsigned sx_num_of_sets;
2097 unsigned sx_max_export_size;
2098 unsigned sx_max_export_pos_size;
2099 unsigned sx_max_export_smx_size;
2100 unsigned max_hw_contexts;
2101 unsigned sq_num_cf_insts;
2102 unsigned sc_prim_fifo_size;
2103 unsigned sc_hiz_tile_fifo_size;
2104 unsigned sc_earlyz_tile_fifo_size;
2105
2106 unsigned num_shader_engines;
2107 unsigned num_shader_pipes_per_simd;
2108 unsigned num_tile_pipes;
2109 unsigned num_simds_per_se;
2110 unsigned num_backends_per_se;
2111 unsigned backend_disable_mask_per_asic;
2112 unsigned backend_map;
2113 unsigned num_texture_channel_caches;
2114 unsigned mem_max_burst_length_bytes;
2115 unsigned mem_row_size_in_kb;
2116 unsigned shader_engine_tile_size;
2117 unsigned num_gpus;
2118 unsigned multi_gpu_tile_size;
2119
2120 unsigned tile_config;
2121 unsigned active_simds;
2122};
2123
2124struct si_asic {
2125 unsigned max_shader_engines;
2126 unsigned max_tile_pipes;
2127 unsigned max_cu_per_sh;
2128 unsigned max_sh_per_se;
2129 unsigned max_backends_per_se;
2130 unsigned max_texture_channel_caches;
2131 unsigned max_gprs;
2132 unsigned max_gs_threads;
2133 unsigned max_hw_contexts;
2134 unsigned sc_prim_fifo_size_frontend;
2135 unsigned sc_prim_fifo_size_backend;
2136 unsigned sc_hiz_tile_fifo_size;
2137 unsigned sc_earlyz_tile_fifo_size;
2138
2139 unsigned num_tile_pipes;
2140 unsigned backend_enable_mask;
2141 unsigned backend_disable_mask_per_asic;
2142 unsigned backend_map;
2143 unsigned num_texture_channel_caches;
2144 unsigned mem_max_burst_length_bytes;
2145 unsigned mem_row_size_in_kb;
2146 unsigned shader_engine_tile_size;
2147 unsigned num_gpus;
2148 unsigned multi_gpu_tile_size;
2149
2150 unsigned tile_config;
2151 uint32_t tile_mode_array[32];
2152 uint32_t active_cus;
2153};
2154
2155struct cik_asic {
2156 unsigned max_shader_engines;
2157 unsigned max_tile_pipes;
2158 unsigned max_cu_per_sh;
2159 unsigned max_sh_per_se;
2160 unsigned max_backends_per_se;
2161 unsigned max_texture_channel_caches;
2162 unsigned max_gprs;
2163 unsigned max_gs_threads;
2164 unsigned max_hw_contexts;
2165 unsigned sc_prim_fifo_size_frontend;
2166 unsigned sc_prim_fifo_size_backend;
2167 unsigned sc_hiz_tile_fifo_size;
2168 unsigned sc_earlyz_tile_fifo_size;
2169
2170 unsigned num_tile_pipes;
2171 unsigned backend_enable_mask;
2172 unsigned backend_disable_mask_per_asic;
2173 unsigned backend_map;
2174 unsigned num_texture_channel_caches;
2175 unsigned mem_max_burst_length_bytes;
2176 unsigned mem_row_size_in_kb;
2177 unsigned shader_engine_tile_size;
2178 unsigned num_gpus;
2179 unsigned multi_gpu_tile_size;
2180
2181 unsigned tile_config;
2182 uint32_t tile_mode_array[32];
2183 uint32_t macrotile_mode_array[16];
2184 uint32_t active_cus;
2185};
2186
2187union radeon_asic_config {
2188 struct r300_asic r300;
2189 struct r100_asic r100;
2190 struct r600_asic r600;
2191 struct rv770_asic rv770;
2192 struct evergreen_asic evergreen;
2193 struct cayman_asic cayman;
2194 struct si_asic si;
2195 struct cik_asic cik;
2196};
2197
2198/*
2199 * asic initizalization from radeon_asic.c
2200 */
2201void radeon_agp_disable(struct radeon_device *rdev);
2202int radeon_asic_init(struct radeon_device *rdev);
2203
2204
2205/*
2206 * IOCTL.
2207 */
2208int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2209 struct drm_file *filp);
2210int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2211 struct drm_file *filp);
2212int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2213 struct drm_file *filp);
2214int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2215 struct drm_file *file_priv);
2216int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *file_priv);
2218int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
2226int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *filp);
2228int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2231int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *filp);
2233int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *filp);
2235int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2236
2237/* VRAM scratch page for HDP bug, default vram page */
2238struct r600_vram_scratch {
2239 struct radeon_bo *robj;
2240 volatile uint32_t *ptr;
2241 u64 gpu_addr;
2242};
2243
2244/*
2245 * ACPI
2246 */
2247struct radeon_atif_notification_cfg {
2248 bool enabled;
2249 int command_code;
2250};
2251
2252struct radeon_atif_notifications {
2253 bool display_switch;
2254 bool expansion_mode_change;
2255 bool thermal_state;
2256 bool forced_power_state;
2257 bool system_power_state;
2258 bool display_conf_change;
2259 bool px_gfx_switch;
2260 bool brightness_change;
2261 bool dgpu_display_event;
2262};
2263
2264struct radeon_atif_functions {
2265 bool system_params;
2266 bool sbios_requests;
2267 bool select_active_disp;
2268 bool lid_state;
2269 bool get_tv_standard;
2270 bool set_tv_standard;
2271 bool get_panel_expansion_mode;
2272 bool set_panel_expansion_mode;
2273 bool temperature_change;
2274 bool graphics_device_types;
2275};
2276
2277struct radeon_atif {
2278 struct radeon_atif_notifications notifications;
2279 struct radeon_atif_functions functions;
2280 struct radeon_atif_notification_cfg notification_cfg;
2281 struct radeon_encoder *encoder_for_bl;
2282};
2283
2284struct radeon_atcs_functions {
2285 bool get_ext_state;
2286 bool pcie_perf_req;
2287 bool pcie_dev_rdy;
2288 bool pcie_bus_width;
2289};
2290
2291struct radeon_atcs {
2292 struct radeon_atcs_functions functions;
2293};
2294
2295/*
2296 * Core structure, functions and helpers.
2297 */
2298typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2299typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2300
2301struct radeon_device {
2302 struct device *dev;
2303 struct drm_device *ddev;
2304 struct pci_dev *pdev;
2305#ifdef __alpha__
2306 struct pci_controller *hose;
2307#endif
2308 struct radeon_agp_head *agp;
2309 struct rw_semaphore exclusive_lock;
2310 /* ASIC */
2311 union radeon_asic_config config;
2312 enum radeon_family family;
2313 unsigned long flags;
2314 int usec_timeout;
2315 enum radeon_pll_errata pll_errata;
2316 int num_gb_pipes;
2317 int num_z_pipes;
2318 int disp_priority;
2319 /* BIOS */
2320 uint8_t *bios;
2321 bool is_atom_bios;
2322 uint16_t bios_header_start;
2323 struct radeon_bo *stolen_vga_memory;
2324 /* Register mmio */
2325 resource_size_t rmmio_base;
2326 resource_size_t rmmio_size;
2327 /* protects concurrent MM_INDEX/DATA based register access */
2328 spinlock_t mmio_idx_lock;
2329 /* protects concurrent SMC based register access */
2330 spinlock_t smc_idx_lock;
2331 /* protects concurrent PLL register access */
2332 spinlock_t pll_idx_lock;
2333 /* protects concurrent MC register access */
2334 spinlock_t mc_idx_lock;
2335 /* protects concurrent PCIE register access */
2336 spinlock_t pcie_idx_lock;
2337 /* protects concurrent PCIE_PORT register access */
2338 spinlock_t pciep_idx_lock;
2339 /* protects concurrent PIF register access */
2340 spinlock_t pif_idx_lock;
2341 /* protects concurrent CG register access */
2342 spinlock_t cg_idx_lock;
2343 /* protects concurrent UVD register access */
2344 spinlock_t uvd_idx_lock;
2345 /* protects concurrent RCU register access */
2346 spinlock_t rcu_idx_lock;
2347 /* protects concurrent DIDT register access */
2348 spinlock_t didt_idx_lock;
2349 /* protects concurrent ENDPOINT (audio) register access */
2350 spinlock_t end_idx_lock;
2351 void __iomem *rmmio;
2352 radeon_rreg_t mc_rreg;
2353 radeon_wreg_t mc_wreg;
2354 radeon_rreg_t pll_rreg;
2355 radeon_wreg_t pll_wreg;
2356 uint32_t pcie_reg_mask;
2357 radeon_rreg_t pciep_rreg;
2358 radeon_wreg_t pciep_wreg;
2359 /* io port */
2360 void __iomem *rio_mem;
2361 resource_size_t rio_mem_size;
2362 struct radeon_clock clock;
2363 struct radeon_mc mc;
2364 struct radeon_gart gart;
2365 struct radeon_mode_info mode_info;
2366 struct radeon_scratch scratch;
2367 struct radeon_doorbell doorbell;
2368 struct radeon_mman mman;
2369 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2370 wait_queue_head_t fence_queue;
2371 u64 fence_context;
2372 struct mutex ring_lock;
2373 struct radeon_ring ring[RADEON_NUM_RINGS];
2374 bool ib_pool_ready;
2375 struct radeon_sa_manager ring_tmp_bo;
2376 struct radeon_irq irq;
2377 struct radeon_asic *asic;
2378 struct radeon_gem gem;
2379 struct radeon_pm pm;
2380 struct radeon_uvd uvd;
2381 struct radeon_vce vce;
2382 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2383 struct radeon_wb wb;
2384 struct radeon_dummy_page dummy_page;
2385 bool shutdown;
2386 bool need_swiotlb;
2387 bool accel_working;
2388 bool fastfb_working; /* IGP feature*/
2389 bool needs_reset, in_reset;
2390 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2391 const struct firmware *me_fw; /* all family ME firmware */
2392 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2393 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2394 const struct firmware *mc_fw; /* NI MC firmware */
2395 const struct firmware *ce_fw; /* SI CE firmware */
2396 const struct firmware *mec_fw; /* CIK MEC firmware */
2397 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2398 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2399 const struct firmware *smc_fw; /* SMC firmware */
2400 const struct firmware *uvd_fw; /* UVD firmware */
2401 const struct firmware *vce_fw; /* VCE firmware */
2402 bool new_fw;
2403 struct r600_vram_scratch vram_scratch;
2404 int msi_enabled; /* msi enabled */
2405 struct r600_ih ih; /* r6/700 interrupt ring */
2406 struct radeon_rlc rlc;
2407 struct radeon_mec mec;
2408 struct delayed_work hotplug_work;
2409 struct work_struct dp_work;
2410 struct work_struct audio_work;
2411 int num_crtc; /* number of crtcs */
2412 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2413 bool has_uvd;
2414 bool has_vce;
2415 struct r600_audio audio; /* audio stuff */
2416 struct notifier_block acpi_nb;
2417 /* only one userspace can use Hyperz features or CMASK at a time */
2418 struct drm_file *hyperz_filp;
2419 struct drm_file *cmask_filp;
2420 /* i2c buses */
2421 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2422 /* virtual memory */
2423 struct radeon_vm_manager vm_manager;
2424 struct mutex gpu_clock_mutex;
2425 /* memory stats */
2426 atomic64_t num_bytes_moved;
2427 atomic_t gpu_reset_counter;
2428 /* ACPI interface */
2429 struct radeon_atif atif;
2430 struct radeon_atcs atcs;
2431 /* srbm instance registers */
2432 struct mutex srbm_mutex;
2433 /* clock, powergating flags */
2434 u32 cg_flags;
2435 u32 pg_flags;
2436
2437 struct dev_pm_domain vga_pm_domain;
2438 bool have_disp_power_ref;
2439 u32 px_quirk_flags;
2440
2441 /* tracking pinned memory */
2442 u64 vram_pin_size;
2443 u64 gart_pin_size;
2444};
2445
2446bool radeon_is_px(struct drm_device *dev);
2447int radeon_device_init(struct radeon_device *rdev,
2448 struct drm_device *ddev,
2449 struct pci_dev *pdev,
2450 uint32_t flags);
2451void radeon_device_fini(struct radeon_device *rdev);
2452int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2453
2454#define RADEON_MIN_MMIO_SIZE 0x10000
2455
2456uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2457void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2458static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2459 bool always_indirect)
2460{
2461 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2462 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2463 return readl(((void __iomem *)rdev->rmmio) + reg);
2464 else
2465 return r100_mm_rreg_slow(rdev, reg);
2466}
2467static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2468 bool always_indirect)
2469{
2470 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2471 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2472 else
2473 r100_mm_wreg_slow(rdev, reg, v);
2474}
2475
2476u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2477void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2478
2479u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2480void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2481
2482/*
2483 * Cast helper
2484 */
2485extern const struct dma_fence_ops radeon_fence_ops;
2486
2487static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2488{
2489 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2490
2491 if (__f->base.ops == &radeon_fence_ops)
2492 return __f;
2493
2494 return NULL;
2495}
2496
2497/*
2498 * Registers read & write functions.
2499 */
2500#define RREG8(reg) readb((rdev->rmmio) + (reg))
2501#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2502#define RREG16(reg) readw((rdev->rmmio) + (reg))
2503#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2504#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2505#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2506#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2507 r100_mm_rreg(rdev, (reg), false))
2508#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2509#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2510#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2511#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2512#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2513#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2514#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2515#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2516#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2517#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2518#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2519#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2520#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2521#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2522#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2523#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2524#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2525#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2526#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2527#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2528#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2529#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2530#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2531#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2532#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2533#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2534#define WREG32_P(reg, val, mask) \
2535 do { \
2536 uint32_t tmp_ = RREG32(reg); \
2537 tmp_ &= (mask); \
2538 tmp_ |= ((val) & ~(mask)); \
2539 WREG32(reg, tmp_); \
2540 } while (0)
2541#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2542#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2543#define WREG32_PLL_P(reg, val, mask) \
2544 do { \
2545 uint32_t tmp_ = RREG32_PLL(reg); \
2546 tmp_ &= (mask); \
2547 tmp_ |= ((val) & ~(mask)); \
2548 WREG32_PLL(reg, tmp_); \
2549 } while (0)
2550#define WREG32_SMC_P(reg, val, mask) \
2551 do { \
2552 uint32_t tmp_ = RREG32_SMC(reg); \
2553 tmp_ &= (mask); \
2554 tmp_ |= ((val) & ~(mask)); \
2555 WREG32_SMC(reg, tmp_); \
2556 } while (0)
2557#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2558#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2559#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2560
2561#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2562#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2563
2564/*
2565 * Indirect registers accessors.
2566 * They used to be inlined, but this increases code size by ~65 kbytes.
2567 * Since each performs a pair of MMIO ops
2568 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2569 * the cost of call+ret is almost negligible. MMIO and locking
2570 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2571 */
2572uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2573void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2574u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2575void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2576u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2577void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2578u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2579void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2580u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2581void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2582u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2583void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2584u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2585void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2586u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2587void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2588
2589void r100_pll_errata_after_index(struct radeon_device *rdev);
2590
2591
2592/*
2593 * ASICs helpers.
2594 */
2595#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2596 (rdev->pdev->device == 0x5969))
2597#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2598 (rdev->family == CHIP_RV200) || \
2599 (rdev->family == CHIP_RS100) || \
2600 (rdev->family == CHIP_RS200) || \
2601 (rdev->family == CHIP_RV250) || \
2602 (rdev->family == CHIP_RV280) || \
2603 (rdev->family == CHIP_RS300))
2604#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2605 (rdev->family == CHIP_RV350) || \
2606 (rdev->family == CHIP_R350) || \
2607 (rdev->family == CHIP_RV380) || \
2608 (rdev->family == CHIP_R420) || \
2609 (rdev->family == CHIP_R423) || \
2610 (rdev->family == CHIP_RV410) || \
2611 (rdev->family == CHIP_RS400) || \
2612 (rdev->family == CHIP_RS480))
2613#define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2614 (rdev->pdev->device == 0x9443) || \
2615 (rdev->pdev->device == 0x944B) || \
2616 (rdev->pdev->device == 0x9506) || \
2617 (rdev->pdev->device == 0x9509) || \
2618 (rdev->pdev->device == 0x950F) || \
2619 (rdev->pdev->device == 0x689C) || \
2620 (rdev->pdev->device == 0x689D))
2621#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2622#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2623 (rdev->family == CHIP_RS690) || \
2624 (rdev->family == CHIP_RS740) || \
2625 (rdev->family >= CHIP_R600))
2626#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2627#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2628#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2629#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2630 (rdev->flags & RADEON_IS_IGP))
2631#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2632#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2633#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2634 (rdev->flags & RADEON_IS_IGP))
2635#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2636#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2637#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2638#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2639#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2640#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2641 (rdev->family == CHIP_MULLINS))
2642
2643#define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2644 (rdev->pdev->device == 0x6850) || \
2645 (rdev->pdev->device == 0x6858) || \
2646 (rdev->pdev->device == 0x6859) || \
2647 (rdev->pdev->device == 0x6840) || \
2648 (rdev->pdev->device == 0x6841) || \
2649 (rdev->pdev->device == 0x6842) || \
2650 (rdev->pdev->device == 0x6843))
2651
2652/*
2653 * BIOS helpers.
2654 */
2655#define RBIOS8(i) (rdev->bios[i])
2656#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2657#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2658
2659int radeon_combios_init(struct radeon_device *rdev);
2660void radeon_combios_fini(struct radeon_device *rdev);
2661int radeon_atombios_init(struct radeon_device *rdev);
2662void radeon_atombios_fini(struct radeon_device *rdev);
2663
2664
2665/*
2666 * RING helpers.
2667 */
2668
2669/**
2670 * radeon_ring_write - write a value to the ring
2671 *
2672 * @ring: radeon_ring structure holding ring information
2673 * @v: dword (dw) value to write
2674 *
2675 * Write a value to the requested ring buffer (all asics).
2676 */
2677static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2678{
2679 if (ring->count_dw <= 0)
2680 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2681
2682 ring->ring[ring->wptr++] = v;
2683 ring->wptr &= ring->ptr_mask;
2684 ring->count_dw--;
2685 ring->ring_free_dw--;
2686}
2687
2688/*
2689 * ASICs macro.
2690 */
2691#define radeon_init(rdev) (rdev)->asic->init((rdev))
2692#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2693#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2694#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2695#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2696#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2697#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2698#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2699#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2700#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2701#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2702#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2703#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2704#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2705#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2706#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2707#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2708#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2709#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2710#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2711#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2712#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2713#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2714#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2715#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2716#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2717#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2718#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2719#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2720#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2721#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2722#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2723#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2724#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2725#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2726#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2727#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2728#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2729#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2730#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2731#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2732#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2733#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2734#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2735#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2736#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2737#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2738#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2739#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2740#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2741#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2742#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2743#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2744#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2745#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2746#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2747#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2748#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2749#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2750#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2751#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2752#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2753#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2754#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2755#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2756#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2757#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2758#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2759#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2760#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2761#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2762#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2763#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2764#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2765#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2766#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2767#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2768#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2769#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2770#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2771#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2772#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2773#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2774#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2775#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2776#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2777#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2778#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2779#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2780#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2781#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2782
2783/* Common functions */
2784/* AGP */
2785extern int radeon_gpu_reset(struct radeon_device *rdev);
2786extern void radeon_pci_config_reset(struct radeon_device *rdev);
2787extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2788extern void radeon_agp_disable(struct radeon_device *rdev);
2789extern int radeon_modeset_init(struct radeon_device *rdev);
2790extern void radeon_modeset_fini(struct radeon_device *rdev);
2791extern bool radeon_card_posted(struct radeon_device *rdev);
2792extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2793extern void radeon_update_display_priority(struct radeon_device *rdev);
2794extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2795extern void radeon_scratch_init(struct radeon_device *rdev);
2796extern void radeon_wb_fini(struct radeon_device *rdev);
2797extern int radeon_wb_init(struct radeon_device *rdev);
2798extern void radeon_wb_disable(struct radeon_device *rdev);
2799extern void radeon_surface_init(struct radeon_device *rdev);
2800extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2801extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2802extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2803extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2804extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2805extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2806 struct ttm_tt *ttm, uint64_t addr,
2807 uint32_t flags);
2808extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2809extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2810bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2811extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2812extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2813extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2814extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2815 bool fbcon, bool freeze);
2816extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2817extern void radeon_program_register_sequence(struct radeon_device *rdev,
2818 const u32 *registers,
2819 const u32 array_size);
2820struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2821
2822/* KMS */
2823
2824u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2825int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2826void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2827
2828/*
2829 * vm
2830 */
2831int radeon_vm_manager_init(struct radeon_device *rdev);
2832void radeon_vm_manager_fini(struct radeon_device *rdev);
2833int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2834void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2835struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2836 struct radeon_vm *vm,
2837 struct list_head *head);
2838struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2839 struct radeon_vm *vm, int ring);
2840void radeon_vm_flush(struct radeon_device *rdev,
2841 struct radeon_vm *vm,
2842 int ring, struct radeon_fence *fence);
2843void radeon_vm_fence(struct radeon_device *rdev,
2844 struct radeon_vm *vm,
2845 struct radeon_fence *fence);
2846uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2847int radeon_vm_update_page_directory(struct radeon_device *rdev,
2848 struct radeon_vm *vm);
2849int radeon_vm_clear_freed(struct radeon_device *rdev,
2850 struct radeon_vm *vm);
2851int radeon_vm_clear_invalids(struct radeon_device *rdev,
2852 struct radeon_vm *vm);
2853int radeon_vm_bo_update(struct radeon_device *rdev,
2854 struct radeon_bo_va *bo_va,
2855 struct ttm_resource *mem);
2856void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2857 struct radeon_bo *bo);
2858struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2859 struct radeon_bo *bo);
2860struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2861 struct radeon_vm *vm,
2862 struct radeon_bo *bo);
2863int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2864 struct radeon_bo_va *bo_va,
2865 uint64_t offset,
2866 uint32_t flags);
2867void radeon_vm_bo_rmv(struct radeon_device *rdev,
2868 struct radeon_bo_va *bo_va);
2869
2870/* audio */
2871void r600_audio_update_hdmi(struct work_struct *work);
2872struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2873struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2874void r600_audio_enable(struct radeon_device *rdev,
2875 struct r600_audio_pin *pin,
2876 u8 enable_mask);
2877void dce6_audio_enable(struct radeon_device *rdev,
2878 struct r600_audio_pin *pin,
2879 u8 enable_mask);
2880
2881/*
2882 * R600 vram scratch functions
2883 */
2884int r600_vram_scratch_init(struct radeon_device *rdev);
2885void r600_vram_scratch_fini(struct radeon_device *rdev);
2886
2887/*
2888 * r600 cs checking helper
2889 */
2890unsigned r600_mip_minify(unsigned size, unsigned level);
2891bool r600_fmt_is_valid_color(u32 format);
2892bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2893int r600_fmt_get_blocksize(u32 format);
2894int r600_fmt_get_nblocksx(u32 format, u32 w);
2895int r600_fmt_get_nblocksy(u32 format, u32 h);
2896
2897/*
2898 * r600 functions used by radeon_encoder.c
2899 */
2900struct radeon_hdmi_acr {
2901 u32 clock;
2902
2903 int n_32khz;
2904 int cts_32khz;
2905
2906 int n_44_1khz;
2907 int cts_44_1khz;
2908
2909 int n_48khz;
2910 int cts_48khz;
2911
2912};
2913
2914extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2915 u32 tiling_pipe_num,
2916 u32 max_rb_num,
2917 u32 total_max_rb_num,
2918 u32 enabled_rb_mask);
2919
2920/*
2921 * evergreen functions used by radeon_encoder.c
2922 */
2923
2924extern int ni_init_microcode(struct radeon_device *rdev);
2925extern int ni_mc_load_microcode(struct radeon_device *rdev);
2926
2927/* radeon_acpi.c */
2928#if defined(CONFIG_ACPI)
2929extern int radeon_acpi_init(struct radeon_device *rdev);
2930extern void radeon_acpi_fini(struct radeon_device *rdev);
2931extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2932extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2933 u8 perf_req, bool advertise);
2934extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2935#else
2936static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2937static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2938#endif
2939
2940int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2941 struct radeon_cs_packet *pkt,
2942 unsigned idx);
2943bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2944void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2945 struct radeon_cs_packet *pkt);
2946int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2947 struct radeon_bo_list **cs_reloc,
2948 int nomm);
2949int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2950 uint32_t *vline_start_end,
2951 uint32_t *vline_status);
2952
2953/* interrupt control register helpers */
2954void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2955 u32 reg, u32 mask,
2956 bool enable, const char *name,
2957 unsigned n);
2958
2959/* Audio component binding */
2960void radeon_audio_component_init(struct radeon_device *rdev);
2961void radeon_audio_component_fini(struct radeon_device *rdev);
2962
2963#include "radeon_object.h"
2964
2965#endif