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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103/* RADEON_IB_POOL_SIZE must be a power of 2 */
104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
107#define RADEON_BIOS_NUM_SCRATCH 8
108
109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
125#define ATRM_BIOS_PAGE 4096
126
127#if defined(CONFIG_VGA_SWITCHEROO)
128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
140bool radeon_get_bios(struct radeon_device *rdev);
141
142
143/*
144 * Dummy page
145 */
146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
153
154/*
155 * Clocks
156 */
157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
168 uint32_t max_pixel_clock;
169};
170
171/*
172 * Power management
173 */
174int radeon_pm_init(struct radeon_device *rdev);
175void radeon_pm_fini(struct radeon_device *rdev);
176void radeon_pm_compute_clocks(struct radeon_device *rdev);
177void radeon_pm_suspend(struct radeon_device *rdev);
178void radeon_pm_resume(struct radeon_device *rdev);
179void radeon_combios_get_power_modes(struct radeon_device *rdev);
180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
183void rs690_pm_info(struct radeon_device *rdev);
184extern int rv6xx_get_temp(struct radeon_device *rdev);
185extern int rv770_get_temp(struct radeon_device *rdev);
186extern int evergreen_get_temp(struct radeon_device *rdev);
187extern int sumo_get_temp(struct radeon_device *rdev);
188
189/*
190 * Fences.
191 */
192struct radeon_fence_driver {
193 uint32_t scratch_reg;
194 atomic_t seq;
195 uint32_t last_seq;
196 unsigned long last_jiffies;
197 unsigned long last_timeout;
198 wait_queue_head_t queue;
199 rwlock_t lock;
200 struct list_head created;
201 struct list_head emited;
202 struct list_head signaled;
203 bool initialized;
204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
212 bool emited;
213 bool signaled;
214};
215
216int radeon_fence_driver_init(struct radeon_device *rdev);
217void radeon_fence_driver_fini(struct radeon_device *rdev);
218int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
219int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
220void radeon_fence_process(struct radeon_device *rdev);
221bool radeon_fence_signaled(struct radeon_fence *fence);
222int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
223int radeon_fence_wait_next(struct radeon_device *rdev);
224int radeon_fence_wait_last(struct radeon_device *rdev);
225struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
226void radeon_fence_unref(struct radeon_fence **fence);
227
228/*
229 * Tiling registers
230 */
231struct radeon_surface_reg {
232 struct radeon_bo *bo;
233};
234
235#define RADEON_GEM_MAX_SURFACES 8
236
237/*
238 * TTM.
239 */
240struct radeon_mman {
241 struct ttm_bo_global_ref bo_global_ref;
242 struct drm_global_reference mem_global_ref;
243 struct ttm_bo_device bdev;
244 bool mem_global_referenced;
245 bool initialized;
246};
247
248struct radeon_bo {
249 /* Protected by gem.mutex */
250 struct list_head list;
251 /* Protected by tbo.reserved */
252 u32 placements[3];
253 struct ttm_placement placement;
254 struct ttm_buffer_object tbo;
255 struct ttm_bo_kmap_obj kmap;
256 unsigned pin_count;
257 void *kptr;
258 u32 tiling_flags;
259 u32 pitch;
260 int surface_reg;
261 /* Constant after initialization */
262 struct radeon_device *rdev;
263 struct drm_gem_object gem_base;
264};
265#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
266
267struct radeon_bo_list {
268 struct ttm_validate_buffer tv;
269 struct radeon_bo *bo;
270 uint64_t gpu_offset;
271 unsigned rdomain;
272 unsigned wdomain;
273 u32 tiling_flags;
274};
275
276/*
277 * GEM objects.
278 */
279struct radeon_gem {
280 struct mutex mutex;
281 struct list_head objects;
282};
283
284int radeon_gem_init(struct radeon_device *rdev);
285void radeon_gem_fini(struct radeon_device *rdev);
286int radeon_gem_object_create(struct radeon_device *rdev, int size,
287 int alignment, int initial_domain,
288 bool discardable, bool kernel,
289 struct drm_gem_object **obj);
290int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
291 uint64_t *gpu_addr);
292void radeon_gem_object_unpin(struct drm_gem_object *obj);
293
294int radeon_mode_dumb_create(struct drm_file *file_priv,
295 struct drm_device *dev,
296 struct drm_mode_create_dumb *args);
297int radeon_mode_dumb_mmap(struct drm_file *filp,
298 struct drm_device *dev,
299 uint32_t handle, uint64_t *offset_p);
300int radeon_mode_dumb_destroy(struct drm_file *file_priv,
301 struct drm_device *dev,
302 uint32_t handle);
303
304/*
305 * GART structures, functions & helpers
306 */
307struct radeon_mc;
308
309struct radeon_gart_table_ram {
310 volatile uint32_t *ptr;
311};
312
313struct radeon_gart_table_vram {
314 struct radeon_bo *robj;
315 volatile uint32_t *ptr;
316};
317
318union radeon_gart_table {
319 struct radeon_gart_table_ram ram;
320 struct radeon_gart_table_vram vram;
321};
322
323#define RADEON_GPU_PAGE_SIZE 4096
324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
325#define RADEON_GPU_PAGE_SHIFT 12
326
327struct radeon_gart {
328 dma_addr_t table_addr;
329 unsigned num_gpu_pages;
330 unsigned num_cpu_pages;
331 unsigned table_size;
332 union radeon_gart_table table;
333 struct page **pages;
334 dma_addr_t *pages_addr;
335 bool *ttm_alloced;
336 bool ready;
337};
338
339int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
340void radeon_gart_table_ram_free(struct radeon_device *rdev);
341int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
342void radeon_gart_table_vram_free(struct radeon_device *rdev);
343int radeon_gart_init(struct radeon_device *rdev);
344void radeon_gart_fini(struct radeon_device *rdev);
345void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
346 int pages);
347int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
348 int pages, struct page **pagelist,
349 dma_addr_t *dma_addr);
350
351
352/*
353 * GPU MC structures, functions & helpers
354 */
355struct radeon_mc {
356 resource_size_t aper_size;
357 resource_size_t aper_base;
358 resource_size_t agp_base;
359 /* for some chips with <= 32MB we need to lie
360 * about vram size near mc fb location */
361 u64 mc_vram_size;
362 u64 visible_vram_size;
363 u64 gtt_size;
364 u64 gtt_start;
365 u64 gtt_end;
366 u64 vram_start;
367 u64 vram_end;
368 unsigned vram_width;
369 u64 real_vram_size;
370 int vram_mtrr;
371 bool vram_is_ddr;
372 bool igp_sideport_enabled;
373 u64 gtt_base_align;
374};
375
376bool radeon_combios_sideport_present(struct radeon_device *rdev);
377bool radeon_atombios_sideport_present(struct radeon_device *rdev);
378
379/*
380 * GPU scratch registers structures, functions & helpers
381 */
382struct radeon_scratch {
383 unsigned num_reg;
384 uint32_t reg_base;
385 bool free[32];
386 uint32_t reg[32];
387};
388
389int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
390void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
391
392
393/*
394 * IRQS.
395 */
396
397struct radeon_unpin_work {
398 struct work_struct work;
399 struct radeon_device *rdev;
400 int crtc_id;
401 struct radeon_fence *fence;
402 struct drm_pending_vblank_event *event;
403 struct radeon_bo *old_rbo;
404 u64 new_crtc_base;
405};
406
407struct r500_irq_stat_regs {
408 u32 disp_int;
409};
410
411struct r600_irq_stat_regs {
412 u32 disp_int;
413 u32 disp_int_cont;
414 u32 disp_int_cont2;
415 u32 d1grph_int;
416 u32 d2grph_int;
417};
418
419struct evergreen_irq_stat_regs {
420 u32 disp_int;
421 u32 disp_int_cont;
422 u32 disp_int_cont2;
423 u32 disp_int_cont3;
424 u32 disp_int_cont4;
425 u32 disp_int_cont5;
426 u32 d1grph_int;
427 u32 d2grph_int;
428 u32 d3grph_int;
429 u32 d4grph_int;
430 u32 d5grph_int;
431 u32 d6grph_int;
432};
433
434union radeon_irq_stat_regs {
435 struct r500_irq_stat_regs r500;
436 struct r600_irq_stat_regs r600;
437 struct evergreen_irq_stat_regs evergreen;
438};
439
440struct radeon_irq {
441 bool installed;
442 bool sw_int;
443 /* FIXME: use a define max crtc rather than hardcode it */
444 bool crtc_vblank_int[6];
445 bool pflip[6];
446 wait_queue_head_t vblank_queue;
447 /* FIXME: use defines for max hpd/dacs */
448 bool hpd[6];
449 bool gui_idle;
450 bool gui_idle_acked;
451 wait_queue_head_t idle_queue;
452 /* FIXME: use defines for max HDMI blocks */
453 bool hdmi[2];
454 spinlock_t sw_lock;
455 int sw_refcount;
456 union radeon_irq_stat_regs stat_regs;
457 spinlock_t pflip_lock[6];
458 int pflip_refcount[6];
459};
460
461int radeon_irq_kms_init(struct radeon_device *rdev);
462void radeon_irq_kms_fini(struct radeon_device *rdev);
463void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
464void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
465void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
466void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
467
468/*
469 * CP & ring.
470 */
471struct radeon_ib {
472 struct list_head list;
473 unsigned idx;
474 uint64_t gpu_addr;
475 struct radeon_fence *fence;
476 uint32_t *ptr;
477 uint32_t length_dw;
478 bool free;
479};
480
481/*
482 * locking -
483 * mutex protects scheduled_ibs, ready, alloc_bm
484 */
485struct radeon_ib_pool {
486 struct mutex mutex;
487 struct radeon_bo *robj;
488 struct list_head bogus_ib;
489 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
490 bool ready;
491 unsigned head_id;
492};
493
494struct radeon_cp {
495 struct radeon_bo *ring_obj;
496 volatile uint32_t *ring;
497 unsigned rptr;
498 unsigned wptr;
499 unsigned wptr_old;
500 unsigned ring_size;
501 unsigned ring_free_dw;
502 int count_dw;
503 uint64_t gpu_addr;
504 uint32_t align_mask;
505 uint32_t ptr_mask;
506 struct mutex mutex;
507 bool ready;
508};
509
510/*
511 * R6xx+ IH ring
512 */
513struct r600_ih {
514 struct radeon_bo *ring_obj;
515 volatile uint32_t *ring;
516 unsigned rptr;
517 unsigned wptr;
518 unsigned wptr_old;
519 unsigned ring_size;
520 uint64_t gpu_addr;
521 uint32_t ptr_mask;
522 spinlock_t lock;
523 bool enabled;
524};
525
526struct r600_blit {
527 struct mutex mutex;
528 struct radeon_bo *shader_obj;
529 u64 shader_gpu_addr;
530 u32 vs_offset, ps_offset;
531 u32 state_offset;
532 u32 state_len;
533 u32 vb_used, vb_total;
534 struct radeon_ib *vb_ib;
535};
536
537int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
538void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
539int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
540int radeon_ib_pool_init(struct radeon_device *rdev);
541void radeon_ib_pool_fini(struct radeon_device *rdev);
542int radeon_ib_test(struct radeon_device *rdev);
543extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
544/* Ring access between begin & end cannot sleep */
545void radeon_ring_free_size(struct radeon_device *rdev);
546int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
547int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
548void radeon_ring_commit(struct radeon_device *rdev);
549void radeon_ring_unlock_commit(struct radeon_device *rdev);
550void radeon_ring_unlock_undo(struct radeon_device *rdev);
551int radeon_ring_test(struct radeon_device *rdev);
552int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
553void radeon_ring_fini(struct radeon_device *rdev);
554
555
556/*
557 * CS.
558 */
559struct radeon_cs_reloc {
560 struct drm_gem_object *gobj;
561 struct radeon_bo *robj;
562 struct radeon_bo_list lobj;
563 uint32_t handle;
564 uint32_t flags;
565};
566
567struct radeon_cs_chunk {
568 uint32_t chunk_id;
569 uint32_t length_dw;
570 int kpage_idx[2];
571 uint32_t *kpage[2];
572 uint32_t *kdata;
573 void __user *user_ptr;
574 int last_copied_page;
575 int last_page_index;
576};
577
578struct radeon_cs_parser {
579 struct device *dev;
580 struct radeon_device *rdev;
581 struct drm_file *filp;
582 /* chunks */
583 unsigned nchunks;
584 struct radeon_cs_chunk *chunks;
585 uint64_t *chunks_array;
586 /* IB */
587 unsigned idx;
588 /* relocations */
589 unsigned nrelocs;
590 struct radeon_cs_reloc *relocs;
591 struct radeon_cs_reloc **relocs_ptr;
592 struct list_head validated;
593 /* indices of various chunks */
594 int chunk_ib_idx;
595 int chunk_relocs_idx;
596 struct radeon_ib *ib;
597 void *track;
598 unsigned family;
599 int parser_error;
600};
601
602extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
603extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
604
605
606static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
607{
608 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 u32 pg_idx, pg_offset;
610 u32 idx_value = 0;
611 int new_page;
612
613 pg_idx = (idx * 4) / PAGE_SIZE;
614 pg_offset = (idx * 4) % PAGE_SIZE;
615
616 if (ibc->kpage_idx[0] == pg_idx)
617 return ibc->kpage[0][pg_offset/4];
618 if (ibc->kpage_idx[1] == pg_idx)
619 return ibc->kpage[1][pg_offset/4];
620
621 new_page = radeon_cs_update_pages(p, pg_idx);
622 if (new_page < 0) {
623 p->parser_error = new_page;
624 return 0;
625 }
626
627 idx_value = ibc->kpage[new_page][pg_offset/4];
628 return idx_value;
629}
630
631struct radeon_cs_packet {
632 unsigned idx;
633 unsigned type;
634 unsigned reg;
635 unsigned opcode;
636 int count;
637 unsigned one_reg_wr;
638};
639
640typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt,
642 unsigned idx, unsigned reg);
643typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
644 struct radeon_cs_packet *pkt);
645
646
647/*
648 * AGP
649 */
650int radeon_agp_init(struct radeon_device *rdev);
651void radeon_agp_resume(struct radeon_device *rdev);
652void radeon_agp_suspend(struct radeon_device *rdev);
653void radeon_agp_fini(struct radeon_device *rdev);
654
655
656/*
657 * Writeback
658 */
659struct radeon_wb {
660 struct radeon_bo *wb_obj;
661 volatile uint32_t *wb;
662 uint64_t gpu_addr;
663 bool enabled;
664 bool use_event;
665};
666
667#define RADEON_WB_SCRATCH_OFFSET 0
668#define RADEON_WB_CP_RPTR_OFFSET 1024
669#define RADEON_WB_CP1_RPTR_OFFSET 1280
670#define RADEON_WB_CP2_RPTR_OFFSET 1536
671#define R600_WB_IH_WPTR_OFFSET 2048
672#define R600_WB_EVENT_OFFSET 3072
673
674/**
675 * struct radeon_pm - power management datas
676 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
677 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
678 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
679 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
680 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
681 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
682 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
683 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
684 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
685 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
686 * @needed_bandwidth: current bandwidth needs
687 *
688 * It keeps track of various data needed to take powermanagement decision.
689 * Bandwidth need is used to determine minimun clock of the GPU and memory.
690 * Equation between gpu/memory clock and available bandwidth is hw dependent
691 * (type of memory, bus size, efficiency, ...)
692 */
693
694enum radeon_pm_method {
695 PM_METHOD_PROFILE,
696 PM_METHOD_DYNPM,
697};
698
699enum radeon_dynpm_state {
700 DYNPM_STATE_DISABLED,
701 DYNPM_STATE_MINIMUM,
702 DYNPM_STATE_PAUSED,
703 DYNPM_STATE_ACTIVE,
704 DYNPM_STATE_SUSPENDED,
705};
706enum radeon_dynpm_action {
707 DYNPM_ACTION_NONE,
708 DYNPM_ACTION_MINIMUM,
709 DYNPM_ACTION_DOWNCLOCK,
710 DYNPM_ACTION_UPCLOCK,
711 DYNPM_ACTION_DEFAULT
712};
713
714enum radeon_voltage_type {
715 VOLTAGE_NONE = 0,
716 VOLTAGE_GPIO,
717 VOLTAGE_VDDC,
718 VOLTAGE_SW
719};
720
721enum radeon_pm_state_type {
722 POWER_STATE_TYPE_DEFAULT,
723 POWER_STATE_TYPE_POWERSAVE,
724 POWER_STATE_TYPE_BATTERY,
725 POWER_STATE_TYPE_BALANCED,
726 POWER_STATE_TYPE_PERFORMANCE,
727};
728
729enum radeon_pm_profile_type {
730 PM_PROFILE_DEFAULT,
731 PM_PROFILE_AUTO,
732 PM_PROFILE_LOW,
733 PM_PROFILE_MID,
734 PM_PROFILE_HIGH,
735};
736
737#define PM_PROFILE_DEFAULT_IDX 0
738#define PM_PROFILE_LOW_SH_IDX 1
739#define PM_PROFILE_MID_SH_IDX 2
740#define PM_PROFILE_HIGH_SH_IDX 3
741#define PM_PROFILE_LOW_MH_IDX 4
742#define PM_PROFILE_MID_MH_IDX 5
743#define PM_PROFILE_HIGH_MH_IDX 6
744#define PM_PROFILE_MAX 7
745
746struct radeon_pm_profile {
747 int dpms_off_ps_idx;
748 int dpms_on_ps_idx;
749 int dpms_off_cm_idx;
750 int dpms_on_cm_idx;
751};
752
753enum radeon_int_thermal_type {
754 THERMAL_TYPE_NONE,
755 THERMAL_TYPE_RV6XX,
756 THERMAL_TYPE_RV770,
757 THERMAL_TYPE_EVERGREEN,
758 THERMAL_TYPE_SUMO,
759 THERMAL_TYPE_NI,
760};
761
762struct radeon_voltage {
763 enum radeon_voltage_type type;
764 /* gpio voltage */
765 struct radeon_gpio_rec gpio;
766 u32 delay; /* delay in usec from voltage drop to sclk change */
767 bool active_high; /* voltage drop is active when bit is high */
768 /* VDDC voltage */
769 u8 vddc_id; /* index into vddc voltage table */
770 u8 vddci_id; /* index into vddci voltage table */
771 bool vddci_enabled;
772 /* r6xx+ sw */
773 u16 voltage;
774 /* evergreen+ vddci */
775 u16 vddci;
776};
777
778/* clock mode flags */
779#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
780
781struct radeon_pm_clock_info {
782 /* memory clock */
783 u32 mclk;
784 /* engine clock */
785 u32 sclk;
786 /* voltage info */
787 struct radeon_voltage voltage;
788 /* standardized clock flags */
789 u32 flags;
790};
791
792/* state flags */
793#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
794
795struct radeon_power_state {
796 enum radeon_pm_state_type type;
797 /* XXX: use a define for num clock modes */
798 struct radeon_pm_clock_info clock_info[8];
799 /* number of valid clock modes in this power state */
800 int num_clock_modes;
801 struct radeon_pm_clock_info *default_clock_mode;
802 /* standardized state flags */
803 u32 flags;
804 u32 misc; /* vbios specific flags */
805 u32 misc2; /* vbios specific flags */
806 int pcie_lanes; /* pcie lanes */
807};
808
809/*
810 * Some modes are overclocked by very low value, accept them
811 */
812#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
813
814struct radeon_pm {
815 struct mutex mutex;
816 u32 active_crtcs;
817 int active_crtc_count;
818 int req_vblank;
819 bool vblank_sync;
820 bool gui_idle;
821 fixed20_12 max_bandwidth;
822 fixed20_12 igp_sideport_mclk;
823 fixed20_12 igp_system_mclk;
824 fixed20_12 igp_ht_link_clk;
825 fixed20_12 igp_ht_link_width;
826 fixed20_12 k8_bandwidth;
827 fixed20_12 sideport_bandwidth;
828 fixed20_12 ht_bandwidth;
829 fixed20_12 core_bandwidth;
830 fixed20_12 sclk;
831 fixed20_12 mclk;
832 fixed20_12 needed_bandwidth;
833 struct radeon_power_state *power_state;
834 /* number of valid power states */
835 int num_power_states;
836 int current_power_state_index;
837 int current_clock_mode_index;
838 int requested_power_state_index;
839 int requested_clock_mode_index;
840 int default_power_state_index;
841 u32 current_sclk;
842 u32 current_mclk;
843 u16 current_vddc;
844 u16 current_vddci;
845 u32 default_sclk;
846 u32 default_mclk;
847 u16 default_vddc;
848 u16 default_vddci;
849 struct radeon_i2c_chan *i2c_bus;
850 /* selected pm method */
851 enum radeon_pm_method pm_method;
852 /* dynpm power management */
853 struct delayed_work dynpm_idle_work;
854 enum radeon_dynpm_state dynpm_state;
855 enum radeon_dynpm_action dynpm_planned_action;
856 unsigned long dynpm_action_timeout;
857 bool dynpm_can_upclock;
858 bool dynpm_can_downclock;
859 /* profile-based power management */
860 enum radeon_pm_profile_type profile;
861 int profile_index;
862 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
863 /* internal thermal controller on rv6xx+ */
864 enum radeon_int_thermal_type int_thermal_type;
865 struct device *int_hwmon_dev;
866};
867
868
869/*
870 * Benchmarking
871 */
872void radeon_benchmark(struct radeon_device *rdev);
873
874
875/*
876 * Testing
877 */
878void radeon_test_moves(struct radeon_device *rdev);
879
880
881/*
882 * Debugfs
883 */
884int radeon_debugfs_add_files(struct radeon_device *rdev,
885 struct drm_info_list *files,
886 unsigned nfiles);
887int radeon_debugfs_fence_init(struct radeon_device *rdev);
888
889
890/*
891 * ASIC specific functions.
892 */
893struct radeon_asic {
894 int (*init)(struct radeon_device *rdev);
895 void (*fini)(struct radeon_device *rdev);
896 int (*resume)(struct radeon_device *rdev);
897 int (*suspend)(struct radeon_device *rdev);
898 void (*vga_set_state)(struct radeon_device *rdev, bool state);
899 bool (*gpu_is_lockup)(struct radeon_device *rdev);
900 int (*asic_reset)(struct radeon_device *rdev);
901 void (*gart_tlb_flush)(struct radeon_device *rdev);
902 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
903 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
904 void (*cp_fini)(struct radeon_device *rdev);
905 void (*cp_disable)(struct radeon_device *rdev);
906 void (*cp_commit)(struct radeon_device *rdev);
907 void (*ring_start)(struct radeon_device *rdev);
908 int (*ring_test)(struct radeon_device *rdev);
909 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
910 int (*irq_set)(struct radeon_device *rdev);
911 int (*irq_process)(struct radeon_device *rdev);
912 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
913 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
914 int (*cs_parse)(struct radeon_cs_parser *p);
915 int (*copy_blit)(struct radeon_device *rdev,
916 uint64_t src_offset,
917 uint64_t dst_offset,
918 unsigned num_gpu_pages,
919 struct radeon_fence *fence);
920 int (*copy_dma)(struct radeon_device *rdev,
921 uint64_t src_offset,
922 uint64_t dst_offset,
923 unsigned num_gpu_pages,
924 struct radeon_fence *fence);
925 int (*copy)(struct radeon_device *rdev,
926 uint64_t src_offset,
927 uint64_t dst_offset,
928 unsigned num_gpu_pages,
929 struct radeon_fence *fence);
930 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
931 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
932 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
933 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
934 int (*get_pcie_lanes)(struct radeon_device *rdev);
935 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
936 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
937 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
938 uint32_t tiling_flags, uint32_t pitch,
939 uint32_t offset, uint32_t obj_size);
940 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
941 void (*bandwidth_update)(struct radeon_device *rdev);
942 void (*hpd_init)(struct radeon_device *rdev);
943 void (*hpd_fini)(struct radeon_device *rdev);
944 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
945 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
946 /* ioctl hw specific callback. Some hw might want to perform special
947 * operation on specific ioctl. For instance on wait idle some hw
948 * might want to perform and HDP flush through MMIO as it seems that
949 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
950 * through ring.
951 */
952 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
953 bool (*gui_idle)(struct radeon_device *rdev);
954 /* power management */
955 void (*pm_misc)(struct radeon_device *rdev);
956 void (*pm_prepare)(struct radeon_device *rdev);
957 void (*pm_finish)(struct radeon_device *rdev);
958 void (*pm_init_profile)(struct radeon_device *rdev);
959 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
960 /* pageflipping */
961 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
962 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
963 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
964};
965
966/*
967 * Asic structures
968 */
969struct r100_gpu_lockup {
970 unsigned long last_jiffies;
971 u32 last_cp_rptr;
972};
973
974struct r100_asic {
975 const unsigned *reg_safe_bm;
976 unsigned reg_safe_bm_size;
977 u32 hdp_cntl;
978 struct r100_gpu_lockup lockup;
979};
980
981struct r300_asic {
982 const unsigned *reg_safe_bm;
983 unsigned reg_safe_bm_size;
984 u32 resync_scratch;
985 u32 hdp_cntl;
986 struct r100_gpu_lockup lockup;
987};
988
989struct r600_asic {
990 unsigned max_pipes;
991 unsigned max_tile_pipes;
992 unsigned max_simds;
993 unsigned max_backends;
994 unsigned max_gprs;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned tiling_nbanks;
1004 unsigned tiling_npipes;
1005 unsigned tiling_group_size;
1006 unsigned tile_config;
1007 unsigned backend_map;
1008 struct r100_gpu_lockup lockup;
1009};
1010
1011struct rv770_asic {
1012 unsigned max_pipes;
1013 unsigned max_tile_pipes;
1014 unsigned max_simds;
1015 unsigned max_backends;
1016 unsigned max_gprs;
1017 unsigned max_threads;
1018 unsigned max_stack_entries;
1019 unsigned max_hw_contexts;
1020 unsigned max_gs_threads;
1021 unsigned sx_max_export_size;
1022 unsigned sx_max_export_pos_size;
1023 unsigned sx_max_export_smx_size;
1024 unsigned sq_num_cf_insts;
1025 unsigned sx_num_of_sets;
1026 unsigned sc_prim_fifo_size;
1027 unsigned sc_hiz_tile_fifo_size;
1028 unsigned sc_earlyz_tile_fifo_fize;
1029 unsigned tiling_nbanks;
1030 unsigned tiling_npipes;
1031 unsigned tiling_group_size;
1032 unsigned tile_config;
1033 unsigned backend_map;
1034 struct r100_gpu_lockup lockup;
1035};
1036
1037struct evergreen_asic {
1038 unsigned num_ses;
1039 unsigned max_pipes;
1040 unsigned max_tile_pipes;
1041 unsigned max_simds;
1042 unsigned max_backends;
1043 unsigned max_gprs;
1044 unsigned max_threads;
1045 unsigned max_stack_entries;
1046 unsigned max_hw_contexts;
1047 unsigned max_gs_threads;
1048 unsigned sx_max_export_size;
1049 unsigned sx_max_export_pos_size;
1050 unsigned sx_max_export_smx_size;
1051 unsigned sq_num_cf_insts;
1052 unsigned sx_num_of_sets;
1053 unsigned sc_prim_fifo_size;
1054 unsigned sc_hiz_tile_fifo_size;
1055 unsigned sc_earlyz_tile_fifo_size;
1056 unsigned tiling_nbanks;
1057 unsigned tiling_npipes;
1058 unsigned tiling_group_size;
1059 unsigned tile_config;
1060 unsigned backend_map;
1061 struct r100_gpu_lockup lockup;
1062};
1063
1064struct cayman_asic {
1065 unsigned max_shader_engines;
1066 unsigned max_pipes_per_simd;
1067 unsigned max_tile_pipes;
1068 unsigned max_simds_per_se;
1069 unsigned max_backends_per_se;
1070 unsigned max_texture_channel_caches;
1071 unsigned max_gprs;
1072 unsigned max_threads;
1073 unsigned max_gs_threads;
1074 unsigned max_stack_entries;
1075 unsigned sx_num_of_sets;
1076 unsigned sx_max_export_size;
1077 unsigned sx_max_export_pos_size;
1078 unsigned sx_max_export_smx_size;
1079 unsigned max_hw_contexts;
1080 unsigned sq_num_cf_insts;
1081 unsigned sc_prim_fifo_size;
1082 unsigned sc_hiz_tile_fifo_size;
1083 unsigned sc_earlyz_tile_fifo_size;
1084
1085 unsigned num_shader_engines;
1086 unsigned num_shader_pipes_per_simd;
1087 unsigned num_tile_pipes;
1088 unsigned num_simds_per_se;
1089 unsigned num_backends_per_se;
1090 unsigned backend_disable_mask_per_asic;
1091 unsigned backend_map;
1092 unsigned num_texture_channel_caches;
1093 unsigned mem_max_burst_length_bytes;
1094 unsigned mem_row_size_in_kb;
1095 unsigned shader_engine_tile_size;
1096 unsigned num_gpus;
1097 unsigned multi_gpu_tile_size;
1098
1099 unsigned tile_config;
1100 struct r100_gpu_lockup lockup;
1101};
1102
1103union radeon_asic_config {
1104 struct r300_asic r300;
1105 struct r100_asic r100;
1106 struct r600_asic r600;
1107 struct rv770_asic rv770;
1108 struct evergreen_asic evergreen;
1109 struct cayman_asic cayman;
1110};
1111
1112/*
1113 * asic initizalization from radeon_asic.c
1114 */
1115void radeon_agp_disable(struct radeon_device *rdev);
1116int radeon_asic_init(struct radeon_device *rdev);
1117
1118
1119/*
1120 * IOCTL.
1121 */
1122int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *filp);
1124int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *filp);
1126int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
1138int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1139 struct drm_file *filp);
1140int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1141 struct drm_file *filp);
1142int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1143int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *filp);
1145int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1146 struct drm_file *filp);
1147
1148/* VRAM scratch page for HDP bug */
1149struct r700_vram_scratch {
1150 struct radeon_bo *robj;
1151 volatile uint32_t *ptr;
1152};
1153
1154/*
1155 * Core structure, functions and helpers.
1156 */
1157typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1158typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1159
1160struct radeon_device {
1161 struct device *dev;
1162 struct drm_device *ddev;
1163 struct pci_dev *pdev;
1164 /* ASIC */
1165 union radeon_asic_config config;
1166 enum radeon_family family;
1167 unsigned long flags;
1168 int usec_timeout;
1169 enum radeon_pll_errata pll_errata;
1170 int num_gb_pipes;
1171 int num_z_pipes;
1172 int disp_priority;
1173 /* BIOS */
1174 uint8_t *bios;
1175 bool is_atom_bios;
1176 uint16_t bios_header_start;
1177 struct radeon_bo *stollen_vga_memory;
1178 /* Register mmio */
1179 resource_size_t rmmio_base;
1180 resource_size_t rmmio_size;
1181 void __iomem *rmmio;
1182 radeon_rreg_t mc_rreg;
1183 radeon_wreg_t mc_wreg;
1184 radeon_rreg_t pll_rreg;
1185 radeon_wreg_t pll_wreg;
1186 uint32_t pcie_reg_mask;
1187 radeon_rreg_t pciep_rreg;
1188 radeon_wreg_t pciep_wreg;
1189 /* io port */
1190 void __iomem *rio_mem;
1191 resource_size_t rio_mem_size;
1192 struct radeon_clock clock;
1193 struct radeon_mc mc;
1194 struct radeon_gart gart;
1195 struct radeon_mode_info mode_info;
1196 struct radeon_scratch scratch;
1197 struct radeon_mman mman;
1198 struct radeon_fence_driver fence_drv;
1199 struct radeon_cp cp;
1200 /* cayman compute rings */
1201 struct radeon_cp cp1;
1202 struct radeon_cp cp2;
1203 struct radeon_ib_pool ib_pool;
1204 struct radeon_irq irq;
1205 struct radeon_asic *asic;
1206 struct radeon_gem gem;
1207 struct radeon_pm pm;
1208 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1209 struct mutex cs_mutex;
1210 struct radeon_wb wb;
1211 struct radeon_dummy_page dummy_page;
1212 bool gpu_lockup;
1213 bool shutdown;
1214 bool suspend;
1215 bool need_dma32;
1216 bool accel_working;
1217 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1218 const struct firmware *me_fw; /* all family ME firmware */
1219 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1220 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1221 const struct firmware *mc_fw; /* NI MC firmware */
1222 struct r600_blit r600_blit;
1223 struct r700_vram_scratch vram_scratch;
1224 int msi_enabled; /* msi enabled */
1225 struct r600_ih ih; /* r6/700 interrupt ring */
1226 struct work_struct hotplug_work;
1227 int num_crtc; /* number of crtcs */
1228 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1229 struct mutex vram_mutex;
1230
1231 /* audio stuff */
1232 bool audio_enabled;
1233 struct timer_list audio_timer;
1234 int audio_channels;
1235 int audio_rate;
1236 int audio_bits_per_sample;
1237 uint8_t audio_status_bits;
1238 uint8_t audio_category_code;
1239
1240 struct notifier_block acpi_nb;
1241 /* only one userspace can use Hyperz features or CMASK at a time */
1242 struct drm_file *hyperz_filp;
1243 struct drm_file *cmask_filp;
1244 /* i2c buses */
1245 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1246};
1247
1248int radeon_device_init(struct radeon_device *rdev,
1249 struct drm_device *ddev,
1250 struct pci_dev *pdev,
1251 uint32_t flags);
1252void radeon_device_fini(struct radeon_device *rdev);
1253int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254
1255static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1256{
1257 if (reg < rdev->rmmio_size)
1258 return readl((rdev->rmmio) + reg);
1259 else {
1260 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261 return readl((rdev->rmmio) + RADEON_MM_DATA);
1262 }
1263}
1264
1265static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266{
1267 if (reg < rdev->rmmio_size)
1268 writel(v, (rdev->rmmio) + reg);
1269 else {
1270 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1272 }
1273}
1274
1275static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276{
1277 if (reg < rdev->rio_mem_size)
1278 return ioread32(rdev->rio_mem + reg);
1279 else {
1280 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282 }
1283}
1284
1285static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286{
1287 if (reg < rdev->rio_mem_size)
1288 iowrite32(v, rdev->rio_mem + reg);
1289 else {
1290 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292 }
1293}
1294
1295/*
1296 * Cast helper
1297 */
1298#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1299
1300/*
1301 * Registers read & write functions.
1302 */
1303#define RREG8(reg) readb((rdev->rmmio) + (reg))
1304#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305#define RREG16(reg) readw((rdev->rmmio) + (reg))
1306#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1307#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1308#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1309#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1310#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1316#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1318#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1320#define WREG32_P(reg, val, mask) \
1321 do { \
1322 uint32_t tmp_ = RREG32(reg); \
1323 tmp_ &= (mask); \
1324 tmp_ |= ((val) & ~(mask)); \
1325 WREG32(reg, tmp_); \
1326 } while (0)
1327#define WREG32_PLL_P(reg, val, mask) \
1328 do { \
1329 uint32_t tmp_ = RREG32_PLL(reg); \
1330 tmp_ &= (mask); \
1331 tmp_ |= ((val) & ~(mask)); \
1332 WREG32_PLL(reg, tmp_); \
1333 } while (0)
1334#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1335#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1337
1338/*
1339 * Indirect registers accessor
1340 */
1341static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342{
1343 uint32_t r;
1344
1345 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346 r = RREG32(RADEON_PCIE_DATA);
1347 return r;
1348}
1349
1350static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351{
1352 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353 WREG32(RADEON_PCIE_DATA, (v));
1354}
1355
1356void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359/*
1360 * ASICs helpers.
1361 */
1362#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363 (rdev->pdev->device == 0x5969))
1364#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365 (rdev->family == CHIP_RV200) || \
1366 (rdev->family == CHIP_RS100) || \
1367 (rdev->family == CHIP_RS200) || \
1368 (rdev->family == CHIP_RV250) || \
1369 (rdev->family == CHIP_RV280) || \
1370 (rdev->family == CHIP_RS300))
1371#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1372 (rdev->family == CHIP_RV350) || \
1373 (rdev->family == CHIP_R350) || \
1374 (rdev->family == CHIP_RV380) || \
1375 (rdev->family == CHIP_R420) || \
1376 (rdev->family == CHIP_R423) || \
1377 (rdev->family == CHIP_RV410) || \
1378 (rdev->family == CHIP_RS400) || \
1379 (rdev->family == CHIP_RS480))
1380#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381 (rdev->ddev->pdev->device == 0x9443) || \
1382 (rdev->ddev->pdev->device == 0x944B) || \
1383 (rdev->ddev->pdev->device == 0x9506) || \
1384 (rdev->ddev->pdev->device == 0x9509) || \
1385 (rdev->ddev->pdev->device == 0x950F) || \
1386 (rdev->ddev->pdev->device == 0x689C) || \
1387 (rdev->ddev->pdev->device == 0x689D))
1388#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1389#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1390 (rdev->family == CHIP_RS690) || \
1391 (rdev->family == CHIP_RS740) || \
1392 (rdev->family >= CHIP_R600))
1393#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1395#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1396#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397 (rdev->flags & RADEON_IS_IGP))
1398#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1399
1400/*
1401 * BIOS helpers.
1402 */
1403#define RBIOS8(i) (rdev->bios[i])
1404#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407int radeon_combios_init(struct radeon_device *rdev);
1408void radeon_combios_fini(struct radeon_device *rdev);
1409int radeon_atombios_init(struct radeon_device *rdev);
1410void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413/*
1414 * RING helpers.
1415 */
1416static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417{
1418#if DRM_DEBUG_CODE
1419 if (rdev->cp.count_dw <= 0) {
1420 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 }
1422#endif
1423 rdev->cp.ring[rdev->cp.wptr++] = v;
1424 rdev->cp.wptr &= rdev->cp.ptr_mask;
1425 rdev->cp.count_dw--;
1426 rdev->cp.ring_free_dw--;
1427}
1428
1429
1430/*
1431 * ASICs macro.
1432 */
1433#define radeon_init(rdev) (rdev)->asic->init((rdev))
1434#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1437#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1438#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1439#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1440#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1441#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1443#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1444#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1445#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1447#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1449#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1450#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1454#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1455#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1456#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1457#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1458#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1459#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1461#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1463#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1464#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1468#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1469#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1472#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1474#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1477
1478/* Common functions */
1479/* AGP */
1480extern int radeon_gpu_reset(struct radeon_device *rdev);
1481extern void radeon_agp_disable(struct radeon_device *rdev);
1482extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1483extern void radeon_gart_restore(struct radeon_device *rdev);
1484extern int radeon_modeset_init(struct radeon_device *rdev);
1485extern void radeon_modeset_fini(struct radeon_device *rdev);
1486extern bool radeon_card_posted(struct radeon_device *rdev);
1487extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1488extern void radeon_update_display_priority(struct radeon_device *rdev);
1489extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1490extern void radeon_scratch_init(struct radeon_device *rdev);
1491extern void radeon_wb_fini(struct radeon_device *rdev);
1492extern int radeon_wb_init(struct radeon_device *rdev);
1493extern void radeon_wb_disable(struct radeon_device *rdev);
1494extern void radeon_surface_init(struct radeon_device *rdev);
1495extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1496extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1497extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1498extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1499extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1500extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1501extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1502extern int radeon_resume_kms(struct drm_device *dev);
1503extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1504extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1505
1506/*
1507 * r600 functions used by radeon_encoder.c
1508 */
1509extern void r600_hdmi_enable(struct drm_encoder *encoder);
1510extern void r600_hdmi_disable(struct drm_encoder *encoder);
1511extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1512
1513extern int ni_init_microcode(struct radeon_device *rdev);
1514extern int ni_mc_load_microcode(struct radeon_device *rdev);
1515
1516/* radeon_acpi.c */
1517#if defined(CONFIG_ACPI)
1518extern int radeon_acpi_init(struct radeon_device *rdev);
1519#else
1520static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521#endif
1522
1523#include "radeon_object.h"
1524
1525#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/agp_backend.h>
64#include <linux/atomic.h>
65#include <linux/wait.h>
66#include <linux/list.h>
67#include <linux/kref.h>
68#include <linux/interval_tree.h>
69#include <linux/hashtable.h>
70#include <linux/dma-fence.h>
71
72#ifdef CONFIG_MMU_NOTIFIER
73#include <linux/mmu_notifier.h>
74#endif
75
76#include <drm/ttm/ttm_bo_api.h>
77#include <drm/ttm/ttm_bo_driver.h>
78#include <drm/ttm/ttm_placement.h>
79#include <drm/ttm/ttm_execbuf_util.h>
80
81#include <drm/drm_gem.h>
82
83#include "radeon_family.h"
84#include "radeon_mode.h"
85#include "radeon_reg.h"
86
87/*
88 * Modules parameters.
89 */
90extern int radeon_no_wb;
91extern int radeon_modeset;
92extern int radeon_dynclks;
93extern int radeon_r4xx_atom;
94extern int radeon_agpmode;
95extern int radeon_vram_limit;
96extern int radeon_gart_size;
97extern int radeon_benchmarking;
98extern int radeon_testing;
99extern int radeon_connector_table;
100extern int radeon_tv;
101extern int radeon_audio;
102extern int radeon_disp_priority;
103extern int radeon_hw_i2c;
104extern int radeon_pcie_gen2;
105extern int radeon_msi;
106extern int radeon_lockup_timeout;
107extern int radeon_fastfb;
108extern int radeon_dpm;
109extern int radeon_aspm;
110extern int radeon_runtime_pm;
111extern int radeon_hard_reset;
112extern int radeon_vm_size;
113extern int radeon_vm_block_size;
114extern int radeon_deep_color;
115extern int radeon_use_pflipirq;
116extern int radeon_bapm;
117extern int radeon_backlight;
118extern int radeon_auxch;
119extern int radeon_mst;
120extern int radeon_uvd;
121extern int radeon_vce;
122extern int radeon_si_support;
123extern int radeon_cik_support;
124
125/*
126 * Copy from radeon_drv.h so we don't have to include both and have conflicting
127 * symbol;
128 */
129#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
130#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
131#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
132/* RADEON_IB_POOL_SIZE must be a power of 2 */
133#define RADEON_IB_POOL_SIZE 16
134#define RADEON_DEBUGFS_MAX_COMPONENTS 32
135#define RADEONFB_CONN_LIMIT 4
136#define RADEON_BIOS_NUM_SCRATCH 8
137
138/* internal ring indices */
139/* r1xx+ has gfx CP ring */
140#define RADEON_RING_TYPE_GFX_INDEX 0
141
142/* cayman has 2 compute CP rings */
143#define CAYMAN_RING_TYPE_CP1_INDEX 1
144#define CAYMAN_RING_TYPE_CP2_INDEX 2
145
146/* R600+ has an async dma ring */
147#define R600_RING_TYPE_DMA_INDEX 3
148/* cayman add a second async dma ring */
149#define CAYMAN_RING_TYPE_DMA1_INDEX 4
150
151/* R600+ */
152#define R600_RING_TYPE_UVD_INDEX 5
153
154/* TN+ */
155#define TN_RING_TYPE_VCE1_INDEX 6
156#define TN_RING_TYPE_VCE2_INDEX 7
157
158/* max number of rings */
159#define RADEON_NUM_RINGS 8
160
161/* number of hw syncs before falling back on blocking */
162#define RADEON_NUM_SYNCS 4
163
164/* hardcode those limit for now */
165#define RADEON_VA_IB_OFFSET (1 << 20)
166#define RADEON_VA_RESERVED_SIZE (8 << 20)
167#define RADEON_IB_VM_MAX_SIZE (64 << 10)
168
169/* hard reset data */
170#define RADEON_ASIC_RESET_DATA 0x39d5e86b
171
172/* reset flags */
173#define RADEON_RESET_GFX (1 << 0)
174#define RADEON_RESET_COMPUTE (1 << 1)
175#define RADEON_RESET_DMA (1 << 2)
176#define RADEON_RESET_CP (1 << 3)
177#define RADEON_RESET_GRBM (1 << 4)
178#define RADEON_RESET_DMA1 (1 << 5)
179#define RADEON_RESET_RLC (1 << 6)
180#define RADEON_RESET_SEM (1 << 7)
181#define RADEON_RESET_IH (1 << 8)
182#define RADEON_RESET_VMC (1 << 9)
183#define RADEON_RESET_MC (1 << 10)
184#define RADEON_RESET_DISPLAY (1 << 11)
185
186/* CG block flags */
187#define RADEON_CG_BLOCK_GFX (1 << 0)
188#define RADEON_CG_BLOCK_MC (1 << 1)
189#define RADEON_CG_BLOCK_SDMA (1 << 2)
190#define RADEON_CG_BLOCK_UVD (1 << 3)
191#define RADEON_CG_BLOCK_VCE (1 << 4)
192#define RADEON_CG_BLOCK_HDP (1 << 5)
193#define RADEON_CG_BLOCK_BIF (1 << 6)
194
195/* CG flags */
196#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
197#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
198#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
199#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
200#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
201#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
202#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
203#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
204#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
205#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
206#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
207#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
208#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
209#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
210#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
211#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
212#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
213
214/* PG flags */
215#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
216#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
217#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
218#define RADEON_PG_SUPPORT_UVD (1 << 3)
219#define RADEON_PG_SUPPORT_VCE (1 << 4)
220#define RADEON_PG_SUPPORT_CP (1 << 5)
221#define RADEON_PG_SUPPORT_GDS (1 << 6)
222#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
223#define RADEON_PG_SUPPORT_SDMA (1 << 8)
224#define RADEON_PG_SUPPORT_ACP (1 << 9)
225#define RADEON_PG_SUPPORT_SAMU (1 << 10)
226
227/* max cursor sizes (in pixels) */
228#define CURSOR_WIDTH 64
229#define CURSOR_HEIGHT 64
230
231#define CIK_CURSOR_WIDTH 128
232#define CIK_CURSOR_HEIGHT 128
233
234/*
235 * Errata workarounds.
236 */
237enum radeon_pll_errata {
238 CHIP_ERRATA_R300_CG = 0x00000001,
239 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
240 CHIP_ERRATA_PLL_DELAY = 0x00000004
241};
242
243
244struct radeon_device;
245
246
247/*
248 * BIOS.
249 */
250bool radeon_get_bios(struct radeon_device *rdev);
251
252/*
253 * Dummy page
254 */
255struct radeon_dummy_page {
256 uint64_t entry;
257 struct page *page;
258 dma_addr_t addr;
259};
260int radeon_dummy_page_init(struct radeon_device *rdev);
261void radeon_dummy_page_fini(struct radeon_device *rdev);
262
263
264/*
265 * Clocks
266 */
267struct radeon_clock {
268 struct radeon_pll p1pll;
269 struct radeon_pll p2pll;
270 struct radeon_pll dcpll;
271 struct radeon_pll spll;
272 struct radeon_pll mpll;
273 /* 10 Khz units */
274 uint32_t default_mclk;
275 uint32_t default_sclk;
276 uint32_t default_dispclk;
277 uint32_t current_dispclk;
278 uint32_t dp_extclk;
279 uint32_t max_pixel_clock;
280 uint32_t vco_freq;
281};
282
283/*
284 * Power management
285 */
286int radeon_pm_init(struct radeon_device *rdev);
287int radeon_pm_late_init(struct radeon_device *rdev);
288void radeon_pm_fini(struct radeon_device *rdev);
289void radeon_pm_compute_clocks(struct radeon_device *rdev);
290void radeon_pm_suspend(struct radeon_device *rdev);
291void radeon_pm_resume(struct radeon_device *rdev);
292void radeon_combios_get_power_modes(struct radeon_device *rdev);
293void radeon_atombios_get_power_modes(struct radeon_device *rdev);
294int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
295 u8 clock_type,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_clock_dividers *dividers);
299int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
300 u32 clock,
301 bool strobe_mode,
302 struct atom_mpll_param *mpll_param);
303void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
304int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
305 u16 voltage_level, u8 voltage_type,
306 u32 *gpio_value, u32 *gpio_mask);
307void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
308 u32 eng_clock, u32 mem_clock);
309int radeon_atom_get_voltage_step(struct radeon_device *rdev,
310 u8 voltage_type, u16 *voltage_step);
311int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
312 u16 voltage_id, u16 *voltage);
313int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
314 u16 *voltage,
315 u16 leakage_idx);
316int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
317 u16 *leakage_id);
318int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
319 u16 *vddc, u16 *vddci,
320 u16 virtual_voltage_id,
321 u16 vbios_voltage_id);
322int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
323 u16 virtual_voltage_id,
324 u16 *voltage);
325int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
326 u8 voltage_type,
327 u16 nominal_voltage,
328 u16 *true_voltage);
329int radeon_atom_get_min_voltage(struct radeon_device *rdev,
330 u8 voltage_type, u16 *min_voltage);
331int radeon_atom_get_max_voltage(struct radeon_device *rdev,
332 u8 voltage_type, u16 *max_voltage);
333int radeon_atom_get_voltage_table(struct radeon_device *rdev,
334 u8 voltage_type, u8 voltage_mode,
335 struct atom_voltage_table *voltage_table);
336bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
337 u8 voltage_type, u8 voltage_mode);
338int radeon_atom_get_svi2_info(struct radeon_device *rdev,
339 u8 voltage_type,
340 u8 *svd_gpio_id, u8 *svc_gpio_id);
341void radeon_atom_update_memory_dll(struct radeon_device *rdev,
342 u32 mem_clock);
343void radeon_atom_set_ac_timing(struct radeon_device *rdev,
344 u32 mem_clock);
345int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
346 u8 module_index,
347 struct atom_mc_reg_table *reg_table);
348int radeon_atom_get_memory_info(struct radeon_device *rdev,
349 u8 module_index, struct atom_memory_info *mem_info);
350int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
351 bool gddr5, u8 module_index,
352 struct atom_memory_clock_range_table *mclk_range_table);
353int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
354 u16 voltage_id, u16 *voltage);
355void rs690_pm_info(struct radeon_device *rdev);
356extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
357 unsigned *bankh, unsigned *mtaspect,
358 unsigned *tile_split);
359
360/*
361 * Fences.
362 */
363struct radeon_fence_driver {
364 struct radeon_device *rdev;
365 uint32_t scratch_reg;
366 uint64_t gpu_addr;
367 volatile uint32_t *cpu_addr;
368 /* sync_seq is protected by ring emission lock */
369 uint64_t sync_seq[RADEON_NUM_RINGS];
370 atomic64_t last_seq;
371 bool initialized, delayed_irq;
372 struct delayed_work lockup_work;
373};
374
375struct radeon_fence {
376 struct dma_fence base;
377
378 struct radeon_device *rdev;
379 uint64_t seq;
380 /* RB, DMA, etc. */
381 unsigned ring;
382 bool is_vm_update;
383
384 wait_queue_entry_t fence_wake;
385};
386
387int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
388void radeon_fence_driver_init(struct radeon_device *rdev);
389void radeon_fence_driver_fini(struct radeon_device *rdev);
390void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
391int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
392void radeon_fence_process(struct radeon_device *rdev, int ring);
393bool radeon_fence_signaled(struct radeon_fence *fence);
394long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
395int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
396int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
397int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
398int radeon_fence_wait_any(struct radeon_device *rdev,
399 struct radeon_fence **fences,
400 bool intr);
401struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
402void radeon_fence_unref(struct radeon_fence **fence);
403unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
404bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
405void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
406static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
407 struct radeon_fence *b)
408{
409 if (!a) {
410 return b;
411 }
412
413 if (!b) {
414 return a;
415 }
416
417 BUG_ON(a->ring != b->ring);
418
419 if (a->seq > b->seq) {
420 return a;
421 } else {
422 return b;
423 }
424}
425
426static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
427 struct radeon_fence *b)
428{
429 if (!a) {
430 return false;
431 }
432
433 if (!b) {
434 return true;
435 }
436
437 BUG_ON(a->ring != b->ring);
438
439 return a->seq < b->seq;
440}
441
442/*
443 * Tiling registers
444 */
445struct radeon_surface_reg {
446 struct radeon_bo *bo;
447};
448
449#define RADEON_GEM_MAX_SURFACES 8
450
451/*
452 * TTM.
453 */
454struct radeon_mman {
455 struct ttm_device bdev;
456 bool initialized;
457};
458
459struct radeon_bo_list {
460 struct radeon_bo *robj;
461 struct ttm_validate_buffer tv;
462 uint64_t gpu_offset;
463 unsigned preferred_domains;
464 unsigned allowed_domains;
465 uint32_t tiling_flags;
466};
467
468/* bo virtual address in a specific vm */
469struct radeon_bo_va {
470 /* protected by bo being reserved */
471 struct list_head bo_list;
472 uint32_t flags;
473 struct radeon_fence *last_pt_update;
474 unsigned ref_count;
475
476 /* protected by vm mutex */
477 struct interval_tree_node it;
478 struct list_head vm_status;
479
480 /* constant after initialization */
481 struct radeon_vm *vm;
482 struct radeon_bo *bo;
483};
484
485struct radeon_bo {
486 /* Protected by gem.mutex */
487 struct list_head list;
488 /* Protected by tbo.reserved */
489 u32 initial_domain;
490 struct ttm_place placements[4];
491 struct ttm_placement placement;
492 struct ttm_buffer_object tbo;
493 struct ttm_bo_kmap_obj kmap;
494 u32 flags;
495 void *kptr;
496 u32 tiling_flags;
497 u32 pitch;
498 int surface_reg;
499 unsigned prime_shared_count;
500 /* list of all virtual address to which this bo
501 * is associated to
502 */
503 struct list_head va;
504 /* Constant after initialization */
505 struct radeon_device *rdev;
506
507 pid_t pid;
508
509#ifdef CONFIG_MMU_NOTIFIER
510 struct mmu_interval_notifier notifier;
511#endif
512};
513#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
514
515/* sub-allocation manager, it has to be protected by another lock.
516 * By conception this is an helper for other part of the driver
517 * like the indirect buffer or semaphore, which both have their
518 * locking.
519 *
520 * Principe is simple, we keep a list of sub allocation in offset
521 * order (first entry has offset == 0, last entry has the highest
522 * offset).
523 *
524 * When allocating new object we first check if there is room at
525 * the end total_size - (last_object_offset + last_object_size) >=
526 * alloc_size. If so we allocate new object there.
527 *
528 * When there is not enough room at the end, we start waiting for
529 * each sub object until we reach object_offset+object_size >=
530 * alloc_size, this object then become the sub object we return.
531 *
532 * Alignment can't be bigger than page size.
533 *
534 * Hole are not considered for allocation to keep things simple.
535 * Assumption is that there won't be hole (all object on same
536 * alignment).
537 */
538struct radeon_sa_manager {
539 wait_queue_head_t wq;
540 struct radeon_bo *bo;
541 struct list_head *hole;
542 struct list_head flist[RADEON_NUM_RINGS];
543 struct list_head olist;
544 unsigned size;
545 uint64_t gpu_addr;
546 void *cpu_ptr;
547 uint32_t domain;
548 uint32_t align;
549};
550
551struct radeon_sa_bo;
552
553/* sub-allocation buffer */
554struct radeon_sa_bo {
555 struct list_head olist;
556 struct list_head flist;
557 struct radeon_sa_manager *manager;
558 unsigned soffset;
559 unsigned eoffset;
560 struct radeon_fence *fence;
561};
562
563/*
564 * GEM objects.
565 */
566struct radeon_gem {
567 struct mutex mutex;
568 struct list_head objects;
569};
570
571extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
572
573int radeon_gem_init(struct radeon_device *rdev);
574void radeon_gem_fini(struct radeon_device *rdev);
575int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
576 int alignment, int initial_domain,
577 u32 flags, bool kernel,
578 struct drm_gem_object **obj);
579
580int radeon_mode_dumb_create(struct drm_file *file_priv,
581 struct drm_device *dev,
582 struct drm_mode_create_dumb *args);
583int radeon_mode_dumb_mmap(struct drm_file *filp,
584 struct drm_device *dev,
585 uint32_t handle, uint64_t *offset_p);
586
587/*
588 * Semaphores.
589 */
590struct radeon_semaphore {
591 struct radeon_sa_bo *sa_bo;
592 signed waiters;
593 uint64_t gpu_addr;
594};
595
596int radeon_semaphore_create(struct radeon_device *rdev,
597 struct radeon_semaphore **semaphore);
598bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
599 struct radeon_semaphore *semaphore);
600bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
601 struct radeon_semaphore *semaphore);
602void radeon_semaphore_free(struct radeon_device *rdev,
603 struct radeon_semaphore **semaphore,
604 struct radeon_fence *fence);
605
606/*
607 * Synchronization
608 */
609struct radeon_sync {
610 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
611 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
612 struct radeon_fence *last_vm_update;
613};
614
615void radeon_sync_create(struct radeon_sync *sync);
616void radeon_sync_fence(struct radeon_sync *sync,
617 struct radeon_fence *fence);
618int radeon_sync_resv(struct radeon_device *rdev,
619 struct radeon_sync *sync,
620 struct dma_resv *resv,
621 bool shared);
622int radeon_sync_rings(struct radeon_device *rdev,
623 struct radeon_sync *sync,
624 int waiting_ring);
625void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
626 struct radeon_fence *fence);
627
628/*
629 * GART structures, functions & helpers
630 */
631struct radeon_mc;
632
633#define RADEON_GPU_PAGE_SIZE 4096
634#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
635#define RADEON_GPU_PAGE_SHIFT 12
636#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
637
638#define RADEON_GART_PAGE_DUMMY 0
639#define RADEON_GART_PAGE_VALID (1 << 0)
640#define RADEON_GART_PAGE_READ (1 << 1)
641#define RADEON_GART_PAGE_WRITE (1 << 2)
642#define RADEON_GART_PAGE_SNOOP (1 << 3)
643
644struct radeon_gart {
645 dma_addr_t table_addr;
646 struct radeon_bo *robj;
647 void *ptr;
648 unsigned num_gpu_pages;
649 unsigned num_cpu_pages;
650 unsigned table_size;
651 struct page **pages;
652 uint64_t *pages_entry;
653 bool ready;
654};
655
656int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
657void radeon_gart_table_ram_free(struct radeon_device *rdev);
658int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
659void radeon_gart_table_vram_free(struct radeon_device *rdev);
660int radeon_gart_table_vram_pin(struct radeon_device *rdev);
661void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
662int radeon_gart_init(struct radeon_device *rdev);
663void radeon_gart_fini(struct radeon_device *rdev);
664void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
665 int pages);
666int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
667 int pages, struct page **pagelist,
668 dma_addr_t *dma_addr, uint32_t flags);
669
670
671/*
672 * GPU MC structures, functions & helpers
673 */
674struct radeon_mc {
675 resource_size_t aper_size;
676 resource_size_t aper_base;
677 resource_size_t agp_base;
678 /* for some chips with <= 32MB we need to lie
679 * about vram size near mc fb location */
680 u64 mc_vram_size;
681 u64 visible_vram_size;
682 u64 gtt_size;
683 u64 gtt_start;
684 u64 gtt_end;
685 u64 vram_start;
686 u64 vram_end;
687 unsigned vram_width;
688 u64 real_vram_size;
689 int vram_mtrr;
690 bool vram_is_ddr;
691 bool igp_sideport_enabled;
692 u64 gtt_base_align;
693 u64 mc_mask;
694};
695
696bool radeon_combios_sideport_present(struct radeon_device *rdev);
697bool radeon_atombios_sideport_present(struct radeon_device *rdev);
698
699/*
700 * GPU scratch registers structures, functions & helpers
701 */
702struct radeon_scratch {
703 unsigned num_reg;
704 uint32_t reg_base;
705 bool free[32];
706 uint32_t reg[32];
707};
708
709int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
710void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
711
712/*
713 * GPU doorbell structures, functions & helpers
714 */
715#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
716
717struct radeon_doorbell {
718 /* doorbell mmio */
719 resource_size_t base;
720 resource_size_t size;
721 u32 __iomem *ptr;
722 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
723 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
724};
725
726int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
727void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
728
729/*
730 * IRQS.
731 */
732
733struct radeon_flip_work {
734 struct work_struct flip_work;
735 struct work_struct unpin_work;
736 struct radeon_device *rdev;
737 int crtc_id;
738 u32 target_vblank;
739 uint64_t base;
740 struct drm_pending_vblank_event *event;
741 struct radeon_bo *old_rbo;
742 struct dma_fence *fence;
743 bool async;
744};
745
746struct r500_irq_stat_regs {
747 u32 disp_int;
748 u32 hdmi0_status;
749};
750
751struct r600_irq_stat_regs {
752 u32 disp_int;
753 u32 disp_int_cont;
754 u32 disp_int_cont2;
755 u32 d1grph_int;
756 u32 d2grph_int;
757 u32 hdmi0_status;
758 u32 hdmi1_status;
759};
760
761struct evergreen_irq_stat_regs {
762 u32 disp_int[6];
763 u32 grph_int[6];
764 u32 afmt_status[6];
765};
766
767struct cik_irq_stat_regs {
768 u32 disp_int;
769 u32 disp_int_cont;
770 u32 disp_int_cont2;
771 u32 disp_int_cont3;
772 u32 disp_int_cont4;
773 u32 disp_int_cont5;
774 u32 disp_int_cont6;
775 u32 d1grph_int;
776 u32 d2grph_int;
777 u32 d3grph_int;
778 u32 d4grph_int;
779 u32 d5grph_int;
780 u32 d6grph_int;
781};
782
783union radeon_irq_stat_regs {
784 struct r500_irq_stat_regs r500;
785 struct r600_irq_stat_regs r600;
786 struct evergreen_irq_stat_regs evergreen;
787 struct cik_irq_stat_regs cik;
788};
789
790struct radeon_irq {
791 bool installed;
792 spinlock_t lock;
793 atomic_t ring_int[RADEON_NUM_RINGS];
794 bool crtc_vblank_int[RADEON_MAX_CRTCS];
795 atomic_t pflip[RADEON_MAX_CRTCS];
796 wait_queue_head_t vblank_queue;
797 bool hpd[RADEON_MAX_HPD_PINS];
798 bool afmt[RADEON_MAX_AFMT_BLOCKS];
799 union radeon_irq_stat_regs stat_regs;
800 bool dpm_thermal;
801};
802
803int radeon_irq_kms_init(struct radeon_device *rdev);
804void radeon_irq_kms_fini(struct radeon_device *rdev);
805void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
806bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
807void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
808void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
809void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
810void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
811void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
812void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
813void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
814
815/*
816 * CP & rings.
817 */
818
819struct radeon_ib {
820 struct radeon_sa_bo *sa_bo;
821 uint32_t length_dw;
822 uint64_t gpu_addr;
823 uint32_t *ptr;
824 int ring;
825 struct radeon_fence *fence;
826 struct radeon_vm *vm;
827 bool is_const_ib;
828 struct radeon_sync sync;
829};
830
831struct radeon_ring {
832 struct radeon_device *rdev;
833 struct radeon_bo *ring_obj;
834 volatile uint32_t *ring;
835 unsigned rptr_offs;
836 unsigned rptr_save_reg;
837 u64 next_rptr_gpu_addr;
838 volatile u32 *next_rptr_cpu_addr;
839 unsigned wptr;
840 unsigned wptr_old;
841 unsigned ring_size;
842 unsigned ring_free_dw;
843 int count_dw;
844 atomic_t last_rptr;
845 atomic64_t last_activity;
846 uint64_t gpu_addr;
847 uint32_t align_mask;
848 uint32_t ptr_mask;
849 bool ready;
850 u32 nop;
851 u32 idx;
852 u64 last_semaphore_signal_addr;
853 u64 last_semaphore_wait_addr;
854 /* for CIK queues */
855 u32 me;
856 u32 pipe;
857 u32 queue;
858 struct radeon_bo *mqd_obj;
859 u32 doorbell_index;
860 unsigned wptr_offs;
861};
862
863struct radeon_mec {
864 struct radeon_bo *hpd_eop_obj;
865 u64 hpd_eop_gpu_addr;
866 u32 num_pipe;
867 u32 num_mec;
868 u32 num_queue;
869};
870
871/*
872 * VM
873 */
874
875/* maximum number of VMIDs */
876#define RADEON_NUM_VM 16
877
878/* number of entries in page table */
879#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
880
881/* PTBs (Page Table Blocks) need to be aligned to 32K */
882#define RADEON_VM_PTB_ALIGN_SIZE 32768
883#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
884#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
885
886#define R600_PTE_VALID (1 << 0)
887#define R600_PTE_SYSTEM (1 << 1)
888#define R600_PTE_SNOOPED (1 << 2)
889#define R600_PTE_READABLE (1 << 5)
890#define R600_PTE_WRITEABLE (1 << 6)
891
892/* PTE (Page Table Entry) fragment field for different page sizes */
893#define R600_PTE_FRAG_4KB (0 << 7)
894#define R600_PTE_FRAG_64KB (4 << 7)
895#define R600_PTE_FRAG_256KB (6 << 7)
896
897/* flags needed to be set so we can copy directly from the GART table */
898#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
899 R600_PTE_SYSTEM | R600_PTE_VALID )
900
901struct radeon_vm_pt {
902 struct radeon_bo *bo;
903 uint64_t addr;
904};
905
906struct radeon_vm_id {
907 unsigned id;
908 uint64_t pd_gpu_addr;
909 /* last flushed PD/PT update */
910 struct radeon_fence *flushed_updates;
911 /* last use of vmid */
912 struct radeon_fence *last_id_use;
913};
914
915struct radeon_vm {
916 struct mutex mutex;
917
918 struct rb_root_cached va;
919
920 /* protecting invalidated and freed */
921 spinlock_t status_lock;
922
923 /* BOs moved, but not yet updated in the PT */
924 struct list_head invalidated;
925
926 /* BOs freed, but not yet updated in the PT */
927 struct list_head freed;
928
929 /* BOs cleared in the PT */
930 struct list_head cleared;
931
932 /* contains the page directory */
933 struct radeon_bo *page_directory;
934 unsigned max_pde_used;
935
936 /* array of page tables, one for each page directory entry */
937 struct radeon_vm_pt *page_tables;
938
939 struct radeon_bo_va *ib_bo_va;
940
941 /* for id and flush management per ring */
942 struct radeon_vm_id ids[RADEON_NUM_RINGS];
943};
944
945struct radeon_vm_manager {
946 struct radeon_fence *active[RADEON_NUM_VM];
947 uint32_t max_pfn;
948 /* number of VMIDs */
949 unsigned nvm;
950 /* vram base address for page table entry */
951 u64 vram_base_offset;
952 /* is vm enabled? */
953 bool enabled;
954 /* for hw to save the PD addr on suspend/resume */
955 uint32_t saved_table_addr[RADEON_NUM_VM];
956};
957
958/*
959 * file private structure
960 */
961struct radeon_fpriv {
962 struct radeon_vm vm;
963};
964
965/*
966 * R6xx+ IH ring
967 */
968struct r600_ih {
969 struct radeon_bo *ring_obj;
970 volatile uint32_t *ring;
971 unsigned rptr;
972 unsigned ring_size;
973 uint64_t gpu_addr;
974 uint32_t ptr_mask;
975 atomic_t lock;
976 bool enabled;
977};
978
979/*
980 * RLC stuff
981 */
982#include "clearstate_defs.h"
983
984struct radeon_rlc {
985 /* for power gating */
986 struct radeon_bo *save_restore_obj;
987 uint64_t save_restore_gpu_addr;
988 volatile uint32_t *sr_ptr;
989 const u32 *reg_list;
990 u32 reg_list_size;
991 /* for clear state */
992 struct radeon_bo *clear_state_obj;
993 uint64_t clear_state_gpu_addr;
994 volatile uint32_t *cs_ptr;
995 const struct cs_section_def *cs_data;
996 u32 clear_state_size;
997 /* for cp tables */
998 struct radeon_bo *cp_table_obj;
999 uint64_t cp_table_gpu_addr;
1000 volatile uint32_t *cp_table_ptr;
1001 u32 cp_table_size;
1002};
1003
1004int radeon_ib_get(struct radeon_device *rdev, int ring,
1005 struct radeon_ib *ib, struct radeon_vm *vm,
1006 unsigned size);
1007void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1008int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1009 struct radeon_ib *const_ib, bool hdp_flush);
1010int radeon_ib_pool_init(struct radeon_device *rdev);
1011void radeon_ib_pool_fini(struct radeon_device *rdev);
1012int radeon_ib_ring_tests(struct radeon_device *rdev);
1013/* Ring access between begin & end cannot sleep */
1014bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1015 struct radeon_ring *ring);
1016void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1017int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1018int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1019void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1020 bool hdp_flush);
1021void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1022 bool hdp_flush);
1023void radeon_ring_undo(struct radeon_ring *ring);
1024void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1025int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1026void radeon_ring_lockup_update(struct radeon_device *rdev,
1027 struct radeon_ring *ring);
1028bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1029unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1030 uint32_t **data);
1031int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1032 unsigned size, uint32_t *data);
1033int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1034 unsigned rptr_offs, u32 nop);
1035void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1036
1037
1038/* r600 async dma */
1039void r600_dma_stop(struct radeon_device *rdev);
1040int r600_dma_resume(struct radeon_device *rdev);
1041void r600_dma_fini(struct radeon_device *rdev);
1042
1043void cayman_dma_stop(struct radeon_device *rdev);
1044int cayman_dma_resume(struct radeon_device *rdev);
1045void cayman_dma_fini(struct radeon_device *rdev);
1046
1047/*
1048 * CS.
1049 */
1050struct radeon_cs_chunk {
1051 uint32_t length_dw;
1052 uint32_t *kdata;
1053 void __user *user_ptr;
1054};
1055
1056struct radeon_cs_parser {
1057 struct device *dev;
1058 struct radeon_device *rdev;
1059 struct drm_file *filp;
1060 /* chunks */
1061 unsigned nchunks;
1062 struct radeon_cs_chunk *chunks;
1063 uint64_t *chunks_array;
1064 /* IB */
1065 unsigned idx;
1066 /* relocations */
1067 unsigned nrelocs;
1068 struct radeon_bo_list *relocs;
1069 struct radeon_bo_list *vm_bos;
1070 struct list_head validated;
1071 unsigned dma_reloc_idx;
1072 /* indices of various chunks */
1073 struct radeon_cs_chunk *chunk_ib;
1074 struct radeon_cs_chunk *chunk_relocs;
1075 struct radeon_cs_chunk *chunk_flags;
1076 struct radeon_cs_chunk *chunk_const_ib;
1077 struct radeon_ib ib;
1078 struct radeon_ib const_ib;
1079 void *track;
1080 unsigned family;
1081 int parser_error;
1082 u32 cs_flags;
1083 u32 ring;
1084 s32 priority;
1085 struct ww_acquire_ctx ticket;
1086};
1087
1088static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1089{
1090 struct radeon_cs_chunk *ibc = p->chunk_ib;
1091
1092 if (ibc->kdata)
1093 return ibc->kdata[idx];
1094 return p->ib.ptr[idx];
1095}
1096
1097
1098struct radeon_cs_packet {
1099 unsigned idx;
1100 unsigned type;
1101 unsigned reg;
1102 unsigned opcode;
1103 int count;
1104 unsigned one_reg_wr;
1105};
1106
1107typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1108 struct radeon_cs_packet *pkt,
1109 unsigned idx, unsigned reg);
1110
1111/*
1112 * AGP
1113 */
1114
1115struct radeon_agp_mode {
1116 unsigned long mode; /**< AGP mode */
1117};
1118
1119struct radeon_agp_info {
1120 int agp_version_major;
1121 int agp_version_minor;
1122 unsigned long mode;
1123 unsigned long aperture_base; /* physical address */
1124 unsigned long aperture_size; /* bytes */
1125 unsigned long memory_allowed; /* bytes */
1126 unsigned long memory_used;
1127
1128 /* PCI information */
1129 unsigned short id_vendor;
1130 unsigned short id_device;
1131};
1132
1133struct radeon_agp_head {
1134 struct agp_kern_info agp_info;
1135 struct list_head memory;
1136 unsigned long mode;
1137 struct agp_bridge_data *bridge;
1138 int enabled;
1139 int acquired;
1140 unsigned long base;
1141 int agp_mtrr;
1142 int cant_use_aperture;
1143 unsigned long page_mask;
1144};
1145
1146#if IS_ENABLED(CONFIG_AGP)
1147struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1148#else
1149static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1150{
1151 return NULL;
1152}
1153#endif
1154int radeon_agp_init(struct radeon_device *rdev);
1155void radeon_agp_resume(struct radeon_device *rdev);
1156void radeon_agp_suspend(struct radeon_device *rdev);
1157void radeon_agp_fini(struct radeon_device *rdev);
1158
1159
1160/*
1161 * Writeback
1162 */
1163struct radeon_wb {
1164 struct radeon_bo *wb_obj;
1165 volatile uint32_t *wb;
1166 uint64_t gpu_addr;
1167 bool enabled;
1168 bool use_event;
1169};
1170
1171#define RADEON_WB_SCRATCH_OFFSET 0
1172#define RADEON_WB_RING0_NEXT_RPTR 256
1173#define RADEON_WB_CP_RPTR_OFFSET 1024
1174#define RADEON_WB_CP1_RPTR_OFFSET 1280
1175#define RADEON_WB_CP2_RPTR_OFFSET 1536
1176#define R600_WB_DMA_RPTR_OFFSET 1792
1177#define R600_WB_IH_WPTR_OFFSET 2048
1178#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1179#define R600_WB_EVENT_OFFSET 3072
1180#define CIK_WB_CP1_WPTR_OFFSET 3328
1181#define CIK_WB_CP2_WPTR_OFFSET 3584
1182#define R600_WB_DMA_RING_TEST_OFFSET 3588
1183#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1184
1185/**
1186 * struct radeon_pm - power management datas
1187 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1188 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1189 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1190 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1191 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1192 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1193 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1194 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1195 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1196 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1197 * @needed_bandwidth: current bandwidth needs
1198 *
1199 * It keeps track of various data needed to take powermanagement decision.
1200 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1201 * Equation between gpu/memory clock and available bandwidth is hw dependent
1202 * (type of memory, bus size, efficiency, ...)
1203 */
1204
1205enum radeon_pm_method {
1206 PM_METHOD_PROFILE,
1207 PM_METHOD_DYNPM,
1208 PM_METHOD_DPM,
1209};
1210
1211enum radeon_dynpm_state {
1212 DYNPM_STATE_DISABLED,
1213 DYNPM_STATE_MINIMUM,
1214 DYNPM_STATE_PAUSED,
1215 DYNPM_STATE_ACTIVE,
1216 DYNPM_STATE_SUSPENDED,
1217};
1218enum radeon_dynpm_action {
1219 DYNPM_ACTION_NONE,
1220 DYNPM_ACTION_MINIMUM,
1221 DYNPM_ACTION_DOWNCLOCK,
1222 DYNPM_ACTION_UPCLOCK,
1223 DYNPM_ACTION_DEFAULT
1224};
1225
1226enum radeon_voltage_type {
1227 VOLTAGE_NONE = 0,
1228 VOLTAGE_GPIO,
1229 VOLTAGE_VDDC,
1230 VOLTAGE_SW
1231};
1232
1233enum radeon_pm_state_type {
1234 /* not used for dpm */
1235 POWER_STATE_TYPE_DEFAULT,
1236 POWER_STATE_TYPE_POWERSAVE,
1237 /* user selectable states */
1238 POWER_STATE_TYPE_BATTERY,
1239 POWER_STATE_TYPE_BALANCED,
1240 POWER_STATE_TYPE_PERFORMANCE,
1241 /* internal states */
1242 POWER_STATE_TYPE_INTERNAL_UVD,
1243 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1244 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1245 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1246 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1247 POWER_STATE_TYPE_INTERNAL_BOOT,
1248 POWER_STATE_TYPE_INTERNAL_THERMAL,
1249 POWER_STATE_TYPE_INTERNAL_ACPI,
1250 POWER_STATE_TYPE_INTERNAL_ULV,
1251 POWER_STATE_TYPE_INTERNAL_3DPERF,
1252};
1253
1254enum radeon_pm_profile_type {
1255 PM_PROFILE_DEFAULT,
1256 PM_PROFILE_AUTO,
1257 PM_PROFILE_LOW,
1258 PM_PROFILE_MID,
1259 PM_PROFILE_HIGH,
1260};
1261
1262#define PM_PROFILE_DEFAULT_IDX 0
1263#define PM_PROFILE_LOW_SH_IDX 1
1264#define PM_PROFILE_MID_SH_IDX 2
1265#define PM_PROFILE_HIGH_SH_IDX 3
1266#define PM_PROFILE_LOW_MH_IDX 4
1267#define PM_PROFILE_MID_MH_IDX 5
1268#define PM_PROFILE_HIGH_MH_IDX 6
1269#define PM_PROFILE_MAX 7
1270
1271struct radeon_pm_profile {
1272 int dpms_off_ps_idx;
1273 int dpms_on_ps_idx;
1274 int dpms_off_cm_idx;
1275 int dpms_on_cm_idx;
1276};
1277
1278enum radeon_int_thermal_type {
1279 THERMAL_TYPE_NONE,
1280 THERMAL_TYPE_EXTERNAL,
1281 THERMAL_TYPE_EXTERNAL_GPIO,
1282 THERMAL_TYPE_RV6XX,
1283 THERMAL_TYPE_RV770,
1284 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1285 THERMAL_TYPE_EVERGREEN,
1286 THERMAL_TYPE_SUMO,
1287 THERMAL_TYPE_NI,
1288 THERMAL_TYPE_SI,
1289 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1290 THERMAL_TYPE_CI,
1291 THERMAL_TYPE_KV,
1292};
1293
1294struct radeon_voltage {
1295 enum radeon_voltage_type type;
1296 /* gpio voltage */
1297 struct radeon_gpio_rec gpio;
1298 u32 delay; /* delay in usec from voltage drop to sclk change */
1299 bool active_high; /* voltage drop is active when bit is high */
1300 /* VDDC voltage */
1301 u8 vddc_id; /* index into vddc voltage table */
1302 u8 vddci_id; /* index into vddci voltage table */
1303 bool vddci_enabled;
1304 /* r6xx+ sw */
1305 u16 voltage;
1306 /* evergreen+ vddci */
1307 u16 vddci;
1308};
1309
1310/* clock mode flags */
1311#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1312
1313struct radeon_pm_clock_info {
1314 /* memory clock */
1315 u32 mclk;
1316 /* engine clock */
1317 u32 sclk;
1318 /* voltage info */
1319 struct radeon_voltage voltage;
1320 /* standardized clock flags */
1321 u32 flags;
1322};
1323
1324/* state flags */
1325#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1326
1327struct radeon_power_state {
1328 enum radeon_pm_state_type type;
1329 struct radeon_pm_clock_info *clock_info;
1330 /* number of valid clock modes in this power state */
1331 int num_clock_modes;
1332 struct radeon_pm_clock_info *default_clock_mode;
1333 /* standardized state flags */
1334 u32 flags;
1335 u32 misc; /* vbios specific flags */
1336 u32 misc2; /* vbios specific flags */
1337 int pcie_lanes; /* pcie lanes */
1338};
1339
1340/*
1341 * Some modes are overclocked by very low value, accept them
1342 */
1343#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1344
1345enum radeon_dpm_auto_throttle_src {
1346 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1347 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1348};
1349
1350enum radeon_dpm_event_src {
1351 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1352 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1353 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1354 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1355 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1356};
1357
1358#define RADEON_MAX_VCE_LEVELS 6
1359
1360enum radeon_vce_level {
1361 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1362 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1363 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1364 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1365 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1366 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1367};
1368
1369struct radeon_ps {
1370 u32 caps; /* vbios flags */
1371 u32 class; /* vbios flags */
1372 u32 class2; /* vbios flags */
1373 /* UVD clocks */
1374 u32 vclk;
1375 u32 dclk;
1376 /* VCE clocks */
1377 u32 evclk;
1378 u32 ecclk;
1379 bool vce_active;
1380 enum radeon_vce_level vce_level;
1381 /* asic priv */
1382 void *ps_priv;
1383};
1384
1385struct radeon_dpm_thermal {
1386 /* thermal interrupt work */
1387 struct work_struct work;
1388 /* low temperature threshold */
1389 int min_temp;
1390 /* high temperature threshold */
1391 int max_temp;
1392 /* was interrupt low to high or high to low */
1393 bool high_to_low;
1394};
1395
1396enum radeon_clk_action
1397{
1398 RADEON_SCLK_UP = 1,
1399 RADEON_SCLK_DOWN
1400};
1401
1402struct radeon_blacklist_clocks
1403{
1404 u32 sclk;
1405 u32 mclk;
1406 enum radeon_clk_action action;
1407};
1408
1409struct radeon_clock_and_voltage_limits {
1410 u32 sclk;
1411 u32 mclk;
1412 u16 vddc;
1413 u16 vddci;
1414};
1415
1416struct radeon_clock_array {
1417 u32 count;
1418 u32 *values;
1419};
1420
1421struct radeon_clock_voltage_dependency_entry {
1422 u32 clk;
1423 u16 v;
1424};
1425
1426struct radeon_clock_voltage_dependency_table {
1427 u32 count;
1428 struct radeon_clock_voltage_dependency_entry *entries;
1429};
1430
1431union radeon_cac_leakage_entry {
1432 struct {
1433 u16 vddc;
1434 u32 leakage;
1435 };
1436 struct {
1437 u16 vddc1;
1438 u16 vddc2;
1439 u16 vddc3;
1440 };
1441};
1442
1443struct radeon_cac_leakage_table {
1444 u32 count;
1445 union radeon_cac_leakage_entry *entries;
1446};
1447
1448struct radeon_phase_shedding_limits_entry {
1449 u16 voltage;
1450 u32 sclk;
1451 u32 mclk;
1452};
1453
1454struct radeon_phase_shedding_limits_table {
1455 u32 count;
1456 struct radeon_phase_shedding_limits_entry *entries;
1457};
1458
1459struct radeon_uvd_clock_voltage_dependency_entry {
1460 u32 vclk;
1461 u32 dclk;
1462 u16 v;
1463};
1464
1465struct radeon_uvd_clock_voltage_dependency_table {
1466 u8 count;
1467 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1468};
1469
1470struct radeon_vce_clock_voltage_dependency_entry {
1471 u32 ecclk;
1472 u32 evclk;
1473 u16 v;
1474};
1475
1476struct radeon_vce_clock_voltage_dependency_table {
1477 u8 count;
1478 struct radeon_vce_clock_voltage_dependency_entry *entries;
1479};
1480
1481struct radeon_ppm_table {
1482 u8 ppm_design;
1483 u16 cpu_core_number;
1484 u32 platform_tdp;
1485 u32 small_ac_platform_tdp;
1486 u32 platform_tdc;
1487 u32 small_ac_platform_tdc;
1488 u32 apu_tdp;
1489 u32 dgpu_tdp;
1490 u32 dgpu_ulv_power;
1491 u32 tj_max;
1492};
1493
1494struct radeon_cac_tdp_table {
1495 u16 tdp;
1496 u16 configurable_tdp;
1497 u16 tdc;
1498 u16 battery_power_limit;
1499 u16 small_power_limit;
1500 u16 low_cac_leakage;
1501 u16 high_cac_leakage;
1502 u16 maximum_power_delivery_limit;
1503};
1504
1505struct radeon_dpm_dynamic_state {
1506 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1507 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1508 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1509 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1510 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1511 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1512 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1513 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1514 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1515 struct radeon_clock_array valid_sclk_values;
1516 struct radeon_clock_array valid_mclk_values;
1517 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1518 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1519 u32 mclk_sclk_ratio;
1520 u32 sclk_mclk_delta;
1521 u16 vddc_vddci_delta;
1522 u16 min_vddc_for_pcie_gen2;
1523 struct radeon_cac_leakage_table cac_leakage_table;
1524 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1525 struct radeon_ppm_table *ppm_table;
1526 struct radeon_cac_tdp_table *cac_tdp_table;
1527};
1528
1529struct radeon_dpm_fan {
1530 u16 t_min;
1531 u16 t_med;
1532 u16 t_high;
1533 u16 pwm_min;
1534 u16 pwm_med;
1535 u16 pwm_high;
1536 u8 t_hyst;
1537 u32 cycle_delay;
1538 u16 t_max;
1539 u8 control_mode;
1540 u16 default_max_fan_pwm;
1541 u16 default_fan_output_sensitivity;
1542 u16 fan_output_sensitivity;
1543 bool ucode_fan_control;
1544};
1545
1546enum radeon_pcie_gen {
1547 RADEON_PCIE_GEN1 = 0,
1548 RADEON_PCIE_GEN2 = 1,
1549 RADEON_PCIE_GEN3 = 2,
1550 RADEON_PCIE_GEN_INVALID = 0xffff
1551};
1552
1553enum radeon_dpm_forced_level {
1554 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1555 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1556 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1557};
1558
1559struct radeon_vce_state {
1560 /* vce clocks */
1561 u32 evclk;
1562 u32 ecclk;
1563 /* gpu clocks */
1564 u32 sclk;
1565 u32 mclk;
1566 u8 clk_idx;
1567 u8 pstate;
1568};
1569
1570struct radeon_dpm {
1571 struct radeon_ps *ps;
1572 /* number of valid power states */
1573 int num_ps;
1574 /* current power state that is active */
1575 struct radeon_ps *current_ps;
1576 /* requested power state */
1577 struct radeon_ps *requested_ps;
1578 /* boot up power state */
1579 struct radeon_ps *boot_ps;
1580 /* default uvd power state */
1581 struct radeon_ps *uvd_ps;
1582 /* vce requirements */
1583 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1584 enum radeon_vce_level vce_level;
1585 enum radeon_pm_state_type state;
1586 enum radeon_pm_state_type user_state;
1587 u32 platform_caps;
1588 u32 voltage_response_time;
1589 u32 backbias_response_time;
1590 void *priv;
1591 u32 new_active_crtcs;
1592 int new_active_crtc_count;
1593 int high_pixelclock_count;
1594 u32 current_active_crtcs;
1595 int current_active_crtc_count;
1596 bool single_display;
1597 struct radeon_dpm_dynamic_state dyn_state;
1598 struct radeon_dpm_fan fan;
1599 u32 tdp_limit;
1600 u32 near_tdp_limit;
1601 u32 near_tdp_limit_adjusted;
1602 u32 sq_ramping_threshold;
1603 u32 cac_leakage;
1604 u16 tdp_od_limit;
1605 u32 tdp_adjustment;
1606 u16 load_line_slope;
1607 bool power_control;
1608 bool ac_power;
1609 /* special states active */
1610 bool thermal_active;
1611 bool uvd_active;
1612 bool vce_active;
1613 /* thermal handling */
1614 struct radeon_dpm_thermal thermal;
1615 /* forced levels */
1616 enum radeon_dpm_forced_level forced_level;
1617 /* track UVD streams */
1618 unsigned sd;
1619 unsigned hd;
1620};
1621
1622void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1623void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1624
1625struct radeon_pm {
1626 struct mutex mutex;
1627 /* write locked while reprogramming mclk */
1628 struct rw_semaphore mclk_lock;
1629 u32 active_crtcs;
1630 int active_crtc_count;
1631 int req_vblank;
1632 bool vblank_sync;
1633 fixed20_12 max_bandwidth;
1634 fixed20_12 igp_sideport_mclk;
1635 fixed20_12 igp_system_mclk;
1636 fixed20_12 igp_ht_link_clk;
1637 fixed20_12 igp_ht_link_width;
1638 fixed20_12 k8_bandwidth;
1639 fixed20_12 sideport_bandwidth;
1640 fixed20_12 ht_bandwidth;
1641 fixed20_12 core_bandwidth;
1642 fixed20_12 sclk;
1643 fixed20_12 mclk;
1644 fixed20_12 needed_bandwidth;
1645 struct radeon_power_state *power_state;
1646 /* number of valid power states */
1647 int num_power_states;
1648 int current_power_state_index;
1649 int current_clock_mode_index;
1650 int requested_power_state_index;
1651 int requested_clock_mode_index;
1652 int default_power_state_index;
1653 u32 current_sclk;
1654 u32 current_mclk;
1655 u16 current_vddc;
1656 u16 current_vddci;
1657 u32 default_sclk;
1658 u32 default_mclk;
1659 u16 default_vddc;
1660 u16 default_vddci;
1661 struct radeon_i2c_chan *i2c_bus;
1662 /* selected pm method */
1663 enum radeon_pm_method pm_method;
1664 /* dynpm power management */
1665 struct delayed_work dynpm_idle_work;
1666 enum radeon_dynpm_state dynpm_state;
1667 enum radeon_dynpm_action dynpm_planned_action;
1668 unsigned long dynpm_action_timeout;
1669 bool dynpm_can_upclock;
1670 bool dynpm_can_downclock;
1671 /* profile-based power management */
1672 enum radeon_pm_profile_type profile;
1673 int profile_index;
1674 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1675 /* internal thermal controller on rv6xx+ */
1676 enum radeon_int_thermal_type int_thermal_type;
1677 struct device *int_hwmon_dev;
1678 /* fan control parameters */
1679 bool no_fan;
1680 u8 fan_pulses_per_revolution;
1681 u8 fan_min_rpm;
1682 u8 fan_max_rpm;
1683 /* dpm */
1684 bool dpm_enabled;
1685 bool sysfs_initialized;
1686 struct radeon_dpm dpm;
1687};
1688
1689#define RADEON_PCIE_SPEED_25 1
1690#define RADEON_PCIE_SPEED_50 2
1691#define RADEON_PCIE_SPEED_80 4
1692
1693int radeon_pm_get_type_index(struct radeon_device *rdev,
1694 enum radeon_pm_state_type ps_type,
1695 int instance);
1696/*
1697 * UVD
1698 */
1699#define RADEON_DEFAULT_UVD_HANDLES 10
1700#define RADEON_MAX_UVD_HANDLES 30
1701#define RADEON_UVD_STACK_SIZE (200*1024)
1702#define RADEON_UVD_HEAP_SIZE (256*1024)
1703#define RADEON_UVD_SESSION_SIZE (50*1024)
1704
1705struct radeon_uvd {
1706 bool fw_header_present;
1707 struct radeon_bo *vcpu_bo;
1708 void *cpu_addr;
1709 uint64_t gpu_addr;
1710 unsigned max_handles;
1711 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1712 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1713 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1714 struct delayed_work idle_work;
1715};
1716
1717int radeon_uvd_init(struct radeon_device *rdev);
1718void radeon_uvd_fini(struct radeon_device *rdev);
1719int radeon_uvd_suspend(struct radeon_device *rdev);
1720int radeon_uvd_resume(struct radeon_device *rdev);
1721int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1722 uint32_t handle, struct radeon_fence **fence);
1723int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1724 uint32_t handle, struct radeon_fence **fence);
1725void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1726 uint32_t allowed_domains);
1727void radeon_uvd_free_handles(struct radeon_device *rdev,
1728 struct drm_file *filp);
1729int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1730void radeon_uvd_note_usage(struct radeon_device *rdev);
1731int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1732 unsigned vclk, unsigned dclk,
1733 unsigned vco_min, unsigned vco_max,
1734 unsigned fb_factor, unsigned fb_mask,
1735 unsigned pd_min, unsigned pd_max,
1736 unsigned pd_even,
1737 unsigned *optimal_fb_div,
1738 unsigned *optimal_vclk_div,
1739 unsigned *optimal_dclk_div);
1740int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1741 unsigned cg_upll_func_cntl);
1742
1743/*
1744 * VCE
1745 */
1746#define RADEON_MAX_VCE_HANDLES 16
1747
1748struct radeon_vce {
1749 struct radeon_bo *vcpu_bo;
1750 uint64_t gpu_addr;
1751 unsigned fw_version;
1752 unsigned fb_version;
1753 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1754 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1755 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1756 struct delayed_work idle_work;
1757 uint32_t keyselect;
1758};
1759
1760int radeon_vce_init(struct radeon_device *rdev);
1761void radeon_vce_fini(struct radeon_device *rdev);
1762int radeon_vce_suspend(struct radeon_device *rdev);
1763int radeon_vce_resume(struct radeon_device *rdev);
1764int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1765 uint32_t handle, struct radeon_fence **fence);
1766int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1767 uint32_t handle, struct radeon_fence **fence);
1768void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1769void radeon_vce_note_usage(struct radeon_device *rdev);
1770int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1771int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1772bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1773 struct radeon_ring *ring,
1774 struct radeon_semaphore *semaphore,
1775 bool emit_wait);
1776void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1777void radeon_vce_fence_emit(struct radeon_device *rdev,
1778 struct radeon_fence *fence);
1779int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1780int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1781
1782struct r600_audio_pin {
1783 int channels;
1784 int rate;
1785 int bits_per_sample;
1786 u8 status_bits;
1787 u8 category_code;
1788 u32 offset;
1789 bool connected;
1790 u32 id;
1791};
1792
1793struct r600_audio {
1794 bool enabled;
1795 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1796 int num_pins;
1797 struct radeon_audio_funcs *hdmi_funcs;
1798 struct radeon_audio_funcs *dp_funcs;
1799 struct radeon_audio_basic_funcs *funcs;
1800};
1801
1802/*
1803 * Benchmarking
1804 */
1805void radeon_benchmark(struct radeon_device *rdev, int test_number);
1806
1807
1808/*
1809 * Testing
1810 */
1811void radeon_test_moves(struct radeon_device *rdev);
1812void radeon_test_ring_sync(struct radeon_device *rdev,
1813 struct radeon_ring *cpA,
1814 struct radeon_ring *cpB);
1815void radeon_test_syncing(struct radeon_device *rdev);
1816
1817/*
1818 * MMU Notifier
1819 */
1820#if defined(CONFIG_MMU_NOTIFIER)
1821int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1822void radeon_mn_unregister(struct radeon_bo *bo);
1823#else
1824static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1825{
1826 return -ENODEV;
1827}
1828static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1829#endif
1830
1831/*
1832 * Debugfs
1833 */
1834void radeon_debugfs_fence_init(struct radeon_device *rdev);
1835void radeon_gem_debugfs_init(struct radeon_device *rdev);
1836
1837/*
1838 * ASIC ring specific functions.
1839 */
1840struct radeon_asic_ring {
1841 /* ring read/write ptr handling */
1842 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1843 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1844 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1845
1846 /* validating and patching of IBs */
1847 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1848 int (*cs_parse)(struct radeon_cs_parser *p);
1849
1850 /* command emmit functions */
1851 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1852 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1853 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1854 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1855 struct radeon_semaphore *semaphore, bool emit_wait);
1856 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1857 unsigned vm_id, uint64_t pd_addr);
1858
1859 /* testing functions */
1860 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1861 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1862 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1863
1864 /* deprecated */
1865 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1866};
1867
1868/*
1869 * ASIC specific functions.
1870 */
1871struct radeon_asic {
1872 int (*init)(struct radeon_device *rdev);
1873 void (*fini)(struct radeon_device *rdev);
1874 int (*resume)(struct radeon_device *rdev);
1875 int (*suspend)(struct radeon_device *rdev);
1876 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1877 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1878 /* Flush the HDP cache via MMIO */
1879 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1880 /* check if 3D engine is idle */
1881 bool (*gui_idle)(struct radeon_device *rdev);
1882 /* wait for mc_idle */
1883 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1884 /* get the reference clock */
1885 u32 (*get_xclk)(struct radeon_device *rdev);
1886 /* get the gpu clock counter */
1887 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1888 /* get register for info ioctl */
1889 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1890 /* gart */
1891 struct {
1892 void (*tlb_flush)(struct radeon_device *rdev);
1893 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1894 void (*set_page)(struct radeon_device *rdev, unsigned i,
1895 uint64_t entry);
1896 } gart;
1897 struct {
1898 int (*init)(struct radeon_device *rdev);
1899 void (*fini)(struct radeon_device *rdev);
1900 void (*copy_pages)(struct radeon_device *rdev,
1901 struct radeon_ib *ib,
1902 uint64_t pe, uint64_t src,
1903 unsigned count);
1904 void (*write_pages)(struct radeon_device *rdev,
1905 struct radeon_ib *ib,
1906 uint64_t pe,
1907 uint64_t addr, unsigned count,
1908 uint32_t incr, uint32_t flags);
1909 void (*set_pages)(struct radeon_device *rdev,
1910 struct radeon_ib *ib,
1911 uint64_t pe,
1912 uint64_t addr, unsigned count,
1913 uint32_t incr, uint32_t flags);
1914 void (*pad_ib)(struct radeon_ib *ib);
1915 } vm;
1916 /* ring specific callbacks */
1917 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1918 /* irqs */
1919 struct {
1920 int (*set)(struct radeon_device *rdev);
1921 int (*process)(struct radeon_device *rdev);
1922 } irq;
1923 /* displays */
1924 struct {
1925 /* display watermarks */
1926 void (*bandwidth_update)(struct radeon_device *rdev);
1927 /* get frame count */
1928 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1929 /* wait for vblank */
1930 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1931 /* set backlight level */
1932 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1933 /* get backlight level */
1934 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1935 /* audio callbacks */
1936 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1937 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1938 } display;
1939 /* copy functions for bo handling */
1940 struct {
1941 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1942 uint64_t src_offset,
1943 uint64_t dst_offset,
1944 unsigned num_gpu_pages,
1945 struct dma_resv *resv);
1946 u32 blit_ring_index;
1947 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1948 uint64_t src_offset,
1949 uint64_t dst_offset,
1950 unsigned num_gpu_pages,
1951 struct dma_resv *resv);
1952 u32 dma_ring_index;
1953 /* method used for bo copy */
1954 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1955 uint64_t src_offset,
1956 uint64_t dst_offset,
1957 unsigned num_gpu_pages,
1958 struct dma_resv *resv);
1959 /* ring used for bo copies */
1960 u32 copy_ring_index;
1961 } copy;
1962 /* surfaces */
1963 struct {
1964 int (*set_reg)(struct radeon_device *rdev, int reg,
1965 uint32_t tiling_flags, uint32_t pitch,
1966 uint32_t offset, uint32_t obj_size);
1967 void (*clear_reg)(struct radeon_device *rdev, int reg);
1968 } surface;
1969 /* hotplug detect */
1970 struct {
1971 void (*init)(struct radeon_device *rdev);
1972 void (*fini)(struct radeon_device *rdev);
1973 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1974 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1975 } hpd;
1976 /* static power management */
1977 struct {
1978 void (*misc)(struct radeon_device *rdev);
1979 void (*prepare)(struct radeon_device *rdev);
1980 void (*finish)(struct radeon_device *rdev);
1981 void (*init_profile)(struct radeon_device *rdev);
1982 void (*get_dynpm_state)(struct radeon_device *rdev);
1983 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1984 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1985 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1986 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1987 int (*get_pcie_lanes)(struct radeon_device *rdev);
1988 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1989 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1990 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1991 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1992 int (*get_temperature)(struct radeon_device *rdev);
1993 } pm;
1994 /* dynamic power management */
1995 struct {
1996 int (*init)(struct radeon_device *rdev);
1997 void (*setup_asic)(struct radeon_device *rdev);
1998 int (*enable)(struct radeon_device *rdev);
1999 int (*late_enable)(struct radeon_device *rdev);
2000 void (*disable)(struct radeon_device *rdev);
2001 int (*pre_set_power_state)(struct radeon_device *rdev);
2002 int (*set_power_state)(struct radeon_device *rdev);
2003 void (*post_set_power_state)(struct radeon_device *rdev);
2004 void (*display_configuration_changed)(struct radeon_device *rdev);
2005 void (*fini)(struct radeon_device *rdev);
2006 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
2007 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
2008 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
2009 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
2010 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
2011 bool (*vblank_too_short)(struct radeon_device *rdev);
2012 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
2013 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
2014 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2015 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2016 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2017 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2018 u32 (*get_current_sclk)(struct radeon_device *rdev);
2019 u32 (*get_current_mclk)(struct radeon_device *rdev);
2020 u16 (*get_current_vddc)(struct radeon_device *rdev);
2021 } dpm;
2022 /* pageflipping */
2023 struct {
2024 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2025 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2026 } pflip;
2027};
2028
2029/*
2030 * Asic structures
2031 */
2032struct r100_asic {
2033 const unsigned *reg_safe_bm;
2034 unsigned reg_safe_bm_size;
2035 u32 hdp_cntl;
2036};
2037
2038struct r300_asic {
2039 const unsigned *reg_safe_bm;
2040 unsigned reg_safe_bm_size;
2041 u32 resync_scratch;
2042 u32 hdp_cntl;
2043};
2044
2045struct r600_asic {
2046 unsigned max_pipes;
2047 unsigned max_tile_pipes;
2048 unsigned max_simds;
2049 unsigned max_backends;
2050 unsigned max_gprs;
2051 unsigned max_threads;
2052 unsigned max_stack_entries;
2053 unsigned max_hw_contexts;
2054 unsigned max_gs_threads;
2055 unsigned sx_max_export_size;
2056 unsigned sx_max_export_pos_size;
2057 unsigned sx_max_export_smx_size;
2058 unsigned sq_num_cf_insts;
2059 unsigned tiling_nbanks;
2060 unsigned tiling_npipes;
2061 unsigned tiling_group_size;
2062 unsigned tile_config;
2063 unsigned backend_map;
2064 unsigned active_simds;
2065};
2066
2067struct rv770_asic {
2068 unsigned max_pipes;
2069 unsigned max_tile_pipes;
2070 unsigned max_simds;
2071 unsigned max_backends;
2072 unsigned max_gprs;
2073 unsigned max_threads;
2074 unsigned max_stack_entries;
2075 unsigned max_hw_contexts;
2076 unsigned max_gs_threads;
2077 unsigned sx_max_export_size;
2078 unsigned sx_max_export_pos_size;
2079 unsigned sx_max_export_smx_size;
2080 unsigned sq_num_cf_insts;
2081 unsigned sx_num_of_sets;
2082 unsigned sc_prim_fifo_size;
2083 unsigned sc_hiz_tile_fifo_size;
2084 unsigned sc_earlyz_tile_fifo_fize;
2085 unsigned tiling_nbanks;
2086 unsigned tiling_npipes;
2087 unsigned tiling_group_size;
2088 unsigned tile_config;
2089 unsigned backend_map;
2090 unsigned active_simds;
2091};
2092
2093struct evergreen_asic {
2094 unsigned num_ses;
2095 unsigned max_pipes;
2096 unsigned max_tile_pipes;
2097 unsigned max_simds;
2098 unsigned max_backends;
2099 unsigned max_gprs;
2100 unsigned max_threads;
2101 unsigned max_stack_entries;
2102 unsigned max_hw_contexts;
2103 unsigned max_gs_threads;
2104 unsigned sx_max_export_size;
2105 unsigned sx_max_export_pos_size;
2106 unsigned sx_max_export_smx_size;
2107 unsigned sq_num_cf_insts;
2108 unsigned sx_num_of_sets;
2109 unsigned sc_prim_fifo_size;
2110 unsigned sc_hiz_tile_fifo_size;
2111 unsigned sc_earlyz_tile_fifo_size;
2112 unsigned tiling_nbanks;
2113 unsigned tiling_npipes;
2114 unsigned tiling_group_size;
2115 unsigned tile_config;
2116 unsigned backend_map;
2117 unsigned active_simds;
2118};
2119
2120struct cayman_asic {
2121 unsigned max_shader_engines;
2122 unsigned max_pipes_per_simd;
2123 unsigned max_tile_pipes;
2124 unsigned max_simds_per_se;
2125 unsigned max_backends_per_se;
2126 unsigned max_texture_channel_caches;
2127 unsigned max_gprs;
2128 unsigned max_threads;
2129 unsigned max_gs_threads;
2130 unsigned max_stack_entries;
2131 unsigned sx_num_of_sets;
2132 unsigned sx_max_export_size;
2133 unsigned sx_max_export_pos_size;
2134 unsigned sx_max_export_smx_size;
2135 unsigned max_hw_contexts;
2136 unsigned sq_num_cf_insts;
2137 unsigned sc_prim_fifo_size;
2138 unsigned sc_hiz_tile_fifo_size;
2139 unsigned sc_earlyz_tile_fifo_size;
2140
2141 unsigned num_shader_engines;
2142 unsigned num_shader_pipes_per_simd;
2143 unsigned num_tile_pipes;
2144 unsigned num_simds_per_se;
2145 unsigned num_backends_per_se;
2146 unsigned backend_disable_mask_per_asic;
2147 unsigned backend_map;
2148 unsigned num_texture_channel_caches;
2149 unsigned mem_max_burst_length_bytes;
2150 unsigned mem_row_size_in_kb;
2151 unsigned shader_engine_tile_size;
2152 unsigned num_gpus;
2153 unsigned multi_gpu_tile_size;
2154
2155 unsigned tile_config;
2156 unsigned active_simds;
2157};
2158
2159struct si_asic {
2160 unsigned max_shader_engines;
2161 unsigned max_tile_pipes;
2162 unsigned max_cu_per_sh;
2163 unsigned max_sh_per_se;
2164 unsigned max_backends_per_se;
2165 unsigned max_texture_channel_caches;
2166 unsigned max_gprs;
2167 unsigned max_gs_threads;
2168 unsigned max_hw_contexts;
2169 unsigned sc_prim_fifo_size_frontend;
2170 unsigned sc_prim_fifo_size_backend;
2171 unsigned sc_hiz_tile_fifo_size;
2172 unsigned sc_earlyz_tile_fifo_size;
2173
2174 unsigned num_tile_pipes;
2175 unsigned backend_enable_mask;
2176 unsigned backend_disable_mask_per_asic;
2177 unsigned backend_map;
2178 unsigned num_texture_channel_caches;
2179 unsigned mem_max_burst_length_bytes;
2180 unsigned mem_row_size_in_kb;
2181 unsigned shader_engine_tile_size;
2182 unsigned num_gpus;
2183 unsigned multi_gpu_tile_size;
2184
2185 unsigned tile_config;
2186 uint32_t tile_mode_array[32];
2187 uint32_t active_cus;
2188};
2189
2190struct cik_asic {
2191 unsigned max_shader_engines;
2192 unsigned max_tile_pipes;
2193 unsigned max_cu_per_sh;
2194 unsigned max_sh_per_se;
2195 unsigned max_backends_per_se;
2196 unsigned max_texture_channel_caches;
2197 unsigned max_gprs;
2198 unsigned max_gs_threads;
2199 unsigned max_hw_contexts;
2200 unsigned sc_prim_fifo_size_frontend;
2201 unsigned sc_prim_fifo_size_backend;
2202 unsigned sc_hiz_tile_fifo_size;
2203 unsigned sc_earlyz_tile_fifo_size;
2204
2205 unsigned num_tile_pipes;
2206 unsigned backend_enable_mask;
2207 unsigned backend_disable_mask_per_asic;
2208 unsigned backend_map;
2209 unsigned num_texture_channel_caches;
2210 unsigned mem_max_burst_length_bytes;
2211 unsigned mem_row_size_in_kb;
2212 unsigned shader_engine_tile_size;
2213 unsigned num_gpus;
2214 unsigned multi_gpu_tile_size;
2215
2216 unsigned tile_config;
2217 uint32_t tile_mode_array[32];
2218 uint32_t macrotile_mode_array[16];
2219 uint32_t active_cus;
2220};
2221
2222union radeon_asic_config {
2223 struct r300_asic r300;
2224 struct r100_asic r100;
2225 struct r600_asic r600;
2226 struct rv770_asic rv770;
2227 struct evergreen_asic evergreen;
2228 struct cayman_asic cayman;
2229 struct si_asic si;
2230 struct cik_asic cik;
2231};
2232
2233/*
2234 * asic initizalization from radeon_asic.c
2235 */
2236void radeon_agp_disable(struct radeon_device *rdev);
2237int radeon_asic_init(struct radeon_device *rdev);
2238
2239
2240/*
2241 * IOCTL.
2242 */
2243int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2244 struct drm_file *filp);
2245int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *filp);
2247int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
2249int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *file_priv);
2251int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2252 struct drm_file *file_priv);
2253int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2254 struct drm_file *file_priv);
2255int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2256 struct drm_file *file_priv);
2257int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2258 struct drm_file *filp);
2259int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2260 struct drm_file *filp);
2261int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2262 struct drm_file *filp);
2263int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2264 struct drm_file *filp);
2265int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2266 struct drm_file *filp);
2267int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2268 struct drm_file *filp);
2269int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2270int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2271 struct drm_file *filp);
2272int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2273 struct drm_file *filp);
2274int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2275
2276/* VRAM scratch page for HDP bug, default vram page */
2277struct r600_vram_scratch {
2278 struct radeon_bo *robj;
2279 volatile uint32_t *ptr;
2280 u64 gpu_addr;
2281};
2282
2283/*
2284 * ACPI
2285 */
2286struct radeon_atif_notification_cfg {
2287 bool enabled;
2288 int command_code;
2289};
2290
2291struct radeon_atif_notifications {
2292 bool display_switch;
2293 bool expansion_mode_change;
2294 bool thermal_state;
2295 bool forced_power_state;
2296 bool system_power_state;
2297 bool display_conf_change;
2298 bool px_gfx_switch;
2299 bool brightness_change;
2300 bool dgpu_display_event;
2301};
2302
2303struct radeon_atif_functions {
2304 bool system_params;
2305 bool sbios_requests;
2306 bool select_active_disp;
2307 bool lid_state;
2308 bool get_tv_standard;
2309 bool set_tv_standard;
2310 bool get_panel_expansion_mode;
2311 bool set_panel_expansion_mode;
2312 bool temperature_change;
2313 bool graphics_device_types;
2314};
2315
2316struct radeon_atif {
2317 struct radeon_atif_notifications notifications;
2318 struct radeon_atif_functions functions;
2319 struct radeon_atif_notification_cfg notification_cfg;
2320 struct radeon_encoder *encoder_for_bl;
2321};
2322
2323struct radeon_atcs_functions {
2324 bool get_ext_state;
2325 bool pcie_perf_req;
2326 bool pcie_dev_rdy;
2327 bool pcie_bus_width;
2328};
2329
2330struct radeon_atcs {
2331 struct radeon_atcs_functions functions;
2332};
2333
2334/*
2335 * Core structure, functions and helpers.
2336 */
2337typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2338typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2339
2340struct radeon_device {
2341 struct device *dev;
2342 struct drm_device *ddev;
2343 struct pci_dev *pdev;
2344#ifdef __alpha__
2345 struct pci_controller *hose;
2346#endif
2347 struct radeon_agp_head *agp;
2348 struct rw_semaphore exclusive_lock;
2349 /* ASIC */
2350 union radeon_asic_config config;
2351 enum radeon_family family;
2352 unsigned long flags;
2353 int usec_timeout;
2354 enum radeon_pll_errata pll_errata;
2355 int num_gb_pipes;
2356 int num_z_pipes;
2357 int disp_priority;
2358 /* BIOS */
2359 uint8_t *bios;
2360 bool is_atom_bios;
2361 uint16_t bios_header_start;
2362 struct radeon_bo *stolen_vga_memory;
2363 /* Register mmio */
2364 resource_size_t rmmio_base;
2365 resource_size_t rmmio_size;
2366 /* protects concurrent MM_INDEX/DATA based register access */
2367 spinlock_t mmio_idx_lock;
2368 /* protects concurrent SMC based register access */
2369 spinlock_t smc_idx_lock;
2370 /* protects concurrent PLL register access */
2371 spinlock_t pll_idx_lock;
2372 /* protects concurrent MC register access */
2373 spinlock_t mc_idx_lock;
2374 /* protects concurrent PCIE register access */
2375 spinlock_t pcie_idx_lock;
2376 /* protects concurrent PCIE_PORT register access */
2377 spinlock_t pciep_idx_lock;
2378 /* protects concurrent PIF register access */
2379 spinlock_t pif_idx_lock;
2380 /* protects concurrent CG register access */
2381 spinlock_t cg_idx_lock;
2382 /* protects concurrent UVD register access */
2383 spinlock_t uvd_idx_lock;
2384 /* protects concurrent RCU register access */
2385 spinlock_t rcu_idx_lock;
2386 /* protects concurrent DIDT register access */
2387 spinlock_t didt_idx_lock;
2388 /* protects concurrent ENDPOINT (audio) register access */
2389 spinlock_t end_idx_lock;
2390 void __iomem *rmmio;
2391 radeon_rreg_t mc_rreg;
2392 radeon_wreg_t mc_wreg;
2393 radeon_rreg_t pll_rreg;
2394 radeon_wreg_t pll_wreg;
2395 uint32_t pcie_reg_mask;
2396 radeon_rreg_t pciep_rreg;
2397 radeon_wreg_t pciep_wreg;
2398 /* io port */
2399 void __iomem *rio_mem;
2400 resource_size_t rio_mem_size;
2401 struct radeon_clock clock;
2402 struct radeon_mc mc;
2403 struct radeon_gart gart;
2404 struct radeon_mode_info mode_info;
2405 struct radeon_scratch scratch;
2406 struct radeon_doorbell doorbell;
2407 struct radeon_mman mman;
2408 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2409 wait_queue_head_t fence_queue;
2410 u64 fence_context;
2411 struct mutex ring_lock;
2412 struct radeon_ring ring[RADEON_NUM_RINGS];
2413 bool ib_pool_ready;
2414 struct radeon_sa_manager ring_tmp_bo;
2415 struct radeon_irq irq;
2416 struct radeon_asic *asic;
2417 struct radeon_gem gem;
2418 struct radeon_pm pm;
2419 struct radeon_uvd uvd;
2420 struct radeon_vce vce;
2421 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2422 struct radeon_wb wb;
2423 struct radeon_dummy_page dummy_page;
2424 bool shutdown;
2425 bool need_swiotlb;
2426 bool accel_working;
2427 bool fastfb_working; /* IGP feature*/
2428 bool needs_reset, in_reset;
2429 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2430 const struct firmware *me_fw; /* all family ME firmware */
2431 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2432 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2433 const struct firmware *mc_fw; /* NI MC firmware */
2434 const struct firmware *ce_fw; /* SI CE firmware */
2435 const struct firmware *mec_fw; /* CIK MEC firmware */
2436 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2437 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2438 const struct firmware *smc_fw; /* SMC firmware */
2439 const struct firmware *uvd_fw; /* UVD firmware */
2440 const struct firmware *vce_fw; /* VCE firmware */
2441 bool new_fw;
2442 struct r600_vram_scratch vram_scratch;
2443 int msi_enabled; /* msi enabled */
2444 struct r600_ih ih; /* r6/700 interrupt ring */
2445 struct radeon_rlc rlc;
2446 struct radeon_mec mec;
2447 struct delayed_work hotplug_work;
2448 struct work_struct dp_work;
2449 struct work_struct audio_work;
2450 int num_crtc; /* number of crtcs */
2451 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2452 bool has_uvd;
2453 bool has_vce;
2454 struct r600_audio audio; /* audio stuff */
2455 struct notifier_block acpi_nb;
2456 /* only one userspace can use Hyperz features or CMASK at a time */
2457 struct drm_file *hyperz_filp;
2458 struct drm_file *cmask_filp;
2459 /* i2c buses */
2460 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2461 /* virtual memory */
2462 struct radeon_vm_manager vm_manager;
2463 struct mutex gpu_clock_mutex;
2464 /* memory stats */
2465 atomic64_t vram_usage;
2466 atomic64_t gtt_usage;
2467 atomic64_t num_bytes_moved;
2468 atomic_t gpu_reset_counter;
2469 /* ACPI interface */
2470 struct radeon_atif atif;
2471 struct radeon_atcs atcs;
2472 /* srbm instance registers */
2473 struct mutex srbm_mutex;
2474 /* clock, powergating flags */
2475 u32 cg_flags;
2476 u32 pg_flags;
2477
2478 struct dev_pm_domain vga_pm_domain;
2479 bool have_disp_power_ref;
2480 u32 px_quirk_flags;
2481
2482 /* tracking pinned memory */
2483 u64 vram_pin_size;
2484 u64 gart_pin_size;
2485};
2486
2487bool radeon_is_px(struct drm_device *dev);
2488int radeon_device_init(struct radeon_device *rdev,
2489 struct drm_device *ddev,
2490 struct pci_dev *pdev,
2491 uint32_t flags);
2492void radeon_device_fini(struct radeon_device *rdev);
2493int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2494
2495#define RADEON_MIN_MMIO_SIZE 0x10000
2496
2497uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2498void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2499static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2500 bool always_indirect)
2501{
2502 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2503 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2504 return readl(((void __iomem *)rdev->rmmio) + reg);
2505 else
2506 return r100_mm_rreg_slow(rdev, reg);
2507}
2508static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2509 bool always_indirect)
2510{
2511 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2512 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2513 else
2514 r100_mm_wreg_slow(rdev, reg, v);
2515}
2516
2517u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2518void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2519
2520u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2521void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2522
2523/*
2524 * Cast helper
2525 */
2526extern const struct dma_fence_ops radeon_fence_ops;
2527
2528static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2529{
2530 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2531
2532 if (__f->base.ops == &radeon_fence_ops)
2533 return __f;
2534
2535 return NULL;
2536}
2537
2538/*
2539 * Registers read & write functions.
2540 */
2541#define RREG8(reg) readb((rdev->rmmio) + (reg))
2542#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2543#define RREG16(reg) readw((rdev->rmmio) + (reg))
2544#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2545#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2546#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2547#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2548 r100_mm_rreg(rdev, (reg), false))
2549#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2550#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2551#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2552#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2553#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2554#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2555#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2556#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2557#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2558#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2559#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2560#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2561#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2562#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2563#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2564#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2565#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2566#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2567#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2568#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2569#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2570#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2571#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2572#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2573#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2574#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2575#define WREG32_P(reg, val, mask) \
2576 do { \
2577 uint32_t tmp_ = RREG32(reg); \
2578 tmp_ &= (mask); \
2579 tmp_ |= ((val) & ~(mask)); \
2580 WREG32(reg, tmp_); \
2581 } while (0)
2582#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2583#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2584#define WREG32_PLL_P(reg, val, mask) \
2585 do { \
2586 uint32_t tmp_ = RREG32_PLL(reg); \
2587 tmp_ &= (mask); \
2588 tmp_ |= ((val) & ~(mask)); \
2589 WREG32_PLL(reg, tmp_); \
2590 } while (0)
2591#define WREG32_SMC_P(reg, val, mask) \
2592 do { \
2593 uint32_t tmp_ = RREG32_SMC(reg); \
2594 tmp_ &= (mask); \
2595 tmp_ |= ((val) & ~(mask)); \
2596 WREG32_SMC(reg, tmp_); \
2597 } while (0)
2598#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2599#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2600#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2601
2602#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2603#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2604
2605/*
2606 * Indirect registers accessors.
2607 * They used to be inlined, but this increases code size by ~65 kbytes.
2608 * Since each performs a pair of MMIO ops
2609 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2610 * the cost of call+ret is almost negligible. MMIO and locking
2611 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2612 */
2613uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2614void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2615u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2616void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2617u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2618void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2619u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2620void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2621u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2622void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2623u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2624void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2625u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2626void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2627u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2628void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2629
2630void r100_pll_errata_after_index(struct radeon_device *rdev);
2631
2632
2633/*
2634 * ASICs helpers.
2635 */
2636#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2637 (rdev->pdev->device == 0x5969))
2638#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2639 (rdev->family == CHIP_RV200) || \
2640 (rdev->family == CHIP_RS100) || \
2641 (rdev->family == CHIP_RS200) || \
2642 (rdev->family == CHIP_RV250) || \
2643 (rdev->family == CHIP_RV280) || \
2644 (rdev->family == CHIP_RS300))
2645#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2646 (rdev->family == CHIP_RV350) || \
2647 (rdev->family == CHIP_R350) || \
2648 (rdev->family == CHIP_RV380) || \
2649 (rdev->family == CHIP_R420) || \
2650 (rdev->family == CHIP_R423) || \
2651 (rdev->family == CHIP_RV410) || \
2652 (rdev->family == CHIP_RS400) || \
2653 (rdev->family == CHIP_RS480))
2654#define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2655 (rdev->pdev->device == 0x9443) || \
2656 (rdev->pdev->device == 0x944B) || \
2657 (rdev->pdev->device == 0x9506) || \
2658 (rdev->pdev->device == 0x9509) || \
2659 (rdev->pdev->device == 0x950F) || \
2660 (rdev->pdev->device == 0x689C) || \
2661 (rdev->pdev->device == 0x689D))
2662#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2663#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2664 (rdev->family == CHIP_RS690) || \
2665 (rdev->family == CHIP_RS740) || \
2666 (rdev->family >= CHIP_R600))
2667#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2668#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2669#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2670#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2671 (rdev->flags & RADEON_IS_IGP))
2672#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2673#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2674#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2675 (rdev->flags & RADEON_IS_IGP))
2676#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2677#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2678#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2679#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2680#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2681#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2682 (rdev->family == CHIP_MULLINS))
2683
2684#define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2685 (rdev->pdev->device == 0x6850) || \
2686 (rdev->pdev->device == 0x6858) || \
2687 (rdev->pdev->device == 0x6859) || \
2688 (rdev->pdev->device == 0x6840) || \
2689 (rdev->pdev->device == 0x6841) || \
2690 (rdev->pdev->device == 0x6842) || \
2691 (rdev->pdev->device == 0x6843))
2692
2693/*
2694 * BIOS helpers.
2695 */
2696#define RBIOS8(i) (rdev->bios[i])
2697#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2698#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2699
2700int radeon_combios_init(struct radeon_device *rdev);
2701void radeon_combios_fini(struct radeon_device *rdev);
2702int radeon_atombios_init(struct radeon_device *rdev);
2703void radeon_atombios_fini(struct radeon_device *rdev);
2704
2705
2706/*
2707 * RING helpers.
2708 */
2709
2710/**
2711 * radeon_ring_write - write a value to the ring
2712 *
2713 * @ring: radeon_ring structure holding ring information
2714 * @v: dword (dw) value to write
2715 *
2716 * Write a value to the requested ring buffer (all asics).
2717 */
2718static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2719{
2720 if (ring->count_dw <= 0)
2721 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2722
2723 ring->ring[ring->wptr++] = v;
2724 ring->wptr &= ring->ptr_mask;
2725 ring->count_dw--;
2726 ring->ring_free_dw--;
2727}
2728
2729/*
2730 * ASICs macro.
2731 */
2732#define radeon_init(rdev) (rdev)->asic->init((rdev))
2733#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2734#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2735#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2736#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2737#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2738#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2739#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2740#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2741#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2742#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2743#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2744#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2745#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2746#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2747#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2748#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2749#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2750#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2751#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2752#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2753#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2754#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2755#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2756#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2757#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2758#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2759#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2760#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2761#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2762#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2763#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2764#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2765#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2766#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2767#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2768#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2769#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2770#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2771#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2772#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2773#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2774#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2775#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2776#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2777#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2778#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2779#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2780#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2781#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2782#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2783#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2784#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2785#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2786#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2787#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2788#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2789#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2790#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2791#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2792#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2793#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2794#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2795#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2796#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2797#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2798#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2799#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2800#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2801#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2802#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2803#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2804#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2805#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2806#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2807#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2808#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2809#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2810#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2811#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2812#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2813#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2814#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2815#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2816#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2817#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2818#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2819#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2820#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2821#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2822#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2823
2824/* Common functions */
2825/* AGP */
2826extern int radeon_gpu_reset(struct radeon_device *rdev);
2827extern void radeon_pci_config_reset(struct radeon_device *rdev);
2828extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2829extern void radeon_agp_disable(struct radeon_device *rdev);
2830extern int radeon_modeset_init(struct radeon_device *rdev);
2831extern void radeon_modeset_fini(struct radeon_device *rdev);
2832extern bool radeon_card_posted(struct radeon_device *rdev);
2833extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2834extern void radeon_update_display_priority(struct radeon_device *rdev);
2835extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2836extern void radeon_scratch_init(struct radeon_device *rdev);
2837extern void radeon_wb_fini(struct radeon_device *rdev);
2838extern int radeon_wb_init(struct radeon_device *rdev);
2839extern void radeon_wb_disable(struct radeon_device *rdev);
2840extern void radeon_surface_init(struct radeon_device *rdev);
2841extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2842extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2843extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2844extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2845extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2846extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2847 struct ttm_tt *ttm, uint64_t addr,
2848 uint32_t flags);
2849extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2850extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2851bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2852extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2853extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2854extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2855extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2856 bool fbcon, bool freeze);
2857extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2858extern void radeon_program_register_sequence(struct radeon_device *rdev,
2859 const u32 *registers,
2860 const u32 array_size);
2861struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2862
2863/* KMS */
2864
2865u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2866int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2867void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2868
2869/*
2870 * vm
2871 */
2872int radeon_vm_manager_init(struct radeon_device *rdev);
2873void radeon_vm_manager_fini(struct radeon_device *rdev);
2874int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2875void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2876struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2877 struct radeon_vm *vm,
2878 struct list_head *head);
2879struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2880 struct radeon_vm *vm, int ring);
2881void radeon_vm_flush(struct radeon_device *rdev,
2882 struct radeon_vm *vm,
2883 int ring, struct radeon_fence *fence);
2884void radeon_vm_fence(struct radeon_device *rdev,
2885 struct radeon_vm *vm,
2886 struct radeon_fence *fence);
2887uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2888int radeon_vm_update_page_directory(struct radeon_device *rdev,
2889 struct radeon_vm *vm);
2890int radeon_vm_clear_freed(struct radeon_device *rdev,
2891 struct radeon_vm *vm);
2892int radeon_vm_clear_invalids(struct radeon_device *rdev,
2893 struct radeon_vm *vm);
2894int radeon_vm_bo_update(struct radeon_device *rdev,
2895 struct radeon_bo_va *bo_va,
2896 struct ttm_resource *mem);
2897void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2898 struct radeon_bo *bo);
2899struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2900 struct radeon_bo *bo);
2901struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2902 struct radeon_vm *vm,
2903 struct radeon_bo *bo);
2904int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2905 struct radeon_bo_va *bo_va,
2906 uint64_t offset,
2907 uint32_t flags);
2908void radeon_vm_bo_rmv(struct radeon_device *rdev,
2909 struct radeon_bo_va *bo_va);
2910
2911/* audio */
2912void r600_audio_update_hdmi(struct work_struct *work);
2913struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2914struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2915void r600_audio_enable(struct radeon_device *rdev,
2916 struct r600_audio_pin *pin,
2917 u8 enable_mask);
2918void dce6_audio_enable(struct radeon_device *rdev,
2919 struct r600_audio_pin *pin,
2920 u8 enable_mask);
2921
2922/*
2923 * R600 vram scratch functions
2924 */
2925int r600_vram_scratch_init(struct radeon_device *rdev);
2926void r600_vram_scratch_fini(struct radeon_device *rdev);
2927
2928/*
2929 * r600 cs checking helper
2930 */
2931unsigned r600_mip_minify(unsigned size, unsigned level);
2932bool r600_fmt_is_valid_color(u32 format);
2933bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2934int r600_fmt_get_blocksize(u32 format);
2935int r600_fmt_get_nblocksx(u32 format, u32 w);
2936int r600_fmt_get_nblocksy(u32 format, u32 h);
2937
2938/*
2939 * r600 functions used by radeon_encoder.c
2940 */
2941struct radeon_hdmi_acr {
2942 u32 clock;
2943
2944 int n_32khz;
2945 int cts_32khz;
2946
2947 int n_44_1khz;
2948 int cts_44_1khz;
2949
2950 int n_48khz;
2951 int cts_48khz;
2952
2953};
2954
2955extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2956
2957extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2958 u32 tiling_pipe_num,
2959 u32 max_rb_num,
2960 u32 total_max_rb_num,
2961 u32 enabled_rb_mask);
2962
2963/*
2964 * evergreen functions used by radeon_encoder.c
2965 */
2966
2967extern int ni_init_microcode(struct radeon_device *rdev);
2968extern int ni_mc_load_microcode(struct radeon_device *rdev);
2969
2970/* radeon_acpi.c */
2971#if defined(CONFIG_ACPI)
2972extern int radeon_acpi_init(struct radeon_device *rdev);
2973extern void radeon_acpi_fini(struct radeon_device *rdev);
2974extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2975extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2976 u8 perf_req, bool advertise);
2977extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2978#else
2979static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2980static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2981#endif
2982
2983int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2984 struct radeon_cs_packet *pkt,
2985 unsigned idx);
2986bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2987void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2988 struct radeon_cs_packet *pkt);
2989int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2990 struct radeon_bo_list **cs_reloc,
2991 int nomm);
2992int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2993 uint32_t *vline_start_end,
2994 uint32_t *vline_status);
2995
2996/* interrupt control register helpers */
2997void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2998 u32 reg, u32 mask,
2999 bool enable, const char *name,
3000 unsigned n);
3001
3002#include "radeon_object.h"
3003
3004#endif