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1// SPDX-License-Identifier: GPL-2.0
2//
3// STMicroelectronics STM32 SPI Controller driver (master mode only)
4//
5// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8#include <linux/bitfield.h>
9#include <linux/debugfs.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/of_platform.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/pm_runtime.h>
19#include <linux/reset.h>
20#include <linux/spi/spi.h>
21
22#define DRIVER_NAME "spi_stm32"
23
24/* STM32F4 SPI registers */
25#define STM32F4_SPI_CR1 0x00
26#define STM32F4_SPI_CR2 0x04
27#define STM32F4_SPI_SR 0x08
28#define STM32F4_SPI_DR 0x0C
29#define STM32F4_SPI_I2SCFGR 0x1C
30
31/* STM32F4_SPI_CR1 bit fields */
32#define STM32F4_SPI_CR1_CPHA BIT(0)
33#define STM32F4_SPI_CR1_CPOL BIT(1)
34#define STM32F4_SPI_CR1_MSTR BIT(2)
35#define STM32F4_SPI_CR1_BR_SHIFT 3
36#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
37#define STM32F4_SPI_CR1_SPE BIT(6)
38#define STM32F4_SPI_CR1_LSBFRST BIT(7)
39#define STM32F4_SPI_CR1_SSI BIT(8)
40#define STM32F4_SPI_CR1_SSM BIT(9)
41#define STM32F4_SPI_CR1_RXONLY BIT(10)
42#define STM32F4_SPI_CR1_DFF BIT(11)
43#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
44#define STM32F4_SPI_CR1_CRCEN BIT(13)
45#define STM32F4_SPI_CR1_BIDIOE BIT(14)
46#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
47#define STM32F4_SPI_CR1_BR_MIN 0
48#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
49
50/* STM32F4_SPI_CR2 bit fields */
51#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
52#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
53#define STM32F4_SPI_CR2_SSOE BIT(2)
54#define STM32F4_SPI_CR2_FRF BIT(4)
55#define STM32F4_SPI_CR2_ERRIE BIT(5)
56#define STM32F4_SPI_CR2_RXNEIE BIT(6)
57#define STM32F4_SPI_CR2_TXEIE BIT(7)
58
59/* STM32F4_SPI_SR bit fields */
60#define STM32F4_SPI_SR_RXNE BIT(0)
61#define STM32F4_SPI_SR_TXE BIT(1)
62#define STM32F4_SPI_SR_CHSIDE BIT(2)
63#define STM32F4_SPI_SR_UDR BIT(3)
64#define STM32F4_SPI_SR_CRCERR BIT(4)
65#define STM32F4_SPI_SR_MODF BIT(5)
66#define STM32F4_SPI_SR_OVR BIT(6)
67#define STM32F4_SPI_SR_BSY BIT(7)
68#define STM32F4_SPI_SR_FRE BIT(8)
69
70/* STM32F4_SPI_I2SCFGR bit fields */
71#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
72
73/* STM32F4 SPI Baud Rate min/max divisor */
74#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
75#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
76
77/* STM32H7 SPI registers */
78#define STM32H7_SPI_CR1 0x00
79#define STM32H7_SPI_CR2 0x04
80#define STM32H7_SPI_CFG1 0x08
81#define STM32H7_SPI_CFG2 0x0C
82#define STM32H7_SPI_IER 0x10
83#define STM32H7_SPI_SR 0x14
84#define STM32H7_SPI_IFCR 0x18
85#define STM32H7_SPI_TXDR 0x20
86#define STM32H7_SPI_RXDR 0x30
87#define STM32H7_SPI_I2SCFGR 0x50
88
89/* STM32H7_SPI_CR1 bit fields */
90#define STM32H7_SPI_CR1_SPE BIT(0)
91#define STM32H7_SPI_CR1_MASRX BIT(8)
92#define STM32H7_SPI_CR1_CSTART BIT(9)
93#define STM32H7_SPI_CR1_CSUSP BIT(10)
94#define STM32H7_SPI_CR1_HDDIR BIT(11)
95#define STM32H7_SPI_CR1_SSI BIT(12)
96
97/* STM32H7_SPI_CR2 bit fields */
98#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
100
101/* STM32H7_SPI_CFG1 bit fields */
102#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
107#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108#define STM32H7_SPI_CFG1_MBR_MIN 0
109#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
110
111/* STM32H7_SPI_CFG2 bit fields */
112#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
113#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
114#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
115#define STM32H7_SPI_CFG2_MASTER BIT(22)
116#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
117#define STM32H7_SPI_CFG2_CPHA BIT(24)
118#define STM32H7_SPI_CFG2_CPOL BIT(25)
119#define STM32H7_SPI_CFG2_SSM BIT(26)
120#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
121
122/* STM32H7_SPI_IER bit fields */
123#define STM32H7_SPI_IER_RXPIE BIT(0)
124#define STM32H7_SPI_IER_TXPIE BIT(1)
125#define STM32H7_SPI_IER_DXPIE BIT(2)
126#define STM32H7_SPI_IER_EOTIE BIT(3)
127#define STM32H7_SPI_IER_TXTFIE BIT(4)
128#define STM32H7_SPI_IER_OVRIE BIT(6)
129#define STM32H7_SPI_IER_MODFIE BIT(9)
130#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
131
132/* STM32H7_SPI_SR bit fields */
133#define STM32H7_SPI_SR_RXP BIT(0)
134#define STM32H7_SPI_SR_TXP BIT(1)
135#define STM32H7_SPI_SR_EOT BIT(3)
136#define STM32H7_SPI_SR_OVR BIT(6)
137#define STM32H7_SPI_SR_MODF BIT(9)
138#define STM32H7_SPI_SR_SUSP BIT(11)
139#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
140#define STM32H7_SPI_SR_RXWNE BIT(15)
141
142/* STM32H7_SPI_IFCR bit fields */
143#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
144
145/* STM32H7_SPI_I2SCFGR bit fields */
146#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
147
148/* STM32H7 SPI Master Baud Rate min/max divisor */
149#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
150#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
151
152/* STM32H7 SPI Communication mode */
153#define STM32H7_SPI_FULL_DUPLEX 0
154#define STM32H7_SPI_SIMPLEX_TX 1
155#define STM32H7_SPI_SIMPLEX_RX 2
156#define STM32H7_SPI_HALF_DUPLEX 3
157
158/* SPI Communication type */
159#define SPI_FULL_DUPLEX 0
160#define SPI_SIMPLEX_TX 1
161#define SPI_SIMPLEX_RX 2
162#define SPI_3WIRE_TX 3
163#define SPI_3WIRE_RX 4
164
165#define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
166
167/*
168 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
169 * without fifo buffers.
170 */
171#define SPI_DMA_MIN_BYTES 16
172
173/**
174 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
175 * @reg: register offset
176 * @mask: bitfield mask
177 * @shift: left shift
178 */
179struct stm32_spi_reg {
180 int reg;
181 int mask;
182 int shift;
183};
184
185/**
186 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
187 * @en: enable register and SPI enable bit
188 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
189 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
190 * @cpol: clock polarity register and polarity bit
191 * @cpha: clock phase register and phase bit
192 * @lsb_first: LSB transmitted first register and bit
193 * @br: baud rate register and bitfields
194 * @rx: SPI RX data register
195 * @tx: SPI TX data register
196 */
197struct stm32_spi_regspec {
198 const struct stm32_spi_reg en;
199 const struct stm32_spi_reg dma_rx_en;
200 const struct stm32_spi_reg dma_tx_en;
201 const struct stm32_spi_reg cpol;
202 const struct stm32_spi_reg cpha;
203 const struct stm32_spi_reg lsb_first;
204 const struct stm32_spi_reg br;
205 const struct stm32_spi_reg rx;
206 const struct stm32_spi_reg tx;
207};
208
209struct stm32_spi;
210
211/**
212 * struct stm32_spi_cfg - stm32 compatible configuration data
213 * @regs: registers descriptions
214 * @get_fifo_size: routine to get fifo size
215 * @get_bpw_mask: routine to get bits per word mask
216 * @disable: routine to disable controller
217 * @config: routine to configure controller as SPI Master
218 * @set_bpw: routine to configure registers to for bits per word
219 * @set_mode: routine to configure registers to desired mode
220 * @set_data_idleness: optional routine to configure registers to desired idle
221 * time between frames (if driver has this functionality)
222 * @set_number_of_data: optional routine to configure registers to desired
223 * number of data (if driver has this functionality)
224 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
225 * using DMA
226 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
227 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
228 * @transfer_one_irq: routine to configure interrupts for driver
229 * @irq_handler_event: Interrupt handler for SPI controller events
230 * @irq_handler_thread: thread of interrupt handler for SPI controller
231 * @baud_rate_div_min: minimum baud rate divisor
232 * @baud_rate_div_max: maximum baud rate divisor
233 * @has_fifo: boolean to know if fifo is used for driver
234 * @flags: compatible specific SPI controller flags used at registration time
235 */
236struct stm32_spi_cfg {
237 const struct stm32_spi_regspec *regs;
238 int (*get_fifo_size)(struct stm32_spi *spi);
239 int (*get_bpw_mask)(struct stm32_spi *spi);
240 void (*disable)(struct stm32_spi *spi);
241 int (*config)(struct stm32_spi *spi);
242 void (*set_bpw)(struct stm32_spi *spi);
243 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
244 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
245 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
246 void (*transfer_one_dma_start)(struct stm32_spi *spi);
247 void (*dma_rx_cb)(void *data);
248 void (*dma_tx_cb)(void *data);
249 int (*transfer_one_irq)(struct stm32_spi *spi);
250 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
251 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
252 unsigned int baud_rate_div_min;
253 unsigned int baud_rate_div_max;
254 bool has_fifo;
255 u16 flags;
256};
257
258/**
259 * struct stm32_spi - private data of the SPI controller
260 * @dev: driver model representation of the controller
261 * @master: controller master interface
262 * @cfg: compatible configuration data
263 * @base: virtual memory area
264 * @clk: hw kernel clock feeding the SPI clock generator
265 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
266 * @lock: prevent I/O concurrent access
267 * @irq: SPI controller interrupt line
268 * @fifo_size: size of the embedded fifo in bytes
269 * @cur_midi: master inter-data idleness in ns
270 * @cur_speed: speed configured in Hz
271 * @cur_bpw: number of bits in a single SPI data frame
272 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
273 * @cur_comm: SPI communication mode
274 * @cur_xferlen: current transfer length in bytes
275 * @cur_usedma: boolean to know if dma is used in current transfer
276 * @tx_buf: data to be written, or NULL
277 * @rx_buf: data to be read, or NULL
278 * @tx_len: number of data to be written in bytes
279 * @rx_len: number of data to be read in bytes
280 * @dma_tx: dma channel for TX transfer
281 * @dma_rx: dma channel for RX transfer
282 * @phys_addr: SPI registers physical base address
283 */
284struct stm32_spi {
285 struct device *dev;
286 struct spi_master *master;
287 const struct stm32_spi_cfg *cfg;
288 void __iomem *base;
289 struct clk *clk;
290 u32 clk_rate;
291 spinlock_t lock; /* prevent I/O concurrent access */
292 int irq;
293 unsigned int fifo_size;
294
295 unsigned int cur_midi;
296 unsigned int cur_speed;
297 unsigned int cur_bpw;
298 unsigned int cur_fthlv;
299 unsigned int cur_comm;
300 unsigned int cur_xferlen;
301 bool cur_usedma;
302
303 const void *tx_buf;
304 void *rx_buf;
305 int tx_len;
306 int rx_len;
307 struct dma_chan *dma_tx;
308 struct dma_chan *dma_rx;
309 dma_addr_t phys_addr;
310};
311
312static const struct stm32_spi_regspec stm32f4_spi_regspec = {
313 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
314
315 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
316 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
317
318 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
319 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
320 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
321 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
322
323 .rx = { STM32F4_SPI_DR },
324 .tx = { STM32F4_SPI_DR },
325};
326
327static const struct stm32_spi_regspec stm32h7_spi_regspec = {
328 /* SPI data transfer is enabled but spi_ker_ck is idle.
329 * CFG1 and CFG2 registers are write protected when SPE is enabled.
330 */
331 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
332
333 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
334 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
335
336 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
337 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
338 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
339 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
340 STM32H7_SPI_CFG1_MBR_SHIFT },
341
342 .rx = { STM32H7_SPI_RXDR },
343 .tx = { STM32H7_SPI_TXDR },
344};
345
346static inline void stm32_spi_set_bits(struct stm32_spi *spi,
347 u32 offset, u32 bits)
348{
349 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
350 spi->base + offset);
351}
352
353static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
354 u32 offset, u32 bits)
355{
356 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
357 spi->base + offset);
358}
359
360/**
361 * stm32h7_spi_get_fifo_size - Return fifo size
362 * @spi: pointer to the spi controller data structure
363 */
364static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
365{
366 unsigned long flags;
367 u32 count = 0;
368
369 spin_lock_irqsave(&spi->lock, flags);
370
371 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
372
373 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
374 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
375
376 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
377
378 spin_unlock_irqrestore(&spi->lock, flags);
379
380 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
381
382 return count;
383}
384
385/**
386 * stm32f4_spi_get_bpw_mask - Return bits per word mask
387 * @spi: pointer to the spi controller data structure
388 */
389static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
390{
391 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
392 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
393}
394
395/**
396 * stm32h7_spi_get_bpw_mask - Return bits per word mask
397 * @spi: pointer to the spi controller data structure
398 */
399static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
400{
401 unsigned long flags;
402 u32 cfg1, max_bpw;
403
404 spin_lock_irqsave(&spi->lock, flags);
405
406 /*
407 * The most significant bit at DSIZE bit field is reserved when the
408 * maximum data size of periperal instances is limited to 16-bit
409 */
410 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
411
412 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
413 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
414
415 spin_unlock_irqrestore(&spi->lock, flags);
416
417 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
418
419 return SPI_BPW_RANGE_MASK(4, max_bpw);
420}
421
422/**
423 * stm32_spi_prepare_mbr - Determine baud rate divisor value
424 * @spi: pointer to the spi controller data structure
425 * @speed_hz: requested speed
426 * @min_div: minimum baud rate divisor
427 * @max_div: maximum baud rate divisor
428 *
429 * Return baud rate divisor value in case of success or -EINVAL
430 */
431static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
432 u32 min_div, u32 max_div)
433{
434 u32 div, mbrdiv;
435
436 /* Ensure spi->clk_rate is even */
437 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
438
439 /*
440 * SPI framework set xfer->speed_hz to master->max_speed_hz if
441 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
442 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
443 * no need to check it there.
444 * However, we need to ensure the following calculations.
445 */
446 if ((div < min_div) || (div > max_div))
447 return -EINVAL;
448
449 /* Determine the first power of 2 greater than or equal to div */
450 if (div & (div - 1))
451 mbrdiv = fls(div);
452 else
453 mbrdiv = fls(div) - 1;
454
455 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
456
457 return mbrdiv - 1;
458}
459
460/**
461 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
462 * @spi: pointer to the spi controller data structure
463 * @xfer_len: length of the message to be transferred
464 */
465static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
466{
467 u32 packet, bpw;
468
469 /* data packet should not exceed 1/2 of fifo space */
470 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
471
472 /* align packet size with data registers access */
473 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
474 return DIV_ROUND_UP(packet, bpw);
475}
476
477/**
478 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
479 * @spi: pointer to the spi controller data structure
480 *
481 * Read from tx_buf depends on remaining bytes to avoid to read beyond
482 * tx_buf end.
483 */
484static void stm32f4_spi_write_tx(struct stm32_spi *spi)
485{
486 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
487 STM32F4_SPI_SR_TXE)) {
488 u32 offs = spi->cur_xferlen - spi->tx_len;
489
490 if (spi->cur_bpw == 16) {
491 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
492
493 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
494 spi->tx_len -= sizeof(u16);
495 } else {
496 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
497
498 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
499 spi->tx_len -= sizeof(u8);
500 }
501 }
502
503 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
504}
505
506/**
507 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
508 * @spi: pointer to the spi controller data structure
509 *
510 * Read from tx_buf depends on remaining bytes to avoid to read beyond
511 * tx_buf end.
512 */
513static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
514{
515 while ((spi->tx_len > 0) &&
516 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
517 STM32H7_SPI_SR_TXP)) {
518 u32 offs = spi->cur_xferlen - spi->tx_len;
519
520 if (spi->tx_len >= sizeof(u32)) {
521 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
522
523 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
524 spi->tx_len -= sizeof(u32);
525 } else if (spi->tx_len >= sizeof(u16)) {
526 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
527
528 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
529 spi->tx_len -= sizeof(u16);
530 } else {
531 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
532
533 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
534 spi->tx_len -= sizeof(u8);
535 }
536 }
537
538 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
539}
540
541/**
542 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
543 * @spi: pointer to the spi controller data structure
544 *
545 * Write in rx_buf depends on remaining bytes to avoid to write beyond
546 * rx_buf end.
547 */
548static void stm32f4_spi_read_rx(struct stm32_spi *spi)
549{
550 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
551 STM32F4_SPI_SR_RXNE)) {
552 u32 offs = spi->cur_xferlen - spi->rx_len;
553
554 if (spi->cur_bpw == 16) {
555 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
556
557 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
558 spi->rx_len -= sizeof(u16);
559 } else {
560 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
561
562 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
563 spi->rx_len -= sizeof(u8);
564 }
565 }
566
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
568}
569
570/**
571 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
572 * @spi: pointer to the spi controller data structure
573 *
574 * Write in rx_buf depends on remaining bytes to avoid to write beyond
575 * rx_buf end.
576 */
577static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
578{
579 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
580 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
581
582 while ((spi->rx_len > 0) &&
583 ((sr & STM32H7_SPI_SR_RXP) ||
584 ((sr & STM32H7_SPI_SR_EOT) &&
585 ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
586 u32 offs = spi->cur_xferlen - spi->rx_len;
587
588 if ((spi->rx_len >= sizeof(u32)) ||
589 (sr & STM32H7_SPI_SR_RXWNE)) {
590 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
591
592 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
593 spi->rx_len -= sizeof(u32);
594 } else if ((spi->rx_len >= sizeof(u16)) ||
595 (!(sr & STM32H7_SPI_SR_RXWNE) &&
596 (rxplvl >= 2 || spi->cur_bpw > 8))) {
597 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
598
599 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
600 spi->rx_len -= sizeof(u16);
601 } else {
602 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
603
604 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
605 spi->rx_len -= sizeof(u8);
606 }
607
608 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
609 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
610 }
611
612 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
613 __func__, spi->rx_len, sr);
614}
615
616/**
617 * stm32_spi_enable - Enable SPI controller
618 * @spi: pointer to the spi controller data structure
619 */
620static void stm32_spi_enable(struct stm32_spi *spi)
621{
622 dev_dbg(spi->dev, "enable controller\n");
623
624 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
625 spi->cfg->regs->en.mask);
626}
627
628/**
629 * stm32f4_spi_disable - Disable SPI controller
630 * @spi: pointer to the spi controller data structure
631 */
632static void stm32f4_spi_disable(struct stm32_spi *spi)
633{
634 unsigned long flags;
635 u32 sr;
636
637 dev_dbg(spi->dev, "disable controller\n");
638
639 spin_lock_irqsave(&spi->lock, flags);
640
641 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
642 STM32F4_SPI_CR1_SPE)) {
643 spin_unlock_irqrestore(&spi->lock, flags);
644 return;
645 }
646
647 /* Disable interrupts */
648 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
649 STM32F4_SPI_CR2_RXNEIE |
650 STM32F4_SPI_CR2_ERRIE);
651
652 /* Wait until BSY = 0 */
653 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
654 sr, !(sr & STM32F4_SPI_SR_BSY),
655 10, 100000) < 0) {
656 dev_warn(spi->dev, "disabling condition timeout\n");
657 }
658
659 if (spi->cur_usedma && spi->dma_tx)
660 dmaengine_terminate_all(spi->dma_tx);
661 if (spi->cur_usedma && spi->dma_rx)
662 dmaengine_terminate_all(spi->dma_rx);
663
664 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
665
666 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
667 STM32F4_SPI_CR2_RXDMAEN);
668
669 /* Sequence to clear OVR flag */
670 readl_relaxed(spi->base + STM32F4_SPI_DR);
671 readl_relaxed(spi->base + STM32F4_SPI_SR);
672
673 spin_unlock_irqrestore(&spi->lock, flags);
674}
675
676/**
677 * stm32h7_spi_disable - Disable SPI controller
678 * @spi: pointer to the spi controller data structure
679 *
680 * RX-Fifo is flushed when SPI controller is disabled.
681 */
682static void stm32h7_spi_disable(struct stm32_spi *spi)
683{
684 unsigned long flags;
685 u32 cr1;
686
687 dev_dbg(spi->dev, "disable controller\n");
688
689 spin_lock_irqsave(&spi->lock, flags);
690
691 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
692
693 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
694 spin_unlock_irqrestore(&spi->lock, flags);
695 return;
696 }
697
698 if (spi->cur_usedma && spi->dma_tx)
699 dmaengine_terminate_all(spi->dma_tx);
700 if (spi->cur_usedma && spi->dma_rx)
701 dmaengine_terminate_all(spi->dma_rx);
702
703 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
704
705 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
706 STM32H7_SPI_CFG1_RXDMAEN);
707
708 /* Disable interrupts and clear status flags */
709 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
710 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
711
712 spin_unlock_irqrestore(&spi->lock, flags);
713}
714
715/**
716 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
717 * @master: controller master interface
718 * @spi_dev: pointer to the spi device
719 * @transfer: pointer to spi transfer
720 *
721 * If driver has fifo and the current transfer size is greater than fifo size,
722 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
723 */
724static bool stm32_spi_can_dma(struct spi_master *master,
725 struct spi_device *spi_dev,
726 struct spi_transfer *transfer)
727{
728 unsigned int dma_size;
729 struct stm32_spi *spi = spi_master_get_devdata(master);
730
731 if (spi->cfg->has_fifo)
732 dma_size = spi->fifo_size;
733 else
734 dma_size = SPI_DMA_MIN_BYTES;
735
736 dev_dbg(spi->dev, "%s: %s\n", __func__,
737 (transfer->len > dma_size) ? "true" : "false");
738
739 return (transfer->len > dma_size);
740}
741
742/**
743 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
744 * @irq: interrupt line
745 * @dev_id: SPI controller master interface
746 */
747static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
748{
749 struct spi_master *master = dev_id;
750 struct stm32_spi *spi = spi_master_get_devdata(master);
751 u32 sr, mask = 0;
752 bool end = false;
753
754 spin_lock(&spi->lock);
755
756 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
757 /*
758 * BSY flag is not handled in interrupt but it is normal behavior when
759 * this flag is set.
760 */
761 sr &= ~STM32F4_SPI_SR_BSY;
762
763 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
764 spi->cur_comm == SPI_3WIRE_TX)) {
765 /* OVR flag shouldn't be handled for TX only mode */
766 sr &= ~(STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE);
767 mask |= STM32F4_SPI_SR_TXE;
768 }
769
770 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
771 spi->cur_comm == SPI_SIMPLEX_RX ||
772 spi->cur_comm == SPI_3WIRE_RX)) {
773 /* TXE flag is set and is handled when RXNE flag occurs */
774 sr &= ~STM32F4_SPI_SR_TXE;
775 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
776 }
777
778 if (!(sr & mask)) {
779 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
780 spin_unlock(&spi->lock);
781 return IRQ_NONE;
782 }
783
784 if (sr & STM32F4_SPI_SR_OVR) {
785 dev_warn(spi->dev, "Overrun: received value discarded\n");
786
787 /* Sequence to clear OVR flag */
788 readl_relaxed(spi->base + STM32F4_SPI_DR);
789 readl_relaxed(spi->base + STM32F4_SPI_SR);
790
791 /*
792 * If overrun is detected, it means that something went wrong,
793 * so stop the current transfer. Transfer can wait for next
794 * RXNE but DR is already read and end never happens.
795 */
796 end = true;
797 goto end_irq;
798 }
799
800 if (sr & STM32F4_SPI_SR_TXE) {
801 if (spi->tx_buf)
802 stm32f4_spi_write_tx(spi);
803 if (spi->tx_len == 0)
804 end = true;
805 }
806
807 if (sr & STM32F4_SPI_SR_RXNE) {
808 stm32f4_spi_read_rx(spi);
809 if (spi->rx_len == 0)
810 end = true;
811 else if (spi->tx_buf)/* Load data for discontinuous mode */
812 stm32f4_spi_write_tx(spi);
813 }
814
815end_irq:
816 if (end) {
817 /* Immediately disable interrupts to do not generate new one */
818 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
819 STM32F4_SPI_CR2_TXEIE |
820 STM32F4_SPI_CR2_RXNEIE |
821 STM32F4_SPI_CR2_ERRIE);
822 spin_unlock(&spi->lock);
823 return IRQ_WAKE_THREAD;
824 }
825
826 spin_unlock(&spi->lock);
827 return IRQ_HANDLED;
828}
829
830/**
831 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
832 * @irq: interrupt line
833 * @dev_id: SPI controller master interface
834 */
835static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
836{
837 struct spi_master *master = dev_id;
838 struct stm32_spi *spi = spi_master_get_devdata(master);
839
840 spi_finalize_current_transfer(master);
841 stm32f4_spi_disable(spi);
842
843 return IRQ_HANDLED;
844}
845
846/**
847 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
848 * @irq: interrupt line
849 * @dev_id: SPI controller master interface
850 */
851static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
852{
853 struct spi_master *master = dev_id;
854 struct stm32_spi *spi = spi_master_get_devdata(master);
855 u32 sr, ier, mask;
856 unsigned long flags;
857 bool end = false;
858
859 spin_lock_irqsave(&spi->lock, flags);
860
861 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
862 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
863
864 mask = ier;
865 /*
866 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
867 * SUSP to acknowledge it later. TXC is automatically cleared
868 */
869
870 mask |= STM32H7_SPI_SR_SUSP;
871 /*
872 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
873 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
874 */
875 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
876 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
877
878 if (!(sr & mask)) {
879 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
880 sr, ier);
881 spin_unlock_irqrestore(&spi->lock, flags);
882 return IRQ_NONE;
883 }
884
885 if (sr & STM32H7_SPI_SR_SUSP) {
886 static DEFINE_RATELIMIT_STATE(rs,
887 DEFAULT_RATELIMIT_INTERVAL * 10,
888 1);
889 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
890 if (__ratelimit(&rs))
891 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
892 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
893 stm32h7_spi_read_rxfifo(spi);
894 /*
895 * If communication is suspended while using DMA, it means
896 * that something went wrong, so stop the current transfer
897 */
898 if (spi->cur_usedma)
899 end = true;
900 }
901
902 if (sr & STM32H7_SPI_SR_MODF) {
903 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
904 end = true;
905 }
906
907 if (sr & STM32H7_SPI_SR_OVR) {
908 dev_err(spi->dev, "Overrun: RX data lost\n");
909 end = true;
910 }
911
912 if (sr & STM32H7_SPI_SR_EOT) {
913 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
914 stm32h7_spi_read_rxfifo(spi);
915 if (!spi->cur_usedma ||
916 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
917 end = true;
918 }
919
920 if (sr & STM32H7_SPI_SR_TXP)
921 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
922 stm32h7_spi_write_txfifo(spi);
923
924 if (sr & STM32H7_SPI_SR_RXP)
925 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
926 stm32h7_spi_read_rxfifo(spi);
927
928 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
929
930 spin_unlock_irqrestore(&spi->lock, flags);
931
932 if (end) {
933 stm32h7_spi_disable(spi);
934 spi_finalize_current_transfer(master);
935 }
936
937 return IRQ_HANDLED;
938}
939
940/**
941 * stm32_spi_prepare_msg - set up the controller to transfer a single message
942 * @master: controller master interface
943 * @msg: pointer to spi message
944 */
945static int stm32_spi_prepare_msg(struct spi_master *master,
946 struct spi_message *msg)
947{
948 struct stm32_spi *spi = spi_master_get_devdata(master);
949 struct spi_device *spi_dev = msg->spi;
950 struct device_node *np = spi_dev->dev.of_node;
951 unsigned long flags;
952 u32 clrb = 0, setb = 0;
953
954 /* SPI slave device may need time between data frames */
955 spi->cur_midi = 0;
956 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
957 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
958
959 if (spi_dev->mode & SPI_CPOL)
960 setb |= spi->cfg->regs->cpol.mask;
961 else
962 clrb |= spi->cfg->regs->cpol.mask;
963
964 if (spi_dev->mode & SPI_CPHA)
965 setb |= spi->cfg->regs->cpha.mask;
966 else
967 clrb |= spi->cfg->regs->cpha.mask;
968
969 if (spi_dev->mode & SPI_LSB_FIRST)
970 setb |= spi->cfg->regs->lsb_first.mask;
971 else
972 clrb |= spi->cfg->regs->lsb_first.mask;
973
974 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
975 !!(spi_dev->mode & SPI_CPOL),
976 !!(spi_dev->mode & SPI_CPHA),
977 !!(spi_dev->mode & SPI_LSB_FIRST),
978 !!(spi_dev->mode & SPI_CS_HIGH));
979
980 /* On STM32H7, messages should not exceed a maximum size setted
981 * afterward via the set_number_of_data function. In order to
982 * ensure that, split large messages into several messages
983 */
984 if (spi->cfg->set_number_of_data) {
985 int ret;
986
987 ret = spi_split_transfers_maxsize(master, msg,
988 STM32H7_SPI_TSIZE_MAX,
989 GFP_KERNEL | GFP_DMA);
990 if (ret)
991 return ret;
992 }
993
994 spin_lock_irqsave(&spi->lock, flags);
995
996 /* CPOL, CPHA and LSB FIRST bits have common register */
997 if (clrb || setb)
998 writel_relaxed(
999 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1000 ~clrb) | setb,
1001 spi->base + spi->cfg->regs->cpol.reg);
1002
1003 spin_unlock_irqrestore(&spi->lock, flags);
1004
1005 return 0;
1006}
1007
1008/**
1009 * stm32f4_spi_dma_tx_cb - dma callback
1010 * @data: pointer to the spi controller data structure
1011 *
1012 * DMA callback is called when the transfer is complete for DMA TX channel.
1013 */
1014static void stm32f4_spi_dma_tx_cb(void *data)
1015{
1016 struct stm32_spi *spi = data;
1017
1018 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1019 spi_finalize_current_transfer(spi->master);
1020 stm32f4_spi_disable(spi);
1021 }
1022}
1023
1024/**
1025 * stm32_spi_dma_rx_cb - dma callback
1026 * @data: pointer to the spi controller data structure
1027 *
1028 * DMA callback is called when the transfer is complete for DMA RX channel.
1029 */
1030static void stm32_spi_dma_rx_cb(void *data)
1031{
1032 struct stm32_spi *spi = data;
1033
1034 spi_finalize_current_transfer(spi->master);
1035 spi->cfg->disable(spi);
1036}
1037
1038/**
1039 * stm32_spi_dma_config - configure dma slave channel depending on current
1040 * transfer bits_per_word.
1041 * @spi: pointer to the spi controller data structure
1042 * @dma_conf: pointer to the dma_slave_config structure
1043 * @dir: direction of the dma transfer
1044 */
1045static void stm32_spi_dma_config(struct stm32_spi *spi,
1046 struct dma_slave_config *dma_conf,
1047 enum dma_transfer_direction dir)
1048{
1049 enum dma_slave_buswidth buswidth;
1050 u32 maxburst;
1051
1052 if (spi->cur_bpw <= 8)
1053 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1054 else if (spi->cur_bpw <= 16)
1055 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1056 else
1057 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1058
1059 if (spi->cfg->has_fifo) {
1060 /* Valid for DMA Half or Full Fifo threshold */
1061 if (spi->cur_fthlv == 2)
1062 maxburst = 1;
1063 else
1064 maxburst = spi->cur_fthlv;
1065 } else {
1066 maxburst = 1;
1067 }
1068
1069 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1070 dma_conf->direction = dir;
1071 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1072 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1073 dma_conf->src_addr_width = buswidth;
1074 dma_conf->src_maxburst = maxburst;
1075
1076 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1077 buswidth, maxburst);
1078 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1079 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1080 dma_conf->dst_addr_width = buswidth;
1081 dma_conf->dst_maxburst = maxburst;
1082
1083 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1084 buswidth, maxburst);
1085 }
1086}
1087
1088/**
1089 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1090 * interrupts
1091 * @spi: pointer to the spi controller data structure
1092 *
1093 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1094 * in progress.
1095 */
1096static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1097{
1098 unsigned long flags;
1099 u32 cr2 = 0;
1100
1101 /* Enable the interrupts relative to the current communication mode */
1102 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1103 cr2 |= STM32F4_SPI_CR2_TXEIE;
1104 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1105 spi->cur_comm == SPI_SIMPLEX_RX ||
1106 spi->cur_comm == SPI_3WIRE_RX) {
1107 /* In transmit-only mode, the OVR flag is set in the SR register
1108 * since the received data are never read. Therefore set OVR
1109 * interrupt only when rx buffer is available.
1110 */
1111 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1112 } else {
1113 return -EINVAL;
1114 }
1115
1116 spin_lock_irqsave(&spi->lock, flags);
1117
1118 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1119
1120 stm32_spi_enable(spi);
1121
1122 /* starting data transfer when buffer is loaded */
1123 if (spi->tx_buf)
1124 stm32f4_spi_write_tx(spi);
1125
1126 spin_unlock_irqrestore(&spi->lock, flags);
1127
1128 return 1;
1129}
1130
1131/**
1132 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1133 * interrupts
1134 * @spi: pointer to the spi controller data structure
1135 *
1136 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1137 * in progress.
1138 */
1139static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1140{
1141 unsigned long flags;
1142 u32 ier = 0;
1143
1144 /* Enable the interrupts relative to the current communication mode */
1145 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1146 ier |= STM32H7_SPI_IER_DXPIE;
1147 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1148 ier |= STM32H7_SPI_IER_TXPIE;
1149 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1150 ier |= STM32H7_SPI_IER_RXPIE;
1151
1152 /* Enable the interrupts relative to the end of transfer */
1153 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1154 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1155
1156 spin_lock_irqsave(&spi->lock, flags);
1157
1158 stm32_spi_enable(spi);
1159
1160 /* Be sure to have data in fifo before starting data transfer */
1161 if (spi->tx_buf)
1162 stm32h7_spi_write_txfifo(spi);
1163
1164 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1165
1166 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1167
1168 spin_unlock_irqrestore(&spi->lock, flags);
1169
1170 return 1;
1171}
1172
1173/**
1174 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1175 * transfer using DMA
1176 * @spi: pointer to the spi controller data structure
1177 */
1178static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1179{
1180 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1181 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1182 spi->cur_comm == SPI_FULL_DUPLEX) {
1183 /*
1184 * In transmit-only mode, the OVR flag is set in the SR register
1185 * since the received data are never read. Therefore set OVR
1186 * interrupt only when rx buffer is available.
1187 */
1188 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1189 }
1190
1191 stm32_spi_enable(spi);
1192}
1193
1194/**
1195 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1196 * transfer using DMA
1197 * @spi: pointer to the spi controller data structure
1198 */
1199static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1200{
1201 uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1202
1203 /* Enable the interrupts */
1204 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1205 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1206
1207 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1208
1209 stm32_spi_enable(spi);
1210
1211 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1212}
1213
1214/**
1215 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1216 * @spi: pointer to the spi controller data structure
1217 * @xfer: pointer to the spi_transfer structure
1218 *
1219 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1220 * in progress.
1221 */
1222static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1223 struct spi_transfer *xfer)
1224{
1225 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1226 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1227 unsigned long flags;
1228
1229 spin_lock_irqsave(&spi->lock, flags);
1230
1231 rx_dma_desc = NULL;
1232 if (spi->rx_buf && spi->dma_rx) {
1233 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1234 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1235
1236 /* Enable Rx DMA request */
1237 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1238 spi->cfg->regs->dma_rx_en.mask);
1239
1240 rx_dma_desc = dmaengine_prep_slave_sg(
1241 spi->dma_rx, xfer->rx_sg.sgl,
1242 xfer->rx_sg.nents,
1243 rx_dma_conf.direction,
1244 DMA_PREP_INTERRUPT);
1245 }
1246
1247 tx_dma_desc = NULL;
1248 if (spi->tx_buf && spi->dma_tx) {
1249 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1250 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1251
1252 tx_dma_desc = dmaengine_prep_slave_sg(
1253 spi->dma_tx, xfer->tx_sg.sgl,
1254 xfer->tx_sg.nents,
1255 tx_dma_conf.direction,
1256 DMA_PREP_INTERRUPT);
1257 }
1258
1259 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1260 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1261 goto dma_desc_error;
1262
1263 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1264 goto dma_desc_error;
1265
1266 if (rx_dma_desc) {
1267 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1268 rx_dma_desc->callback_param = spi;
1269
1270 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1271 dev_err(spi->dev, "Rx DMA submit failed\n");
1272 goto dma_desc_error;
1273 }
1274 /* Enable Rx DMA channel */
1275 dma_async_issue_pending(spi->dma_rx);
1276 }
1277
1278 if (tx_dma_desc) {
1279 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1280 spi->cur_comm == SPI_3WIRE_TX) {
1281 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1282 tx_dma_desc->callback_param = spi;
1283 }
1284
1285 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1286 dev_err(spi->dev, "Tx DMA submit failed\n");
1287 goto dma_submit_error;
1288 }
1289 /* Enable Tx DMA channel */
1290 dma_async_issue_pending(spi->dma_tx);
1291
1292 /* Enable Tx DMA request */
1293 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1294 spi->cfg->regs->dma_tx_en.mask);
1295 }
1296
1297 spi->cfg->transfer_one_dma_start(spi);
1298
1299 spin_unlock_irqrestore(&spi->lock, flags);
1300
1301 return 1;
1302
1303dma_submit_error:
1304 if (spi->dma_rx)
1305 dmaengine_terminate_all(spi->dma_rx);
1306
1307dma_desc_error:
1308 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1309 spi->cfg->regs->dma_rx_en.mask);
1310
1311 spin_unlock_irqrestore(&spi->lock, flags);
1312
1313 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1314
1315 spi->cur_usedma = false;
1316 return spi->cfg->transfer_one_irq(spi);
1317}
1318
1319/**
1320 * stm32f4_spi_set_bpw - Configure bits per word
1321 * @spi: pointer to the spi controller data structure
1322 */
1323static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1324{
1325 if (spi->cur_bpw == 16)
1326 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1327 else
1328 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1329}
1330
1331/**
1332 * stm32h7_spi_set_bpw - configure bits per word
1333 * @spi: pointer to the spi controller data structure
1334 */
1335static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1336{
1337 u32 bpw, fthlv;
1338 u32 cfg1_clrb = 0, cfg1_setb = 0;
1339
1340 bpw = spi->cur_bpw - 1;
1341
1342 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1343 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1344
1345 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1346 fthlv = spi->cur_fthlv - 1;
1347
1348 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1349 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1350
1351 writel_relaxed(
1352 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1353 ~cfg1_clrb) | cfg1_setb,
1354 spi->base + STM32H7_SPI_CFG1);
1355}
1356
1357/**
1358 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1359 * @spi: pointer to the spi controller data structure
1360 * @mbrdiv: baud rate divisor value
1361 */
1362static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1363{
1364 u32 clrb = 0, setb = 0;
1365
1366 clrb |= spi->cfg->regs->br.mask;
1367 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1368
1369 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1370 ~clrb) | setb,
1371 spi->base + spi->cfg->regs->br.reg);
1372}
1373
1374/**
1375 * stm32_spi_communication_type - return transfer communication type
1376 * @spi_dev: pointer to the spi device
1377 * @transfer: pointer to spi transfer
1378 */
1379static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1380 struct spi_transfer *transfer)
1381{
1382 unsigned int type = SPI_FULL_DUPLEX;
1383
1384 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1385 /*
1386 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1387 * is forbidden and unvalidated by SPI subsystem so depending
1388 * on the valid buffer, we can determine the direction of the
1389 * transfer.
1390 */
1391 if (!transfer->tx_buf)
1392 type = SPI_3WIRE_RX;
1393 else
1394 type = SPI_3WIRE_TX;
1395 } else {
1396 if (!transfer->tx_buf)
1397 type = SPI_SIMPLEX_RX;
1398 else if (!transfer->rx_buf)
1399 type = SPI_SIMPLEX_TX;
1400 }
1401
1402 return type;
1403}
1404
1405/**
1406 * stm32f4_spi_set_mode - configure communication mode
1407 * @spi: pointer to the spi controller data structure
1408 * @comm_type: type of communication to configure
1409 */
1410static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1411{
1412 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1413 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1414 STM32F4_SPI_CR1_BIDIMODE |
1415 STM32F4_SPI_CR1_BIDIOE);
1416 } else if (comm_type == SPI_FULL_DUPLEX ||
1417 comm_type == SPI_SIMPLEX_RX) {
1418 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1419 STM32F4_SPI_CR1_BIDIMODE |
1420 STM32F4_SPI_CR1_BIDIOE);
1421 } else if (comm_type == SPI_3WIRE_RX) {
1422 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1423 STM32F4_SPI_CR1_BIDIMODE);
1424 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1425 STM32F4_SPI_CR1_BIDIOE);
1426 } else {
1427 return -EINVAL;
1428 }
1429
1430 return 0;
1431}
1432
1433/**
1434 * stm32h7_spi_set_mode - configure communication mode
1435 * @spi: pointer to the spi controller data structure
1436 * @comm_type: type of communication to configure
1437 */
1438static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1439{
1440 u32 mode;
1441 u32 cfg2_clrb = 0, cfg2_setb = 0;
1442
1443 if (comm_type == SPI_3WIRE_RX) {
1444 mode = STM32H7_SPI_HALF_DUPLEX;
1445 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1446 } else if (comm_type == SPI_3WIRE_TX) {
1447 mode = STM32H7_SPI_HALF_DUPLEX;
1448 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1449 } else if (comm_type == SPI_SIMPLEX_RX) {
1450 mode = STM32H7_SPI_SIMPLEX_RX;
1451 } else if (comm_type == SPI_SIMPLEX_TX) {
1452 mode = STM32H7_SPI_SIMPLEX_TX;
1453 } else {
1454 mode = STM32H7_SPI_FULL_DUPLEX;
1455 }
1456
1457 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1458 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1459
1460 writel_relaxed(
1461 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1462 ~cfg2_clrb) | cfg2_setb,
1463 spi->base + STM32H7_SPI_CFG2);
1464
1465 return 0;
1466}
1467
1468/**
1469 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1470 * consecutive data frames in master mode
1471 * @spi: pointer to the spi controller data structure
1472 * @len: transfer len
1473 */
1474static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1475{
1476 u32 cfg2_clrb = 0, cfg2_setb = 0;
1477
1478 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1479 if ((len > 1) && (spi->cur_midi > 0)) {
1480 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1481 u32 midi = min_t(u32,
1482 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1483 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1484 STM32H7_SPI_CFG2_MIDI));
1485
1486
1487 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1488 sck_period_ns, midi, midi * sck_period_ns);
1489 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1490 }
1491
1492 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1493 ~cfg2_clrb) | cfg2_setb,
1494 spi->base + STM32H7_SPI_CFG2);
1495}
1496
1497/**
1498 * stm32h7_spi_number_of_data - configure number of data at current transfer
1499 * @spi: pointer to the spi controller data structure
1500 * @nb_words: transfer length (in words)
1501 */
1502static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1503{
1504 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1505 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1506 spi->base + STM32H7_SPI_CR2);
1507 } else {
1508 return -EMSGSIZE;
1509 }
1510
1511 return 0;
1512}
1513
1514/**
1515 * stm32_spi_transfer_one_setup - common setup to transfer a single
1516 * spi_transfer either using DMA or
1517 * interrupts.
1518 * @spi: pointer to the spi controller data structure
1519 * @spi_dev: pointer to the spi device
1520 * @transfer: pointer to spi transfer
1521 */
1522static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1523 struct spi_device *spi_dev,
1524 struct spi_transfer *transfer)
1525{
1526 unsigned long flags;
1527 unsigned int comm_type;
1528 int nb_words, ret = 0;
1529 int mbr;
1530
1531 spin_lock_irqsave(&spi->lock, flags);
1532
1533 spi->cur_xferlen = transfer->len;
1534
1535 spi->cur_bpw = transfer->bits_per_word;
1536 spi->cfg->set_bpw(spi);
1537
1538 /* Update spi->cur_speed with real clock speed */
1539 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1540 spi->cfg->baud_rate_div_min,
1541 spi->cfg->baud_rate_div_max);
1542 if (mbr < 0) {
1543 ret = mbr;
1544 goto out;
1545 }
1546
1547 transfer->speed_hz = spi->cur_speed;
1548 stm32_spi_set_mbr(spi, mbr);
1549
1550 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1551 ret = spi->cfg->set_mode(spi, comm_type);
1552 if (ret < 0)
1553 goto out;
1554
1555 spi->cur_comm = comm_type;
1556
1557 if (spi->cfg->set_data_idleness)
1558 spi->cfg->set_data_idleness(spi, transfer->len);
1559
1560 if (spi->cur_bpw <= 8)
1561 nb_words = transfer->len;
1562 else if (spi->cur_bpw <= 16)
1563 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1564 else
1565 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1566
1567 if (spi->cfg->set_number_of_data) {
1568 ret = spi->cfg->set_number_of_data(spi, nb_words);
1569 if (ret < 0)
1570 goto out;
1571 }
1572
1573 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1574 spi->cur_comm);
1575 dev_dbg(spi->dev,
1576 "data frame of %d-bit, data packet of %d data frames\n",
1577 spi->cur_bpw, spi->cur_fthlv);
1578 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1579 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1580 spi->cur_xferlen, nb_words);
1581 dev_dbg(spi->dev, "dma %s\n",
1582 (spi->cur_usedma) ? "enabled" : "disabled");
1583
1584out:
1585 spin_unlock_irqrestore(&spi->lock, flags);
1586
1587 return ret;
1588}
1589
1590/**
1591 * stm32_spi_transfer_one - transfer a single spi_transfer
1592 * @master: controller master interface
1593 * @spi_dev: pointer to the spi device
1594 * @transfer: pointer to spi transfer
1595 *
1596 * It must return 0 if the transfer is finished or 1 if the transfer is still
1597 * in progress.
1598 */
1599static int stm32_spi_transfer_one(struct spi_master *master,
1600 struct spi_device *spi_dev,
1601 struct spi_transfer *transfer)
1602{
1603 struct stm32_spi *spi = spi_master_get_devdata(master);
1604 int ret;
1605
1606 spi->tx_buf = transfer->tx_buf;
1607 spi->rx_buf = transfer->rx_buf;
1608 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1609 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1610
1611 spi->cur_usedma = (master->can_dma &&
1612 master->can_dma(master, spi_dev, transfer));
1613
1614 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1615 if (ret) {
1616 dev_err(spi->dev, "SPI transfer setup failed\n");
1617 return ret;
1618 }
1619
1620 if (spi->cur_usedma)
1621 return stm32_spi_transfer_one_dma(spi, transfer);
1622 else
1623 return spi->cfg->transfer_one_irq(spi);
1624}
1625
1626/**
1627 * stm32_spi_unprepare_msg - relax the hardware
1628 * @master: controller master interface
1629 * @msg: pointer to the spi message
1630 */
1631static int stm32_spi_unprepare_msg(struct spi_master *master,
1632 struct spi_message *msg)
1633{
1634 struct stm32_spi *spi = spi_master_get_devdata(master);
1635
1636 spi->cfg->disable(spi);
1637
1638 return 0;
1639}
1640
1641/**
1642 * stm32f4_spi_config - Configure SPI controller as SPI master
1643 * @spi: pointer to the spi controller data structure
1644 */
1645static int stm32f4_spi_config(struct stm32_spi *spi)
1646{
1647 unsigned long flags;
1648
1649 spin_lock_irqsave(&spi->lock, flags);
1650
1651 /* Ensure I2SMOD bit is kept cleared */
1652 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1653 STM32F4_SPI_I2SCFGR_I2SMOD);
1654
1655 /*
1656 * - SS input value high
1657 * - transmitter half duplex direction
1658 * - Set the master mode (default Motorola mode)
1659 * - Consider 1 master/n slaves configuration and
1660 * SS input value is determined by the SSI bit
1661 */
1662 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1663 STM32F4_SPI_CR1_BIDIOE |
1664 STM32F4_SPI_CR1_MSTR |
1665 STM32F4_SPI_CR1_SSM);
1666
1667 spin_unlock_irqrestore(&spi->lock, flags);
1668
1669 return 0;
1670}
1671
1672/**
1673 * stm32h7_spi_config - Configure SPI controller as SPI master
1674 * @spi: pointer to the spi controller data structure
1675 */
1676static int stm32h7_spi_config(struct stm32_spi *spi)
1677{
1678 unsigned long flags;
1679
1680 spin_lock_irqsave(&spi->lock, flags);
1681
1682 /* Ensure I2SMOD bit is kept cleared */
1683 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1684 STM32H7_SPI_I2SCFGR_I2SMOD);
1685
1686 /*
1687 * - SS input value high
1688 * - transmitter half duplex direction
1689 * - automatic communication suspend when RX-Fifo is full
1690 */
1691 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1692 STM32H7_SPI_CR1_HDDIR |
1693 STM32H7_SPI_CR1_MASRX);
1694
1695 /*
1696 * - Set the master mode (default Motorola mode)
1697 * - Consider 1 master/n slaves configuration and
1698 * SS input value is determined by the SSI bit
1699 * - keep control of all associated GPIOs
1700 */
1701 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1702 STM32H7_SPI_CFG2_SSM |
1703 STM32H7_SPI_CFG2_AFCNTR);
1704
1705 spin_unlock_irqrestore(&spi->lock, flags);
1706
1707 return 0;
1708}
1709
1710static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1711 .regs = &stm32f4_spi_regspec,
1712 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1713 .disable = stm32f4_spi_disable,
1714 .config = stm32f4_spi_config,
1715 .set_bpw = stm32f4_spi_set_bpw,
1716 .set_mode = stm32f4_spi_set_mode,
1717 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1718 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1719 .dma_rx_cb = stm32_spi_dma_rx_cb,
1720 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1721 .irq_handler_event = stm32f4_spi_irq_event,
1722 .irq_handler_thread = stm32f4_spi_irq_thread,
1723 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1724 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1725 .has_fifo = false,
1726 .flags = SPI_MASTER_MUST_TX,
1727};
1728
1729static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1730 .regs = &stm32h7_spi_regspec,
1731 .get_fifo_size = stm32h7_spi_get_fifo_size,
1732 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1733 .disable = stm32h7_spi_disable,
1734 .config = stm32h7_spi_config,
1735 .set_bpw = stm32h7_spi_set_bpw,
1736 .set_mode = stm32h7_spi_set_mode,
1737 .set_data_idleness = stm32h7_spi_data_idleness,
1738 .set_number_of_data = stm32h7_spi_number_of_data,
1739 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1740 .dma_rx_cb = stm32_spi_dma_rx_cb,
1741 /*
1742 * dma_tx_cb is not necessary since in case of TX, dma is followed by
1743 * SPI access hence handling is performed within the SPI interrupt
1744 */
1745 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1746 .irq_handler_thread = stm32h7_spi_irq_thread,
1747 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1748 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1749 .has_fifo = true,
1750};
1751
1752static const struct of_device_id stm32_spi_of_match[] = {
1753 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1754 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1755 {},
1756};
1757MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1758
1759static int stm32_spi_probe(struct platform_device *pdev)
1760{
1761 struct spi_master *master;
1762 struct stm32_spi *spi;
1763 struct resource *res;
1764 struct reset_control *rst;
1765 int ret;
1766
1767 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1768 if (!master) {
1769 dev_err(&pdev->dev, "spi master allocation failed\n");
1770 return -ENOMEM;
1771 }
1772 platform_set_drvdata(pdev, master);
1773
1774 spi = spi_master_get_devdata(master);
1775 spi->dev = &pdev->dev;
1776 spi->master = master;
1777 spin_lock_init(&spi->lock);
1778
1779 spi->cfg = (const struct stm32_spi_cfg *)
1780 of_match_device(pdev->dev.driver->of_match_table,
1781 &pdev->dev)->data;
1782
1783 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1784 spi->base = devm_ioremap_resource(&pdev->dev, res);
1785 if (IS_ERR(spi->base))
1786 return PTR_ERR(spi->base);
1787
1788 spi->phys_addr = (dma_addr_t)res->start;
1789
1790 spi->irq = platform_get_irq(pdev, 0);
1791 if (spi->irq <= 0)
1792 return dev_err_probe(&pdev->dev, spi->irq,
1793 "failed to get irq\n");
1794
1795 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1796 spi->cfg->irq_handler_event,
1797 spi->cfg->irq_handler_thread,
1798 IRQF_ONESHOT, pdev->name, master);
1799 if (ret) {
1800 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1801 ret);
1802 return ret;
1803 }
1804
1805 spi->clk = devm_clk_get(&pdev->dev, NULL);
1806 if (IS_ERR(spi->clk)) {
1807 ret = PTR_ERR(spi->clk);
1808 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1809 return ret;
1810 }
1811
1812 ret = clk_prepare_enable(spi->clk);
1813 if (ret) {
1814 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1815 return ret;
1816 }
1817 spi->clk_rate = clk_get_rate(spi->clk);
1818 if (!spi->clk_rate) {
1819 dev_err(&pdev->dev, "clk rate = 0\n");
1820 ret = -EINVAL;
1821 goto err_clk_disable;
1822 }
1823
1824 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1825 if (rst) {
1826 if (IS_ERR(rst)) {
1827 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1828 "failed to get reset\n");
1829 goto err_clk_disable;
1830 }
1831
1832 reset_control_assert(rst);
1833 udelay(2);
1834 reset_control_deassert(rst);
1835 }
1836
1837 if (spi->cfg->has_fifo)
1838 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1839
1840 ret = spi->cfg->config(spi);
1841 if (ret) {
1842 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1843 ret);
1844 goto err_clk_disable;
1845 }
1846
1847 master->dev.of_node = pdev->dev.of_node;
1848 master->auto_runtime_pm = true;
1849 master->bus_num = pdev->id;
1850 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1851 SPI_3WIRE;
1852 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1853 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1854 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1855 master->use_gpio_descriptors = true;
1856 master->prepare_message = stm32_spi_prepare_msg;
1857 master->transfer_one = stm32_spi_transfer_one;
1858 master->unprepare_message = stm32_spi_unprepare_msg;
1859 master->flags = spi->cfg->flags;
1860
1861 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1862 if (IS_ERR(spi->dma_tx)) {
1863 ret = PTR_ERR(spi->dma_tx);
1864 spi->dma_tx = NULL;
1865 if (ret == -EPROBE_DEFER)
1866 goto err_clk_disable;
1867
1868 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1869 } else {
1870 master->dma_tx = spi->dma_tx;
1871 }
1872
1873 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1874 if (IS_ERR(spi->dma_rx)) {
1875 ret = PTR_ERR(spi->dma_rx);
1876 spi->dma_rx = NULL;
1877 if (ret == -EPROBE_DEFER)
1878 goto err_dma_release;
1879
1880 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1881 } else {
1882 master->dma_rx = spi->dma_rx;
1883 }
1884
1885 if (spi->dma_tx || spi->dma_rx)
1886 master->can_dma = stm32_spi_can_dma;
1887
1888 pm_runtime_set_autosuspend_delay(&pdev->dev,
1889 STM32_SPI_AUTOSUSPEND_DELAY);
1890 pm_runtime_use_autosuspend(&pdev->dev);
1891 pm_runtime_set_active(&pdev->dev);
1892 pm_runtime_get_noresume(&pdev->dev);
1893 pm_runtime_enable(&pdev->dev);
1894
1895 ret = spi_register_master(master);
1896 if (ret) {
1897 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1898 ret);
1899 goto err_pm_disable;
1900 }
1901
1902 pm_runtime_mark_last_busy(&pdev->dev);
1903 pm_runtime_put_autosuspend(&pdev->dev);
1904
1905 dev_info(&pdev->dev, "driver initialized\n");
1906
1907 return 0;
1908
1909err_pm_disable:
1910 pm_runtime_disable(&pdev->dev);
1911 pm_runtime_put_noidle(&pdev->dev);
1912 pm_runtime_set_suspended(&pdev->dev);
1913 pm_runtime_dont_use_autosuspend(&pdev->dev);
1914err_dma_release:
1915 if (spi->dma_tx)
1916 dma_release_channel(spi->dma_tx);
1917 if (spi->dma_rx)
1918 dma_release_channel(spi->dma_rx);
1919err_clk_disable:
1920 clk_disable_unprepare(spi->clk);
1921
1922 return ret;
1923}
1924
1925static int stm32_spi_remove(struct platform_device *pdev)
1926{
1927 struct spi_master *master = platform_get_drvdata(pdev);
1928 struct stm32_spi *spi = spi_master_get_devdata(master);
1929
1930 pm_runtime_get_sync(&pdev->dev);
1931
1932 spi_unregister_master(master);
1933 spi->cfg->disable(spi);
1934
1935 pm_runtime_disable(&pdev->dev);
1936 pm_runtime_put_noidle(&pdev->dev);
1937 pm_runtime_set_suspended(&pdev->dev);
1938 pm_runtime_dont_use_autosuspend(&pdev->dev);
1939
1940 if (master->dma_tx)
1941 dma_release_channel(master->dma_tx);
1942 if (master->dma_rx)
1943 dma_release_channel(master->dma_rx);
1944
1945 clk_disable_unprepare(spi->clk);
1946
1947
1948 pinctrl_pm_select_sleep_state(&pdev->dev);
1949
1950 return 0;
1951}
1952
1953static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
1954{
1955 struct spi_master *master = dev_get_drvdata(dev);
1956 struct stm32_spi *spi = spi_master_get_devdata(master);
1957
1958 clk_disable_unprepare(spi->clk);
1959
1960 return pinctrl_pm_select_sleep_state(dev);
1961}
1962
1963static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
1964{
1965 struct spi_master *master = dev_get_drvdata(dev);
1966 struct stm32_spi *spi = spi_master_get_devdata(master);
1967 int ret;
1968
1969 ret = pinctrl_pm_select_default_state(dev);
1970 if (ret)
1971 return ret;
1972
1973 return clk_prepare_enable(spi->clk);
1974}
1975
1976static int __maybe_unused stm32_spi_suspend(struct device *dev)
1977{
1978 struct spi_master *master = dev_get_drvdata(dev);
1979 int ret;
1980
1981 ret = spi_master_suspend(master);
1982 if (ret)
1983 return ret;
1984
1985 return pm_runtime_force_suspend(dev);
1986}
1987
1988static int __maybe_unused stm32_spi_resume(struct device *dev)
1989{
1990 struct spi_master *master = dev_get_drvdata(dev);
1991 struct stm32_spi *spi = spi_master_get_devdata(master);
1992 int ret;
1993
1994 ret = pm_runtime_force_resume(dev);
1995 if (ret)
1996 return ret;
1997
1998 ret = spi_master_resume(master);
1999 if (ret) {
2000 clk_disable_unprepare(spi->clk);
2001 return ret;
2002 }
2003
2004 ret = pm_runtime_resume_and_get(dev);
2005 if (ret < 0) {
2006 dev_err(dev, "Unable to power device:%d\n", ret);
2007 return ret;
2008 }
2009
2010 spi->cfg->config(spi);
2011
2012 pm_runtime_mark_last_busy(dev);
2013 pm_runtime_put_autosuspend(dev);
2014
2015 return 0;
2016}
2017
2018static const struct dev_pm_ops stm32_spi_pm_ops = {
2019 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2020 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2021 stm32_spi_runtime_resume, NULL)
2022};
2023
2024static struct platform_driver stm32_spi_driver = {
2025 .probe = stm32_spi_probe,
2026 .remove = stm32_spi_remove,
2027 .driver = {
2028 .name = DRIVER_NAME,
2029 .pm = &stm32_spi_pm_ops,
2030 .of_match_table = stm32_spi_of_match,
2031 },
2032};
2033
2034module_platform_driver(stm32_spi_driver);
2035
2036MODULE_ALIAS("platform:" DRIVER_NAME);
2037MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2038MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2039MODULE_LICENSE("GPL v2");