Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2//
3// STMicroelectronics STM32 SPI Controller driver (master mode only)
4//
5// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8#include <linux/debugfs.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/interrupt.h>
13#include <linux/iopoll.h>
14#include <linux/module.h>
15#include <linux/of_platform.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19#include <linux/spi/spi.h>
20
21#define DRIVER_NAME "spi_stm32"
22
23/* STM32F4 SPI registers */
24#define STM32F4_SPI_CR1 0x00
25#define STM32F4_SPI_CR2 0x04
26#define STM32F4_SPI_SR 0x08
27#define STM32F4_SPI_DR 0x0C
28#define STM32F4_SPI_I2SCFGR 0x1C
29
30/* STM32F4_SPI_CR1 bit fields */
31#define STM32F4_SPI_CR1_CPHA BIT(0)
32#define STM32F4_SPI_CR1_CPOL BIT(1)
33#define STM32F4_SPI_CR1_MSTR BIT(2)
34#define STM32F4_SPI_CR1_BR_SHIFT 3
35#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
36#define STM32F4_SPI_CR1_SPE BIT(6)
37#define STM32F4_SPI_CR1_LSBFRST BIT(7)
38#define STM32F4_SPI_CR1_SSI BIT(8)
39#define STM32F4_SPI_CR1_SSM BIT(9)
40#define STM32F4_SPI_CR1_RXONLY BIT(10)
41#define STM32F4_SPI_CR1_DFF BIT(11)
42#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
43#define STM32F4_SPI_CR1_CRCEN BIT(13)
44#define STM32F4_SPI_CR1_BIDIOE BIT(14)
45#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
46#define STM32F4_SPI_CR1_BR_MIN 0
47#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
48
49/* STM32F4_SPI_CR2 bit fields */
50#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
51#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
52#define STM32F4_SPI_CR2_SSOE BIT(2)
53#define STM32F4_SPI_CR2_FRF BIT(4)
54#define STM32F4_SPI_CR2_ERRIE BIT(5)
55#define STM32F4_SPI_CR2_RXNEIE BIT(6)
56#define STM32F4_SPI_CR2_TXEIE BIT(7)
57
58/* STM32F4_SPI_SR bit fields */
59#define STM32F4_SPI_SR_RXNE BIT(0)
60#define STM32F4_SPI_SR_TXE BIT(1)
61#define STM32F4_SPI_SR_CHSIDE BIT(2)
62#define STM32F4_SPI_SR_UDR BIT(3)
63#define STM32F4_SPI_SR_CRCERR BIT(4)
64#define STM32F4_SPI_SR_MODF BIT(5)
65#define STM32F4_SPI_SR_OVR BIT(6)
66#define STM32F4_SPI_SR_BSY BIT(7)
67#define STM32F4_SPI_SR_FRE BIT(8)
68
69/* STM32F4_SPI_I2SCFGR bit fields */
70#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
71
72/* STM32F4 SPI Baud Rate min/max divisor */
73#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
74#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
75
76/* STM32H7 SPI registers */
77#define STM32H7_SPI_CR1 0x00
78#define STM32H7_SPI_CR2 0x04
79#define STM32H7_SPI_CFG1 0x08
80#define STM32H7_SPI_CFG2 0x0C
81#define STM32H7_SPI_IER 0x10
82#define STM32H7_SPI_SR 0x14
83#define STM32H7_SPI_IFCR 0x18
84#define STM32H7_SPI_TXDR 0x20
85#define STM32H7_SPI_RXDR 0x30
86#define STM32H7_SPI_I2SCFGR 0x50
87
88/* STM32H7_SPI_CR1 bit fields */
89#define STM32H7_SPI_CR1_SPE BIT(0)
90#define STM32H7_SPI_CR1_MASRX BIT(8)
91#define STM32H7_SPI_CR1_CSTART BIT(9)
92#define STM32H7_SPI_CR1_CSUSP BIT(10)
93#define STM32H7_SPI_CR1_HDDIR BIT(11)
94#define STM32H7_SPI_CR1_SSI BIT(12)
95
96/* STM32H7_SPI_CR2 bit fields */
97#define STM32H7_SPI_CR2_TSIZE_SHIFT 0
98#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99
100/* STM32H7_SPI_CFG1 bit fields */
101#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
102#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
104#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
105#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
106#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
107#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
109#define STM32H7_SPI_CFG1_MBR_MIN 0
110#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
111
112/* STM32H7_SPI_CFG2 bit fields */
113#define STM32H7_SPI_CFG2_MIDI_SHIFT 4
114#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
115#define STM32H7_SPI_CFG2_COMM_SHIFT 17
116#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
117#define STM32H7_SPI_CFG2_SP_SHIFT 19
118#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
119#define STM32H7_SPI_CFG2_MASTER BIT(22)
120#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
121#define STM32H7_SPI_CFG2_CPHA BIT(24)
122#define STM32H7_SPI_CFG2_CPOL BIT(25)
123#define STM32H7_SPI_CFG2_SSM BIT(26)
124#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
125
126/* STM32H7_SPI_IER bit fields */
127#define STM32H7_SPI_IER_RXPIE BIT(0)
128#define STM32H7_SPI_IER_TXPIE BIT(1)
129#define STM32H7_SPI_IER_DXPIE BIT(2)
130#define STM32H7_SPI_IER_EOTIE BIT(3)
131#define STM32H7_SPI_IER_TXTFIE BIT(4)
132#define STM32H7_SPI_IER_OVRIE BIT(6)
133#define STM32H7_SPI_IER_MODFIE BIT(9)
134#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
135
136/* STM32H7_SPI_SR bit fields */
137#define STM32H7_SPI_SR_RXP BIT(0)
138#define STM32H7_SPI_SR_TXP BIT(1)
139#define STM32H7_SPI_SR_EOT BIT(3)
140#define STM32H7_SPI_SR_OVR BIT(6)
141#define STM32H7_SPI_SR_MODF BIT(9)
142#define STM32H7_SPI_SR_SUSP BIT(11)
143#define STM32H7_SPI_SR_RXPLVL_SHIFT 13
144#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
145#define STM32H7_SPI_SR_RXWNE BIT(15)
146
147/* STM32H7_SPI_IFCR bit fields */
148#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
149
150/* STM32H7_SPI_I2SCFGR bit fields */
151#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
152
153/* STM32H7 SPI Master Baud Rate min/max divisor */
154#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
155#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
156
157/* STM32H7 SPI Communication mode */
158#define STM32H7_SPI_FULL_DUPLEX 0
159#define STM32H7_SPI_SIMPLEX_TX 1
160#define STM32H7_SPI_SIMPLEX_RX 2
161#define STM32H7_SPI_HALF_DUPLEX 3
162
163/* SPI Communication type */
164#define SPI_FULL_DUPLEX 0
165#define SPI_SIMPLEX_TX 1
166#define SPI_SIMPLEX_RX 2
167#define SPI_3WIRE_TX 3
168#define SPI_3WIRE_RX 4
169
170#define SPI_1HZ_NS 1000000000
171
172/*
173 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
174 * without fifo buffers.
175 */
176#define SPI_DMA_MIN_BYTES 16
177
178/**
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
180 * @reg: register offset
181 * @mask: bitfield mask
182 * @shift: left shift
183 */
184struct stm32_spi_reg {
185 int reg;
186 int mask;
187 int shift;
188};
189
190/**
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
192 * @en: enable register and SPI enable bit
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
194 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
195 * @cpol: clock polarity register and polarity bit
196 * @cpha: clock phase register and phase bit
197 * @lsb_first: LSB transmitted first register and bit
198 * @br: baud rate register and bitfields
199 * @rx: SPI RX data register
200 * @tx: SPI TX data register
201 */
202struct stm32_spi_regspec {
203 const struct stm32_spi_reg en;
204 const struct stm32_spi_reg dma_rx_en;
205 const struct stm32_spi_reg dma_tx_en;
206 const struct stm32_spi_reg cpol;
207 const struct stm32_spi_reg cpha;
208 const struct stm32_spi_reg lsb_first;
209 const struct stm32_spi_reg br;
210 const struct stm32_spi_reg rx;
211 const struct stm32_spi_reg tx;
212};
213
214struct stm32_spi;
215
216/**
217 * struct stm32_spi_cfg - stm32 compatible configuration data
218 * @regs: registers descriptions
219 * @get_fifo_size: routine to get fifo size
220 * @get_bpw_mask: routine to get bits per word mask
221 * @disable: routine to disable controller
222 * @config: routine to configure controller as SPI Master
223 * @set_bpw: routine to configure registers to for bits per word
224 * @set_mode: routine to configure registers to desired mode
225 * @set_data_idleness: optional routine to configure registers to desired idle
226 * time between frames (if driver has this functionality)
227 * @set_number_of_data: optional routine to configure registers to desired
228 * number of data (if driver has this functionality)
229 * @can_dma: routine to determine if the transfer is eligible for DMA use
230 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
231 * using DMA
232 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
233 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
234 * @transfer_one_irq: routine to configure interrupts for driver
235 * @irq_handler_event: Interrupt handler for SPI controller events
236 * @irq_handler_thread: thread of interrupt handler for SPI controller
237 * @baud_rate_div_min: minimum baud rate divisor
238 * @baud_rate_div_max: maximum baud rate divisor
239 * @has_fifo: boolean to know if fifo is used for driver
240 * @has_startbit: boolean to know if start bit is used to start transfer
241 */
242struct stm32_spi_cfg {
243 const struct stm32_spi_regspec *regs;
244 int (*get_fifo_size)(struct stm32_spi *spi);
245 int (*get_bpw_mask)(struct stm32_spi *spi);
246 void (*disable)(struct stm32_spi *spi);
247 int (*config)(struct stm32_spi *spi);
248 void (*set_bpw)(struct stm32_spi *spi);
249 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
250 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
251 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
252 void (*transfer_one_dma_start)(struct stm32_spi *spi);
253 void (*dma_rx_cb)(void *data);
254 void (*dma_tx_cb)(void *data);
255 int (*transfer_one_irq)(struct stm32_spi *spi);
256 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
257 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
258 unsigned int baud_rate_div_min;
259 unsigned int baud_rate_div_max;
260 bool has_fifo;
261};
262
263/**
264 * struct stm32_spi - private data of the SPI controller
265 * @dev: driver model representation of the controller
266 * @master: controller master interface
267 * @cfg: compatible configuration data
268 * @base: virtual memory area
269 * @clk: hw kernel clock feeding the SPI clock generator
270 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
271 * @rst: SPI controller reset line
272 * @lock: prevent I/O concurrent access
273 * @irq: SPI controller interrupt line
274 * @fifo_size: size of the embedded fifo in bytes
275 * @cur_midi: master inter-data idleness in ns
276 * @cur_speed: speed configured in Hz
277 * @cur_bpw: number of bits in a single SPI data frame
278 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
279 * @cur_comm: SPI communication mode
280 * @cur_xferlen: current transfer length in bytes
281 * @cur_usedma: boolean to know if dma is used in current transfer
282 * @tx_buf: data to be written, or NULL
283 * @rx_buf: data to be read, or NULL
284 * @tx_len: number of data to be written in bytes
285 * @rx_len: number of data to be read in bytes
286 * @dma_tx: dma channel for TX transfer
287 * @dma_rx: dma channel for RX transfer
288 * @phys_addr: SPI registers physical base address
289 */
290struct stm32_spi {
291 struct device *dev;
292 struct spi_master *master;
293 const struct stm32_spi_cfg *cfg;
294 void __iomem *base;
295 struct clk *clk;
296 u32 clk_rate;
297 struct reset_control *rst;
298 spinlock_t lock; /* prevent I/O concurrent access */
299 int irq;
300 unsigned int fifo_size;
301
302 unsigned int cur_midi;
303 unsigned int cur_speed;
304 unsigned int cur_bpw;
305 unsigned int cur_fthlv;
306 unsigned int cur_comm;
307 unsigned int cur_xferlen;
308 bool cur_usedma;
309
310 const void *tx_buf;
311 void *rx_buf;
312 int tx_len;
313 int rx_len;
314 struct dma_chan *dma_tx;
315 struct dma_chan *dma_rx;
316 dma_addr_t phys_addr;
317};
318
319static const struct stm32_spi_regspec stm32f4_spi_regspec = {
320 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
321
322 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
323 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
324
325 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
326 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
327 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
328 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
329
330 .rx = { STM32F4_SPI_DR },
331 .tx = { STM32F4_SPI_DR },
332};
333
334static const struct stm32_spi_regspec stm32h7_spi_regspec = {
335 /* SPI data transfer is enabled but spi_ker_ck is idle.
336 * CFG1 and CFG2 registers are write protected when SPE is enabled.
337 */
338 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
339
340 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
341 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
342
343 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
344 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
345 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
346 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
347 STM32H7_SPI_CFG1_MBR_SHIFT },
348
349 .rx = { STM32H7_SPI_RXDR },
350 .tx = { STM32H7_SPI_TXDR },
351};
352
353static inline void stm32_spi_set_bits(struct stm32_spi *spi,
354 u32 offset, u32 bits)
355{
356 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
357 spi->base + offset);
358}
359
360static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
361 u32 offset, u32 bits)
362{
363 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
364 spi->base + offset);
365}
366
367/**
368 * stm32h7_spi_get_fifo_size - Return fifo size
369 * @spi: pointer to the spi controller data structure
370 */
371static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
372{
373 unsigned long flags;
374 u32 count = 0;
375
376 spin_lock_irqsave(&spi->lock, flags);
377
378 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
379
380 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
381 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
382
383 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
384
385 spin_unlock_irqrestore(&spi->lock, flags);
386
387 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
388
389 return count;
390}
391
392/**
393 * stm32f4_spi_get_bpw_mask - Return bits per word mask
394 * @spi: pointer to the spi controller data structure
395 */
396static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
397{
398 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
399 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
400}
401
402/**
403 * stm32h7_spi_get_bpw_mask - Return bits per word mask
404 * @spi: pointer to the spi controller data structure
405 */
406static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
407{
408 unsigned long flags;
409 u32 cfg1, max_bpw;
410
411 spin_lock_irqsave(&spi->lock, flags);
412
413 /*
414 * The most significant bit at DSIZE bit field is reserved when the
415 * maximum data size of periperal instances is limited to 16-bit
416 */
417 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
418
419 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
420 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
421 STM32H7_SPI_CFG1_DSIZE_SHIFT;
422 max_bpw += 1;
423
424 spin_unlock_irqrestore(&spi->lock, flags);
425
426 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
427
428 return SPI_BPW_RANGE_MASK(4, max_bpw);
429}
430
431/**
432 * stm32_spi_prepare_mbr - Determine baud rate divisor value
433 * @spi: pointer to the spi controller data structure
434 * @speed_hz: requested speed
435 * @min_div: minimum baud rate divisor
436 * @max_div: maximum baud rate divisor
437 *
438 * Return baud rate divisor value in case of success or -EINVAL
439 */
440static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
441 u32 min_div, u32 max_div)
442{
443 u32 div, mbrdiv;
444
445 /* Ensure spi->clk_rate is even */
446 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
447
448 /*
449 * SPI framework set xfer->speed_hz to master->max_speed_hz if
450 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
451 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
452 * no need to check it there.
453 * However, we need to ensure the following calculations.
454 */
455 if ((div < min_div) || (div > max_div))
456 return -EINVAL;
457
458 /* Determine the first power of 2 greater than or equal to div */
459 if (div & (div - 1))
460 mbrdiv = fls(div);
461 else
462 mbrdiv = fls(div) - 1;
463
464 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
465
466 return mbrdiv - 1;
467}
468
469/**
470 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
471 * @spi: pointer to the spi controller data structure
472 * @xfer_len: length of the message to be transferred
473 */
474static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
475{
476 u32 fthlv, half_fifo, packet;
477
478 /* data packet should not exceed 1/2 of fifo space */
479 half_fifo = (spi->fifo_size / 2);
480
481 /* data_packet should not exceed transfer length */
482 if (half_fifo > xfer_len)
483 packet = xfer_len;
484 else
485 packet = half_fifo;
486
487 if (spi->cur_bpw <= 8)
488 fthlv = packet;
489 else if (spi->cur_bpw <= 16)
490 fthlv = packet / 2;
491 else
492 fthlv = packet / 4;
493
494 /* align packet size with data registers access */
495 if (spi->cur_bpw > 8)
496 fthlv -= (fthlv % 2); /* multiple of 2 */
497 else
498 fthlv -= (fthlv % 4); /* multiple of 4 */
499
500 if (!fthlv)
501 fthlv = 1;
502
503 return fthlv;
504}
505
506/**
507 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
508 * @spi: pointer to the spi controller data structure
509 *
510 * Read from tx_buf depends on remaining bytes to avoid to read beyond
511 * tx_buf end.
512 */
513static void stm32f4_spi_write_tx(struct stm32_spi *spi)
514{
515 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
516 STM32F4_SPI_SR_TXE)) {
517 u32 offs = spi->cur_xferlen - spi->tx_len;
518
519 if (spi->cur_bpw == 16) {
520 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
521
522 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
523 spi->tx_len -= sizeof(u16);
524 } else {
525 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
526
527 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
528 spi->tx_len -= sizeof(u8);
529 }
530 }
531
532 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
533}
534
535/**
536 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
537 * @spi: pointer to the spi controller data structure
538 *
539 * Read from tx_buf depends on remaining bytes to avoid to read beyond
540 * tx_buf end.
541 */
542static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
543{
544 while ((spi->tx_len > 0) &&
545 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
546 STM32H7_SPI_SR_TXP)) {
547 u32 offs = spi->cur_xferlen - spi->tx_len;
548
549 if (spi->tx_len >= sizeof(u32)) {
550 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
551
552 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
553 spi->tx_len -= sizeof(u32);
554 } else if (spi->tx_len >= sizeof(u16)) {
555 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
556
557 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
558 spi->tx_len -= sizeof(u16);
559 } else {
560 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
561
562 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
563 spi->tx_len -= sizeof(u8);
564 }
565 }
566
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
568}
569
570/**
571 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
572 * @spi: pointer to the spi controller data structure
573 *
574 * Write in rx_buf depends on remaining bytes to avoid to write beyond
575 * rx_buf end.
576 */
577static void stm32f4_spi_read_rx(struct stm32_spi *spi)
578{
579 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
580 STM32F4_SPI_SR_RXNE)) {
581 u32 offs = spi->cur_xferlen - spi->rx_len;
582
583 if (spi->cur_bpw == 16) {
584 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
585
586 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
587 spi->rx_len -= sizeof(u16);
588 } else {
589 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
590
591 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
592 spi->rx_len -= sizeof(u8);
593 }
594 }
595
596 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
597}
598
599/**
600 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
601 * @spi: pointer to the spi controller data structure
602 * @flush: boolean indicating that FIFO should be flushed
603 *
604 * Write in rx_buf depends on remaining bytes to avoid to write beyond
605 * rx_buf end.
606 */
607static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
608{
609 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
610 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
611 STM32H7_SPI_SR_RXPLVL_SHIFT;
612
613 while ((spi->rx_len > 0) &&
614 ((sr & STM32H7_SPI_SR_RXP) ||
615 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
616 u32 offs = spi->cur_xferlen - spi->rx_len;
617
618 if ((spi->rx_len >= sizeof(u32)) ||
619 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
620 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
621
622 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
623 spi->rx_len -= sizeof(u32);
624 } else if ((spi->rx_len >= sizeof(u16)) ||
625 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
626 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
627
628 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
629 spi->rx_len -= sizeof(u16);
630 } else {
631 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
632
633 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
634 spi->rx_len -= sizeof(u8);
635 }
636
637 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
638 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
639 STM32H7_SPI_SR_RXPLVL_SHIFT;
640 }
641
642 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
643 flush ? "(flush)" : "", spi->rx_len);
644}
645
646/**
647 * stm32_spi_enable - Enable SPI controller
648 * @spi: pointer to the spi controller data structure
649 */
650static void stm32_spi_enable(struct stm32_spi *spi)
651{
652 dev_dbg(spi->dev, "enable controller\n");
653
654 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
655 spi->cfg->regs->en.mask);
656}
657
658/**
659 * stm32f4_spi_disable - Disable SPI controller
660 * @spi: pointer to the spi controller data structure
661 */
662static void stm32f4_spi_disable(struct stm32_spi *spi)
663{
664 unsigned long flags;
665 u32 sr;
666
667 dev_dbg(spi->dev, "disable controller\n");
668
669 spin_lock_irqsave(&spi->lock, flags);
670
671 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
672 STM32F4_SPI_CR1_SPE)) {
673 spin_unlock_irqrestore(&spi->lock, flags);
674 return;
675 }
676
677 /* Disable interrupts */
678 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
679 STM32F4_SPI_CR2_RXNEIE |
680 STM32F4_SPI_CR2_ERRIE);
681
682 /* Wait until BSY = 0 */
683 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
684 sr, !(sr & STM32F4_SPI_SR_BSY),
685 10, 100000) < 0) {
686 dev_warn(spi->dev, "disabling condition timeout\n");
687 }
688
689 if (spi->cur_usedma && spi->dma_tx)
690 dmaengine_terminate_all(spi->dma_tx);
691 if (spi->cur_usedma && spi->dma_rx)
692 dmaengine_terminate_all(spi->dma_rx);
693
694 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
695
696 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
697 STM32F4_SPI_CR2_RXDMAEN);
698
699 /* Sequence to clear OVR flag */
700 readl_relaxed(spi->base + STM32F4_SPI_DR);
701 readl_relaxed(spi->base + STM32F4_SPI_SR);
702
703 spin_unlock_irqrestore(&spi->lock, flags);
704}
705
706/**
707 * stm32h7_spi_disable - Disable SPI controller
708 * @spi: pointer to the spi controller data structure
709 *
710 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
711 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
712 * RX-Fifo.
713 * Normally, if TSIZE has been configured, we should relax the hardware at the
714 * reception of the EOT interrupt. But in case of error, EOT will not be
715 * raised. So the subsystem unprepare_message call allows us to properly
716 * complete the transfer from an hardware point of view.
717 */
718static void stm32h7_spi_disable(struct stm32_spi *spi)
719{
720 unsigned long flags;
721 u32 cr1, sr;
722
723 dev_dbg(spi->dev, "disable controller\n");
724
725 spin_lock_irqsave(&spi->lock, flags);
726
727 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
728
729 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
730 spin_unlock_irqrestore(&spi->lock, flags);
731 return;
732 }
733
734 /* Wait on EOT or suspend the flow */
735 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
736 sr, !(sr & STM32H7_SPI_SR_EOT),
737 10, 100000) < 0) {
738 if (cr1 & STM32H7_SPI_CR1_CSTART) {
739 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
740 spi->base + STM32H7_SPI_CR1);
741 if (readl_relaxed_poll_timeout_atomic(
742 spi->base + STM32H7_SPI_SR,
743 sr, !(sr & STM32H7_SPI_SR_SUSP),
744 10, 100000) < 0)
745 dev_warn(spi->dev,
746 "Suspend request timeout\n");
747 }
748 }
749
750 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
751 stm32h7_spi_read_rxfifo(spi, true);
752
753 if (spi->cur_usedma && spi->dma_tx)
754 dmaengine_terminate_all(spi->dma_tx);
755 if (spi->cur_usedma && spi->dma_rx)
756 dmaengine_terminate_all(spi->dma_rx);
757
758 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
759
760 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
761 STM32H7_SPI_CFG1_RXDMAEN);
762
763 /* Disable interrupts and clear status flags */
764 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
765 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
766
767 spin_unlock_irqrestore(&spi->lock, flags);
768}
769
770/**
771 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
772 * @master: controller master interface
773 * @spi_dev: pointer to the spi device
774 * @transfer: pointer to spi transfer
775 *
776 * If driver has fifo and the current transfer size is greater than fifo size,
777 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
778 */
779static bool stm32_spi_can_dma(struct spi_master *master,
780 struct spi_device *spi_dev,
781 struct spi_transfer *transfer)
782{
783 unsigned int dma_size;
784 struct stm32_spi *spi = spi_master_get_devdata(master);
785
786 if (spi->cfg->has_fifo)
787 dma_size = spi->fifo_size;
788 else
789 dma_size = SPI_DMA_MIN_BYTES;
790
791 dev_dbg(spi->dev, "%s: %s\n", __func__,
792 (transfer->len > dma_size) ? "true" : "false");
793
794 return (transfer->len > dma_size);
795}
796
797/**
798 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
799 * @irq: interrupt line
800 * @dev_id: SPI controller master interface
801 */
802static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
803{
804 struct spi_master *master = dev_id;
805 struct stm32_spi *spi = spi_master_get_devdata(master);
806 u32 sr, mask = 0;
807 unsigned long flags;
808 bool end = false;
809
810 spin_lock_irqsave(&spi->lock, flags);
811
812 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
813 /*
814 * BSY flag is not handled in interrupt but it is normal behavior when
815 * this flag is set.
816 */
817 sr &= ~STM32F4_SPI_SR_BSY;
818
819 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
820 spi->cur_comm == SPI_3WIRE_TX)) {
821 /* OVR flag shouldn't be handled for TX only mode */
822 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
823 mask |= STM32F4_SPI_SR_TXE;
824 }
825
826 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
827 spi->cur_comm == SPI_SIMPLEX_RX ||
828 spi->cur_comm == SPI_3WIRE_RX)) {
829 /* TXE flag is set and is handled when RXNE flag occurs */
830 sr &= ~STM32F4_SPI_SR_TXE;
831 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
832 }
833
834 if (!(sr & mask)) {
835 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
836 spin_unlock_irqrestore(&spi->lock, flags);
837 return IRQ_NONE;
838 }
839
840 if (sr & STM32F4_SPI_SR_OVR) {
841 dev_warn(spi->dev, "Overrun: received value discarded\n");
842
843 /* Sequence to clear OVR flag */
844 readl_relaxed(spi->base + STM32F4_SPI_DR);
845 readl_relaxed(spi->base + STM32F4_SPI_SR);
846
847 /*
848 * If overrun is detected, it means that something went wrong,
849 * so stop the current transfer. Transfer can wait for next
850 * RXNE but DR is already read and end never happens.
851 */
852 end = true;
853 goto end_irq;
854 }
855
856 if (sr & STM32F4_SPI_SR_TXE) {
857 if (spi->tx_buf)
858 stm32f4_spi_write_tx(spi);
859 if (spi->tx_len == 0)
860 end = true;
861 }
862
863 if (sr & STM32F4_SPI_SR_RXNE) {
864 stm32f4_spi_read_rx(spi);
865 if (spi->rx_len == 0)
866 end = true;
867 else if (spi->tx_buf)/* Load data for discontinuous mode */
868 stm32f4_spi_write_tx(spi);
869 }
870
871end_irq:
872 if (end) {
873 /* Immediately disable interrupts to do not generate new one */
874 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
875 STM32F4_SPI_CR2_TXEIE |
876 STM32F4_SPI_CR2_RXNEIE |
877 STM32F4_SPI_CR2_ERRIE);
878 spin_unlock_irqrestore(&spi->lock, flags);
879 return IRQ_WAKE_THREAD;
880 }
881
882 spin_unlock_irqrestore(&spi->lock, flags);
883 return IRQ_HANDLED;
884}
885
886/**
887 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
888 * @irq: interrupt line
889 * @dev_id: SPI controller master interface
890 */
891static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
892{
893 struct spi_master *master = dev_id;
894 struct stm32_spi *spi = spi_master_get_devdata(master);
895
896 spi_finalize_current_transfer(master);
897 stm32f4_spi_disable(spi);
898
899 return IRQ_HANDLED;
900}
901
902/**
903 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
904 * @irq: interrupt line
905 * @dev_id: SPI controller master interface
906 */
907static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
908{
909 struct spi_master *master = dev_id;
910 struct stm32_spi *spi = spi_master_get_devdata(master);
911 u32 sr, ier, mask;
912 unsigned long flags;
913 bool end = false;
914
915 spin_lock_irqsave(&spi->lock, flags);
916
917 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
918 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
919
920 mask = ier;
921 /* EOTIE is triggered on EOT, SUSP and TXC events. */
922 mask |= STM32H7_SPI_SR_SUSP;
923 /*
924 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
925 * Full-Duplex, need to poll RXP event to know if there are remaining
926 * data, before disabling SPI.
927 */
928 if (spi->rx_buf && !spi->cur_usedma)
929 mask |= STM32H7_SPI_SR_RXP;
930
931 if (!(sr & mask)) {
932 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
933 sr, ier);
934 spin_unlock_irqrestore(&spi->lock, flags);
935 return IRQ_NONE;
936 }
937
938 if (sr & STM32H7_SPI_SR_SUSP) {
939 static DEFINE_RATELIMIT_STATE(rs,
940 DEFAULT_RATELIMIT_INTERVAL * 10,
941 1);
942 if (__ratelimit(&rs))
943 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
944 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
945 stm32h7_spi_read_rxfifo(spi, false);
946 /*
947 * If communication is suspended while using DMA, it means
948 * that something went wrong, so stop the current transfer
949 */
950 if (spi->cur_usedma)
951 end = true;
952 }
953
954 if (sr & STM32H7_SPI_SR_MODF) {
955 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
956 end = true;
957 }
958
959 if (sr & STM32H7_SPI_SR_OVR) {
960 dev_warn(spi->dev, "Overrun: received value discarded\n");
961 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
962 stm32h7_spi_read_rxfifo(spi, false);
963 /*
964 * If overrun is detected while using DMA, it means that
965 * something went wrong, so stop the current transfer
966 */
967 if (spi->cur_usedma)
968 end = true;
969 }
970
971 if (sr & STM32H7_SPI_SR_EOT) {
972 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
973 stm32h7_spi_read_rxfifo(spi, true);
974 end = true;
975 }
976
977 if (sr & STM32H7_SPI_SR_TXP)
978 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
979 stm32h7_spi_write_txfifo(spi);
980
981 if (sr & STM32H7_SPI_SR_RXP)
982 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
983 stm32h7_spi_read_rxfifo(spi, false);
984
985 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
986
987 spin_unlock_irqrestore(&spi->lock, flags);
988
989 if (end) {
990 stm32h7_spi_disable(spi);
991 spi_finalize_current_transfer(master);
992 }
993
994 return IRQ_HANDLED;
995}
996
997/**
998 * stm32_spi_prepare_msg - set up the controller to transfer a single message
999 * @master: controller master interface
1000 * @msg: pointer to spi message
1001 */
1002static int stm32_spi_prepare_msg(struct spi_master *master,
1003 struct spi_message *msg)
1004{
1005 struct stm32_spi *spi = spi_master_get_devdata(master);
1006 struct spi_device *spi_dev = msg->spi;
1007 struct device_node *np = spi_dev->dev.of_node;
1008 unsigned long flags;
1009 u32 clrb = 0, setb = 0;
1010
1011 /* SPI slave device may need time between data frames */
1012 spi->cur_midi = 0;
1013 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
1014 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1015
1016 if (spi_dev->mode & SPI_CPOL)
1017 setb |= spi->cfg->regs->cpol.mask;
1018 else
1019 clrb |= spi->cfg->regs->cpol.mask;
1020
1021 if (spi_dev->mode & SPI_CPHA)
1022 setb |= spi->cfg->regs->cpha.mask;
1023 else
1024 clrb |= spi->cfg->regs->cpha.mask;
1025
1026 if (spi_dev->mode & SPI_LSB_FIRST)
1027 setb |= spi->cfg->regs->lsb_first.mask;
1028 else
1029 clrb |= spi->cfg->regs->lsb_first.mask;
1030
1031 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1032 spi_dev->mode & SPI_CPOL,
1033 spi_dev->mode & SPI_CPHA,
1034 spi_dev->mode & SPI_LSB_FIRST,
1035 spi_dev->mode & SPI_CS_HIGH);
1036
1037 spin_lock_irqsave(&spi->lock, flags);
1038
1039 /* CPOL, CPHA and LSB FIRST bits have common register */
1040 if (clrb || setb)
1041 writel_relaxed(
1042 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1043 ~clrb) | setb,
1044 spi->base + spi->cfg->regs->cpol.reg);
1045
1046 spin_unlock_irqrestore(&spi->lock, flags);
1047
1048 return 0;
1049}
1050
1051/**
1052 * stm32f4_spi_dma_tx_cb - dma callback
1053 * @data: pointer to the spi controller data structure
1054 *
1055 * DMA callback is called when the transfer is complete for DMA TX channel.
1056 */
1057static void stm32f4_spi_dma_tx_cb(void *data)
1058{
1059 struct stm32_spi *spi = data;
1060
1061 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1062 spi_finalize_current_transfer(spi->master);
1063 stm32f4_spi_disable(spi);
1064 }
1065}
1066
1067/**
1068 * stm32f4_spi_dma_rx_cb - dma callback
1069 * @data: pointer to the spi controller data structure
1070 *
1071 * DMA callback is called when the transfer is complete for DMA RX channel.
1072 */
1073static void stm32f4_spi_dma_rx_cb(void *data)
1074{
1075 struct stm32_spi *spi = data;
1076
1077 spi_finalize_current_transfer(spi->master);
1078 stm32f4_spi_disable(spi);
1079}
1080
1081/**
1082 * stm32h7_spi_dma_cb - dma callback
1083 * @data: pointer to the spi controller data structure
1084 *
1085 * DMA callback is called when the transfer is complete or when an error
1086 * occurs. If the transfer is complete, EOT flag is raised.
1087 */
1088static void stm32h7_spi_dma_cb(void *data)
1089{
1090 struct stm32_spi *spi = data;
1091 unsigned long flags;
1092 u32 sr;
1093
1094 spin_lock_irqsave(&spi->lock, flags);
1095
1096 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1097
1098 spin_unlock_irqrestore(&spi->lock, flags);
1099
1100 if (!(sr & STM32H7_SPI_SR_EOT))
1101 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1102
1103 /* Now wait for EOT, or SUSP or OVR in case of error */
1104}
1105
1106/**
1107 * stm32_spi_dma_config - configure dma slave channel depending on current
1108 * transfer bits_per_word.
1109 * @spi: pointer to the spi controller data structure
1110 * @dma_conf: pointer to the dma_slave_config structure
1111 * @dir: direction of the dma transfer
1112 */
1113static void stm32_spi_dma_config(struct stm32_spi *spi,
1114 struct dma_slave_config *dma_conf,
1115 enum dma_transfer_direction dir)
1116{
1117 enum dma_slave_buswidth buswidth;
1118 u32 maxburst;
1119
1120 if (spi->cur_bpw <= 8)
1121 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1122 else if (spi->cur_bpw <= 16)
1123 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1124 else
1125 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1126
1127 if (spi->cfg->has_fifo) {
1128 /* Valid for DMA Half or Full Fifo threshold */
1129 if (spi->cur_fthlv == 2)
1130 maxburst = 1;
1131 else
1132 maxburst = spi->cur_fthlv;
1133 } else {
1134 maxburst = 1;
1135 }
1136
1137 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1138 dma_conf->direction = dir;
1139 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1140 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1141 dma_conf->src_addr_width = buswidth;
1142 dma_conf->src_maxburst = maxburst;
1143
1144 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1145 buswidth, maxburst);
1146 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1147 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1148 dma_conf->dst_addr_width = buswidth;
1149 dma_conf->dst_maxburst = maxburst;
1150
1151 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1152 buswidth, maxburst);
1153 }
1154}
1155
1156/**
1157 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1158 * interrupts
1159 * @spi: pointer to the spi controller data structure
1160 *
1161 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1162 * in progress.
1163 */
1164static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1165{
1166 unsigned long flags;
1167 u32 cr2 = 0;
1168
1169 /* Enable the interrupts relative to the current communication mode */
1170 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1171 cr2 |= STM32F4_SPI_CR2_TXEIE;
1172 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1173 spi->cur_comm == SPI_SIMPLEX_RX ||
1174 spi->cur_comm == SPI_3WIRE_RX) {
1175 /* In transmit-only mode, the OVR flag is set in the SR register
1176 * since the received data are never read. Therefore set OVR
1177 * interrupt only when rx buffer is available.
1178 */
1179 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1180 } else {
1181 return -EINVAL;
1182 }
1183
1184 spin_lock_irqsave(&spi->lock, flags);
1185
1186 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1187
1188 stm32_spi_enable(spi);
1189
1190 /* starting data transfer when buffer is loaded */
1191 if (spi->tx_buf)
1192 stm32f4_spi_write_tx(spi);
1193
1194 spin_unlock_irqrestore(&spi->lock, flags);
1195
1196 return 1;
1197}
1198
1199/**
1200 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1201 * interrupts
1202 * @spi: pointer to the spi controller data structure
1203 *
1204 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1205 * in progress.
1206 */
1207static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1208{
1209 unsigned long flags;
1210 u32 ier = 0;
1211
1212 /* Enable the interrupts relative to the current communication mode */
1213 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1214 ier |= STM32H7_SPI_IER_DXPIE;
1215 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1216 ier |= STM32H7_SPI_IER_TXPIE;
1217 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1218 ier |= STM32H7_SPI_IER_RXPIE;
1219
1220 /* Enable the interrupts relative to the end of transfer */
1221 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1222 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1223
1224 spin_lock_irqsave(&spi->lock, flags);
1225
1226 stm32_spi_enable(spi);
1227
1228 /* Be sure to have data in fifo before starting data transfer */
1229 if (spi->tx_buf)
1230 stm32h7_spi_write_txfifo(spi);
1231
1232 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1233
1234 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1235
1236 spin_unlock_irqrestore(&spi->lock, flags);
1237
1238 return 1;
1239}
1240
1241/**
1242 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1243 * transfer using DMA
1244 * @spi: pointer to the spi controller data structure
1245 */
1246static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1247{
1248 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1249 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1250 spi->cur_comm == SPI_FULL_DUPLEX) {
1251 /*
1252 * In transmit-only mode, the OVR flag is set in the SR register
1253 * since the received data are never read. Therefore set OVR
1254 * interrupt only when rx buffer is available.
1255 */
1256 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1257 }
1258
1259 stm32_spi_enable(spi);
1260}
1261
1262/**
1263 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1264 * transfer using DMA
1265 * @spi: pointer to the spi controller data structure
1266 */
1267static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1268{
1269 /* Enable the interrupts relative to the end of transfer */
1270 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1271 STM32H7_SPI_IER_TXTFIE |
1272 STM32H7_SPI_IER_OVRIE |
1273 STM32H7_SPI_IER_MODFIE);
1274
1275 stm32_spi_enable(spi);
1276
1277 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1278}
1279
1280/**
1281 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1282 * @spi: pointer to the spi controller data structure
1283 * @xfer: pointer to the spi_transfer structure
1284 *
1285 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1286 * in progress.
1287 */
1288static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1289 struct spi_transfer *xfer)
1290{
1291 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1292 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1293 unsigned long flags;
1294
1295 spin_lock_irqsave(&spi->lock, flags);
1296
1297 rx_dma_desc = NULL;
1298 if (spi->rx_buf && spi->dma_rx) {
1299 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1300 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1301
1302 /* Enable Rx DMA request */
1303 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1304 spi->cfg->regs->dma_rx_en.mask);
1305
1306 rx_dma_desc = dmaengine_prep_slave_sg(
1307 spi->dma_rx, xfer->rx_sg.sgl,
1308 xfer->rx_sg.nents,
1309 rx_dma_conf.direction,
1310 DMA_PREP_INTERRUPT);
1311 }
1312
1313 tx_dma_desc = NULL;
1314 if (spi->tx_buf && spi->dma_tx) {
1315 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1316 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1317
1318 tx_dma_desc = dmaengine_prep_slave_sg(
1319 spi->dma_tx, xfer->tx_sg.sgl,
1320 xfer->tx_sg.nents,
1321 tx_dma_conf.direction,
1322 DMA_PREP_INTERRUPT);
1323 }
1324
1325 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1326 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1327 goto dma_desc_error;
1328
1329 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1330 goto dma_desc_error;
1331
1332 if (rx_dma_desc) {
1333 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1334 rx_dma_desc->callback_param = spi;
1335
1336 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1337 dev_err(spi->dev, "Rx DMA submit failed\n");
1338 goto dma_desc_error;
1339 }
1340 /* Enable Rx DMA channel */
1341 dma_async_issue_pending(spi->dma_rx);
1342 }
1343
1344 if (tx_dma_desc) {
1345 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1346 spi->cur_comm == SPI_3WIRE_TX) {
1347 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1348 tx_dma_desc->callback_param = spi;
1349 }
1350
1351 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1352 dev_err(spi->dev, "Tx DMA submit failed\n");
1353 goto dma_submit_error;
1354 }
1355 /* Enable Tx DMA channel */
1356 dma_async_issue_pending(spi->dma_tx);
1357
1358 /* Enable Tx DMA request */
1359 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1360 spi->cfg->regs->dma_tx_en.mask);
1361 }
1362
1363 spi->cfg->transfer_one_dma_start(spi);
1364
1365 spin_unlock_irqrestore(&spi->lock, flags);
1366
1367 return 1;
1368
1369dma_submit_error:
1370 if (spi->dma_rx)
1371 dmaengine_terminate_all(spi->dma_rx);
1372
1373dma_desc_error:
1374 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1375 spi->cfg->regs->dma_rx_en.mask);
1376
1377 spin_unlock_irqrestore(&spi->lock, flags);
1378
1379 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1380
1381 spi->cur_usedma = false;
1382 return spi->cfg->transfer_one_irq(spi);
1383}
1384
1385/**
1386 * stm32f4_spi_set_bpw - Configure bits per word
1387 * @spi: pointer to the spi controller data structure
1388 */
1389static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1390{
1391 if (spi->cur_bpw == 16)
1392 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1393 else
1394 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1395}
1396
1397/**
1398 * stm32h7_spi_set_bpw - configure bits per word
1399 * @spi: pointer to the spi controller data structure
1400 */
1401static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1402{
1403 u32 bpw, fthlv;
1404 u32 cfg1_clrb = 0, cfg1_setb = 0;
1405
1406 bpw = spi->cur_bpw - 1;
1407
1408 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1409 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
1410 STM32H7_SPI_CFG1_DSIZE;
1411
1412 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1413 fthlv = spi->cur_fthlv - 1;
1414
1415 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1416 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
1417 STM32H7_SPI_CFG1_FTHLV;
1418
1419 writel_relaxed(
1420 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1421 ~cfg1_clrb) | cfg1_setb,
1422 spi->base + STM32H7_SPI_CFG1);
1423}
1424
1425/**
1426 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1427 * @spi: pointer to the spi controller data structure
1428 * @mbrdiv: baud rate divisor value
1429 */
1430static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1431{
1432 u32 clrb = 0, setb = 0;
1433
1434 clrb |= spi->cfg->regs->br.mask;
1435 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
1436 spi->cfg->regs->br.mask;
1437
1438 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1439 ~clrb) | setb,
1440 spi->base + spi->cfg->regs->br.reg);
1441}
1442
1443/**
1444 * stm32_spi_communication_type - return transfer communication type
1445 * @spi_dev: pointer to the spi device
1446 * @transfer: pointer to spi transfer
1447 */
1448static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1449 struct spi_transfer *transfer)
1450{
1451 unsigned int type = SPI_FULL_DUPLEX;
1452
1453 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1454 /*
1455 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1456 * is forbidden and unvalidated by SPI subsystem so depending
1457 * on the valid buffer, we can determine the direction of the
1458 * transfer.
1459 */
1460 if (!transfer->tx_buf)
1461 type = SPI_3WIRE_RX;
1462 else
1463 type = SPI_3WIRE_TX;
1464 } else {
1465 if (!transfer->tx_buf)
1466 type = SPI_SIMPLEX_RX;
1467 else if (!transfer->rx_buf)
1468 type = SPI_SIMPLEX_TX;
1469 }
1470
1471 return type;
1472}
1473
1474/**
1475 * stm32f4_spi_set_mode - configure communication mode
1476 * @spi: pointer to the spi controller data structure
1477 * @comm_type: type of communication to configure
1478 */
1479static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1480{
1481 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1482 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1483 STM32F4_SPI_CR1_BIDIMODE |
1484 STM32F4_SPI_CR1_BIDIOE);
1485 } else if (comm_type == SPI_FULL_DUPLEX ||
1486 comm_type == SPI_SIMPLEX_RX) {
1487 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1488 STM32F4_SPI_CR1_BIDIMODE |
1489 STM32F4_SPI_CR1_BIDIOE);
1490 } else if (comm_type == SPI_3WIRE_RX) {
1491 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1492 STM32F4_SPI_CR1_BIDIMODE);
1493 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1494 STM32F4_SPI_CR1_BIDIOE);
1495 } else {
1496 return -EINVAL;
1497 }
1498
1499 return 0;
1500}
1501
1502/**
1503 * stm32h7_spi_set_mode - configure communication mode
1504 * @spi: pointer to the spi controller data structure
1505 * @comm_type: type of communication to configure
1506 */
1507static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1508{
1509 u32 mode;
1510 u32 cfg2_clrb = 0, cfg2_setb = 0;
1511
1512 if (comm_type == SPI_3WIRE_RX) {
1513 mode = STM32H7_SPI_HALF_DUPLEX;
1514 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1515 } else if (comm_type == SPI_3WIRE_TX) {
1516 mode = STM32H7_SPI_HALF_DUPLEX;
1517 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1518 } else if (comm_type == SPI_SIMPLEX_RX) {
1519 mode = STM32H7_SPI_SIMPLEX_RX;
1520 } else if (comm_type == SPI_SIMPLEX_TX) {
1521 mode = STM32H7_SPI_SIMPLEX_TX;
1522 } else {
1523 mode = STM32H7_SPI_FULL_DUPLEX;
1524 }
1525
1526 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1527 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) &
1528 STM32H7_SPI_CFG2_COMM;
1529
1530 writel_relaxed(
1531 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1532 ~cfg2_clrb) | cfg2_setb,
1533 spi->base + STM32H7_SPI_CFG2);
1534
1535 return 0;
1536}
1537
1538/**
1539 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1540 * consecutive data frames in master mode
1541 * @spi: pointer to the spi controller data structure
1542 * @len: transfer len
1543 */
1544static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1545{
1546 u32 cfg2_clrb = 0, cfg2_setb = 0;
1547
1548 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1549 if ((len > 1) && (spi->cur_midi > 0)) {
1550 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
1551 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1552 (u32)STM32H7_SPI_CFG2_MIDI >>
1553 STM32H7_SPI_CFG2_MIDI_SHIFT);
1554
1555 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1556 sck_period_ns, midi, midi * sck_period_ns);
1557 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) &
1558 STM32H7_SPI_CFG2_MIDI;
1559 }
1560
1561 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1562 ~cfg2_clrb) | cfg2_setb,
1563 spi->base + STM32H7_SPI_CFG2);
1564}
1565
1566/**
1567 * stm32h7_spi_number_of_data - configure number of data at current transfer
1568 * @spi: pointer to the spi controller data structure
1569 * @nb_words: transfer length (in words)
1570 */
1571static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1572{
1573 u32 cr2_clrb = 0, cr2_setb = 0;
1574
1575 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >>
1576 STM32H7_SPI_CR2_TSIZE_SHIFT)) {
1577 cr2_clrb |= STM32H7_SPI_CR2_TSIZE;
1578 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT;
1579 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) &
1580 ~cr2_clrb) | cr2_setb,
1581 spi->base + STM32H7_SPI_CR2);
1582 } else {
1583 return -EMSGSIZE;
1584 }
1585
1586 return 0;
1587}
1588
1589/**
1590 * stm32_spi_transfer_one_setup - common setup to transfer a single
1591 * spi_transfer either using DMA or
1592 * interrupts.
1593 * @spi: pointer to the spi controller data structure
1594 * @spi_dev: pointer to the spi device
1595 * @transfer: pointer to spi transfer
1596 */
1597static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1598 struct spi_device *spi_dev,
1599 struct spi_transfer *transfer)
1600{
1601 unsigned long flags;
1602 unsigned int comm_type;
1603 int nb_words, ret = 0;
1604 int mbr;
1605
1606 spin_lock_irqsave(&spi->lock, flags);
1607
1608 spi->cur_xferlen = transfer->len;
1609
1610 spi->cur_bpw = transfer->bits_per_word;
1611 spi->cfg->set_bpw(spi);
1612
1613 /* Update spi->cur_speed with real clock speed */
1614 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1615 spi->cfg->baud_rate_div_min,
1616 spi->cfg->baud_rate_div_max);
1617 if (mbr < 0) {
1618 ret = mbr;
1619 goto out;
1620 }
1621
1622 transfer->speed_hz = spi->cur_speed;
1623 stm32_spi_set_mbr(spi, mbr);
1624
1625 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1626 ret = spi->cfg->set_mode(spi, comm_type);
1627 if (ret < 0)
1628 goto out;
1629
1630 spi->cur_comm = comm_type;
1631
1632 if (spi->cfg->set_data_idleness)
1633 spi->cfg->set_data_idleness(spi, transfer->len);
1634
1635 if (spi->cur_bpw <= 8)
1636 nb_words = transfer->len;
1637 else if (spi->cur_bpw <= 16)
1638 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1639 else
1640 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1641
1642 if (spi->cfg->set_number_of_data) {
1643 ret = spi->cfg->set_number_of_data(spi, nb_words);
1644 if (ret < 0)
1645 goto out;
1646 }
1647
1648 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1649 spi->cur_comm);
1650 dev_dbg(spi->dev,
1651 "data frame of %d-bit, data packet of %d data frames\n",
1652 spi->cur_bpw, spi->cur_fthlv);
1653 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1654 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1655 spi->cur_xferlen, nb_words);
1656 dev_dbg(spi->dev, "dma %s\n",
1657 (spi->cur_usedma) ? "enabled" : "disabled");
1658
1659out:
1660 spin_unlock_irqrestore(&spi->lock, flags);
1661
1662 return ret;
1663}
1664
1665/**
1666 * stm32_spi_transfer_one - transfer a single spi_transfer
1667 * @master: controller master interface
1668 * @spi_dev: pointer to the spi device
1669 * @transfer: pointer to spi transfer
1670 *
1671 * It must return 0 if the transfer is finished or 1 if the transfer is still
1672 * in progress.
1673 */
1674static int stm32_spi_transfer_one(struct spi_master *master,
1675 struct spi_device *spi_dev,
1676 struct spi_transfer *transfer)
1677{
1678 struct stm32_spi *spi = spi_master_get_devdata(master);
1679 int ret;
1680
1681 spi->tx_buf = transfer->tx_buf;
1682 spi->rx_buf = transfer->rx_buf;
1683 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1684 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1685
1686 spi->cur_usedma = (master->can_dma &&
1687 master->can_dma(master, spi_dev, transfer));
1688
1689 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1690 if (ret) {
1691 dev_err(spi->dev, "SPI transfer setup failed\n");
1692 return ret;
1693 }
1694
1695 if (spi->cur_usedma)
1696 return stm32_spi_transfer_one_dma(spi, transfer);
1697 else
1698 return spi->cfg->transfer_one_irq(spi);
1699}
1700
1701/**
1702 * stm32_spi_unprepare_msg - relax the hardware
1703 * @master: controller master interface
1704 * @msg: pointer to the spi message
1705 */
1706static int stm32_spi_unprepare_msg(struct spi_master *master,
1707 struct spi_message *msg)
1708{
1709 struct stm32_spi *spi = spi_master_get_devdata(master);
1710
1711 spi->cfg->disable(spi);
1712
1713 return 0;
1714}
1715
1716/**
1717 * stm32f4_spi_config - Configure SPI controller as SPI master
1718 * @spi: pointer to the spi controller data structure
1719 */
1720static int stm32f4_spi_config(struct stm32_spi *spi)
1721{
1722 unsigned long flags;
1723
1724 spin_lock_irqsave(&spi->lock, flags);
1725
1726 /* Ensure I2SMOD bit is kept cleared */
1727 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1728 STM32F4_SPI_I2SCFGR_I2SMOD);
1729
1730 /*
1731 * - SS input value high
1732 * - transmitter half duplex direction
1733 * - Set the master mode (default Motorola mode)
1734 * - Consider 1 master/n slaves configuration and
1735 * SS input value is determined by the SSI bit
1736 */
1737 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1738 STM32F4_SPI_CR1_BIDIOE |
1739 STM32F4_SPI_CR1_MSTR |
1740 STM32F4_SPI_CR1_SSM);
1741
1742 spin_unlock_irqrestore(&spi->lock, flags);
1743
1744 return 0;
1745}
1746
1747/**
1748 * stm32h7_spi_config - Configure SPI controller as SPI master
1749 * @spi: pointer to the spi controller data structure
1750 */
1751static int stm32h7_spi_config(struct stm32_spi *spi)
1752{
1753 unsigned long flags;
1754
1755 spin_lock_irqsave(&spi->lock, flags);
1756
1757 /* Ensure I2SMOD bit is kept cleared */
1758 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1759 STM32H7_SPI_I2SCFGR_I2SMOD);
1760
1761 /*
1762 * - SS input value high
1763 * - transmitter half duplex direction
1764 * - automatic communication suspend when RX-Fifo is full
1765 */
1766 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1767 STM32H7_SPI_CR1_HDDIR |
1768 STM32H7_SPI_CR1_MASRX);
1769
1770 /*
1771 * - Set the master mode (default Motorola mode)
1772 * - Consider 1 master/n slaves configuration and
1773 * SS input value is determined by the SSI bit
1774 * - keep control of all associated GPIOs
1775 */
1776 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1777 STM32H7_SPI_CFG2_SSM |
1778 STM32H7_SPI_CFG2_AFCNTR);
1779
1780 spin_unlock_irqrestore(&spi->lock, flags);
1781
1782 return 0;
1783}
1784
1785static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1786 .regs = &stm32f4_spi_regspec,
1787 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1788 .disable = stm32f4_spi_disable,
1789 .config = stm32f4_spi_config,
1790 .set_bpw = stm32f4_spi_set_bpw,
1791 .set_mode = stm32f4_spi_set_mode,
1792 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1793 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1794 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1795 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1796 .irq_handler_event = stm32f4_spi_irq_event,
1797 .irq_handler_thread = stm32f4_spi_irq_thread,
1798 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1799 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1800 .has_fifo = false,
1801};
1802
1803static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1804 .regs = &stm32h7_spi_regspec,
1805 .get_fifo_size = stm32h7_spi_get_fifo_size,
1806 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1807 .disable = stm32h7_spi_disable,
1808 .config = stm32h7_spi_config,
1809 .set_bpw = stm32h7_spi_set_bpw,
1810 .set_mode = stm32h7_spi_set_mode,
1811 .set_data_idleness = stm32h7_spi_data_idleness,
1812 .set_number_of_data = stm32h7_spi_number_of_data,
1813 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1814 .dma_rx_cb = stm32h7_spi_dma_cb,
1815 .dma_tx_cb = stm32h7_spi_dma_cb,
1816 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1817 .irq_handler_thread = stm32h7_spi_irq_thread,
1818 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1819 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1820 .has_fifo = true,
1821};
1822
1823static const struct of_device_id stm32_spi_of_match[] = {
1824 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1825 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1826 {},
1827};
1828MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1829
1830static int stm32_spi_probe(struct platform_device *pdev)
1831{
1832 struct spi_master *master;
1833 struct stm32_spi *spi;
1834 struct resource *res;
1835 int ret;
1836
1837 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1838 if (!master) {
1839 dev_err(&pdev->dev, "spi master allocation failed\n");
1840 return -ENOMEM;
1841 }
1842 platform_set_drvdata(pdev, master);
1843
1844 spi = spi_master_get_devdata(master);
1845 spi->dev = &pdev->dev;
1846 spi->master = master;
1847 spin_lock_init(&spi->lock);
1848
1849 spi->cfg = (const struct stm32_spi_cfg *)
1850 of_match_device(pdev->dev.driver->of_match_table,
1851 &pdev->dev)->data;
1852
1853 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1854 spi->base = devm_ioremap_resource(&pdev->dev, res);
1855 if (IS_ERR(spi->base)) {
1856 ret = PTR_ERR(spi->base);
1857 goto err_master_put;
1858 }
1859
1860 spi->phys_addr = (dma_addr_t)res->start;
1861
1862 spi->irq = platform_get_irq(pdev, 0);
1863 if (spi->irq <= 0) {
1864 ret = spi->irq;
1865 if (ret != -EPROBE_DEFER)
1866 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
1867 goto err_master_put;
1868 }
1869 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1870 spi->cfg->irq_handler_event,
1871 spi->cfg->irq_handler_thread,
1872 IRQF_ONESHOT, pdev->name, master);
1873 if (ret) {
1874 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1875 ret);
1876 goto err_master_put;
1877 }
1878
1879 spi->clk = devm_clk_get(&pdev->dev, NULL);
1880 if (IS_ERR(spi->clk)) {
1881 ret = PTR_ERR(spi->clk);
1882 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1883 goto err_master_put;
1884 }
1885
1886 ret = clk_prepare_enable(spi->clk);
1887 if (ret) {
1888 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1889 goto err_master_put;
1890 }
1891 spi->clk_rate = clk_get_rate(spi->clk);
1892 if (!spi->clk_rate) {
1893 dev_err(&pdev->dev, "clk rate = 0\n");
1894 ret = -EINVAL;
1895 goto err_clk_disable;
1896 }
1897
1898 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1899 if (!IS_ERR(spi->rst)) {
1900 reset_control_assert(spi->rst);
1901 udelay(2);
1902 reset_control_deassert(spi->rst);
1903 }
1904
1905 if (spi->cfg->has_fifo)
1906 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1907
1908 ret = spi->cfg->config(spi);
1909 if (ret) {
1910 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1911 ret);
1912 goto err_clk_disable;
1913 }
1914
1915 master->dev.of_node = pdev->dev.of_node;
1916 master->auto_runtime_pm = true;
1917 master->bus_num = pdev->id;
1918 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1919 SPI_3WIRE;
1920 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1921 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1922 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1923 master->use_gpio_descriptors = true;
1924 master->prepare_message = stm32_spi_prepare_msg;
1925 master->transfer_one = stm32_spi_transfer_one;
1926 master->unprepare_message = stm32_spi_unprepare_msg;
1927 master->flags = SPI_MASTER_MUST_TX;
1928
1929 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1930 if (IS_ERR(spi->dma_tx)) {
1931 ret = PTR_ERR(spi->dma_tx);
1932 spi->dma_tx = NULL;
1933 if (ret == -EPROBE_DEFER)
1934 goto err_clk_disable;
1935
1936 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1937 } else {
1938 master->dma_tx = spi->dma_tx;
1939 }
1940
1941 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1942 if (IS_ERR(spi->dma_rx)) {
1943 ret = PTR_ERR(spi->dma_rx);
1944 spi->dma_rx = NULL;
1945 if (ret == -EPROBE_DEFER)
1946 goto err_dma_release;
1947
1948 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1949 } else {
1950 master->dma_rx = spi->dma_rx;
1951 }
1952
1953 if (spi->dma_tx || spi->dma_rx)
1954 master->can_dma = stm32_spi_can_dma;
1955
1956 pm_runtime_set_active(&pdev->dev);
1957 pm_runtime_enable(&pdev->dev);
1958
1959 ret = devm_spi_register_master(&pdev->dev, master);
1960 if (ret) {
1961 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1962 ret);
1963 goto err_pm_disable;
1964 }
1965
1966 if (!master->cs_gpiods) {
1967 dev_err(&pdev->dev, "no CS gpios available\n");
1968 ret = -EINVAL;
1969 goto err_pm_disable;
1970 }
1971
1972 dev_info(&pdev->dev, "driver initialized\n");
1973
1974 return 0;
1975
1976err_pm_disable:
1977 pm_runtime_disable(&pdev->dev);
1978err_dma_release:
1979 if (spi->dma_tx)
1980 dma_release_channel(spi->dma_tx);
1981 if (spi->dma_rx)
1982 dma_release_channel(spi->dma_rx);
1983err_clk_disable:
1984 clk_disable_unprepare(spi->clk);
1985err_master_put:
1986 spi_master_put(master);
1987
1988 return ret;
1989}
1990
1991static int stm32_spi_remove(struct platform_device *pdev)
1992{
1993 struct spi_master *master = platform_get_drvdata(pdev);
1994 struct stm32_spi *spi = spi_master_get_devdata(master);
1995
1996 spi->cfg->disable(spi);
1997
1998 if (master->dma_tx)
1999 dma_release_channel(master->dma_tx);
2000 if (master->dma_rx)
2001 dma_release_channel(master->dma_rx);
2002
2003 clk_disable_unprepare(spi->clk);
2004
2005 pm_runtime_disable(&pdev->dev);
2006
2007 pinctrl_pm_select_sleep_state(&pdev->dev);
2008
2009 return 0;
2010}
2011
2012#ifdef CONFIG_PM
2013static int stm32_spi_runtime_suspend(struct device *dev)
2014{
2015 struct spi_master *master = dev_get_drvdata(dev);
2016 struct stm32_spi *spi = spi_master_get_devdata(master);
2017
2018 clk_disable_unprepare(spi->clk);
2019
2020 return pinctrl_pm_select_sleep_state(dev);
2021}
2022
2023static int stm32_spi_runtime_resume(struct device *dev)
2024{
2025 struct spi_master *master = dev_get_drvdata(dev);
2026 struct stm32_spi *spi = spi_master_get_devdata(master);
2027 int ret;
2028
2029 ret = pinctrl_pm_select_default_state(dev);
2030 if (ret)
2031 return ret;
2032
2033 return clk_prepare_enable(spi->clk);
2034}
2035#endif
2036
2037#ifdef CONFIG_PM_SLEEP
2038static int stm32_spi_suspend(struct device *dev)
2039{
2040 struct spi_master *master = dev_get_drvdata(dev);
2041 int ret;
2042
2043 ret = spi_master_suspend(master);
2044 if (ret)
2045 return ret;
2046
2047 return pm_runtime_force_suspend(dev);
2048}
2049
2050static int stm32_spi_resume(struct device *dev)
2051{
2052 struct spi_master *master = dev_get_drvdata(dev);
2053 struct stm32_spi *spi = spi_master_get_devdata(master);
2054 int ret;
2055
2056 ret = pm_runtime_force_resume(dev);
2057 if (ret)
2058 return ret;
2059
2060 ret = spi_master_resume(master);
2061 if (ret) {
2062 clk_disable_unprepare(spi->clk);
2063 return ret;
2064 }
2065
2066 ret = pm_runtime_get_sync(dev);
2067 if (ret < 0) {
2068 dev_err(dev, "Unable to power device:%d\n", ret);
2069 return ret;
2070 }
2071
2072 spi->cfg->config(spi);
2073
2074 pm_runtime_mark_last_busy(dev);
2075 pm_runtime_put_autosuspend(dev);
2076
2077 return 0;
2078}
2079#endif
2080
2081static const struct dev_pm_ops stm32_spi_pm_ops = {
2082 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2083 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2084 stm32_spi_runtime_resume, NULL)
2085};
2086
2087static struct platform_driver stm32_spi_driver = {
2088 .probe = stm32_spi_probe,
2089 .remove = stm32_spi_remove,
2090 .driver = {
2091 .name = DRIVER_NAME,
2092 .pm = &stm32_spi_pm_ops,
2093 .of_match_table = stm32_spi_of_match,
2094 },
2095};
2096
2097module_platform_driver(stm32_spi_driver);
2098
2099MODULE_ALIAS("platform:" DRIVER_NAME);
2100MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2101MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2102MODULE_LICENSE("GPL v2");