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1// SPDX-License-Identifier: GPL-2.0
2//
3// STMicroelectronics STM32 SPI Controller driver (master mode only)
4//
5// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8#include <linux/bitfield.h>
9#include <linux/debugfs.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/of_platform.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/pm_runtime.h>
19#include <linux/reset.h>
20#include <linux/spi/spi.h>
21
22#define DRIVER_NAME "spi_stm32"
23
24/* STM32F4 SPI registers */
25#define STM32F4_SPI_CR1 0x00
26#define STM32F4_SPI_CR2 0x04
27#define STM32F4_SPI_SR 0x08
28#define STM32F4_SPI_DR 0x0C
29#define STM32F4_SPI_I2SCFGR 0x1C
30
31/* STM32F4_SPI_CR1 bit fields */
32#define STM32F4_SPI_CR1_CPHA BIT(0)
33#define STM32F4_SPI_CR1_CPOL BIT(1)
34#define STM32F4_SPI_CR1_MSTR BIT(2)
35#define STM32F4_SPI_CR1_BR_SHIFT 3
36#define STM32F4_SPI_CR1_BR GENMASK(5, 3)
37#define STM32F4_SPI_CR1_SPE BIT(6)
38#define STM32F4_SPI_CR1_LSBFRST BIT(7)
39#define STM32F4_SPI_CR1_SSI BIT(8)
40#define STM32F4_SPI_CR1_SSM BIT(9)
41#define STM32F4_SPI_CR1_RXONLY BIT(10)
42#define STM32F4_SPI_CR1_DFF BIT(11)
43#define STM32F4_SPI_CR1_CRCNEXT BIT(12)
44#define STM32F4_SPI_CR1_CRCEN BIT(13)
45#define STM32F4_SPI_CR1_BIDIOE BIT(14)
46#define STM32F4_SPI_CR1_BIDIMODE BIT(15)
47#define STM32F4_SPI_CR1_BR_MIN 0
48#define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
49
50/* STM32F4_SPI_CR2 bit fields */
51#define STM32F4_SPI_CR2_RXDMAEN BIT(0)
52#define STM32F4_SPI_CR2_TXDMAEN BIT(1)
53#define STM32F4_SPI_CR2_SSOE BIT(2)
54#define STM32F4_SPI_CR2_FRF BIT(4)
55#define STM32F4_SPI_CR2_ERRIE BIT(5)
56#define STM32F4_SPI_CR2_RXNEIE BIT(6)
57#define STM32F4_SPI_CR2_TXEIE BIT(7)
58
59/* STM32F4_SPI_SR bit fields */
60#define STM32F4_SPI_SR_RXNE BIT(0)
61#define STM32F4_SPI_SR_TXE BIT(1)
62#define STM32F4_SPI_SR_CHSIDE BIT(2)
63#define STM32F4_SPI_SR_UDR BIT(3)
64#define STM32F4_SPI_SR_CRCERR BIT(4)
65#define STM32F4_SPI_SR_MODF BIT(5)
66#define STM32F4_SPI_SR_OVR BIT(6)
67#define STM32F4_SPI_SR_BSY BIT(7)
68#define STM32F4_SPI_SR_FRE BIT(8)
69
70/* STM32F4_SPI_I2SCFGR bit fields */
71#define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
72
73/* STM32F4 SPI Baud Rate min/max divisor */
74#define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
75#define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
76
77/* STM32H7 SPI registers */
78#define STM32H7_SPI_CR1 0x00
79#define STM32H7_SPI_CR2 0x04
80#define STM32H7_SPI_CFG1 0x08
81#define STM32H7_SPI_CFG2 0x0C
82#define STM32H7_SPI_IER 0x10
83#define STM32H7_SPI_SR 0x14
84#define STM32H7_SPI_IFCR 0x18
85#define STM32H7_SPI_TXDR 0x20
86#define STM32H7_SPI_RXDR 0x30
87#define STM32H7_SPI_I2SCFGR 0x50
88
89/* STM32H7_SPI_CR1 bit fields */
90#define STM32H7_SPI_CR1_SPE BIT(0)
91#define STM32H7_SPI_CR1_MASRX BIT(8)
92#define STM32H7_SPI_CR1_CSTART BIT(9)
93#define STM32H7_SPI_CR1_CSUSP BIT(10)
94#define STM32H7_SPI_CR1_HDDIR BIT(11)
95#define STM32H7_SPI_CR1_SSI BIT(12)
96
97/* STM32H7_SPI_CR2 bit fields */
98#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
100
101/* STM32H7_SPI_CFG1 bit fields */
102#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
107#define STM32H7_SPI_CFG1_MBR_SHIFT 28
108#define STM32H7_SPI_CFG1_MBR_MIN 0
109#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
110
111/* STM32H7_SPI_CFG2 bit fields */
112#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
113#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
114#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
115#define STM32H7_SPI_CFG2_MASTER BIT(22)
116#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
117#define STM32H7_SPI_CFG2_CPHA BIT(24)
118#define STM32H7_SPI_CFG2_CPOL BIT(25)
119#define STM32H7_SPI_CFG2_SSM BIT(26)
120#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
121
122/* STM32H7_SPI_IER bit fields */
123#define STM32H7_SPI_IER_RXPIE BIT(0)
124#define STM32H7_SPI_IER_TXPIE BIT(1)
125#define STM32H7_SPI_IER_DXPIE BIT(2)
126#define STM32H7_SPI_IER_EOTIE BIT(3)
127#define STM32H7_SPI_IER_TXTFIE BIT(4)
128#define STM32H7_SPI_IER_OVRIE BIT(6)
129#define STM32H7_SPI_IER_MODFIE BIT(9)
130#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
131
132/* STM32H7_SPI_SR bit fields */
133#define STM32H7_SPI_SR_RXP BIT(0)
134#define STM32H7_SPI_SR_TXP BIT(1)
135#define STM32H7_SPI_SR_EOT BIT(3)
136#define STM32H7_SPI_SR_OVR BIT(6)
137#define STM32H7_SPI_SR_MODF BIT(9)
138#define STM32H7_SPI_SR_SUSP BIT(11)
139#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
140#define STM32H7_SPI_SR_RXWNE BIT(15)
141
142/* STM32H7_SPI_IFCR bit fields */
143#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
144
145/* STM32H7_SPI_I2SCFGR bit fields */
146#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
147
148/* STM32H7 SPI Master Baud Rate min/max divisor */
149#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
150#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
151
152/* STM32H7 SPI Communication mode */
153#define STM32H7_SPI_FULL_DUPLEX 0
154#define STM32H7_SPI_SIMPLEX_TX 1
155#define STM32H7_SPI_SIMPLEX_RX 2
156#define STM32H7_SPI_HALF_DUPLEX 3
157
158/* SPI Communication type */
159#define SPI_FULL_DUPLEX 0
160#define SPI_SIMPLEX_TX 1
161#define SPI_SIMPLEX_RX 2
162#define SPI_3WIRE_TX 3
163#define SPI_3WIRE_RX 4
164
165/*
166 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
167 * without fifo buffers.
168 */
169#define SPI_DMA_MIN_BYTES 16
170
171/**
172 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
173 * @reg: register offset
174 * @mask: bitfield mask
175 * @shift: left shift
176 */
177struct stm32_spi_reg {
178 int reg;
179 int mask;
180 int shift;
181};
182
183/**
184 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
185 * @en: enable register and SPI enable bit
186 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
187 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
188 * @cpol: clock polarity register and polarity bit
189 * @cpha: clock phase register and phase bit
190 * @lsb_first: LSB transmitted first register and bit
191 * @br: baud rate register and bitfields
192 * @rx: SPI RX data register
193 * @tx: SPI TX data register
194 */
195struct stm32_spi_regspec {
196 const struct stm32_spi_reg en;
197 const struct stm32_spi_reg dma_rx_en;
198 const struct stm32_spi_reg dma_tx_en;
199 const struct stm32_spi_reg cpol;
200 const struct stm32_spi_reg cpha;
201 const struct stm32_spi_reg lsb_first;
202 const struct stm32_spi_reg br;
203 const struct stm32_spi_reg rx;
204 const struct stm32_spi_reg tx;
205};
206
207struct stm32_spi;
208
209/**
210 * struct stm32_spi_cfg - stm32 compatible configuration data
211 * @regs: registers descriptions
212 * @get_fifo_size: routine to get fifo size
213 * @get_bpw_mask: routine to get bits per word mask
214 * @disable: routine to disable controller
215 * @config: routine to configure controller as SPI Master
216 * @set_bpw: routine to configure registers to for bits per word
217 * @set_mode: routine to configure registers to desired mode
218 * @set_data_idleness: optional routine to configure registers to desired idle
219 * time between frames (if driver has this functionality)
220 * @set_number_of_data: optional routine to configure registers to desired
221 * number of data (if driver has this functionality)
222 * @can_dma: routine to determine if the transfer is eligible for DMA use
223 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
224 * using DMA
225 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
226 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
227 * @transfer_one_irq: routine to configure interrupts for driver
228 * @irq_handler_event: Interrupt handler for SPI controller events
229 * @irq_handler_thread: thread of interrupt handler for SPI controller
230 * @baud_rate_div_min: minimum baud rate divisor
231 * @baud_rate_div_max: maximum baud rate divisor
232 * @has_fifo: boolean to know if fifo is used for driver
233 * @has_startbit: boolean to know if start bit is used to start transfer
234 */
235struct stm32_spi_cfg {
236 const struct stm32_spi_regspec *regs;
237 int (*get_fifo_size)(struct stm32_spi *spi);
238 int (*get_bpw_mask)(struct stm32_spi *spi);
239 void (*disable)(struct stm32_spi *spi);
240 int (*config)(struct stm32_spi *spi);
241 void (*set_bpw)(struct stm32_spi *spi);
242 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
243 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
244 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
245 void (*transfer_one_dma_start)(struct stm32_spi *spi);
246 void (*dma_rx_cb)(void *data);
247 void (*dma_tx_cb)(void *data);
248 int (*transfer_one_irq)(struct stm32_spi *spi);
249 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
250 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
251 unsigned int baud_rate_div_min;
252 unsigned int baud_rate_div_max;
253 bool has_fifo;
254};
255
256/**
257 * struct stm32_spi - private data of the SPI controller
258 * @dev: driver model representation of the controller
259 * @master: controller master interface
260 * @cfg: compatible configuration data
261 * @base: virtual memory area
262 * @clk: hw kernel clock feeding the SPI clock generator
263 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
264 * @lock: prevent I/O concurrent access
265 * @irq: SPI controller interrupt line
266 * @fifo_size: size of the embedded fifo in bytes
267 * @cur_midi: master inter-data idleness in ns
268 * @cur_speed: speed configured in Hz
269 * @cur_bpw: number of bits in a single SPI data frame
270 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
271 * @cur_comm: SPI communication mode
272 * @cur_xferlen: current transfer length in bytes
273 * @cur_usedma: boolean to know if dma is used in current transfer
274 * @tx_buf: data to be written, or NULL
275 * @rx_buf: data to be read, or NULL
276 * @tx_len: number of data to be written in bytes
277 * @rx_len: number of data to be read in bytes
278 * @dma_tx: dma channel for TX transfer
279 * @dma_rx: dma channel for RX transfer
280 * @phys_addr: SPI registers physical base address
281 */
282struct stm32_spi {
283 struct device *dev;
284 struct spi_master *master;
285 const struct stm32_spi_cfg *cfg;
286 void __iomem *base;
287 struct clk *clk;
288 u32 clk_rate;
289 spinlock_t lock; /* prevent I/O concurrent access */
290 int irq;
291 unsigned int fifo_size;
292
293 unsigned int cur_midi;
294 unsigned int cur_speed;
295 unsigned int cur_bpw;
296 unsigned int cur_fthlv;
297 unsigned int cur_comm;
298 unsigned int cur_xferlen;
299 bool cur_usedma;
300
301 const void *tx_buf;
302 void *rx_buf;
303 int tx_len;
304 int rx_len;
305 struct dma_chan *dma_tx;
306 struct dma_chan *dma_rx;
307 dma_addr_t phys_addr;
308};
309
310static const struct stm32_spi_regspec stm32f4_spi_regspec = {
311 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
312
313 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
314 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
315
316 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
317 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
318 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
319 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
320
321 .rx = { STM32F4_SPI_DR },
322 .tx = { STM32F4_SPI_DR },
323};
324
325static const struct stm32_spi_regspec stm32h7_spi_regspec = {
326 /* SPI data transfer is enabled but spi_ker_ck is idle.
327 * CFG1 and CFG2 registers are write protected when SPE is enabled.
328 */
329 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
330
331 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
332 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
333
334 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
335 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
336 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
337 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
338 STM32H7_SPI_CFG1_MBR_SHIFT },
339
340 .rx = { STM32H7_SPI_RXDR },
341 .tx = { STM32H7_SPI_TXDR },
342};
343
344static inline void stm32_spi_set_bits(struct stm32_spi *spi,
345 u32 offset, u32 bits)
346{
347 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
348 spi->base + offset);
349}
350
351static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
352 u32 offset, u32 bits)
353{
354 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
355 spi->base + offset);
356}
357
358/**
359 * stm32h7_spi_get_fifo_size - Return fifo size
360 * @spi: pointer to the spi controller data structure
361 */
362static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
363{
364 unsigned long flags;
365 u32 count = 0;
366
367 spin_lock_irqsave(&spi->lock, flags);
368
369 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
370
371 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
372 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
373
374 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
375
376 spin_unlock_irqrestore(&spi->lock, flags);
377
378 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
379
380 return count;
381}
382
383/**
384 * stm32f4_spi_get_bpw_mask - Return bits per word mask
385 * @spi: pointer to the spi controller data structure
386 */
387static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
388{
389 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
390 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
391}
392
393/**
394 * stm32h7_spi_get_bpw_mask - Return bits per word mask
395 * @spi: pointer to the spi controller data structure
396 */
397static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
398{
399 unsigned long flags;
400 u32 cfg1, max_bpw;
401
402 spin_lock_irqsave(&spi->lock, flags);
403
404 /*
405 * The most significant bit at DSIZE bit field is reserved when the
406 * maximum data size of periperal instances is limited to 16-bit
407 */
408 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
409
410 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
411 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
412
413 spin_unlock_irqrestore(&spi->lock, flags);
414
415 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
416
417 return SPI_BPW_RANGE_MASK(4, max_bpw);
418}
419
420/**
421 * stm32_spi_prepare_mbr - Determine baud rate divisor value
422 * @spi: pointer to the spi controller data structure
423 * @speed_hz: requested speed
424 * @min_div: minimum baud rate divisor
425 * @max_div: maximum baud rate divisor
426 *
427 * Return baud rate divisor value in case of success or -EINVAL
428 */
429static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
430 u32 min_div, u32 max_div)
431{
432 u32 div, mbrdiv;
433
434 /* Ensure spi->clk_rate is even */
435 div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
436
437 /*
438 * SPI framework set xfer->speed_hz to master->max_speed_hz if
439 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
440 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
441 * no need to check it there.
442 * However, we need to ensure the following calculations.
443 */
444 if ((div < min_div) || (div > max_div))
445 return -EINVAL;
446
447 /* Determine the first power of 2 greater than or equal to div */
448 if (div & (div - 1))
449 mbrdiv = fls(div);
450 else
451 mbrdiv = fls(div) - 1;
452
453 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
454
455 return mbrdiv - 1;
456}
457
458/**
459 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
460 * @spi: pointer to the spi controller data structure
461 * @xfer_len: length of the message to be transferred
462 */
463static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
464{
465 u32 packet, bpw;
466
467 /* data packet should not exceed 1/2 of fifo space */
468 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
469
470 /* align packet size with data registers access */
471 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
472 return DIV_ROUND_UP(packet, bpw);
473}
474
475/**
476 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
477 * @spi: pointer to the spi controller data structure
478 *
479 * Read from tx_buf depends on remaining bytes to avoid to read beyond
480 * tx_buf end.
481 */
482static void stm32f4_spi_write_tx(struct stm32_spi *spi)
483{
484 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
485 STM32F4_SPI_SR_TXE)) {
486 u32 offs = spi->cur_xferlen - spi->tx_len;
487
488 if (spi->cur_bpw == 16) {
489 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
490
491 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
492 spi->tx_len -= sizeof(u16);
493 } else {
494 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
495
496 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
497 spi->tx_len -= sizeof(u8);
498 }
499 }
500
501 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
502}
503
504/**
505 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
506 * @spi: pointer to the spi controller data structure
507 *
508 * Read from tx_buf depends on remaining bytes to avoid to read beyond
509 * tx_buf end.
510 */
511static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
512{
513 while ((spi->tx_len > 0) &&
514 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
515 STM32H7_SPI_SR_TXP)) {
516 u32 offs = spi->cur_xferlen - spi->tx_len;
517
518 if (spi->tx_len >= sizeof(u32)) {
519 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
520
521 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
522 spi->tx_len -= sizeof(u32);
523 } else if (spi->tx_len >= sizeof(u16)) {
524 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
525
526 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
527 spi->tx_len -= sizeof(u16);
528 } else {
529 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
530
531 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
532 spi->tx_len -= sizeof(u8);
533 }
534 }
535
536 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
537}
538
539/**
540 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
541 * @spi: pointer to the spi controller data structure
542 *
543 * Write in rx_buf depends on remaining bytes to avoid to write beyond
544 * rx_buf end.
545 */
546static void stm32f4_spi_read_rx(struct stm32_spi *spi)
547{
548 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
549 STM32F4_SPI_SR_RXNE)) {
550 u32 offs = spi->cur_xferlen - spi->rx_len;
551
552 if (spi->cur_bpw == 16) {
553 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
554
555 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
556 spi->rx_len -= sizeof(u16);
557 } else {
558 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
559
560 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
561 spi->rx_len -= sizeof(u8);
562 }
563 }
564
565 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
566}
567
568/**
569 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
570 * @spi: pointer to the spi controller data structure
571 * @flush: boolean indicating that FIFO should be flushed
572 *
573 * Write in rx_buf depends on remaining bytes to avoid to write beyond
574 * rx_buf end.
575 */
576static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
577{
578 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
579 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
580
581 while ((spi->rx_len > 0) &&
582 ((sr & STM32H7_SPI_SR_RXP) ||
583 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
584 u32 offs = spi->cur_xferlen - spi->rx_len;
585
586 if ((spi->rx_len >= sizeof(u32)) ||
587 (flush && (sr & STM32H7_SPI_SR_RXWNE))) {
588 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
589
590 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
591 spi->rx_len -= sizeof(u32);
592 } else if ((spi->rx_len >= sizeof(u16)) ||
593 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
594 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
595
596 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
597 spi->rx_len -= sizeof(u16);
598 } else {
599 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
600
601 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
602 spi->rx_len -= sizeof(u8);
603 }
604
605 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
606 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
607 }
608
609 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
610 flush ? "(flush)" : "", spi->rx_len);
611}
612
613/**
614 * stm32_spi_enable - Enable SPI controller
615 * @spi: pointer to the spi controller data structure
616 */
617static void stm32_spi_enable(struct stm32_spi *spi)
618{
619 dev_dbg(spi->dev, "enable controller\n");
620
621 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
622 spi->cfg->regs->en.mask);
623}
624
625/**
626 * stm32f4_spi_disable - Disable SPI controller
627 * @spi: pointer to the spi controller data structure
628 */
629static void stm32f4_spi_disable(struct stm32_spi *spi)
630{
631 unsigned long flags;
632 u32 sr;
633
634 dev_dbg(spi->dev, "disable controller\n");
635
636 spin_lock_irqsave(&spi->lock, flags);
637
638 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
639 STM32F4_SPI_CR1_SPE)) {
640 spin_unlock_irqrestore(&spi->lock, flags);
641 return;
642 }
643
644 /* Disable interrupts */
645 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
646 STM32F4_SPI_CR2_RXNEIE |
647 STM32F4_SPI_CR2_ERRIE);
648
649 /* Wait until BSY = 0 */
650 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
651 sr, !(sr & STM32F4_SPI_SR_BSY),
652 10, 100000) < 0) {
653 dev_warn(spi->dev, "disabling condition timeout\n");
654 }
655
656 if (spi->cur_usedma && spi->dma_tx)
657 dmaengine_terminate_all(spi->dma_tx);
658 if (spi->cur_usedma && spi->dma_rx)
659 dmaengine_terminate_all(spi->dma_rx);
660
661 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
662
663 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
664 STM32F4_SPI_CR2_RXDMAEN);
665
666 /* Sequence to clear OVR flag */
667 readl_relaxed(spi->base + STM32F4_SPI_DR);
668 readl_relaxed(spi->base + STM32F4_SPI_SR);
669
670 spin_unlock_irqrestore(&spi->lock, flags);
671}
672
673/**
674 * stm32h7_spi_disable - Disable SPI controller
675 * @spi: pointer to the spi controller data structure
676 *
677 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
678 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
679 * RX-Fifo.
680 * Normally, if TSIZE has been configured, we should relax the hardware at the
681 * reception of the EOT interrupt. But in case of error, EOT will not be
682 * raised. So the subsystem unprepare_message call allows us to properly
683 * complete the transfer from an hardware point of view.
684 */
685static void stm32h7_spi_disable(struct stm32_spi *spi)
686{
687 unsigned long flags;
688 u32 cr1, sr;
689
690 dev_dbg(spi->dev, "disable controller\n");
691
692 spin_lock_irqsave(&spi->lock, flags);
693
694 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
695
696 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
697 spin_unlock_irqrestore(&spi->lock, flags);
698 return;
699 }
700
701 /* Wait on EOT or suspend the flow */
702 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
703 sr, !(sr & STM32H7_SPI_SR_EOT),
704 10, 100000) < 0) {
705 if (cr1 & STM32H7_SPI_CR1_CSTART) {
706 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
707 spi->base + STM32H7_SPI_CR1);
708 if (readl_relaxed_poll_timeout_atomic(
709 spi->base + STM32H7_SPI_SR,
710 sr, !(sr & STM32H7_SPI_SR_SUSP),
711 10, 100000) < 0)
712 dev_warn(spi->dev,
713 "Suspend request timeout\n");
714 }
715 }
716
717 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
718 stm32h7_spi_read_rxfifo(spi, true);
719
720 if (spi->cur_usedma && spi->dma_tx)
721 dmaengine_terminate_all(spi->dma_tx);
722 if (spi->cur_usedma && spi->dma_rx)
723 dmaengine_terminate_all(spi->dma_rx);
724
725 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
726
727 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
728 STM32H7_SPI_CFG1_RXDMAEN);
729
730 /* Disable interrupts and clear status flags */
731 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
732 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
733
734 spin_unlock_irqrestore(&spi->lock, flags);
735}
736
737/**
738 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
739 * @master: controller master interface
740 * @spi_dev: pointer to the spi device
741 * @transfer: pointer to spi transfer
742 *
743 * If driver has fifo and the current transfer size is greater than fifo size,
744 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
745 */
746static bool stm32_spi_can_dma(struct spi_master *master,
747 struct spi_device *spi_dev,
748 struct spi_transfer *transfer)
749{
750 unsigned int dma_size;
751 struct stm32_spi *spi = spi_master_get_devdata(master);
752
753 if (spi->cfg->has_fifo)
754 dma_size = spi->fifo_size;
755 else
756 dma_size = SPI_DMA_MIN_BYTES;
757
758 dev_dbg(spi->dev, "%s: %s\n", __func__,
759 (transfer->len > dma_size) ? "true" : "false");
760
761 return (transfer->len > dma_size);
762}
763
764/**
765 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
766 * @irq: interrupt line
767 * @dev_id: SPI controller master interface
768 */
769static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
770{
771 struct spi_master *master = dev_id;
772 struct stm32_spi *spi = spi_master_get_devdata(master);
773 u32 sr, mask = 0;
774 bool end = false;
775
776 spin_lock(&spi->lock);
777
778 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
779 /*
780 * BSY flag is not handled in interrupt but it is normal behavior when
781 * this flag is set.
782 */
783 sr &= ~STM32F4_SPI_SR_BSY;
784
785 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
786 spi->cur_comm == SPI_3WIRE_TX)) {
787 /* OVR flag shouldn't be handled for TX only mode */
788 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
789 mask |= STM32F4_SPI_SR_TXE;
790 }
791
792 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
793 spi->cur_comm == SPI_SIMPLEX_RX ||
794 spi->cur_comm == SPI_3WIRE_RX)) {
795 /* TXE flag is set and is handled when RXNE flag occurs */
796 sr &= ~STM32F4_SPI_SR_TXE;
797 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
798 }
799
800 if (!(sr & mask)) {
801 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
802 spin_unlock(&spi->lock);
803 return IRQ_NONE;
804 }
805
806 if (sr & STM32F4_SPI_SR_OVR) {
807 dev_warn(spi->dev, "Overrun: received value discarded\n");
808
809 /* Sequence to clear OVR flag */
810 readl_relaxed(spi->base + STM32F4_SPI_DR);
811 readl_relaxed(spi->base + STM32F4_SPI_SR);
812
813 /*
814 * If overrun is detected, it means that something went wrong,
815 * so stop the current transfer. Transfer can wait for next
816 * RXNE but DR is already read and end never happens.
817 */
818 end = true;
819 goto end_irq;
820 }
821
822 if (sr & STM32F4_SPI_SR_TXE) {
823 if (spi->tx_buf)
824 stm32f4_spi_write_tx(spi);
825 if (spi->tx_len == 0)
826 end = true;
827 }
828
829 if (sr & STM32F4_SPI_SR_RXNE) {
830 stm32f4_spi_read_rx(spi);
831 if (spi->rx_len == 0)
832 end = true;
833 else if (spi->tx_buf)/* Load data for discontinuous mode */
834 stm32f4_spi_write_tx(spi);
835 }
836
837end_irq:
838 if (end) {
839 /* Immediately disable interrupts to do not generate new one */
840 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
841 STM32F4_SPI_CR2_TXEIE |
842 STM32F4_SPI_CR2_RXNEIE |
843 STM32F4_SPI_CR2_ERRIE);
844 spin_unlock(&spi->lock);
845 return IRQ_WAKE_THREAD;
846 }
847
848 spin_unlock(&spi->lock);
849 return IRQ_HANDLED;
850}
851
852/**
853 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
854 * @irq: interrupt line
855 * @dev_id: SPI controller master interface
856 */
857static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
858{
859 struct spi_master *master = dev_id;
860 struct stm32_spi *spi = spi_master_get_devdata(master);
861
862 spi_finalize_current_transfer(master);
863 stm32f4_spi_disable(spi);
864
865 return IRQ_HANDLED;
866}
867
868/**
869 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
870 * @irq: interrupt line
871 * @dev_id: SPI controller master interface
872 */
873static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
874{
875 struct spi_master *master = dev_id;
876 struct stm32_spi *spi = spi_master_get_devdata(master);
877 u32 sr, ier, mask;
878 unsigned long flags;
879 bool end = false;
880
881 spin_lock_irqsave(&spi->lock, flags);
882
883 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
884 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
885
886 mask = ier;
887 /*
888 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
889 * SUSP to acknowledge it later. TXC is automatically cleared
890 */
891
892 mask |= STM32H7_SPI_SR_SUSP;
893 /*
894 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
895 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
896 */
897 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
898 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
899
900 if (!(sr & mask)) {
901 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
902 sr, ier);
903 spin_unlock_irqrestore(&spi->lock, flags);
904 return IRQ_NONE;
905 }
906
907 if (sr & STM32H7_SPI_SR_SUSP) {
908 static DEFINE_RATELIMIT_STATE(rs,
909 DEFAULT_RATELIMIT_INTERVAL * 10,
910 1);
911 if (__ratelimit(&rs))
912 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
913 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
914 stm32h7_spi_read_rxfifo(spi, false);
915 /*
916 * If communication is suspended while using DMA, it means
917 * that something went wrong, so stop the current transfer
918 */
919 if (spi->cur_usedma)
920 end = true;
921 }
922
923 if (sr & STM32H7_SPI_SR_MODF) {
924 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
925 end = true;
926 }
927
928 if (sr & STM32H7_SPI_SR_OVR) {
929 dev_err(spi->dev, "Overrun: RX data lost\n");
930 end = true;
931 }
932
933 if (sr & STM32H7_SPI_SR_EOT) {
934 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
935 stm32h7_spi_read_rxfifo(spi, true);
936 end = true;
937 }
938
939 if (sr & STM32H7_SPI_SR_TXP)
940 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
941 stm32h7_spi_write_txfifo(spi);
942
943 if (sr & STM32H7_SPI_SR_RXP)
944 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
945 stm32h7_spi_read_rxfifo(spi, false);
946
947 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
948
949 spin_unlock_irqrestore(&spi->lock, flags);
950
951 if (end) {
952 stm32h7_spi_disable(spi);
953 spi_finalize_current_transfer(master);
954 }
955
956 return IRQ_HANDLED;
957}
958
959/**
960 * stm32_spi_prepare_msg - set up the controller to transfer a single message
961 * @master: controller master interface
962 * @msg: pointer to spi message
963 */
964static int stm32_spi_prepare_msg(struct spi_master *master,
965 struct spi_message *msg)
966{
967 struct stm32_spi *spi = spi_master_get_devdata(master);
968 struct spi_device *spi_dev = msg->spi;
969 struct device_node *np = spi_dev->dev.of_node;
970 unsigned long flags;
971 u32 clrb = 0, setb = 0;
972
973 /* SPI slave device may need time between data frames */
974 spi->cur_midi = 0;
975 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
976 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
977
978 if (spi_dev->mode & SPI_CPOL)
979 setb |= spi->cfg->regs->cpol.mask;
980 else
981 clrb |= spi->cfg->regs->cpol.mask;
982
983 if (spi_dev->mode & SPI_CPHA)
984 setb |= spi->cfg->regs->cpha.mask;
985 else
986 clrb |= spi->cfg->regs->cpha.mask;
987
988 if (spi_dev->mode & SPI_LSB_FIRST)
989 setb |= spi->cfg->regs->lsb_first.mask;
990 else
991 clrb |= spi->cfg->regs->lsb_first.mask;
992
993 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
994 !!(spi_dev->mode & SPI_CPOL),
995 !!(spi_dev->mode & SPI_CPHA),
996 !!(spi_dev->mode & SPI_LSB_FIRST),
997 !!(spi_dev->mode & SPI_CS_HIGH));
998
999 /* On STM32H7, messages should not exceed a maximum size setted
1000 * afterward via the set_number_of_data function. In order to
1001 * ensure that, split large messages into several messages
1002 */
1003 if (spi->cfg->set_number_of_data) {
1004 int ret;
1005
1006 ret = spi_split_transfers_maxsize(master, msg,
1007 STM32H7_SPI_TSIZE_MAX,
1008 GFP_KERNEL | GFP_DMA);
1009 if (ret)
1010 return ret;
1011 }
1012
1013 spin_lock_irqsave(&spi->lock, flags);
1014
1015 /* CPOL, CPHA and LSB FIRST bits have common register */
1016 if (clrb || setb)
1017 writel_relaxed(
1018 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1019 ~clrb) | setb,
1020 spi->base + spi->cfg->regs->cpol.reg);
1021
1022 spin_unlock_irqrestore(&spi->lock, flags);
1023
1024 return 0;
1025}
1026
1027/**
1028 * stm32f4_spi_dma_tx_cb - dma callback
1029 * @data: pointer to the spi controller data structure
1030 *
1031 * DMA callback is called when the transfer is complete for DMA TX channel.
1032 */
1033static void stm32f4_spi_dma_tx_cb(void *data)
1034{
1035 struct stm32_spi *spi = data;
1036
1037 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1038 spi_finalize_current_transfer(spi->master);
1039 stm32f4_spi_disable(spi);
1040 }
1041}
1042
1043/**
1044 * stm32f4_spi_dma_rx_cb - dma callback
1045 * @data: pointer to the spi controller data structure
1046 *
1047 * DMA callback is called when the transfer is complete for DMA RX channel.
1048 */
1049static void stm32f4_spi_dma_rx_cb(void *data)
1050{
1051 struct stm32_spi *spi = data;
1052
1053 spi_finalize_current_transfer(spi->master);
1054 stm32f4_spi_disable(spi);
1055}
1056
1057/**
1058 * stm32h7_spi_dma_cb - dma callback
1059 * @data: pointer to the spi controller data structure
1060 *
1061 * DMA callback is called when the transfer is complete or when an error
1062 * occurs. If the transfer is complete, EOT flag is raised.
1063 */
1064static void stm32h7_spi_dma_cb(void *data)
1065{
1066 struct stm32_spi *spi = data;
1067 unsigned long flags;
1068 u32 sr;
1069
1070 spin_lock_irqsave(&spi->lock, flags);
1071
1072 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1073
1074 spin_unlock_irqrestore(&spi->lock, flags);
1075
1076 if (!(sr & STM32H7_SPI_SR_EOT))
1077 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
1078
1079 /* Now wait for EOT, or SUSP or OVR in case of error */
1080}
1081
1082/**
1083 * stm32_spi_dma_config - configure dma slave channel depending on current
1084 * transfer bits_per_word.
1085 * @spi: pointer to the spi controller data structure
1086 * @dma_conf: pointer to the dma_slave_config structure
1087 * @dir: direction of the dma transfer
1088 */
1089static void stm32_spi_dma_config(struct stm32_spi *spi,
1090 struct dma_slave_config *dma_conf,
1091 enum dma_transfer_direction dir)
1092{
1093 enum dma_slave_buswidth buswidth;
1094 u32 maxburst;
1095
1096 if (spi->cur_bpw <= 8)
1097 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1098 else if (spi->cur_bpw <= 16)
1099 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1100 else
1101 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1102
1103 if (spi->cfg->has_fifo) {
1104 /* Valid for DMA Half or Full Fifo threshold */
1105 if (spi->cur_fthlv == 2)
1106 maxburst = 1;
1107 else
1108 maxburst = spi->cur_fthlv;
1109 } else {
1110 maxburst = 1;
1111 }
1112
1113 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1114 dma_conf->direction = dir;
1115 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1116 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1117 dma_conf->src_addr_width = buswidth;
1118 dma_conf->src_maxburst = maxburst;
1119
1120 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1121 buswidth, maxburst);
1122 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1123 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1124 dma_conf->dst_addr_width = buswidth;
1125 dma_conf->dst_maxburst = maxburst;
1126
1127 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1128 buswidth, maxburst);
1129 }
1130}
1131
1132/**
1133 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1134 * interrupts
1135 * @spi: pointer to the spi controller data structure
1136 *
1137 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1138 * in progress.
1139 */
1140static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1141{
1142 unsigned long flags;
1143 u32 cr2 = 0;
1144
1145 /* Enable the interrupts relative to the current communication mode */
1146 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1147 cr2 |= STM32F4_SPI_CR2_TXEIE;
1148 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1149 spi->cur_comm == SPI_SIMPLEX_RX ||
1150 spi->cur_comm == SPI_3WIRE_RX) {
1151 /* In transmit-only mode, the OVR flag is set in the SR register
1152 * since the received data are never read. Therefore set OVR
1153 * interrupt only when rx buffer is available.
1154 */
1155 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1156 } else {
1157 return -EINVAL;
1158 }
1159
1160 spin_lock_irqsave(&spi->lock, flags);
1161
1162 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1163
1164 stm32_spi_enable(spi);
1165
1166 /* starting data transfer when buffer is loaded */
1167 if (spi->tx_buf)
1168 stm32f4_spi_write_tx(spi);
1169
1170 spin_unlock_irqrestore(&spi->lock, flags);
1171
1172 return 1;
1173}
1174
1175/**
1176 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1177 * interrupts
1178 * @spi: pointer to the spi controller data structure
1179 *
1180 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1181 * in progress.
1182 */
1183static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1184{
1185 unsigned long flags;
1186 u32 ier = 0;
1187
1188 /* Enable the interrupts relative to the current communication mode */
1189 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1190 ier |= STM32H7_SPI_IER_DXPIE;
1191 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1192 ier |= STM32H7_SPI_IER_TXPIE;
1193 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1194 ier |= STM32H7_SPI_IER_RXPIE;
1195
1196 /* Enable the interrupts relative to the end of transfer */
1197 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1198 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1199
1200 spin_lock_irqsave(&spi->lock, flags);
1201
1202 stm32_spi_enable(spi);
1203
1204 /* Be sure to have data in fifo before starting data transfer */
1205 if (spi->tx_buf)
1206 stm32h7_spi_write_txfifo(spi);
1207
1208 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1209
1210 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1211
1212 spin_unlock_irqrestore(&spi->lock, flags);
1213
1214 return 1;
1215}
1216
1217/**
1218 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1219 * transfer using DMA
1220 * @spi: pointer to the spi controller data structure
1221 */
1222static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1223{
1224 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1225 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1226 spi->cur_comm == SPI_FULL_DUPLEX) {
1227 /*
1228 * In transmit-only mode, the OVR flag is set in the SR register
1229 * since the received data are never read. Therefore set OVR
1230 * interrupt only when rx buffer is available.
1231 */
1232 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1233 }
1234
1235 stm32_spi_enable(spi);
1236}
1237
1238/**
1239 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1240 * transfer using DMA
1241 * @spi: pointer to the spi controller data structure
1242 */
1243static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1244{
1245 /* Enable the interrupts relative to the end of transfer */
1246 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
1247 STM32H7_SPI_IER_TXTFIE |
1248 STM32H7_SPI_IER_OVRIE |
1249 STM32H7_SPI_IER_MODFIE);
1250
1251 stm32_spi_enable(spi);
1252
1253 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1254}
1255
1256/**
1257 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1258 * @spi: pointer to the spi controller data structure
1259 * @xfer: pointer to the spi_transfer structure
1260 *
1261 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1262 * in progress.
1263 */
1264static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1265 struct spi_transfer *xfer)
1266{
1267 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1268 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1269 unsigned long flags;
1270
1271 spin_lock_irqsave(&spi->lock, flags);
1272
1273 rx_dma_desc = NULL;
1274 if (spi->rx_buf && spi->dma_rx) {
1275 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1276 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1277
1278 /* Enable Rx DMA request */
1279 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1280 spi->cfg->regs->dma_rx_en.mask);
1281
1282 rx_dma_desc = dmaengine_prep_slave_sg(
1283 spi->dma_rx, xfer->rx_sg.sgl,
1284 xfer->rx_sg.nents,
1285 rx_dma_conf.direction,
1286 DMA_PREP_INTERRUPT);
1287 }
1288
1289 tx_dma_desc = NULL;
1290 if (spi->tx_buf && spi->dma_tx) {
1291 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1292 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1293
1294 tx_dma_desc = dmaengine_prep_slave_sg(
1295 spi->dma_tx, xfer->tx_sg.sgl,
1296 xfer->tx_sg.nents,
1297 tx_dma_conf.direction,
1298 DMA_PREP_INTERRUPT);
1299 }
1300
1301 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1302 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1303 goto dma_desc_error;
1304
1305 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1306 goto dma_desc_error;
1307
1308 if (rx_dma_desc) {
1309 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1310 rx_dma_desc->callback_param = spi;
1311
1312 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1313 dev_err(spi->dev, "Rx DMA submit failed\n");
1314 goto dma_desc_error;
1315 }
1316 /* Enable Rx DMA channel */
1317 dma_async_issue_pending(spi->dma_rx);
1318 }
1319
1320 if (tx_dma_desc) {
1321 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1322 spi->cur_comm == SPI_3WIRE_TX) {
1323 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1324 tx_dma_desc->callback_param = spi;
1325 }
1326
1327 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1328 dev_err(spi->dev, "Tx DMA submit failed\n");
1329 goto dma_submit_error;
1330 }
1331 /* Enable Tx DMA channel */
1332 dma_async_issue_pending(spi->dma_tx);
1333
1334 /* Enable Tx DMA request */
1335 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1336 spi->cfg->regs->dma_tx_en.mask);
1337 }
1338
1339 spi->cfg->transfer_one_dma_start(spi);
1340
1341 spin_unlock_irqrestore(&spi->lock, flags);
1342
1343 return 1;
1344
1345dma_submit_error:
1346 if (spi->dma_rx)
1347 dmaengine_terminate_all(spi->dma_rx);
1348
1349dma_desc_error:
1350 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1351 spi->cfg->regs->dma_rx_en.mask);
1352
1353 spin_unlock_irqrestore(&spi->lock, flags);
1354
1355 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1356
1357 spi->cur_usedma = false;
1358 return spi->cfg->transfer_one_irq(spi);
1359}
1360
1361/**
1362 * stm32f4_spi_set_bpw - Configure bits per word
1363 * @spi: pointer to the spi controller data structure
1364 */
1365static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1366{
1367 if (spi->cur_bpw == 16)
1368 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1369 else
1370 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1371}
1372
1373/**
1374 * stm32h7_spi_set_bpw - configure bits per word
1375 * @spi: pointer to the spi controller data structure
1376 */
1377static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1378{
1379 u32 bpw, fthlv;
1380 u32 cfg1_clrb = 0, cfg1_setb = 0;
1381
1382 bpw = spi->cur_bpw - 1;
1383
1384 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1385 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1386
1387 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1388 fthlv = spi->cur_fthlv - 1;
1389
1390 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1391 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1392
1393 writel_relaxed(
1394 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1395 ~cfg1_clrb) | cfg1_setb,
1396 spi->base + STM32H7_SPI_CFG1);
1397}
1398
1399/**
1400 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1401 * @spi: pointer to the spi controller data structure
1402 * @mbrdiv: baud rate divisor value
1403 */
1404static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1405{
1406 u32 clrb = 0, setb = 0;
1407
1408 clrb |= spi->cfg->regs->br.mask;
1409 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1410
1411 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1412 ~clrb) | setb,
1413 spi->base + spi->cfg->regs->br.reg);
1414}
1415
1416/**
1417 * stm32_spi_communication_type - return transfer communication type
1418 * @spi_dev: pointer to the spi device
1419 * @transfer: pointer to spi transfer
1420 */
1421static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1422 struct spi_transfer *transfer)
1423{
1424 unsigned int type = SPI_FULL_DUPLEX;
1425
1426 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1427 /*
1428 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1429 * is forbidden and unvalidated by SPI subsystem so depending
1430 * on the valid buffer, we can determine the direction of the
1431 * transfer.
1432 */
1433 if (!transfer->tx_buf)
1434 type = SPI_3WIRE_RX;
1435 else
1436 type = SPI_3WIRE_TX;
1437 } else {
1438 if (!transfer->tx_buf)
1439 type = SPI_SIMPLEX_RX;
1440 else if (!transfer->rx_buf)
1441 type = SPI_SIMPLEX_TX;
1442 }
1443
1444 return type;
1445}
1446
1447/**
1448 * stm32f4_spi_set_mode - configure communication mode
1449 * @spi: pointer to the spi controller data structure
1450 * @comm_type: type of communication to configure
1451 */
1452static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1453{
1454 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1455 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1456 STM32F4_SPI_CR1_BIDIMODE |
1457 STM32F4_SPI_CR1_BIDIOE);
1458 } else if (comm_type == SPI_FULL_DUPLEX ||
1459 comm_type == SPI_SIMPLEX_RX) {
1460 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1461 STM32F4_SPI_CR1_BIDIMODE |
1462 STM32F4_SPI_CR1_BIDIOE);
1463 } else if (comm_type == SPI_3WIRE_RX) {
1464 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1465 STM32F4_SPI_CR1_BIDIMODE);
1466 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1467 STM32F4_SPI_CR1_BIDIOE);
1468 } else {
1469 return -EINVAL;
1470 }
1471
1472 return 0;
1473}
1474
1475/**
1476 * stm32h7_spi_set_mode - configure communication mode
1477 * @spi: pointer to the spi controller data structure
1478 * @comm_type: type of communication to configure
1479 */
1480static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1481{
1482 u32 mode;
1483 u32 cfg2_clrb = 0, cfg2_setb = 0;
1484
1485 if (comm_type == SPI_3WIRE_RX) {
1486 mode = STM32H7_SPI_HALF_DUPLEX;
1487 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1488 } else if (comm_type == SPI_3WIRE_TX) {
1489 mode = STM32H7_SPI_HALF_DUPLEX;
1490 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1491 } else if (comm_type == SPI_SIMPLEX_RX) {
1492 mode = STM32H7_SPI_SIMPLEX_RX;
1493 } else if (comm_type == SPI_SIMPLEX_TX) {
1494 mode = STM32H7_SPI_SIMPLEX_TX;
1495 } else {
1496 mode = STM32H7_SPI_FULL_DUPLEX;
1497 }
1498
1499 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1500 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1501
1502 writel_relaxed(
1503 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1504 ~cfg2_clrb) | cfg2_setb,
1505 spi->base + STM32H7_SPI_CFG2);
1506
1507 return 0;
1508}
1509
1510/**
1511 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1512 * consecutive data frames in master mode
1513 * @spi: pointer to the spi controller data structure
1514 * @len: transfer len
1515 */
1516static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1517{
1518 u32 cfg2_clrb = 0, cfg2_setb = 0;
1519
1520 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1521 if ((len > 1) && (spi->cur_midi > 0)) {
1522 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1523 u32 midi = min_t(u32,
1524 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1525 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1526 STM32H7_SPI_CFG2_MIDI));
1527
1528
1529 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1530 sck_period_ns, midi, midi * sck_period_ns);
1531 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1532 }
1533
1534 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1535 ~cfg2_clrb) | cfg2_setb,
1536 spi->base + STM32H7_SPI_CFG2);
1537}
1538
1539/**
1540 * stm32h7_spi_number_of_data - configure number of data at current transfer
1541 * @spi: pointer to the spi controller data structure
1542 * @nb_words: transfer length (in words)
1543 */
1544static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1545{
1546 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1547 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1548 spi->base + STM32H7_SPI_CR2);
1549 } else {
1550 return -EMSGSIZE;
1551 }
1552
1553 return 0;
1554}
1555
1556/**
1557 * stm32_spi_transfer_one_setup - common setup to transfer a single
1558 * spi_transfer either using DMA or
1559 * interrupts.
1560 * @spi: pointer to the spi controller data structure
1561 * @spi_dev: pointer to the spi device
1562 * @transfer: pointer to spi transfer
1563 */
1564static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1565 struct spi_device *spi_dev,
1566 struct spi_transfer *transfer)
1567{
1568 unsigned long flags;
1569 unsigned int comm_type;
1570 int nb_words, ret = 0;
1571 int mbr;
1572
1573 spin_lock_irqsave(&spi->lock, flags);
1574
1575 spi->cur_xferlen = transfer->len;
1576
1577 spi->cur_bpw = transfer->bits_per_word;
1578 spi->cfg->set_bpw(spi);
1579
1580 /* Update spi->cur_speed with real clock speed */
1581 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1582 spi->cfg->baud_rate_div_min,
1583 spi->cfg->baud_rate_div_max);
1584 if (mbr < 0) {
1585 ret = mbr;
1586 goto out;
1587 }
1588
1589 transfer->speed_hz = spi->cur_speed;
1590 stm32_spi_set_mbr(spi, mbr);
1591
1592 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1593 ret = spi->cfg->set_mode(spi, comm_type);
1594 if (ret < 0)
1595 goto out;
1596
1597 spi->cur_comm = comm_type;
1598
1599 if (spi->cfg->set_data_idleness)
1600 spi->cfg->set_data_idleness(spi, transfer->len);
1601
1602 if (spi->cur_bpw <= 8)
1603 nb_words = transfer->len;
1604 else if (spi->cur_bpw <= 16)
1605 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1606 else
1607 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1608
1609 if (spi->cfg->set_number_of_data) {
1610 ret = spi->cfg->set_number_of_data(spi, nb_words);
1611 if (ret < 0)
1612 goto out;
1613 }
1614
1615 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1616 spi->cur_comm);
1617 dev_dbg(spi->dev,
1618 "data frame of %d-bit, data packet of %d data frames\n",
1619 spi->cur_bpw, spi->cur_fthlv);
1620 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1621 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1622 spi->cur_xferlen, nb_words);
1623 dev_dbg(spi->dev, "dma %s\n",
1624 (spi->cur_usedma) ? "enabled" : "disabled");
1625
1626out:
1627 spin_unlock_irqrestore(&spi->lock, flags);
1628
1629 return ret;
1630}
1631
1632/**
1633 * stm32_spi_transfer_one - transfer a single spi_transfer
1634 * @master: controller master interface
1635 * @spi_dev: pointer to the spi device
1636 * @transfer: pointer to spi transfer
1637 *
1638 * It must return 0 if the transfer is finished or 1 if the transfer is still
1639 * in progress.
1640 */
1641static int stm32_spi_transfer_one(struct spi_master *master,
1642 struct spi_device *spi_dev,
1643 struct spi_transfer *transfer)
1644{
1645 struct stm32_spi *spi = spi_master_get_devdata(master);
1646 int ret;
1647
1648 /* Don't do anything on 0 bytes transfers */
1649 if (transfer->len == 0)
1650 return 0;
1651
1652 spi->tx_buf = transfer->tx_buf;
1653 spi->rx_buf = transfer->rx_buf;
1654 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1655 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1656
1657 spi->cur_usedma = (master->can_dma &&
1658 master->can_dma(master, spi_dev, transfer));
1659
1660 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1661 if (ret) {
1662 dev_err(spi->dev, "SPI transfer setup failed\n");
1663 return ret;
1664 }
1665
1666 if (spi->cur_usedma)
1667 return stm32_spi_transfer_one_dma(spi, transfer);
1668 else
1669 return spi->cfg->transfer_one_irq(spi);
1670}
1671
1672/**
1673 * stm32_spi_unprepare_msg - relax the hardware
1674 * @master: controller master interface
1675 * @msg: pointer to the spi message
1676 */
1677static int stm32_spi_unprepare_msg(struct spi_master *master,
1678 struct spi_message *msg)
1679{
1680 struct stm32_spi *spi = spi_master_get_devdata(master);
1681
1682 spi->cfg->disable(spi);
1683
1684 return 0;
1685}
1686
1687/**
1688 * stm32f4_spi_config - Configure SPI controller as SPI master
1689 * @spi: pointer to the spi controller data structure
1690 */
1691static int stm32f4_spi_config(struct stm32_spi *spi)
1692{
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&spi->lock, flags);
1696
1697 /* Ensure I2SMOD bit is kept cleared */
1698 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1699 STM32F4_SPI_I2SCFGR_I2SMOD);
1700
1701 /*
1702 * - SS input value high
1703 * - transmitter half duplex direction
1704 * - Set the master mode (default Motorola mode)
1705 * - Consider 1 master/n slaves configuration and
1706 * SS input value is determined by the SSI bit
1707 */
1708 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1709 STM32F4_SPI_CR1_BIDIOE |
1710 STM32F4_SPI_CR1_MSTR |
1711 STM32F4_SPI_CR1_SSM);
1712
1713 spin_unlock_irqrestore(&spi->lock, flags);
1714
1715 return 0;
1716}
1717
1718/**
1719 * stm32h7_spi_config - Configure SPI controller as SPI master
1720 * @spi: pointer to the spi controller data structure
1721 */
1722static int stm32h7_spi_config(struct stm32_spi *spi)
1723{
1724 unsigned long flags;
1725
1726 spin_lock_irqsave(&spi->lock, flags);
1727
1728 /* Ensure I2SMOD bit is kept cleared */
1729 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1730 STM32H7_SPI_I2SCFGR_I2SMOD);
1731
1732 /*
1733 * - SS input value high
1734 * - transmitter half duplex direction
1735 * - automatic communication suspend when RX-Fifo is full
1736 */
1737 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1738 STM32H7_SPI_CR1_HDDIR |
1739 STM32H7_SPI_CR1_MASRX);
1740
1741 /*
1742 * - Set the master mode (default Motorola mode)
1743 * - Consider 1 master/n slaves configuration and
1744 * SS input value is determined by the SSI bit
1745 * - keep control of all associated GPIOs
1746 */
1747 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1748 STM32H7_SPI_CFG2_SSM |
1749 STM32H7_SPI_CFG2_AFCNTR);
1750
1751 spin_unlock_irqrestore(&spi->lock, flags);
1752
1753 return 0;
1754}
1755
1756static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1757 .regs = &stm32f4_spi_regspec,
1758 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1759 .disable = stm32f4_spi_disable,
1760 .config = stm32f4_spi_config,
1761 .set_bpw = stm32f4_spi_set_bpw,
1762 .set_mode = stm32f4_spi_set_mode,
1763 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1764 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1765 .dma_rx_cb = stm32f4_spi_dma_rx_cb,
1766 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1767 .irq_handler_event = stm32f4_spi_irq_event,
1768 .irq_handler_thread = stm32f4_spi_irq_thread,
1769 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1770 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1771 .has_fifo = false,
1772};
1773
1774static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1775 .regs = &stm32h7_spi_regspec,
1776 .get_fifo_size = stm32h7_spi_get_fifo_size,
1777 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1778 .disable = stm32h7_spi_disable,
1779 .config = stm32h7_spi_config,
1780 .set_bpw = stm32h7_spi_set_bpw,
1781 .set_mode = stm32h7_spi_set_mode,
1782 .set_data_idleness = stm32h7_spi_data_idleness,
1783 .set_number_of_data = stm32h7_spi_number_of_data,
1784 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1785 .dma_rx_cb = stm32h7_spi_dma_cb,
1786 .dma_tx_cb = stm32h7_spi_dma_cb,
1787 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1788 .irq_handler_thread = stm32h7_spi_irq_thread,
1789 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1790 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1791 .has_fifo = true,
1792};
1793
1794static const struct of_device_id stm32_spi_of_match[] = {
1795 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1796 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1797 {},
1798};
1799MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1800
1801static int stm32_spi_probe(struct platform_device *pdev)
1802{
1803 struct spi_master *master;
1804 struct stm32_spi *spi;
1805 struct resource *res;
1806 struct reset_control *rst;
1807 int ret;
1808
1809 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1810 if (!master) {
1811 dev_err(&pdev->dev, "spi master allocation failed\n");
1812 return -ENOMEM;
1813 }
1814 platform_set_drvdata(pdev, master);
1815
1816 spi = spi_master_get_devdata(master);
1817 spi->dev = &pdev->dev;
1818 spi->master = master;
1819 spin_lock_init(&spi->lock);
1820
1821 spi->cfg = (const struct stm32_spi_cfg *)
1822 of_match_device(pdev->dev.driver->of_match_table,
1823 &pdev->dev)->data;
1824
1825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1826 spi->base = devm_ioremap_resource(&pdev->dev, res);
1827 if (IS_ERR(spi->base))
1828 return PTR_ERR(spi->base);
1829
1830 spi->phys_addr = (dma_addr_t)res->start;
1831
1832 spi->irq = platform_get_irq(pdev, 0);
1833 if (spi->irq <= 0)
1834 return dev_err_probe(&pdev->dev, spi->irq,
1835 "failed to get irq\n");
1836
1837 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1838 spi->cfg->irq_handler_event,
1839 spi->cfg->irq_handler_thread,
1840 IRQF_ONESHOT, pdev->name, master);
1841 if (ret) {
1842 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1843 ret);
1844 return ret;
1845 }
1846
1847 spi->clk = devm_clk_get(&pdev->dev, NULL);
1848 if (IS_ERR(spi->clk)) {
1849 ret = PTR_ERR(spi->clk);
1850 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1851 return ret;
1852 }
1853
1854 ret = clk_prepare_enable(spi->clk);
1855 if (ret) {
1856 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1857 return ret;
1858 }
1859 spi->clk_rate = clk_get_rate(spi->clk);
1860 if (!spi->clk_rate) {
1861 dev_err(&pdev->dev, "clk rate = 0\n");
1862 ret = -EINVAL;
1863 goto err_clk_disable;
1864 }
1865
1866 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1867 if (rst) {
1868 if (IS_ERR(rst)) {
1869 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1870 "failed to get reset\n");
1871 goto err_clk_disable;
1872 }
1873
1874 reset_control_assert(rst);
1875 udelay(2);
1876 reset_control_deassert(rst);
1877 }
1878
1879 if (spi->cfg->has_fifo)
1880 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1881
1882 ret = spi->cfg->config(spi);
1883 if (ret) {
1884 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1885 ret);
1886 goto err_clk_disable;
1887 }
1888
1889 master->dev.of_node = pdev->dev.of_node;
1890 master->auto_runtime_pm = true;
1891 master->bus_num = pdev->id;
1892 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1893 SPI_3WIRE;
1894 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1895 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1896 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1897 master->use_gpio_descriptors = true;
1898 master->prepare_message = stm32_spi_prepare_msg;
1899 master->transfer_one = stm32_spi_transfer_one;
1900 master->unprepare_message = stm32_spi_unprepare_msg;
1901 master->flags = SPI_MASTER_MUST_TX;
1902
1903 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1904 if (IS_ERR(spi->dma_tx)) {
1905 ret = PTR_ERR(spi->dma_tx);
1906 spi->dma_tx = NULL;
1907 if (ret == -EPROBE_DEFER)
1908 goto err_clk_disable;
1909
1910 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1911 } else {
1912 master->dma_tx = spi->dma_tx;
1913 }
1914
1915 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1916 if (IS_ERR(spi->dma_rx)) {
1917 ret = PTR_ERR(spi->dma_rx);
1918 spi->dma_rx = NULL;
1919 if (ret == -EPROBE_DEFER)
1920 goto err_dma_release;
1921
1922 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1923 } else {
1924 master->dma_rx = spi->dma_rx;
1925 }
1926
1927 if (spi->dma_tx || spi->dma_rx)
1928 master->can_dma = stm32_spi_can_dma;
1929
1930 pm_runtime_set_active(&pdev->dev);
1931 pm_runtime_get_noresume(&pdev->dev);
1932 pm_runtime_enable(&pdev->dev);
1933
1934 ret = spi_register_master(master);
1935 if (ret) {
1936 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1937 ret);
1938 goto err_pm_disable;
1939 }
1940
1941 dev_info(&pdev->dev, "driver initialized\n");
1942
1943 return 0;
1944
1945err_pm_disable:
1946 pm_runtime_disable(&pdev->dev);
1947 pm_runtime_put_noidle(&pdev->dev);
1948 pm_runtime_set_suspended(&pdev->dev);
1949err_dma_release:
1950 if (spi->dma_tx)
1951 dma_release_channel(spi->dma_tx);
1952 if (spi->dma_rx)
1953 dma_release_channel(spi->dma_rx);
1954err_clk_disable:
1955 clk_disable_unprepare(spi->clk);
1956
1957 return ret;
1958}
1959
1960static int stm32_spi_remove(struct platform_device *pdev)
1961{
1962 struct spi_master *master = platform_get_drvdata(pdev);
1963 struct stm32_spi *spi = spi_master_get_devdata(master);
1964
1965 pm_runtime_get_sync(&pdev->dev);
1966
1967 spi_unregister_master(master);
1968 spi->cfg->disable(spi);
1969
1970 pm_runtime_disable(&pdev->dev);
1971 pm_runtime_put_noidle(&pdev->dev);
1972 pm_runtime_set_suspended(&pdev->dev);
1973 if (master->dma_tx)
1974 dma_release_channel(master->dma_tx);
1975 if (master->dma_rx)
1976 dma_release_channel(master->dma_rx);
1977
1978 clk_disable_unprepare(spi->clk);
1979
1980
1981 pinctrl_pm_select_sleep_state(&pdev->dev);
1982
1983 return 0;
1984}
1985
1986static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
1987{
1988 struct spi_master *master = dev_get_drvdata(dev);
1989 struct stm32_spi *spi = spi_master_get_devdata(master);
1990
1991 clk_disable_unprepare(spi->clk);
1992
1993 return pinctrl_pm_select_sleep_state(dev);
1994}
1995
1996static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
1997{
1998 struct spi_master *master = dev_get_drvdata(dev);
1999 struct stm32_spi *spi = spi_master_get_devdata(master);
2000 int ret;
2001
2002 ret = pinctrl_pm_select_default_state(dev);
2003 if (ret)
2004 return ret;
2005
2006 return clk_prepare_enable(spi->clk);
2007}
2008
2009static int __maybe_unused stm32_spi_suspend(struct device *dev)
2010{
2011 struct spi_master *master = dev_get_drvdata(dev);
2012 int ret;
2013
2014 ret = spi_master_suspend(master);
2015 if (ret)
2016 return ret;
2017
2018 return pm_runtime_force_suspend(dev);
2019}
2020
2021static int __maybe_unused stm32_spi_resume(struct device *dev)
2022{
2023 struct spi_master *master = dev_get_drvdata(dev);
2024 struct stm32_spi *spi = spi_master_get_devdata(master);
2025 int ret;
2026
2027 ret = pm_runtime_force_resume(dev);
2028 if (ret)
2029 return ret;
2030
2031 ret = spi_master_resume(master);
2032 if (ret) {
2033 clk_disable_unprepare(spi->clk);
2034 return ret;
2035 }
2036
2037 ret = pm_runtime_get_sync(dev);
2038 if (ret < 0) {
2039 pm_runtime_put_noidle(dev);
2040 dev_err(dev, "Unable to power device:%d\n", ret);
2041 return ret;
2042 }
2043
2044 spi->cfg->config(spi);
2045
2046 pm_runtime_mark_last_busy(dev);
2047 pm_runtime_put_autosuspend(dev);
2048
2049 return 0;
2050}
2051
2052static const struct dev_pm_ops stm32_spi_pm_ops = {
2053 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2054 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2055 stm32_spi_runtime_resume, NULL)
2056};
2057
2058static struct platform_driver stm32_spi_driver = {
2059 .probe = stm32_spi_probe,
2060 .remove = stm32_spi_remove,
2061 .driver = {
2062 .name = DRIVER_NAME,
2063 .pm = &stm32_spi_pm_ops,
2064 .of_match_table = stm32_spi_of_match,
2065 },
2066};
2067
2068module_platform_driver(stm32_spi_driver);
2069
2070MODULE_ALIAS("platform:" DRIVER_NAME);
2071MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2072MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2073MODULE_LICENSE("GPL v2");