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1// SPDX-License-Identifier: GPL-2.0
2/* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11#include <linux/cache.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_vlan.h>
19#include <linux/kernel.h>
20#include <linux/list.h>
21#include <linux/module.h>
22#include <linux/net_tstamp.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/of_irq.h>
26#include <linux/of_mdio.h>
27#include <linux/of_net.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/sys_soc.h>
32#include <linux/reset.h>
33#include <linux/math64.h>
34
35#include "ravb.h"
36
37#define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46};
47
48static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51};
52
53void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55{
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57}
58
59int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60{
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69}
70
71static int ravb_config(struct net_device *ndev)
72{
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83}
84
85static void ravb_set_rate_gbeth(struct net_device *ndev)
86{
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 10: /* 10BASE */
91 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
92 break;
93 case 100: /* 100BASE */
94 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
95 break;
96 case 1000: /* 1000BASE */
97 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
98 break;
99 }
100}
101
102static void ravb_set_rate_rcar(struct net_device *ndev)
103{
104 struct ravb_private *priv = netdev_priv(ndev);
105
106 switch (priv->speed) {
107 case 100: /* 100BASE */
108 ravb_write(ndev, GECMR_SPEED_100, GECMR);
109 break;
110 case 1000: /* 1000BASE */
111 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
112 break;
113 }
114}
115
116static void ravb_set_buffer_align(struct sk_buff *skb)
117{
118 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
119
120 if (reserve)
121 skb_reserve(skb, RAVB_ALIGN - reserve);
122}
123
124/* Get MAC address from the MAC address registers
125 *
126 * Ethernet AVB device doesn't have ROM for MAC address.
127 * This function gets the MAC address that was used by a bootloader.
128 */
129static void ravb_read_mac_address(struct device_node *np,
130 struct net_device *ndev)
131{
132 int ret;
133
134 ret = of_get_ethdev_address(np, ndev);
135 if (ret) {
136 u32 mahr = ravb_read(ndev, MAHR);
137 u32 malr = ravb_read(ndev, MALR);
138 u8 addr[ETH_ALEN];
139
140 addr[0] = (mahr >> 24) & 0xFF;
141 addr[1] = (mahr >> 16) & 0xFF;
142 addr[2] = (mahr >> 8) & 0xFF;
143 addr[3] = (mahr >> 0) & 0xFF;
144 addr[4] = (malr >> 8) & 0xFF;
145 addr[5] = (malr >> 0) & 0xFF;
146 eth_hw_addr_set(ndev, addr);
147 }
148}
149
150static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
151{
152 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
153 mdiobb);
154
155 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
156}
157
158/* MDC pin control */
159static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
160{
161 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
162}
163
164/* Data I/O pin control */
165static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
166{
167 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
168}
169
170/* Set data bit */
171static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
172{
173 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
174}
175
176/* Get data bit */
177static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
178{
179 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
180 mdiobb);
181
182 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
183}
184
185/* MDIO bus control struct */
186static const struct mdiobb_ops bb_ops = {
187 .owner = THIS_MODULE,
188 .set_mdc = ravb_set_mdc,
189 .set_mdio_dir = ravb_set_mdio_dir,
190 .set_mdio_data = ravb_set_mdio_data,
191 .get_mdio_data = ravb_get_mdio_data,
192};
193
194/* Free TX skb function for AVB-IP */
195static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
196{
197 struct ravb_private *priv = netdev_priv(ndev);
198 struct net_device_stats *stats = &priv->stats[q];
199 unsigned int num_tx_desc = priv->num_tx_desc;
200 struct ravb_tx_desc *desc;
201 unsigned int entry;
202 int free_num = 0;
203 u32 size;
204
205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
206 bool txed;
207
208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
209 num_tx_desc);
210 desc = &priv->tx_ring[q][entry];
211 txed = desc->die_dt == DT_FEMPTY;
212 if (free_txed_only && !txed)
213 break;
214 /* Descriptor type must be checked before all other reads */
215 dma_rmb();
216 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
217 /* Free the original skb. */
218 if (priv->tx_skb[q][entry / num_tx_desc]) {
219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
220 size, DMA_TO_DEVICE);
221 /* Last packet descriptor? */
222 if (entry % num_tx_desc == num_tx_desc - 1) {
223 entry /= num_tx_desc;
224 dev_kfree_skb_any(priv->tx_skb[q][entry]);
225 priv->tx_skb[q][entry] = NULL;
226 if (txed)
227 stats->tx_packets++;
228 }
229 free_num++;
230 }
231 if (txed)
232 stats->tx_bytes += size;
233 desc->die_dt = DT_EEMPTY;
234 }
235 return free_num;
236}
237
238static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q)
239{
240 struct ravb_private *priv = netdev_priv(ndev);
241 unsigned int ring_size;
242 unsigned int i;
243
244 if (!priv->gbeth_rx_ring)
245 return;
246
247 for (i = 0; i < priv->num_rx_ring[q]; i++) {
248 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i];
249
250 if (!dma_mapping_error(ndev->dev.parent,
251 le32_to_cpu(desc->dptr)))
252 dma_unmap_single(ndev->dev.parent,
253 le32_to_cpu(desc->dptr),
254 GBETH_RX_BUFF_MAX,
255 DMA_FROM_DEVICE);
256 }
257 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
258 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring,
259 priv->rx_desc_dma[q]);
260 priv->gbeth_rx_ring = NULL;
261}
262
263static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q)
264{
265 struct ravb_private *priv = netdev_priv(ndev);
266 unsigned int ring_size;
267 unsigned int i;
268
269 if (!priv->rx_ring[q])
270 return;
271
272 for (i = 0; i < priv->num_rx_ring[q]; i++) {
273 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
274
275 if (!dma_mapping_error(ndev->dev.parent,
276 le32_to_cpu(desc->dptr)))
277 dma_unmap_single(ndev->dev.parent,
278 le32_to_cpu(desc->dptr),
279 RX_BUF_SZ,
280 DMA_FROM_DEVICE);
281 }
282 ring_size = sizeof(struct ravb_ex_rx_desc) *
283 (priv->num_rx_ring[q] + 1);
284 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
285 priv->rx_desc_dma[q]);
286 priv->rx_ring[q] = NULL;
287}
288
289/* Free skb's and DMA buffers for Ethernet AVB */
290static void ravb_ring_free(struct net_device *ndev, int q)
291{
292 struct ravb_private *priv = netdev_priv(ndev);
293 const struct ravb_hw_info *info = priv->info;
294 unsigned int num_tx_desc = priv->num_tx_desc;
295 unsigned int ring_size;
296 unsigned int i;
297
298 info->rx_ring_free(ndev, q);
299
300 if (priv->tx_ring[q]) {
301 ravb_tx_free(ndev, q, false);
302
303 ring_size = sizeof(struct ravb_tx_desc) *
304 (priv->num_tx_ring[q] * num_tx_desc + 1);
305 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
306 priv->tx_desc_dma[q]);
307 priv->tx_ring[q] = NULL;
308 }
309
310 /* Free RX skb ringbuffer */
311 if (priv->rx_skb[q]) {
312 for (i = 0; i < priv->num_rx_ring[q]; i++)
313 dev_kfree_skb(priv->rx_skb[q][i]);
314 }
315 kfree(priv->rx_skb[q]);
316 priv->rx_skb[q] = NULL;
317
318 /* Free aligned TX buffers */
319 kfree(priv->tx_align[q]);
320 priv->tx_align[q] = NULL;
321
322 /* Free TX skb ringbuffer.
323 * SKBs are freed by ravb_tx_free() call above.
324 */
325 kfree(priv->tx_skb[q]);
326 priv->tx_skb[q] = NULL;
327}
328
329static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q)
330{
331 struct ravb_private *priv = netdev_priv(ndev);
332 struct ravb_rx_desc *rx_desc;
333 unsigned int rx_ring_size;
334 dma_addr_t dma_addr;
335 unsigned int i;
336
337 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
338 memset(priv->gbeth_rx_ring, 0, rx_ring_size);
339 /* Build RX ring buffer */
340 for (i = 0; i < priv->num_rx_ring[q]; i++) {
341 /* RX descriptor */
342 rx_desc = &priv->gbeth_rx_ring[i];
343 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
344 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
345 GBETH_RX_BUFF_MAX,
346 DMA_FROM_DEVICE);
347 /* We just set the data size to 0 for a failed mapping which
348 * should prevent DMA from happening...
349 */
350 if (dma_mapping_error(ndev->dev.parent, dma_addr))
351 rx_desc->ds_cc = cpu_to_le16(0);
352 rx_desc->dptr = cpu_to_le32(dma_addr);
353 rx_desc->die_dt = DT_FEMPTY;
354 }
355 rx_desc = &priv->gbeth_rx_ring[i];
356 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
357 rx_desc->die_dt = DT_LINKFIX; /* type */
358}
359
360static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q)
361{
362 struct ravb_private *priv = netdev_priv(ndev);
363 struct ravb_ex_rx_desc *rx_desc;
364 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
365 dma_addr_t dma_addr;
366 unsigned int i;
367
368 memset(priv->rx_ring[q], 0, rx_ring_size);
369 /* Build RX ring buffer */
370 for (i = 0; i < priv->num_rx_ring[q]; i++) {
371 /* RX descriptor */
372 rx_desc = &priv->rx_ring[q][i];
373 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
374 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
375 RX_BUF_SZ,
376 DMA_FROM_DEVICE);
377 /* We just set the data size to 0 for a failed mapping which
378 * should prevent DMA from happening...
379 */
380 if (dma_mapping_error(ndev->dev.parent, dma_addr))
381 rx_desc->ds_cc = cpu_to_le16(0);
382 rx_desc->dptr = cpu_to_le32(dma_addr);
383 rx_desc->die_dt = DT_FEMPTY;
384 }
385 rx_desc = &priv->rx_ring[q][i];
386 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
387 rx_desc->die_dt = DT_LINKFIX; /* type */
388}
389
390/* Format skb and descriptor buffer for Ethernet AVB */
391static void ravb_ring_format(struct net_device *ndev, int q)
392{
393 struct ravb_private *priv = netdev_priv(ndev);
394 const struct ravb_hw_info *info = priv->info;
395 unsigned int num_tx_desc = priv->num_tx_desc;
396 struct ravb_tx_desc *tx_desc;
397 struct ravb_desc *desc;
398 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
399 num_tx_desc;
400 unsigned int i;
401
402 priv->cur_rx[q] = 0;
403 priv->cur_tx[q] = 0;
404 priv->dirty_rx[q] = 0;
405 priv->dirty_tx[q] = 0;
406
407 info->rx_ring_format(ndev, q);
408
409 memset(priv->tx_ring[q], 0, tx_ring_size);
410 /* Build TX ring buffer */
411 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
412 i++, tx_desc++) {
413 tx_desc->die_dt = DT_EEMPTY;
414 if (num_tx_desc > 1) {
415 tx_desc++;
416 tx_desc->die_dt = DT_EEMPTY;
417 }
418 }
419 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
420 tx_desc->die_dt = DT_LINKFIX; /* type */
421
422 /* RX descriptor base address for best effort */
423 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
424 desc->die_dt = DT_LINKFIX; /* type */
425 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
426
427 /* TX descriptor base address for best effort */
428 desc = &priv->desc_bat[q];
429 desc->die_dt = DT_LINKFIX; /* type */
430 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
431}
432
433static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q)
434{
435 struct ravb_private *priv = netdev_priv(ndev);
436 unsigned int ring_size;
437
438 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1);
439
440 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size,
441 &priv->rx_desc_dma[q],
442 GFP_KERNEL);
443 return priv->gbeth_rx_ring;
444}
445
446static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q)
447{
448 struct ravb_private *priv = netdev_priv(ndev);
449 unsigned int ring_size;
450
451 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
452
453 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
454 &priv->rx_desc_dma[q],
455 GFP_KERNEL);
456 return priv->rx_ring[q];
457}
458
459/* Init skb and descriptor buffer for Ethernet AVB */
460static int ravb_ring_init(struct net_device *ndev, int q)
461{
462 struct ravb_private *priv = netdev_priv(ndev);
463 const struct ravb_hw_info *info = priv->info;
464 unsigned int num_tx_desc = priv->num_tx_desc;
465 unsigned int ring_size;
466 struct sk_buff *skb;
467 unsigned int i;
468
469 /* Allocate RX and TX skb rings */
470 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
471 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
472 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
473 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
474 if (!priv->rx_skb[q] || !priv->tx_skb[q])
475 goto error;
476
477 for (i = 0; i < priv->num_rx_ring[q]; i++) {
478 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL);
479 if (!skb)
480 goto error;
481 ravb_set_buffer_align(skb);
482 priv->rx_skb[q][i] = skb;
483 }
484
485 if (num_tx_desc > 1) {
486 /* Allocate rings for the aligned buffers */
487 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
488 DPTR_ALIGN - 1, GFP_KERNEL);
489 if (!priv->tx_align[q])
490 goto error;
491 }
492
493 /* Allocate all RX descriptors. */
494 if (!info->alloc_rx_desc(ndev, q))
495 goto error;
496
497 priv->dirty_rx[q] = 0;
498
499 /* Allocate all TX descriptors. */
500 ring_size = sizeof(struct ravb_tx_desc) *
501 (priv->num_tx_ring[q] * num_tx_desc + 1);
502 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
503 &priv->tx_desc_dma[q],
504 GFP_KERNEL);
505 if (!priv->tx_ring[q])
506 goto error;
507
508 return 0;
509
510error:
511 ravb_ring_free(ndev, q);
512
513 return -ENOMEM;
514}
515
516static void ravb_emac_init_gbeth(struct net_device *ndev)
517{
518 struct ravb_private *priv = netdev_priv(ndev);
519
520 /* Receive frame limit set register */
521 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR);
522
523 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */
524 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
525 ECMR_TE | ECMR_RE | ECMR_RCPT |
526 ECMR_TXF | ECMR_RXF, ECMR);
527
528 ravb_set_rate_gbeth(ndev);
529
530 /* Set MAC address */
531 ravb_write(ndev,
532 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
533 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
534 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
535
536 /* E-MAC status register clear */
537 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
538 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
539
540 /* E-MAC interrupt enable register */
541 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
542
543 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
544 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0);
545 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
546 } else {
547 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1,
548 CXR31_SEL_LINK0);
549 }
550}
551
552static void ravb_emac_init_rcar(struct net_device *ndev)
553{
554 /* Receive frame limit set register */
555 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
556
557 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
558 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
559 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
560 ECMR_TE | ECMR_RE, ECMR);
561
562 ravb_set_rate_rcar(ndev);
563
564 /* Set MAC address */
565 ravb_write(ndev,
566 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
567 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
568 ravb_write(ndev,
569 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
570
571 /* E-MAC status register clear */
572 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
573
574 /* E-MAC interrupt enable register */
575 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
576}
577
578/* E-MAC init function */
579static void ravb_emac_init(struct net_device *ndev)
580{
581 struct ravb_private *priv = netdev_priv(ndev);
582 const struct ravb_hw_info *info = priv->info;
583
584 info->emac_init(ndev);
585}
586
587static int ravb_dmac_init_gbeth(struct net_device *ndev)
588{
589 int error;
590
591 error = ravb_ring_init(ndev, RAVB_BE);
592 if (error)
593 return error;
594
595 /* Descriptor format */
596 ravb_ring_format(ndev, RAVB_BE);
597
598 /* Set DMAC RX */
599 ravb_write(ndev, 0x60000000, RCR);
600
601 /* Set Max Frame Length (RTC) */
602 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC);
603
604 /* Set FIFO size */
605 ravb_write(ndev, 0x00222200, TGC);
606
607 ravb_write(ndev, 0, TCCR);
608
609 /* Frame receive */
610 ravb_write(ndev, RIC0_FRE0, RIC0);
611 /* Disable FIFO full warning */
612 ravb_write(ndev, 0x0, RIC1);
613 /* Receive FIFO full error, descriptor empty */
614 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
615
616 ravb_write(ndev, TIC_FTE0, TIC);
617
618 return 0;
619}
620
621static int ravb_dmac_init_rcar(struct net_device *ndev)
622{
623 struct ravb_private *priv = netdev_priv(ndev);
624 const struct ravb_hw_info *info = priv->info;
625 int error;
626
627 error = ravb_ring_init(ndev, RAVB_BE);
628 if (error)
629 return error;
630 error = ravb_ring_init(ndev, RAVB_NC);
631 if (error) {
632 ravb_ring_free(ndev, RAVB_BE);
633 return error;
634 }
635
636 /* Descriptor format */
637 ravb_ring_format(ndev, RAVB_BE);
638 ravb_ring_format(ndev, RAVB_NC);
639
640 /* Set AVB RX */
641 ravb_write(ndev,
642 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
643
644 /* Set FIFO size */
645 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
646
647 /* Timestamp enable */
648 ravb_write(ndev, TCCR_TFEN, TCCR);
649
650 /* Interrupt init: */
651 if (info->multi_irqs) {
652 /* Clear DIL.DPLx */
653 ravb_write(ndev, 0, DIL);
654 /* Set queue specific interrupt */
655 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
656 }
657 /* Frame receive */
658 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
659 /* Disable FIFO full warning */
660 ravb_write(ndev, 0, RIC1);
661 /* Receive FIFO full error, descriptor empty */
662 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
663 /* Frame transmitted, timestamp FIFO updated */
664 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
665
666 return 0;
667}
668
669/* Device init function for Ethernet AVB */
670static int ravb_dmac_init(struct net_device *ndev)
671{
672 struct ravb_private *priv = netdev_priv(ndev);
673 const struct ravb_hw_info *info = priv->info;
674 int error;
675
676 /* Set CONFIG mode */
677 error = ravb_config(ndev);
678 if (error)
679 return error;
680
681 error = info->dmac_init(ndev);
682 if (error)
683 return error;
684
685 /* Setting the control will start the AVB-DMAC process. */
686 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
687
688 return 0;
689}
690
691static void ravb_get_tx_tstamp(struct net_device *ndev)
692{
693 struct ravb_private *priv = netdev_priv(ndev);
694 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
695 struct skb_shared_hwtstamps shhwtstamps;
696 struct sk_buff *skb;
697 struct timespec64 ts;
698 u16 tag, tfa_tag;
699 int count;
700 u32 tfa2;
701
702 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
703 while (count--) {
704 tfa2 = ravb_read(ndev, TFA2);
705 tfa_tag = (tfa2 & TFA2_TST) >> 16;
706 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
707 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
708 ravb_read(ndev, TFA1);
709 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
710 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
711 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
712 list) {
713 skb = ts_skb->skb;
714 tag = ts_skb->tag;
715 list_del(&ts_skb->list);
716 kfree(ts_skb);
717 if (tag == tfa_tag) {
718 skb_tstamp_tx(skb, &shhwtstamps);
719 dev_consume_skb_any(skb);
720 break;
721 } else {
722 dev_kfree_skb_any(skb);
723 }
724 }
725 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
726 }
727}
728
729static void ravb_rx_csum(struct sk_buff *skb)
730{
731 u8 *hw_csum;
732
733 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
734 * appended to packet data
735 */
736 if (unlikely(skb->len < sizeof(__sum16)))
737 return;
738 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
739 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
740 skb->ip_summed = CHECKSUM_COMPLETE;
741 skb_trim(skb, skb->len - sizeof(__sum16));
742}
743
744static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry,
745 struct ravb_rx_desc *desc)
746{
747 struct ravb_private *priv = netdev_priv(ndev);
748 struct sk_buff *skb;
749
750 skb = priv->rx_skb[RAVB_BE][entry];
751 priv->rx_skb[RAVB_BE][entry] = NULL;
752 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
753 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE);
754
755 return skb;
756}
757
758/* Packet receive function for Gigabit Ethernet */
759static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q)
760{
761 struct ravb_private *priv = netdev_priv(ndev);
762 const struct ravb_hw_info *info = priv->info;
763 struct net_device_stats *stats;
764 struct ravb_rx_desc *desc;
765 struct sk_buff *skb;
766 dma_addr_t dma_addr;
767 u8 desc_status;
768 int boguscnt;
769 u16 pkt_len;
770 u8 die_dt;
771 int entry;
772 int limit;
773
774 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
775 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q];
776 stats = &priv->stats[q];
777
778 boguscnt = min(boguscnt, *quota);
779 limit = boguscnt;
780 desc = &priv->gbeth_rx_ring[entry];
781 while (desc->die_dt != DT_FEMPTY) {
782 /* Descriptor type must be checked before all other reads */
783 dma_rmb();
784 desc_status = desc->msc;
785 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
786
787 if (--boguscnt < 0)
788 break;
789
790 /* We use 0-byte descriptors to mark the DMA mapping errors */
791 if (!pkt_len)
792 continue;
793
794 if (desc_status & MSC_MC)
795 stats->multicast++;
796
797 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) {
798 stats->rx_errors++;
799 if (desc_status & MSC_CRC)
800 stats->rx_crc_errors++;
801 if (desc_status & MSC_RFE)
802 stats->rx_frame_errors++;
803 if (desc_status & (MSC_RTLF | MSC_RTSF))
804 stats->rx_length_errors++;
805 if (desc_status & MSC_CEEF)
806 stats->rx_missed_errors++;
807 } else {
808 die_dt = desc->die_dt & 0xF0;
809 switch (die_dt) {
810 case DT_FSINGLE:
811 skb = ravb_get_skb_gbeth(ndev, entry, desc);
812 skb_put(skb, pkt_len);
813 skb->protocol = eth_type_trans(skb, ndev);
814 napi_gro_receive(&priv->napi[q], skb);
815 stats->rx_packets++;
816 stats->rx_bytes += pkt_len;
817 break;
818 case DT_FSTART:
819 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc);
820 skb_put(priv->rx_1st_skb, pkt_len);
821 break;
822 case DT_FMID:
823 skb = ravb_get_skb_gbeth(ndev, entry, desc);
824 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
825 priv->rx_1st_skb->len,
826 skb->data,
827 pkt_len);
828 skb_put(priv->rx_1st_skb, pkt_len);
829 dev_kfree_skb(skb);
830 break;
831 case DT_FEND:
832 skb = ravb_get_skb_gbeth(ndev, entry, desc);
833 skb_copy_to_linear_data_offset(priv->rx_1st_skb,
834 priv->rx_1st_skb->len,
835 skb->data,
836 pkt_len);
837 skb_put(priv->rx_1st_skb, pkt_len);
838 dev_kfree_skb(skb);
839 priv->rx_1st_skb->protocol =
840 eth_type_trans(priv->rx_1st_skb, ndev);
841 napi_gro_receive(&priv->napi[q],
842 priv->rx_1st_skb);
843 stats->rx_packets++;
844 stats->rx_bytes += pkt_len;
845 break;
846 }
847 }
848
849 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
850 desc = &priv->gbeth_rx_ring[entry];
851 }
852
853 /* Refill the RX ring buffers. */
854 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
855 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
856 desc = &priv->gbeth_rx_ring[entry];
857 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);
858
859 if (!priv->rx_skb[q][entry]) {
860 skb = netdev_alloc_skb(ndev, info->max_rx_len);
861 if (!skb)
862 break;
863 ravb_set_buffer_align(skb);
864 dma_addr = dma_map_single(ndev->dev.parent,
865 skb->data,
866 GBETH_RX_BUFF_MAX,
867 DMA_FROM_DEVICE);
868 skb_checksum_none_assert(skb);
869 /* We just set the data size to 0 for a failed mapping
870 * which should prevent DMA from happening...
871 */
872 if (dma_mapping_error(ndev->dev.parent, dma_addr))
873 desc->ds_cc = cpu_to_le16(0);
874 desc->dptr = cpu_to_le32(dma_addr);
875 priv->rx_skb[q][entry] = skb;
876 }
877 /* Descriptor type must be set after all the above writes */
878 dma_wmb();
879 desc->die_dt = DT_FEMPTY;
880 }
881
882 *quota -= limit - (++boguscnt);
883
884 return boguscnt <= 0;
885}
886
887/* Packet receive function for Ethernet AVB */
888static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q)
889{
890 struct ravb_private *priv = netdev_priv(ndev);
891 const struct ravb_hw_info *info = priv->info;
892 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
893 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
894 priv->cur_rx[q];
895 struct net_device_stats *stats = &priv->stats[q];
896 struct ravb_ex_rx_desc *desc;
897 struct sk_buff *skb;
898 dma_addr_t dma_addr;
899 struct timespec64 ts;
900 u8 desc_status;
901 u16 pkt_len;
902 int limit;
903
904 boguscnt = min(boguscnt, *quota);
905 limit = boguscnt;
906 desc = &priv->rx_ring[q][entry];
907 while (desc->die_dt != DT_FEMPTY) {
908 /* Descriptor type must be checked before all other reads */
909 dma_rmb();
910 desc_status = desc->msc;
911 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
912
913 if (--boguscnt < 0)
914 break;
915
916 /* We use 0-byte descriptors to mark the DMA mapping errors */
917 if (!pkt_len)
918 continue;
919
920 if (desc_status & MSC_MC)
921 stats->multicast++;
922
923 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
924 MSC_CEEF)) {
925 stats->rx_errors++;
926 if (desc_status & MSC_CRC)
927 stats->rx_crc_errors++;
928 if (desc_status & MSC_RFE)
929 stats->rx_frame_errors++;
930 if (desc_status & (MSC_RTLF | MSC_RTSF))
931 stats->rx_length_errors++;
932 if (desc_status & MSC_CEEF)
933 stats->rx_missed_errors++;
934 } else {
935 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
936
937 skb = priv->rx_skb[q][entry];
938 priv->rx_skb[q][entry] = NULL;
939 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
940 RX_BUF_SZ,
941 DMA_FROM_DEVICE);
942 get_ts &= (q == RAVB_NC) ?
943 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
944 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
945 if (get_ts) {
946 struct skb_shared_hwtstamps *shhwtstamps;
947
948 shhwtstamps = skb_hwtstamps(skb);
949 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
950 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
951 32) | le32_to_cpu(desc->ts_sl);
952 ts.tv_nsec = le32_to_cpu(desc->ts_n);
953 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
954 }
955
956 skb_put(skb, pkt_len);
957 skb->protocol = eth_type_trans(skb, ndev);
958 if (ndev->features & NETIF_F_RXCSUM)
959 ravb_rx_csum(skb);
960 napi_gro_receive(&priv->napi[q], skb);
961 stats->rx_packets++;
962 stats->rx_bytes += pkt_len;
963 }
964
965 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
966 desc = &priv->rx_ring[q][entry];
967 }
968
969 /* Refill the RX ring buffers. */
970 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
971 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
972 desc = &priv->rx_ring[q][entry];
973 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
974
975 if (!priv->rx_skb[q][entry]) {
976 skb = netdev_alloc_skb(ndev, info->max_rx_len);
977 if (!skb)
978 break; /* Better luck next round. */
979 ravb_set_buffer_align(skb);
980 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
981 le16_to_cpu(desc->ds_cc),
982 DMA_FROM_DEVICE);
983 skb_checksum_none_assert(skb);
984 /* We just set the data size to 0 for a failed mapping
985 * which should prevent DMA from happening...
986 */
987 if (dma_mapping_error(ndev->dev.parent, dma_addr))
988 desc->ds_cc = cpu_to_le16(0);
989 desc->dptr = cpu_to_le32(dma_addr);
990 priv->rx_skb[q][entry] = skb;
991 }
992 /* Descriptor type must be set after all the above writes */
993 dma_wmb();
994 desc->die_dt = DT_FEMPTY;
995 }
996
997 *quota -= limit - (++boguscnt);
998
999 return boguscnt <= 0;
1000}
1001
1002/* Packet receive function for Ethernet AVB */
1003static bool ravb_rx(struct net_device *ndev, int *quota, int q)
1004{
1005 struct ravb_private *priv = netdev_priv(ndev);
1006 const struct ravb_hw_info *info = priv->info;
1007
1008 return info->receive(ndev, quota, q);
1009}
1010
1011static void ravb_rcv_snd_disable(struct net_device *ndev)
1012{
1013 /* Disable TX and RX */
1014 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1015}
1016
1017static void ravb_rcv_snd_enable(struct net_device *ndev)
1018{
1019 /* Enable TX and RX */
1020 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1021}
1022
1023/* function for waiting dma process finished */
1024static int ravb_stop_dma(struct net_device *ndev)
1025{
1026 struct ravb_private *priv = netdev_priv(ndev);
1027 const struct ravb_hw_info *info = priv->info;
1028 int error;
1029
1030 /* Wait for stopping the hardware TX process */
1031 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0);
1032
1033 if (error)
1034 return error;
1035
1036 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
1037 0);
1038 if (error)
1039 return error;
1040
1041 /* Stop the E-MAC's RX/TX processes. */
1042 ravb_rcv_snd_disable(ndev);
1043
1044 /* Wait for stopping the RX DMA process */
1045 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
1046 if (error)
1047 return error;
1048
1049 /* Stop AVB-DMAC process */
1050 return ravb_config(ndev);
1051}
1052
1053/* E-MAC interrupt handler */
1054static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
1055{
1056 struct ravb_private *priv = netdev_priv(ndev);
1057 u32 ecsr, psr;
1058
1059 ecsr = ravb_read(ndev, ECSR);
1060 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
1061
1062 if (ecsr & ECSR_MPD)
1063 pm_wakeup_event(&priv->pdev->dev, 0);
1064 if (ecsr & ECSR_ICD)
1065 ndev->stats.tx_carrier_errors++;
1066 if (ecsr & ECSR_LCHNG) {
1067 /* Link changed */
1068 if (priv->no_avb_link)
1069 return;
1070 psr = ravb_read(ndev, PSR);
1071 if (priv->avb_link_active_low)
1072 psr ^= PSR_LMON;
1073 if (!(psr & PSR_LMON)) {
1074 /* DIsable RX and TX */
1075 ravb_rcv_snd_disable(ndev);
1076 } else {
1077 /* Enable RX and TX */
1078 ravb_rcv_snd_enable(ndev);
1079 }
1080 }
1081}
1082
1083static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
1084{
1085 struct net_device *ndev = dev_id;
1086 struct ravb_private *priv = netdev_priv(ndev);
1087
1088 spin_lock(&priv->lock);
1089 ravb_emac_interrupt_unlocked(ndev);
1090 spin_unlock(&priv->lock);
1091 return IRQ_HANDLED;
1092}
1093
1094/* Error interrupt handler */
1095static void ravb_error_interrupt(struct net_device *ndev)
1096{
1097 struct ravb_private *priv = netdev_priv(ndev);
1098 u32 eis, ris2;
1099
1100 eis = ravb_read(ndev, EIS);
1101 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
1102 if (eis & EIS_QFS) {
1103 ris2 = ravb_read(ndev, RIS2);
1104 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
1105 RIS2);
1106
1107 /* Receive Descriptor Empty int */
1108 if (ris2 & RIS2_QFF0)
1109 priv->stats[RAVB_BE].rx_over_errors++;
1110
1111 /* Receive Descriptor Empty int */
1112 if (ris2 & RIS2_QFF1)
1113 priv->stats[RAVB_NC].rx_over_errors++;
1114
1115 /* Receive FIFO Overflow int */
1116 if (ris2 & RIS2_RFFF)
1117 priv->rx_fifo_errors++;
1118 }
1119}
1120
1121static bool ravb_queue_interrupt(struct net_device *ndev, int q)
1122{
1123 struct ravb_private *priv = netdev_priv(ndev);
1124 const struct ravb_hw_info *info = priv->info;
1125 u32 ris0 = ravb_read(ndev, RIS0);
1126 u32 ric0 = ravb_read(ndev, RIC0);
1127 u32 tis = ravb_read(ndev, TIS);
1128 u32 tic = ravb_read(ndev, TIC);
1129
1130 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
1131 if (napi_schedule_prep(&priv->napi[q])) {
1132 /* Mask RX and TX interrupts */
1133 if (!info->irq_en_dis) {
1134 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
1135 ravb_write(ndev, tic & ~BIT(q), TIC);
1136 } else {
1137 ravb_write(ndev, BIT(q), RID0);
1138 ravb_write(ndev, BIT(q), TID);
1139 }
1140 __napi_schedule(&priv->napi[q]);
1141 } else {
1142 netdev_warn(ndev,
1143 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
1144 ris0, ric0);
1145 netdev_warn(ndev,
1146 " tx status 0x%08x, tx mask 0x%08x.\n",
1147 tis, tic);
1148 }
1149 return true;
1150 }
1151 return false;
1152}
1153
1154static bool ravb_timestamp_interrupt(struct net_device *ndev)
1155{
1156 u32 tis = ravb_read(ndev, TIS);
1157
1158 if (tis & TIS_TFUF) {
1159 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
1160 ravb_get_tx_tstamp(ndev);
1161 return true;
1162 }
1163 return false;
1164}
1165
1166static irqreturn_t ravb_interrupt(int irq, void *dev_id)
1167{
1168 struct net_device *ndev = dev_id;
1169 struct ravb_private *priv = netdev_priv(ndev);
1170 const struct ravb_hw_info *info = priv->info;
1171 irqreturn_t result = IRQ_NONE;
1172 u32 iss;
1173
1174 spin_lock(&priv->lock);
1175 /* Get interrupt status */
1176 iss = ravb_read(ndev, ISS);
1177
1178 /* Received and transmitted interrupts */
1179 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
1180 int q;
1181
1182 /* Timestamp updated */
1183 if (ravb_timestamp_interrupt(ndev))
1184 result = IRQ_HANDLED;
1185
1186 /* Network control and best effort queue RX/TX */
1187 if (info->nc_queues) {
1188 for (q = RAVB_NC; q >= RAVB_BE; q--) {
1189 if (ravb_queue_interrupt(ndev, q))
1190 result = IRQ_HANDLED;
1191 }
1192 } else {
1193 if (ravb_queue_interrupt(ndev, RAVB_BE))
1194 result = IRQ_HANDLED;
1195 }
1196 }
1197
1198 /* E-MAC status summary */
1199 if (iss & ISS_MS) {
1200 ravb_emac_interrupt_unlocked(ndev);
1201 result = IRQ_HANDLED;
1202 }
1203
1204 /* Error status summary */
1205 if (iss & ISS_ES) {
1206 ravb_error_interrupt(ndev);
1207 result = IRQ_HANDLED;
1208 }
1209
1210 /* gPTP interrupt status summary */
1211 if (iss & ISS_CGIS) {
1212 ravb_ptp_interrupt(ndev);
1213 result = IRQ_HANDLED;
1214 }
1215
1216 spin_unlock(&priv->lock);
1217 return result;
1218}
1219
1220/* Timestamp/Error/gPTP interrupt handler */
1221static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
1222{
1223 struct net_device *ndev = dev_id;
1224 struct ravb_private *priv = netdev_priv(ndev);
1225 irqreturn_t result = IRQ_NONE;
1226 u32 iss;
1227
1228 spin_lock(&priv->lock);
1229 /* Get interrupt status */
1230 iss = ravb_read(ndev, ISS);
1231
1232 /* Timestamp updated */
1233 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
1234 result = IRQ_HANDLED;
1235
1236 /* Error status summary */
1237 if (iss & ISS_ES) {
1238 ravb_error_interrupt(ndev);
1239 result = IRQ_HANDLED;
1240 }
1241
1242 /* gPTP interrupt status summary */
1243 if (iss & ISS_CGIS) {
1244 ravb_ptp_interrupt(ndev);
1245 result = IRQ_HANDLED;
1246 }
1247
1248 spin_unlock(&priv->lock);
1249 return result;
1250}
1251
1252static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
1253{
1254 struct net_device *ndev = dev_id;
1255 struct ravb_private *priv = netdev_priv(ndev);
1256 irqreturn_t result = IRQ_NONE;
1257
1258 spin_lock(&priv->lock);
1259
1260 /* Network control/Best effort queue RX/TX */
1261 if (ravb_queue_interrupt(ndev, q))
1262 result = IRQ_HANDLED;
1263
1264 spin_unlock(&priv->lock);
1265 return result;
1266}
1267
1268static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
1269{
1270 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
1271}
1272
1273static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
1274{
1275 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
1276}
1277
1278static int ravb_poll(struct napi_struct *napi, int budget)
1279{
1280 struct net_device *ndev = napi->dev;
1281 struct ravb_private *priv = netdev_priv(ndev);
1282 const struct ravb_hw_info *info = priv->info;
1283 bool gptp = info->gptp || info->ccc_gac;
1284 struct ravb_rx_desc *desc;
1285 unsigned long flags;
1286 int q = napi - priv->napi;
1287 int mask = BIT(q);
1288 int quota = budget;
1289 unsigned int entry;
1290
1291 if (!gptp) {
1292 entry = priv->cur_rx[q] % priv->num_rx_ring[q];
1293 desc = &priv->gbeth_rx_ring[entry];
1294 }
1295 /* Processing RX Descriptor Ring */
1296 /* Clear RX interrupt */
1297 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
1298 if (gptp || desc->die_dt != DT_FEMPTY) {
1299 if (ravb_rx(ndev, "a, q))
1300 goto out;
1301 }
1302
1303 /* Processing TX Descriptor Ring */
1304 spin_lock_irqsave(&priv->lock, flags);
1305 /* Clear TX interrupt */
1306 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
1307 ravb_tx_free(ndev, q, true);
1308 netif_wake_subqueue(ndev, q);
1309 spin_unlock_irqrestore(&priv->lock, flags);
1310
1311 napi_complete(napi);
1312
1313 /* Re-enable RX/TX interrupts */
1314 spin_lock_irqsave(&priv->lock, flags);
1315 if (!info->irq_en_dis) {
1316 ravb_modify(ndev, RIC0, mask, mask);
1317 ravb_modify(ndev, TIC, mask, mask);
1318 } else {
1319 ravb_write(ndev, mask, RIE0);
1320 ravb_write(ndev, mask, TIE);
1321 }
1322 spin_unlock_irqrestore(&priv->lock, flags);
1323
1324 /* Receive error message handling */
1325 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
1326 if (info->nc_queues)
1327 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
1328 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
1329 ndev->stats.rx_over_errors = priv->rx_over_errors;
1330 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
1331 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
1332out:
1333 return budget - quota;
1334}
1335
1336static void ravb_set_duplex_gbeth(struct net_device *ndev)
1337{
1338 struct ravb_private *priv = netdev_priv(ndev);
1339
1340 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0);
1341}
1342
1343/* PHY state control function */
1344static void ravb_adjust_link(struct net_device *ndev)
1345{
1346 struct ravb_private *priv = netdev_priv(ndev);
1347 const struct ravb_hw_info *info = priv->info;
1348 struct phy_device *phydev = ndev->phydev;
1349 bool new_state = false;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&priv->lock, flags);
1353
1354 /* Disable TX and RX right over here, if E-MAC change is ignored */
1355 if (priv->no_avb_link)
1356 ravb_rcv_snd_disable(ndev);
1357
1358 if (phydev->link) {
1359 if (info->half_duplex && phydev->duplex != priv->duplex) {
1360 new_state = true;
1361 priv->duplex = phydev->duplex;
1362 ravb_set_duplex_gbeth(ndev);
1363 }
1364
1365 if (phydev->speed != priv->speed) {
1366 new_state = true;
1367 priv->speed = phydev->speed;
1368 info->set_rate(ndev);
1369 }
1370 if (!priv->link) {
1371 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
1372 new_state = true;
1373 priv->link = phydev->link;
1374 }
1375 } else if (priv->link) {
1376 new_state = true;
1377 priv->link = 0;
1378 priv->speed = 0;
1379 if (info->half_duplex)
1380 priv->duplex = -1;
1381 }
1382
1383 /* Enable TX and RX right over here, if E-MAC change is ignored */
1384 if (priv->no_avb_link && phydev->link)
1385 ravb_rcv_snd_enable(ndev);
1386
1387 spin_unlock_irqrestore(&priv->lock, flags);
1388
1389 if (new_state && netif_msg_link(priv))
1390 phy_print_status(phydev);
1391}
1392
1393static const struct soc_device_attribute r8a7795es10[] = {
1394 { .soc_id = "r8a7795", .revision = "ES1.0", },
1395 { /* sentinel */ }
1396};
1397
1398/* PHY init function */
1399static int ravb_phy_init(struct net_device *ndev)
1400{
1401 struct device_node *np = ndev->dev.parent->of_node;
1402 struct ravb_private *priv = netdev_priv(ndev);
1403 const struct ravb_hw_info *info = priv->info;
1404 struct phy_device *phydev;
1405 struct device_node *pn;
1406 phy_interface_t iface;
1407 int err;
1408
1409 priv->link = 0;
1410 priv->speed = 0;
1411 priv->duplex = -1;
1412
1413 /* Try connecting to PHY */
1414 pn = of_parse_phandle(np, "phy-handle", 0);
1415 if (!pn) {
1416 /* In the case of a fixed PHY, the DT node associated
1417 * to the PHY is the Ethernet MAC DT node.
1418 */
1419 if (of_phy_is_fixed_link(np)) {
1420 err = of_phy_register_fixed_link(np);
1421 if (err)
1422 return err;
1423 }
1424 pn = of_node_get(np);
1425 }
1426
1427 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII
1428 : priv->phy_interface;
1429 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1430 of_node_put(pn);
1431 if (!phydev) {
1432 netdev_err(ndev, "failed to connect PHY\n");
1433 err = -ENOENT;
1434 goto err_deregister_fixed_link;
1435 }
1436
1437 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1438 * at this time.
1439 */
1440 if (soc_device_match(r8a7795es10)) {
1441 phy_set_max_speed(phydev, SPEED_100);
1442
1443 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1444 }
1445
1446 if (!info->half_duplex) {
1447 /* 10BASE, Pause and Asym Pause is not supported */
1448 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1449 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1450 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1451 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1452
1453 /* Half Duplex is not supported */
1454 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1455 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1456 }
1457
1458 /* Indicate that the MAC is responsible for managing PHY PM */
1459 phydev->mac_managed_pm = true;
1460 phy_attached_info(phydev);
1461
1462 return 0;
1463
1464err_deregister_fixed_link:
1465 if (of_phy_is_fixed_link(np))
1466 of_phy_deregister_fixed_link(np);
1467
1468 return err;
1469}
1470
1471/* PHY control start function */
1472static int ravb_phy_start(struct net_device *ndev)
1473{
1474 int error;
1475
1476 error = ravb_phy_init(ndev);
1477 if (error)
1478 return error;
1479
1480 phy_start(ndev->phydev);
1481
1482 return 0;
1483}
1484
1485static u32 ravb_get_msglevel(struct net_device *ndev)
1486{
1487 struct ravb_private *priv = netdev_priv(ndev);
1488
1489 return priv->msg_enable;
1490}
1491
1492static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1493{
1494 struct ravb_private *priv = netdev_priv(ndev);
1495
1496 priv->msg_enable = value;
1497}
1498
1499static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = {
1500 "rx_queue_0_current",
1501 "tx_queue_0_current",
1502 "rx_queue_0_dirty",
1503 "tx_queue_0_dirty",
1504 "rx_queue_0_packets",
1505 "tx_queue_0_packets",
1506 "rx_queue_0_bytes",
1507 "tx_queue_0_bytes",
1508 "rx_queue_0_mcast_packets",
1509 "rx_queue_0_errors",
1510 "rx_queue_0_crc_errors",
1511 "rx_queue_0_frame_errors",
1512 "rx_queue_0_length_errors",
1513 "rx_queue_0_csum_offload_errors",
1514 "rx_queue_0_over_errors",
1515};
1516
1517static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1518 "rx_queue_0_current",
1519 "tx_queue_0_current",
1520 "rx_queue_0_dirty",
1521 "tx_queue_0_dirty",
1522 "rx_queue_0_packets",
1523 "tx_queue_0_packets",
1524 "rx_queue_0_bytes",
1525 "tx_queue_0_bytes",
1526 "rx_queue_0_mcast_packets",
1527 "rx_queue_0_errors",
1528 "rx_queue_0_crc_errors",
1529 "rx_queue_0_frame_errors",
1530 "rx_queue_0_length_errors",
1531 "rx_queue_0_missed_errors",
1532 "rx_queue_0_over_errors",
1533
1534 "rx_queue_1_current",
1535 "tx_queue_1_current",
1536 "rx_queue_1_dirty",
1537 "tx_queue_1_dirty",
1538 "rx_queue_1_packets",
1539 "tx_queue_1_packets",
1540 "rx_queue_1_bytes",
1541 "tx_queue_1_bytes",
1542 "rx_queue_1_mcast_packets",
1543 "rx_queue_1_errors",
1544 "rx_queue_1_crc_errors",
1545 "rx_queue_1_frame_errors",
1546 "rx_queue_1_length_errors",
1547 "rx_queue_1_missed_errors",
1548 "rx_queue_1_over_errors",
1549};
1550
1551static int ravb_get_sset_count(struct net_device *netdev, int sset)
1552{
1553 struct ravb_private *priv = netdev_priv(netdev);
1554 const struct ravb_hw_info *info = priv->info;
1555
1556 switch (sset) {
1557 case ETH_SS_STATS:
1558 return info->stats_len;
1559 default:
1560 return -EOPNOTSUPP;
1561 }
1562}
1563
1564static void ravb_get_ethtool_stats(struct net_device *ndev,
1565 struct ethtool_stats *estats, u64 *data)
1566{
1567 struct ravb_private *priv = netdev_priv(ndev);
1568 const struct ravb_hw_info *info = priv->info;
1569 int num_rx_q;
1570 int i = 0;
1571 int q;
1572
1573 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1;
1574 /* Device-specific stats */
1575 for (q = RAVB_BE; q < num_rx_q; q++) {
1576 struct net_device_stats *stats = &priv->stats[q];
1577
1578 data[i++] = priv->cur_rx[q];
1579 data[i++] = priv->cur_tx[q];
1580 data[i++] = priv->dirty_rx[q];
1581 data[i++] = priv->dirty_tx[q];
1582 data[i++] = stats->rx_packets;
1583 data[i++] = stats->tx_packets;
1584 data[i++] = stats->rx_bytes;
1585 data[i++] = stats->tx_bytes;
1586 data[i++] = stats->multicast;
1587 data[i++] = stats->rx_errors;
1588 data[i++] = stats->rx_crc_errors;
1589 data[i++] = stats->rx_frame_errors;
1590 data[i++] = stats->rx_length_errors;
1591 data[i++] = stats->rx_missed_errors;
1592 data[i++] = stats->rx_over_errors;
1593 }
1594}
1595
1596static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1597{
1598 struct ravb_private *priv = netdev_priv(ndev);
1599 const struct ravb_hw_info *info = priv->info;
1600
1601 switch (stringset) {
1602 case ETH_SS_STATS:
1603 memcpy(data, info->gstrings_stats, info->gstrings_size);
1604 break;
1605 }
1606}
1607
1608static void ravb_get_ringparam(struct net_device *ndev,
1609 struct ethtool_ringparam *ring,
1610 struct kernel_ethtool_ringparam *kernel_ring,
1611 struct netlink_ext_ack *extack)
1612{
1613 struct ravb_private *priv = netdev_priv(ndev);
1614
1615 ring->rx_max_pending = BE_RX_RING_MAX;
1616 ring->tx_max_pending = BE_TX_RING_MAX;
1617 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1618 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1619}
1620
1621static int ravb_set_ringparam(struct net_device *ndev,
1622 struct ethtool_ringparam *ring,
1623 struct kernel_ethtool_ringparam *kernel_ring,
1624 struct netlink_ext_ack *extack)
1625{
1626 struct ravb_private *priv = netdev_priv(ndev);
1627 const struct ravb_hw_info *info = priv->info;
1628 int error;
1629
1630 if (ring->tx_pending > BE_TX_RING_MAX ||
1631 ring->rx_pending > BE_RX_RING_MAX ||
1632 ring->tx_pending < BE_TX_RING_MIN ||
1633 ring->rx_pending < BE_RX_RING_MIN)
1634 return -EINVAL;
1635 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1636 return -EINVAL;
1637
1638 if (netif_running(ndev)) {
1639 netif_device_detach(ndev);
1640 /* Stop PTP Clock driver */
1641 if (info->gptp)
1642 ravb_ptp_stop(ndev);
1643 /* Wait for DMA stopping */
1644 error = ravb_stop_dma(ndev);
1645 if (error) {
1646 netdev_err(ndev,
1647 "cannot set ringparam! Any AVB processes are still running?\n");
1648 return error;
1649 }
1650 synchronize_irq(ndev->irq);
1651
1652 /* Free all the skb's in the RX queue and the DMA buffers. */
1653 ravb_ring_free(ndev, RAVB_BE);
1654 if (info->nc_queues)
1655 ravb_ring_free(ndev, RAVB_NC);
1656 }
1657
1658 /* Set new parameters */
1659 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1660 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1661
1662 if (netif_running(ndev)) {
1663 error = ravb_dmac_init(ndev);
1664 if (error) {
1665 netdev_err(ndev,
1666 "%s: ravb_dmac_init() failed, error %d\n",
1667 __func__, error);
1668 return error;
1669 }
1670
1671 ravb_emac_init(ndev);
1672
1673 /* Initialise PTP Clock driver */
1674 if (info->gptp)
1675 ravb_ptp_init(ndev, priv->pdev);
1676
1677 netif_device_attach(ndev);
1678 }
1679
1680 return 0;
1681}
1682
1683static int ravb_get_ts_info(struct net_device *ndev,
1684 struct ethtool_ts_info *info)
1685{
1686 struct ravb_private *priv = netdev_priv(ndev);
1687 const struct ravb_hw_info *hw_info = priv->info;
1688
1689 info->so_timestamping =
1690 SOF_TIMESTAMPING_TX_SOFTWARE |
1691 SOF_TIMESTAMPING_RX_SOFTWARE |
1692 SOF_TIMESTAMPING_SOFTWARE |
1693 SOF_TIMESTAMPING_TX_HARDWARE |
1694 SOF_TIMESTAMPING_RX_HARDWARE |
1695 SOF_TIMESTAMPING_RAW_HARDWARE;
1696 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1697 info->rx_filters =
1698 (1 << HWTSTAMP_FILTER_NONE) |
1699 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1700 (1 << HWTSTAMP_FILTER_ALL);
1701 if (hw_info->gptp || hw_info->ccc_gac)
1702 info->phc_index = ptp_clock_index(priv->ptp.clock);
1703
1704 return 0;
1705}
1706
1707static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1708{
1709 struct ravb_private *priv = netdev_priv(ndev);
1710
1711 wol->supported = WAKE_MAGIC;
1712 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1713}
1714
1715static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1716{
1717 struct ravb_private *priv = netdev_priv(ndev);
1718 const struct ravb_hw_info *info = priv->info;
1719
1720 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC))
1721 return -EOPNOTSUPP;
1722
1723 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1724
1725 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1726
1727 return 0;
1728}
1729
1730static const struct ethtool_ops ravb_ethtool_ops = {
1731 .nway_reset = phy_ethtool_nway_reset,
1732 .get_msglevel = ravb_get_msglevel,
1733 .set_msglevel = ravb_set_msglevel,
1734 .get_link = ethtool_op_get_link,
1735 .get_strings = ravb_get_strings,
1736 .get_ethtool_stats = ravb_get_ethtool_stats,
1737 .get_sset_count = ravb_get_sset_count,
1738 .get_ringparam = ravb_get_ringparam,
1739 .set_ringparam = ravb_set_ringparam,
1740 .get_ts_info = ravb_get_ts_info,
1741 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1742 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1743 .get_wol = ravb_get_wol,
1744 .set_wol = ravb_set_wol,
1745};
1746
1747static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1748 struct net_device *ndev, struct device *dev,
1749 const char *ch)
1750{
1751 char *name;
1752 int error;
1753
1754 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1755 if (!name)
1756 return -ENOMEM;
1757 error = request_irq(irq, handler, 0, name, ndev);
1758 if (error)
1759 netdev_err(ndev, "cannot request IRQ %s\n", name);
1760
1761 return error;
1762}
1763
1764/* Network device open function for Ethernet AVB */
1765static int ravb_open(struct net_device *ndev)
1766{
1767 struct ravb_private *priv = netdev_priv(ndev);
1768 const struct ravb_hw_info *info = priv->info;
1769 struct platform_device *pdev = priv->pdev;
1770 struct device *dev = &pdev->dev;
1771 int error;
1772
1773 napi_enable(&priv->napi[RAVB_BE]);
1774 if (info->nc_queues)
1775 napi_enable(&priv->napi[RAVB_NC]);
1776
1777 if (!info->multi_irqs) {
1778 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1779 ndev->name, ndev);
1780 if (error) {
1781 netdev_err(ndev, "cannot request IRQ\n");
1782 goto out_napi_off;
1783 }
1784 } else {
1785 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1786 dev, "ch22:multi");
1787 if (error)
1788 goto out_napi_off;
1789 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1790 dev, "ch24:emac");
1791 if (error)
1792 goto out_free_irq;
1793 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1794 ndev, dev, "ch0:rx_be");
1795 if (error)
1796 goto out_free_irq_emac;
1797 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1798 ndev, dev, "ch18:tx_be");
1799 if (error)
1800 goto out_free_irq_be_rx;
1801 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1802 ndev, dev, "ch1:rx_nc");
1803 if (error)
1804 goto out_free_irq_be_tx;
1805 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1806 ndev, dev, "ch19:tx_nc");
1807 if (error)
1808 goto out_free_irq_nc_rx;
1809
1810 if (info->err_mgmt_irqs) {
1811 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
1812 ndev, dev, "err_a");
1813 if (error)
1814 goto out_free_irq_nc_tx;
1815 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
1816 ndev, dev, "mgmt_a");
1817 if (error)
1818 goto out_free_irq_erra;
1819 }
1820 }
1821
1822 /* Device init */
1823 error = ravb_dmac_init(ndev);
1824 if (error)
1825 goto out_free_irq_mgmta;
1826 ravb_emac_init(ndev);
1827
1828 /* Initialise PTP Clock driver */
1829 if (info->gptp)
1830 ravb_ptp_init(ndev, priv->pdev);
1831
1832 netif_tx_start_all_queues(ndev);
1833
1834 /* PHY control start */
1835 error = ravb_phy_start(ndev);
1836 if (error)
1837 goto out_ptp_stop;
1838
1839 return 0;
1840
1841out_ptp_stop:
1842 /* Stop PTP Clock driver */
1843 if (info->gptp)
1844 ravb_ptp_stop(ndev);
1845out_free_irq_mgmta:
1846 if (!info->multi_irqs)
1847 goto out_free_irq;
1848 if (info->err_mgmt_irqs)
1849 free_irq(priv->mgmta_irq, ndev);
1850out_free_irq_erra:
1851 if (info->err_mgmt_irqs)
1852 free_irq(priv->erra_irq, ndev);
1853out_free_irq_nc_tx:
1854 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1855out_free_irq_nc_rx:
1856 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1857out_free_irq_be_tx:
1858 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1859out_free_irq_be_rx:
1860 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1861out_free_irq_emac:
1862 free_irq(priv->emac_irq, ndev);
1863out_free_irq:
1864 free_irq(ndev->irq, ndev);
1865out_napi_off:
1866 if (info->nc_queues)
1867 napi_disable(&priv->napi[RAVB_NC]);
1868 napi_disable(&priv->napi[RAVB_BE]);
1869 return error;
1870}
1871
1872/* Timeout function for Ethernet AVB */
1873static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1874{
1875 struct ravb_private *priv = netdev_priv(ndev);
1876
1877 netif_err(priv, tx_err, ndev,
1878 "transmit timed out, status %08x, resetting...\n",
1879 ravb_read(ndev, ISS));
1880
1881 /* tx_errors count up */
1882 ndev->stats.tx_errors++;
1883
1884 schedule_work(&priv->work);
1885}
1886
1887static void ravb_tx_timeout_work(struct work_struct *work)
1888{
1889 struct ravb_private *priv = container_of(work, struct ravb_private,
1890 work);
1891 const struct ravb_hw_info *info = priv->info;
1892 struct net_device *ndev = priv->ndev;
1893 int error;
1894
1895 netif_tx_stop_all_queues(ndev);
1896
1897 /* Stop PTP Clock driver */
1898 if (info->gptp)
1899 ravb_ptp_stop(ndev);
1900
1901 /* Wait for DMA stopping */
1902 if (ravb_stop_dma(ndev)) {
1903 /* If ravb_stop_dma() fails, the hardware is still operating
1904 * for TX and/or RX. So, this should not call the following
1905 * functions because ravb_dmac_init() is possible to fail too.
1906 * Also, this should not retry ravb_stop_dma() again and again
1907 * here because it's possible to wait forever. So, this just
1908 * re-enables the TX and RX and skip the following
1909 * re-initialization procedure.
1910 */
1911 ravb_rcv_snd_enable(ndev);
1912 goto out;
1913 }
1914
1915 ravb_ring_free(ndev, RAVB_BE);
1916 if (info->nc_queues)
1917 ravb_ring_free(ndev, RAVB_NC);
1918
1919 /* Device init */
1920 error = ravb_dmac_init(ndev);
1921 if (error) {
1922 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1923 * should return here to avoid re-enabling the TX and RX in
1924 * ravb_emac_init().
1925 */
1926 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1927 __func__, error);
1928 return;
1929 }
1930 ravb_emac_init(ndev);
1931
1932out:
1933 /* Initialise PTP Clock driver */
1934 if (info->gptp)
1935 ravb_ptp_init(ndev, priv->pdev);
1936
1937 netif_tx_start_all_queues(ndev);
1938}
1939
1940/* Packet transmit function for Ethernet AVB */
1941static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1942{
1943 struct ravb_private *priv = netdev_priv(ndev);
1944 const struct ravb_hw_info *info = priv->info;
1945 unsigned int num_tx_desc = priv->num_tx_desc;
1946 u16 q = skb_get_queue_mapping(skb);
1947 struct ravb_tstamp_skb *ts_skb;
1948 struct ravb_tx_desc *desc;
1949 unsigned long flags;
1950 u32 dma_addr;
1951 void *buffer;
1952 u32 entry;
1953 u32 len;
1954
1955 spin_lock_irqsave(&priv->lock, flags);
1956 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1957 num_tx_desc) {
1958 netif_err(priv, tx_queued, ndev,
1959 "still transmitting with the full ring!\n");
1960 netif_stop_subqueue(ndev, q);
1961 spin_unlock_irqrestore(&priv->lock, flags);
1962 return NETDEV_TX_BUSY;
1963 }
1964
1965 if (skb_put_padto(skb, ETH_ZLEN))
1966 goto exit;
1967
1968 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1969 priv->tx_skb[q][entry / num_tx_desc] = skb;
1970
1971 if (num_tx_desc > 1) {
1972 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1973 entry / num_tx_desc * DPTR_ALIGN;
1974 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1975
1976 /* Zero length DMA descriptors are problematic as they seem
1977 * to terminate DMA transfers. Avoid them by simply using a
1978 * length of DPTR_ALIGN (4) when skb data is aligned to
1979 * DPTR_ALIGN.
1980 *
1981 * As skb is guaranteed to have at least ETH_ZLEN (60)
1982 * bytes of data by the call to skb_put_padto() above this
1983 * is safe with respect to both the length of the first DMA
1984 * descriptor (len) overflowing the available data and the
1985 * length of the second DMA descriptor (skb->len - len)
1986 * being negative.
1987 */
1988 if (len == 0)
1989 len = DPTR_ALIGN;
1990
1991 memcpy(buffer, skb->data, len);
1992 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1993 DMA_TO_DEVICE);
1994 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1995 goto drop;
1996
1997 desc = &priv->tx_ring[q][entry];
1998 desc->ds_tagl = cpu_to_le16(len);
1999 desc->dptr = cpu_to_le32(dma_addr);
2000
2001 buffer = skb->data + len;
2002 len = skb->len - len;
2003 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
2004 DMA_TO_DEVICE);
2005 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2006 goto unmap;
2007
2008 desc++;
2009 } else {
2010 desc = &priv->tx_ring[q][entry];
2011 len = skb->len;
2012 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
2013 DMA_TO_DEVICE);
2014 if (dma_mapping_error(ndev->dev.parent, dma_addr))
2015 goto drop;
2016 }
2017 desc->ds_tagl = cpu_to_le16(len);
2018 desc->dptr = cpu_to_le32(dma_addr);
2019
2020 /* TX timestamp required */
2021 if (info->gptp || info->ccc_gac) {
2022 if (q == RAVB_NC) {
2023 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
2024 if (!ts_skb) {
2025 if (num_tx_desc > 1) {
2026 desc--;
2027 dma_unmap_single(ndev->dev.parent, dma_addr,
2028 len, DMA_TO_DEVICE);
2029 }
2030 goto unmap;
2031 }
2032 ts_skb->skb = skb_get(skb);
2033 ts_skb->tag = priv->ts_skb_tag++;
2034 priv->ts_skb_tag &= 0x3ff;
2035 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
2036
2037 /* TAG and timestamp required flag */
2038 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2039 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
2040 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
2041 }
2042
2043 skb_tx_timestamp(skb);
2044 }
2045 /* Descriptor type must be set after all the above writes */
2046 dma_wmb();
2047 if (num_tx_desc > 1) {
2048 desc->die_dt = DT_FEND;
2049 desc--;
2050 desc->die_dt = DT_FSTART;
2051 } else {
2052 desc->die_dt = DT_FSINGLE;
2053 }
2054 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
2055
2056 priv->cur_tx[q] += num_tx_desc;
2057 if (priv->cur_tx[q] - priv->dirty_tx[q] >
2058 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
2059 !ravb_tx_free(ndev, q, true))
2060 netif_stop_subqueue(ndev, q);
2061
2062exit:
2063 spin_unlock_irqrestore(&priv->lock, flags);
2064 return NETDEV_TX_OK;
2065
2066unmap:
2067 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
2068 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
2069drop:
2070 dev_kfree_skb_any(skb);
2071 priv->tx_skb[q][entry / num_tx_desc] = NULL;
2072 goto exit;
2073}
2074
2075static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
2076 struct net_device *sb_dev)
2077{
2078 /* If skb needs TX timestamp, it is handled in network control queue */
2079 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
2080 RAVB_BE;
2081
2082}
2083
2084static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
2085{
2086 struct ravb_private *priv = netdev_priv(ndev);
2087 const struct ravb_hw_info *info = priv->info;
2088 struct net_device_stats *nstats, *stats0, *stats1;
2089
2090 nstats = &ndev->stats;
2091 stats0 = &priv->stats[RAVB_BE];
2092
2093 if (info->tx_counters) {
2094 nstats->tx_dropped += ravb_read(ndev, TROCR);
2095 ravb_write(ndev, 0, TROCR); /* (write clear) */
2096 }
2097
2098 if (info->carrier_counters) {
2099 nstats->collisions += ravb_read(ndev, CXR41);
2100 ravb_write(ndev, 0, CXR41); /* (write clear) */
2101 nstats->tx_carrier_errors += ravb_read(ndev, CXR42);
2102 ravb_write(ndev, 0, CXR42); /* (write clear) */
2103 }
2104
2105 nstats->rx_packets = stats0->rx_packets;
2106 nstats->tx_packets = stats0->tx_packets;
2107 nstats->rx_bytes = stats0->rx_bytes;
2108 nstats->tx_bytes = stats0->tx_bytes;
2109 nstats->multicast = stats0->multicast;
2110 nstats->rx_errors = stats0->rx_errors;
2111 nstats->rx_crc_errors = stats0->rx_crc_errors;
2112 nstats->rx_frame_errors = stats0->rx_frame_errors;
2113 nstats->rx_length_errors = stats0->rx_length_errors;
2114 nstats->rx_missed_errors = stats0->rx_missed_errors;
2115 nstats->rx_over_errors = stats0->rx_over_errors;
2116 if (info->nc_queues) {
2117 stats1 = &priv->stats[RAVB_NC];
2118
2119 nstats->rx_packets += stats1->rx_packets;
2120 nstats->tx_packets += stats1->tx_packets;
2121 nstats->rx_bytes += stats1->rx_bytes;
2122 nstats->tx_bytes += stats1->tx_bytes;
2123 nstats->multicast += stats1->multicast;
2124 nstats->rx_errors += stats1->rx_errors;
2125 nstats->rx_crc_errors += stats1->rx_crc_errors;
2126 nstats->rx_frame_errors += stats1->rx_frame_errors;
2127 nstats->rx_length_errors += stats1->rx_length_errors;
2128 nstats->rx_missed_errors += stats1->rx_missed_errors;
2129 nstats->rx_over_errors += stats1->rx_over_errors;
2130 }
2131
2132 return nstats;
2133}
2134
2135/* Update promiscuous bit */
2136static void ravb_set_rx_mode(struct net_device *ndev)
2137{
2138 struct ravb_private *priv = netdev_priv(ndev);
2139 unsigned long flags;
2140
2141 spin_lock_irqsave(&priv->lock, flags);
2142 ravb_modify(ndev, ECMR, ECMR_PRM,
2143 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
2144 spin_unlock_irqrestore(&priv->lock, flags);
2145}
2146
2147/* Device close function for Ethernet AVB */
2148static int ravb_close(struct net_device *ndev)
2149{
2150 struct device_node *np = ndev->dev.parent->of_node;
2151 struct ravb_private *priv = netdev_priv(ndev);
2152 const struct ravb_hw_info *info = priv->info;
2153 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
2154
2155 netif_tx_stop_all_queues(ndev);
2156
2157 /* Disable interrupts by clearing the interrupt masks. */
2158 ravb_write(ndev, 0, RIC0);
2159 ravb_write(ndev, 0, RIC2);
2160 ravb_write(ndev, 0, TIC);
2161
2162 /* Stop PTP Clock driver */
2163 if (info->gptp)
2164 ravb_ptp_stop(ndev);
2165
2166 /* Set the config mode to stop the AVB-DMAC's processes */
2167 if (ravb_stop_dma(ndev) < 0)
2168 netdev_err(ndev,
2169 "device will be stopped after h/w processes are done.\n");
2170
2171 /* Clear the timestamp list */
2172 if (info->gptp || info->ccc_gac) {
2173 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
2174 list_del(&ts_skb->list);
2175 kfree_skb(ts_skb->skb);
2176 kfree(ts_skb);
2177 }
2178 }
2179
2180 /* PHY disconnect */
2181 if (ndev->phydev) {
2182 phy_stop(ndev->phydev);
2183 phy_disconnect(ndev->phydev);
2184 if (of_phy_is_fixed_link(np))
2185 of_phy_deregister_fixed_link(np);
2186 }
2187
2188 if (info->multi_irqs) {
2189 free_irq(priv->tx_irqs[RAVB_NC], ndev);
2190 free_irq(priv->rx_irqs[RAVB_NC], ndev);
2191 free_irq(priv->tx_irqs[RAVB_BE], ndev);
2192 free_irq(priv->rx_irqs[RAVB_BE], ndev);
2193 free_irq(priv->emac_irq, ndev);
2194 if (info->err_mgmt_irqs) {
2195 free_irq(priv->erra_irq, ndev);
2196 free_irq(priv->mgmta_irq, ndev);
2197 }
2198 }
2199 free_irq(ndev->irq, ndev);
2200
2201 if (info->nc_queues)
2202 napi_disable(&priv->napi[RAVB_NC]);
2203 napi_disable(&priv->napi[RAVB_BE]);
2204
2205 /* Free all the skb's in the RX queue and the DMA buffers. */
2206 ravb_ring_free(ndev, RAVB_BE);
2207 if (info->nc_queues)
2208 ravb_ring_free(ndev, RAVB_NC);
2209
2210 return 0;
2211}
2212
2213static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
2214{
2215 struct ravb_private *priv = netdev_priv(ndev);
2216 struct hwtstamp_config config;
2217
2218 config.flags = 0;
2219 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
2220 HWTSTAMP_TX_OFF;
2221 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
2222 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
2223 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
2224 break;
2225 case RAVB_RXTSTAMP_TYPE_ALL:
2226 config.rx_filter = HWTSTAMP_FILTER_ALL;
2227 break;
2228 default:
2229 config.rx_filter = HWTSTAMP_FILTER_NONE;
2230 }
2231
2232 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2233 -EFAULT : 0;
2234}
2235
2236/* Control hardware time stamping */
2237static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
2238{
2239 struct ravb_private *priv = netdev_priv(ndev);
2240 struct hwtstamp_config config;
2241 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
2242 u32 tstamp_tx_ctrl;
2243
2244 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
2245 return -EFAULT;
2246
2247 switch (config.tx_type) {
2248 case HWTSTAMP_TX_OFF:
2249 tstamp_tx_ctrl = 0;
2250 break;
2251 case HWTSTAMP_TX_ON:
2252 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
2253 break;
2254 default:
2255 return -ERANGE;
2256 }
2257
2258 switch (config.rx_filter) {
2259 case HWTSTAMP_FILTER_NONE:
2260 tstamp_rx_ctrl = 0;
2261 break;
2262 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2263 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
2264 break;
2265 default:
2266 config.rx_filter = HWTSTAMP_FILTER_ALL;
2267 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
2268 }
2269
2270 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
2271 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
2272
2273 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
2274 -EFAULT : 0;
2275}
2276
2277/* ioctl to device function */
2278static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
2279{
2280 struct phy_device *phydev = ndev->phydev;
2281
2282 if (!netif_running(ndev))
2283 return -EINVAL;
2284
2285 if (!phydev)
2286 return -ENODEV;
2287
2288 switch (cmd) {
2289 case SIOCGHWTSTAMP:
2290 return ravb_hwtstamp_get(ndev, req);
2291 case SIOCSHWTSTAMP:
2292 return ravb_hwtstamp_set(ndev, req);
2293 }
2294
2295 return phy_mii_ioctl(phydev, req, cmd);
2296}
2297
2298static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
2299{
2300 struct ravb_private *priv = netdev_priv(ndev);
2301
2302 ndev->mtu = new_mtu;
2303
2304 if (netif_running(ndev)) {
2305 synchronize_irq(priv->emac_irq);
2306 ravb_emac_init(ndev);
2307 }
2308
2309 netdev_update_features(ndev);
2310
2311 return 0;
2312}
2313
2314static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
2315{
2316 struct ravb_private *priv = netdev_priv(ndev);
2317 unsigned long flags;
2318
2319 spin_lock_irqsave(&priv->lock, flags);
2320
2321 /* Disable TX and RX */
2322 ravb_rcv_snd_disable(ndev);
2323
2324 /* Modify RX Checksum setting */
2325 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2326
2327 /* Enable TX and RX */
2328 ravb_rcv_snd_enable(ndev);
2329
2330 spin_unlock_irqrestore(&priv->lock, flags);
2331}
2332
2333static int ravb_set_features_gbeth(struct net_device *ndev,
2334 netdev_features_t features)
2335{
2336 /* Place holder */
2337 return 0;
2338}
2339
2340static int ravb_set_features_rcar(struct net_device *ndev,
2341 netdev_features_t features)
2342{
2343 netdev_features_t changed = ndev->features ^ features;
2344
2345 if (changed & NETIF_F_RXCSUM)
2346 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2347
2348 ndev->features = features;
2349
2350 return 0;
2351}
2352
2353static int ravb_set_features(struct net_device *ndev,
2354 netdev_features_t features)
2355{
2356 struct ravb_private *priv = netdev_priv(ndev);
2357 const struct ravb_hw_info *info = priv->info;
2358
2359 return info->set_feature(ndev, features);
2360}
2361
2362static const struct net_device_ops ravb_netdev_ops = {
2363 .ndo_open = ravb_open,
2364 .ndo_stop = ravb_close,
2365 .ndo_start_xmit = ravb_start_xmit,
2366 .ndo_select_queue = ravb_select_queue,
2367 .ndo_get_stats = ravb_get_stats,
2368 .ndo_set_rx_mode = ravb_set_rx_mode,
2369 .ndo_tx_timeout = ravb_tx_timeout,
2370 .ndo_eth_ioctl = ravb_do_ioctl,
2371 .ndo_change_mtu = ravb_change_mtu,
2372 .ndo_validate_addr = eth_validate_addr,
2373 .ndo_set_mac_address = eth_mac_addr,
2374 .ndo_set_features = ravb_set_features,
2375};
2376
2377/* MDIO bus init function */
2378static int ravb_mdio_init(struct ravb_private *priv)
2379{
2380 struct platform_device *pdev = priv->pdev;
2381 struct device *dev = &pdev->dev;
2382 int error;
2383
2384 /* Bitbang init */
2385 priv->mdiobb.ops = &bb_ops;
2386
2387 /* MII controller setting */
2388 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
2389 if (!priv->mii_bus)
2390 return -ENOMEM;
2391
2392 /* Hook up MII support for ethtool */
2393 priv->mii_bus->name = "ravb_mii";
2394 priv->mii_bus->parent = dev;
2395 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2396 pdev->name, pdev->id);
2397
2398 /* Register MDIO bus */
2399 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
2400 if (error)
2401 goto out_free_bus;
2402
2403 return 0;
2404
2405out_free_bus:
2406 free_mdio_bitbang(priv->mii_bus);
2407 return error;
2408}
2409
2410/* MDIO bus release function */
2411static int ravb_mdio_release(struct ravb_private *priv)
2412{
2413 /* Unregister mdio bus */
2414 mdiobus_unregister(priv->mii_bus);
2415
2416 /* Free bitbang info */
2417 free_mdio_bitbang(priv->mii_bus);
2418
2419 return 0;
2420}
2421
2422static const struct ravb_hw_info ravb_gen3_hw_info = {
2423 .rx_ring_free = ravb_rx_ring_free_rcar,
2424 .rx_ring_format = ravb_rx_ring_format_rcar,
2425 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2426 .receive = ravb_rx_rcar,
2427 .set_rate = ravb_set_rate_rcar,
2428 .set_feature = ravb_set_features_rcar,
2429 .dmac_init = ravb_dmac_init_rcar,
2430 .emac_init = ravb_emac_init_rcar,
2431 .gstrings_stats = ravb_gstrings_stats,
2432 .gstrings_size = sizeof(ravb_gstrings_stats),
2433 .net_hw_features = NETIF_F_RXCSUM,
2434 .net_features = NETIF_F_RXCSUM,
2435 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2436 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2437 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2438 .rx_max_buf_size = SZ_2K,
2439 .internal_delay = 1,
2440 .tx_counters = 1,
2441 .multi_irqs = 1,
2442 .irq_en_dis = 1,
2443 .ccc_gac = 1,
2444 .nc_queues = 1,
2445 .magic_pkt = 1,
2446};
2447
2448static const struct ravb_hw_info ravb_gen2_hw_info = {
2449 .rx_ring_free = ravb_rx_ring_free_rcar,
2450 .rx_ring_format = ravb_rx_ring_format_rcar,
2451 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2452 .receive = ravb_rx_rcar,
2453 .set_rate = ravb_set_rate_rcar,
2454 .set_feature = ravb_set_features_rcar,
2455 .dmac_init = ravb_dmac_init_rcar,
2456 .emac_init = ravb_emac_init_rcar,
2457 .gstrings_stats = ravb_gstrings_stats,
2458 .gstrings_size = sizeof(ravb_gstrings_stats),
2459 .net_hw_features = NETIF_F_RXCSUM,
2460 .net_features = NETIF_F_RXCSUM,
2461 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2462 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2463 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2464 .rx_max_buf_size = SZ_2K,
2465 .aligned_tx = 1,
2466 .gptp = 1,
2467 .nc_queues = 1,
2468 .magic_pkt = 1,
2469};
2470
2471static const struct ravb_hw_info ravb_rzv2m_hw_info = {
2472 .rx_ring_free = ravb_rx_ring_free_rcar,
2473 .rx_ring_format = ravb_rx_ring_format_rcar,
2474 .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
2475 .receive = ravb_rx_rcar,
2476 .set_rate = ravb_set_rate_rcar,
2477 .set_feature = ravb_set_features_rcar,
2478 .dmac_init = ravb_dmac_init_rcar,
2479 .emac_init = ravb_emac_init_rcar,
2480 .gstrings_stats = ravb_gstrings_stats,
2481 .gstrings_size = sizeof(ravb_gstrings_stats),
2482 .net_hw_features = NETIF_F_RXCSUM,
2483 .net_features = NETIF_F_RXCSUM,
2484 .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
2485 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
2486 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
2487 .rx_max_buf_size = SZ_2K,
2488 .multi_irqs = 1,
2489 .err_mgmt_irqs = 1,
2490 .gptp = 1,
2491 .gptp_ref_clk = 1,
2492 .nc_queues = 1,
2493 .magic_pkt = 1,
2494};
2495
2496static const struct ravb_hw_info gbeth_hw_info = {
2497 .rx_ring_free = ravb_rx_ring_free_gbeth,
2498 .rx_ring_format = ravb_rx_ring_format_gbeth,
2499 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth,
2500 .receive = ravb_rx_gbeth,
2501 .set_rate = ravb_set_rate_gbeth,
2502 .set_feature = ravb_set_features_gbeth,
2503 .dmac_init = ravb_dmac_init_gbeth,
2504 .emac_init = ravb_emac_init_gbeth,
2505 .gstrings_stats = ravb_gstrings_stats_gbeth,
2506 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth),
2507 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth),
2508 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN),
2509 .tccr_mask = TCCR_TSRQ0,
2510 .rx_max_buf_size = SZ_8K,
2511 .aligned_tx = 1,
2512 .tx_counters = 1,
2513 .carrier_counters = 1,
2514 .half_duplex = 1,
2515};
2516
2517static const struct of_device_id ravb_match_table[] = {
2518 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info },
2519 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info },
2520 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
2521 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
2522 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
2523 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info },
2524 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
2525 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
2526 { }
2527};
2528MODULE_DEVICE_TABLE(of, ravb_match_table);
2529
2530static int ravb_set_gti(struct net_device *ndev)
2531{
2532 struct ravb_private *priv = netdev_priv(ndev);
2533 const struct ravb_hw_info *info = priv->info;
2534 struct device *dev = ndev->dev.parent;
2535 unsigned long rate;
2536 uint64_t inc;
2537
2538 if (info->gptp_ref_clk)
2539 rate = clk_get_rate(priv->gptp_clk);
2540 else
2541 rate = clk_get_rate(priv->clk);
2542 if (!rate)
2543 return -EINVAL;
2544
2545 inc = div64_ul(1000000000ULL << 20, rate);
2546
2547 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
2548 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
2549 inc, GTI_TIV_MIN, GTI_TIV_MAX);
2550 return -EINVAL;
2551 }
2552
2553 ravb_write(ndev, inc, GTI);
2554
2555 return 0;
2556}
2557
2558static void ravb_set_config_mode(struct net_device *ndev)
2559{
2560 struct ravb_private *priv = netdev_priv(ndev);
2561 const struct ravb_hw_info *info = priv->info;
2562
2563 if (info->gptp) {
2564 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2565 /* Set CSEL value */
2566 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
2567 } else if (info->ccc_gac) {
2568 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
2569 CCC_GAC | CCC_CSEL_HPB);
2570 } else {
2571 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
2572 }
2573}
2574
2575/* Set tx and rx clock internal delay modes */
2576static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev)
2577{
2578 struct ravb_private *priv = netdev_priv(ndev);
2579 bool explicit_delay = false;
2580 u32 delay;
2581
2582 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) {
2583 /* Valid values are 0 and 1800, according to DT bindings */
2584 priv->rxcidm = !!delay;
2585 explicit_delay = true;
2586 }
2587 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) {
2588 /* Valid values are 0 and 2000, according to DT bindings */
2589 priv->txcidm = !!delay;
2590 explicit_delay = true;
2591 }
2592
2593 if (explicit_delay)
2594 return;
2595
2596 /* Fall back to legacy rgmii-*id behavior */
2597 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2598 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) {
2599 priv->rxcidm = 1;
2600 priv->rgmii_override = 1;
2601 }
2602
2603 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2604 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2605 priv->txcidm = 1;
2606 priv->rgmii_override = 1;
2607 }
2608}
2609
2610static void ravb_set_delay_mode(struct net_device *ndev)
2611{
2612 struct ravb_private *priv = netdev_priv(ndev);
2613 u32 set = 0;
2614
2615 if (priv->rxcidm)
2616 set |= APSR_RDM;
2617 if (priv->txcidm)
2618 set |= APSR_TDM;
2619 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set);
2620}
2621
2622static int ravb_probe(struct platform_device *pdev)
2623{
2624 struct device_node *np = pdev->dev.of_node;
2625 const struct ravb_hw_info *info;
2626 struct reset_control *rstc;
2627 struct ravb_private *priv;
2628 struct net_device *ndev;
2629 int error, irq, q;
2630 struct resource *res;
2631 int i;
2632
2633 if (!np) {
2634 dev_err(&pdev->dev,
2635 "this driver is required to be instantiated from device tree\n");
2636 return -EINVAL;
2637 }
2638
2639 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2640 if (IS_ERR(rstc))
2641 return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
2642 "failed to get cpg reset\n");
2643
2644 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2645 NUM_TX_QUEUE, NUM_RX_QUEUE);
2646 if (!ndev)
2647 return -ENOMEM;
2648
2649 info = of_device_get_match_data(&pdev->dev);
2650
2651 ndev->features = info->net_features;
2652 ndev->hw_features = info->net_hw_features;
2653
2654 reset_control_deassert(rstc);
2655 pm_runtime_enable(&pdev->dev);
2656 pm_runtime_get_sync(&pdev->dev);
2657
2658 if (info->multi_irqs) {
2659 if (info->err_mgmt_irqs)
2660 irq = platform_get_irq_byname(pdev, "dia");
2661 else
2662 irq = platform_get_irq_byname(pdev, "ch22");
2663 } else {
2664 irq = platform_get_irq(pdev, 0);
2665 }
2666 if (irq < 0) {
2667 error = irq;
2668 goto out_release;
2669 }
2670 ndev->irq = irq;
2671
2672 SET_NETDEV_DEV(ndev, &pdev->dev);
2673
2674 priv = netdev_priv(ndev);
2675 priv->info = info;
2676 priv->rstc = rstc;
2677 priv->ndev = ndev;
2678 priv->pdev = pdev;
2679 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2680 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2681 if (info->nc_queues) {
2682 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2683 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2684 }
2685
2686 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2687 if (IS_ERR(priv->addr)) {
2688 error = PTR_ERR(priv->addr);
2689 goto out_release;
2690 }
2691
2692 /* The Ether-specific entries in the device structure. */
2693 ndev->base_addr = res->start;
2694
2695 spin_lock_init(&priv->lock);
2696 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2697
2698 error = of_get_phy_mode(np, &priv->phy_interface);
2699 if (error && error != -ENODEV)
2700 goto out_release;
2701
2702 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2703 priv->avb_link_active_low =
2704 of_property_read_bool(np, "renesas,ether-link-active-low");
2705
2706 if (info->multi_irqs) {
2707 if (info->err_mgmt_irqs)
2708 irq = platform_get_irq_byname(pdev, "line3");
2709 else
2710 irq = platform_get_irq_byname(pdev, "ch24");
2711 if (irq < 0) {
2712 error = irq;
2713 goto out_release;
2714 }
2715 priv->emac_irq = irq;
2716 for (i = 0; i < NUM_RX_QUEUE; i++) {
2717 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2718 if (irq < 0) {
2719 error = irq;
2720 goto out_release;
2721 }
2722 priv->rx_irqs[i] = irq;
2723 }
2724 for (i = 0; i < NUM_TX_QUEUE; i++) {
2725 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2726 if (irq < 0) {
2727 error = irq;
2728 goto out_release;
2729 }
2730 priv->tx_irqs[i] = irq;
2731 }
2732
2733 if (info->err_mgmt_irqs) {
2734 irq = platform_get_irq_byname(pdev, "err_a");
2735 if (irq < 0) {
2736 error = irq;
2737 goto out_release;
2738 }
2739 priv->erra_irq = irq;
2740
2741 irq = platform_get_irq_byname(pdev, "mgmt_a");
2742 if (irq < 0) {
2743 error = irq;
2744 goto out_release;
2745 }
2746 priv->mgmta_irq = irq;
2747 }
2748 }
2749
2750 priv->clk = devm_clk_get(&pdev->dev, NULL);
2751 if (IS_ERR(priv->clk)) {
2752 error = PTR_ERR(priv->clk);
2753 goto out_release;
2754 }
2755
2756 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk");
2757 if (IS_ERR(priv->refclk)) {
2758 error = PTR_ERR(priv->refclk);
2759 goto out_release;
2760 }
2761 clk_prepare_enable(priv->refclk);
2762
2763 if (info->gptp_ref_clk) {
2764 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
2765 if (IS_ERR(priv->gptp_clk)) {
2766 error = PTR_ERR(priv->gptp_clk);
2767 goto out_disable_refclk;
2768 }
2769 clk_prepare_enable(priv->gptp_clk);
2770 }
2771
2772 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2773 ndev->min_mtu = ETH_MIN_MTU;
2774
2775 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer
2776 * Use two descriptor to handle such situation. First descriptor to
2777 * handle aligned data buffer and second descriptor to handle the
2778 * overflow data because of alignment.
2779 */
2780 priv->num_tx_desc = info->aligned_tx ? 2 : 1;
2781
2782 /* Set function */
2783 ndev->netdev_ops = &ravb_netdev_ops;
2784 ndev->ethtool_ops = &ravb_ethtool_ops;
2785
2786 /* Set AVB config mode */
2787 ravb_set_config_mode(ndev);
2788
2789 if (info->gptp || info->ccc_gac) {
2790 /* Set GTI value */
2791 error = ravb_set_gti(ndev);
2792 if (error)
2793 goto out_disable_gptp_clk;
2794
2795 /* Request GTI loading */
2796 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2797 }
2798
2799 if (info->internal_delay) {
2800 ravb_parse_delay_mode(np, ndev);
2801 ravb_set_delay_mode(ndev);
2802 }
2803
2804 /* Allocate descriptor base address table */
2805 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2806 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2807 &priv->desc_bat_dma, GFP_KERNEL);
2808 if (!priv->desc_bat) {
2809 dev_err(&pdev->dev,
2810 "Cannot allocate desc base address table (size %d bytes)\n",
2811 priv->desc_bat_size);
2812 error = -ENOMEM;
2813 goto out_disable_gptp_clk;
2814 }
2815 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2816 priv->desc_bat[q].die_dt = DT_EOS;
2817 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2818
2819 /* Initialise HW timestamp list */
2820 INIT_LIST_HEAD(&priv->ts_skb_list);
2821
2822 /* Initialise PTP Clock driver */
2823 if (info->ccc_gac)
2824 ravb_ptp_init(ndev, pdev);
2825
2826 /* Debug message level */
2827 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2828
2829 /* Read and set MAC address */
2830 ravb_read_mac_address(np, ndev);
2831 if (!is_valid_ether_addr(ndev->dev_addr)) {
2832 dev_warn(&pdev->dev,
2833 "no valid MAC address supplied, using a random one\n");
2834 eth_hw_addr_random(ndev);
2835 }
2836
2837 /* MDIO bus init */
2838 error = ravb_mdio_init(priv);
2839 if (error) {
2840 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2841 goto out_dma_free;
2842 }
2843
2844 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll);
2845 if (info->nc_queues)
2846 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll);
2847
2848 /* Network device register */
2849 error = register_netdev(ndev);
2850 if (error)
2851 goto out_napi_del;
2852
2853 device_set_wakeup_capable(&pdev->dev, 1);
2854
2855 /* Print device information */
2856 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2857 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2858
2859 platform_set_drvdata(pdev, ndev);
2860
2861 return 0;
2862
2863out_napi_del:
2864 if (info->nc_queues)
2865 netif_napi_del(&priv->napi[RAVB_NC]);
2866
2867 netif_napi_del(&priv->napi[RAVB_BE]);
2868 ravb_mdio_release(priv);
2869out_dma_free:
2870 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2871 priv->desc_bat_dma);
2872
2873 /* Stop PTP Clock driver */
2874 if (info->ccc_gac)
2875 ravb_ptp_stop(ndev);
2876out_disable_gptp_clk:
2877 clk_disable_unprepare(priv->gptp_clk);
2878out_disable_refclk:
2879 clk_disable_unprepare(priv->refclk);
2880out_release:
2881 free_netdev(ndev);
2882
2883 pm_runtime_put(&pdev->dev);
2884 pm_runtime_disable(&pdev->dev);
2885 reset_control_assert(rstc);
2886 return error;
2887}
2888
2889static int ravb_remove(struct platform_device *pdev)
2890{
2891 struct net_device *ndev = platform_get_drvdata(pdev);
2892 struct ravb_private *priv = netdev_priv(ndev);
2893 const struct ravb_hw_info *info = priv->info;
2894
2895 /* Stop PTP Clock driver */
2896 if (info->ccc_gac)
2897 ravb_ptp_stop(ndev);
2898
2899 clk_disable_unprepare(priv->gptp_clk);
2900 clk_disable_unprepare(priv->refclk);
2901
2902 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2903 priv->desc_bat_dma);
2904 /* Set reset mode */
2905 ravb_write(ndev, CCC_OPC_RESET, CCC);
2906 unregister_netdev(ndev);
2907 if (info->nc_queues)
2908 netif_napi_del(&priv->napi[RAVB_NC]);
2909 netif_napi_del(&priv->napi[RAVB_BE]);
2910 ravb_mdio_release(priv);
2911 pm_runtime_put_sync(&pdev->dev);
2912 pm_runtime_disable(&pdev->dev);
2913 reset_control_assert(priv->rstc);
2914 free_netdev(ndev);
2915 platform_set_drvdata(pdev, NULL);
2916
2917 return 0;
2918}
2919
2920static int ravb_wol_setup(struct net_device *ndev)
2921{
2922 struct ravb_private *priv = netdev_priv(ndev);
2923 const struct ravb_hw_info *info = priv->info;
2924
2925 /* Disable interrupts by clearing the interrupt masks. */
2926 ravb_write(ndev, 0, RIC0);
2927 ravb_write(ndev, 0, RIC2);
2928 ravb_write(ndev, 0, TIC);
2929
2930 /* Only allow ECI interrupts */
2931 synchronize_irq(priv->emac_irq);
2932 if (info->nc_queues)
2933 napi_disable(&priv->napi[RAVB_NC]);
2934 napi_disable(&priv->napi[RAVB_BE]);
2935 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2936
2937 /* Enable MagicPacket */
2938 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2939
2940 return enable_irq_wake(priv->emac_irq);
2941}
2942
2943static int ravb_wol_restore(struct net_device *ndev)
2944{
2945 struct ravb_private *priv = netdev_priv(ndev);
2946 const struct ravb_hw_info *info = priv->info;
2947
2948 if (info->nc_queues)
2949 napi_enable(&priv->napi[RAVB_NC]);
2950 napi_enable(&priv->napi[RAVB_BE]);
2951
2952 /* Disable MagicPacket */
2953 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2954
2955 ravb_close(ndev);
2956
2957 return disable_irq_wake(priv->emac_irq);
2958}
2959
2960static int __maybe_unused ravb_suspend(struct device *dev)
2961{
2962 struct net_device *ndev = dev_get_drvdata(dev);
2963 struct ravb_private *priv = netdev_priv(ndev);
2964 int ret;
2965
2966 if (!netif_running(ndev))
2967 return 0;
2968
2969 netif_device_detach(ndev);
2970
2971 if (priv->wol_enabled)
2972 ret = ravb_wol_setup(ndev);
2973 else
2974 ret = ravb_close(ndev);
2975
2976 if (priv->info->ccc_gac)
2977 ravb_ptp_stop(ndev);
2978
2979 return ret;
2980}
2981
2982static int __maybe_unused ravb_resume(struct device *dev)
2983{
2984 struct net_device *ndev = dev_get_drvdata(dev);
2985 struct ravb_private *priv = netdev_priv(ndev);
2986 const struct ravb_hw_info *info = priv->info;
2987 int ret = 0;
2988
2989 /* If WoL is enabled set reset mode to rearm the WoL logic */
2990 if (priv->wol_enabled)
2991 ravb_write(ndev, CCC_OPC_RESET, CCC);
2992
2993 /* All register have been reset to default values.
2994 * Restore all registers which where setup at probe time and
2995 * reopen device if it was running before system suspended.
2996 */
2997
2998 /* Set AVB config mode */
2999 ravb_set_config_mode(ndev);
3000
3001 if (info->gptp || info->ccc_gac) {
3002 /* Set GTI value */
3003 ret = ravb_set_gti(ndev);
3004 if (ret)
3005 return ret;
3006
3007 /* Request GTI loading */
3008 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
3009 }
3010
3011 if (info->internal_delay)
3012 ravb_set_delay_mode(ndev);
3013
3014 /* Restore descriptor base address table */
3015 ravb_write(ndev, priv->desc_bat_dma, DBAT);
3016
3017 if (priv->info->ccc_gac)
3018 ravb_ptp_init(ndev, priv->pdev);
3019
3020 if (netif_running(ndev)) {
3021 if (priv->wol_enabled) {
3022 ret = ravb_wol_restore(ndev);
3023 if (ret)
3024 return ret;
3025 }
3026 ret = ravb_open(ndev);
3027 if (ret < 0)
3028 return ret;
3029 ravb_set_rx_mode(ndev);
3030 netif_device_attach(ndev);
3031 }
3032
3033 return ret;
3034}
3035
3036static int __maybe_unused ravb_runtime_nop(struct device *dev)
3037{
3038 /* Runtime PM callback shared between ->runtime_suspend()
3039 * and ->runtime_resume(). Simply returns success.
3040 *
3041 * This driver re-initializes all registers after
3042 * pm_runtime_get_sync() anyway so there is no need
3043 * to save and restore registers here.
3044 */
3045 return 0;
3046}
3047
3048static const struct dev_pm_ops ravb_dev_pm_ops = {
3049 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
3050 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
3051};
3052
3053static struct platform_driver ravb_driver = {
3054 .probe = ravb_probe,
3055 .remove = ravb_remove,
3056 .driver = {
3057 .name = "ravb",
3058 .pm = &ravb_dev_pm_ops,
3059 .of_match_table = ravb_match_table,
3060 },
3061};
3062
3063module_platform_driver(ravb_driver);
3064
3065MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
3066MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
3067MODULE_LICENSE("GPL v2");