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1/* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14#include <linux/cache.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/etherdevice.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/module.h>
25#include <linux/net_tstamp.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_irq.h>
29#include <linux/of_mdio.h>
30#include <linux/of_net.h>
31#include <linux/pm_runtime.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35#include <asm/div64.h>
36
37#include "ravb.h"
38
39#define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 "ch0", /* RAVB_BE */
47 "ch1", /* RAVB_NC */
48};
49
50static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 "ch18", /* RAVB_BE */
52 "ch19", /* RAVB_NC */
53};
54
55void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 u32 set)
57{
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59}
60
61int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
62{
63 int i;
64
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
67 return 0;
68 udelay(10);
69 }
70 return -ETIMEDOUT;
71}
72
73static int ravb_config(struct net_device *ndev)
74{
75 int error;
76
77 /* Set config mode */
78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
81 if (error)
82 netdev_err(ndev, "failed to switch device to config mode\n");
83
84 return error;
85}
86
87static void ravb_set_duplex(struct net_device *ndev)
88{
89 struct ravb_private *priv = netdev_priv(ndev);
90
91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
92}
93
94static void ravb_set_rate(struct net_device *ndev)
95{
96 struct ravb_private *priv = netdev_priv(ndev);
97
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
101 break;
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
104 break;
105 }
106}
107
108static void ravb_set_buffer_align(struct sk_buff *skb)
109{
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
111
112 if (reserve)
113 skb_reserve(skb, RAVB_ALIGN - reserve);
114}
115
116/* Get MAC address from the MAC address registers
117 *
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
120 */
121static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
122{
123 if (mac) {
124 ether_addr_copy(ndev->dev_addr, mac);
125 } else {
126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
128
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
135 }
136}
137
138static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
139{
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
141 mdiobb);
142
143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
144}
145
146/* MDC pin control */
147static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
148{
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
150}
151
152/* Data I/O pin control */
153static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
154{
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
156}
157
158/* Set data bit */
159static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
160{
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
162}
163
164/* Get data bit */
165static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
166{
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
168 mdiobb);
169
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
171}
172
173/* MDIO bus control struct */
174static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
180};
181
182/* Free TX skb function for AVB-IP */
183static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
184{
185 struct ravb_private *priv = netdev_priv(ndev);
186 struct net_device_stats *stats = &priv->stats[q];
187 struct ravb_tx_desc *desc;
188 int free_num = 0;
189 int entry;
190 u32 size;
191
192 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
193 bool txed;
194
195 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
196 NUM_TX_DESC);
197 desc = &priv->tx_ring[q][entry];
198 txed = desc->die_dt == DT_FEMPTY;
199 if (free_txed_only && !txed)
200 break;
201 /* Descriptor type must be checked before all other reads */
202 dma_rmb();
203 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
204 /* Free the original skb. */
205 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
206 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
207 size, DMA_TO_DEVICE);
208 /* Last packet descriptor? */
209 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
210 entry /= NUM_TX_DESC;
211 dev_kfree_skb_any(priv->tx_skb[q][entry]);
212 priv->tx_skb[q][entry] = NULL;
213 if (txed)
214 stats->tx_packets++;
215 }
216 free_num++;
217 }
218 if (txed)
219 stats->tx_bytes += size;
220 desc->die_dt = DT_EEMPTY;
221 }
222 return free_num;
223}
224
225/* Free skb's and DMA buffers for Ethernet AVB */
226static void ravb_ring_free(struct net_device *ndev, int q)
227{
228 struct ravb_private *priv = netdev_priv(ndev);
229 int ring_size;
230 int i;
231
232 /* Free RX skb ringbuffer */
233 if (priv->rx_skb[q]) {
234 for (i = 0; i < priv->num_rx_ring[q]; i++)
235 dev_kfree_skb(priv->rx_skb[q][i]);
236 }
237 kfree(priv->rx_skb[q]);
238 priv->rx_skb[q] = NULL;
239
240 /* Free aligned TX buffers */
241 kfree(priv->tx_align[q]);
242 priv->tx_align[q] = NULL;
243
244 if (priv->rx_ring[q]) {
245 for (i = 0; i < priv->num_rx_ring[q]; i++) {
246 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
247
248 if (!dma_mapping_error(ndev->dev.parent,
249 le32_to_cpu(desc->dptr)))
250 dma_unmap_single(ndev->dev.parent,
251 le32_to_cpu(desc->dptr),
252 PKT_BUF_SZ,
253 DMA_FROM_DEVICE);
254 }
255 ring_size = sizeof(struct ravb_ex_rx_desc) *
256 (priv->num_rx_ring[q] + 1);
257 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
258 priv->rx_desc_dma[q]);
259 priv->rx_ring[q] = NULL;
260 }
261
262 if (priv->tx_ring[q]) {
263 ravb_tx_free(ndev, q, false);
264
265 ring_size = sizeof(struct ravb_tx_desc) *
266 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
268 priv->tx_desc_dma[q]);
269 priv->tx_ring[q] = NULL;
270 }
271
272 /* Free TX skb ringbuffer.
273 * SKBs are freed by ravb_tx_free() call above.
274 */
275 kfree(priv->tx_skb[q]);
276 priv->tx_skb[q] = NULL;
277}
278
279/* Format skb and descriptor buffer for Ethernet AVB */
280static void ravb_ring_format(struct net_device *ndev, int q)
281{
282 struct ravb_private *priv = netdev_priv(ndev);
283 struct ravb_ex_rx_desc *rx_desc;
284 struct ravb_tx_desc *tx_desc;
285 struct ravb_desc *desc;
286 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
287 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
288 NUM_TX_DESC;
289 dma_addr_t dma_addr;
290 int i;
291
292 priv->cur_rx[q] = 0;
293 priv->cur_tx[q] = 0;
294 priv->dirty_rx[q] = 0;
295 priv->dirty_tx[q] = 0;
296
297 memset(priv->rx_ring[q], 0, rx_ring_size);
298 /* Build RX ring buffer */
299 for (i = 0; i < priv->num_rx_ring[q]; i++) {
300 /* RX descriptor */
301 rx_desc = &priv->rx_ring[q][i];
302 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
303 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
304 PKT_BUF_SZ,
305 DMA_FROM_DEVICE);
306 /* We just set the data size to 0 for a failed mapping which
307 * should prevent DMA from happening...
308 */
309 if (dma_mapping_error(ndev->dev.parent, dma_addr))
310 rx_desc->ds_cc = cpu_to_le16(0);
311 rx_desc->dptr = cpu_to_le32(dma_addr);
312 rx_desc->die_dt = DT_FEMPTY;
313 }
314 rx_desc = &priv->rx_ring[q][i];
315 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
316 rx_desc->die_dt = DT_LINKFIX; /* type */
317
318 memset(priv->tx_ring[q], 0, tx_ring_size);
319 /* Build TX ring buffer */
320 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
321 i++, tx_desc++) {
322 tx_desc->die_dt = DT_EEMPTY;
323 tx_desc++;
324 tx_desc->die_dt = DT_EEMPTY;
325 }
326 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
327 tx_desc->die_dt = DT_LINKFIX; /* type */
328
329 /* RX descriptor base address for best effort */
330 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
331 desc->die_dt = DT_LINKFIX; /* type */
332 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
333
334 /* TX descriptor base address for best effort */
335 desc = &priv->desc_bat[q];
336 desc->die_dt = DT_LINKFIX; /* type */
337 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
338}
339
340/* Init skb and descriptor buffer for Ethernet AVB */
341static int ravb_ring_init(struct net_device *ndev, int q)
342{
343 struct ravb_private *priv = netdev_priv(ndev);
344 struct sk_buff *skb;
345 int ring_size;
346 int i;
347
348 /* Allocate RX and TX skb rings */
349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
350 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
352 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
353 if (!priv->rx_skb[q] || !priv->tx_skb[q])
354 goto error;
355
356 for (i = 0; i < priv->num_rx_ring[q]; i++) {
357 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
358 if (!skb)
359 goto error;
360 ravb_set_buffer_align(skb);
361 priv->rx_skb[q][i] = skb;
362 }
363
364 /* Allocate rings for the aligned buffers */
365 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
366 DPTR_ALIGN - 1, GFP_KERNEL);
367 if (!priv->tx_align[q])
368 goto error;
369
370 /* Allocate all RX descriptors. */
371 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
372 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
373 &priv->rx_desc_dma[q],
374 GFP_KERNEL);
375 if (!priv->rx_ring[q])
376 goto error;
377
378 priv->dirty_rx[q] = 0;
379
380 /* Allocate all TX descriptors. */
381 ring_size = sizeof(struct ravb_tx_desc) *
382 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
383 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
384 &priv->tx_desc_dma[q],
385 GFP_KERNEL);
386 if (!priv->tx_ring[q])
387 goto error;
388
389 return 0;
390
391error:
392 ravb_ring_free(ndev, q);
393
394 return -ENOMEM;
395}
396
397/* E-MAC init function */
398static void ravb_emac_init(struct net_device *ndev)
399{
400 struct ravb_private *priv = netdev_priv(ndev);
401
402 /* Receive frame limit set register */
403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
404
405 /* PAUSE prohibition */
406 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
407 ECMR_TE | ECMR_RE, ECMR);
408
409 ravb_set_rate(ndev);
410
411 /* Set MAC address */
412 ravb_write(ndev,
413 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
414 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
415 ravb_write(ndev,
416 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
417
418 /* E-MAC status register clear */
419 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
420
421 /* E-MAC interrupt enable register */
422 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
423}
424
425/* Device init function for Ethernet AVB */
426static int ravb_dmac_init(struct net_device *ndev)
427{
428 struct ravb_private *priv = netdev_priv(ndev);
429 int error;
430
431 /* Set CONFIG mode */
432 error = ravb_config(ndev);
433 if (error)
434 return error;
435
436 error = ravb_ring_init(ndev, RAVB_BE);
437 if (error)
438 return error;
439 error = ravb_ring_init(ndev, RAVB_NC);
440 if (error) {
441 ravb_ring_free(ndev, RAVB_BE);
442 return error;
443 }
444
445 /* Descriptor format */
446 ravb_ring_format(ndev, RAVB_BE);
447 ravb_ring_format(ndev, RAVB_NC);
448
449#if defined(__LITTLE_ENDIAN)
450 ravb_modify(ndev, CCC, CCC_BOC, 0);
451#else
452 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
453#endif
454
455 /* Set AVB RX */
456 ravb_write(ndev,
457 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
458
459 /* Set FIFO size */
460 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
461
462 /* Timestamp enable */
463 ravb_write(ndev, TCCR_TFEN, TCCR);
464
465 /* Interrupt init: */
466 if (priv->chip_id == RCAR_GEN3) {
467 /* Clear DIL.DPLx */
468 ravb_write(ndev, 0, DIL);
469 /* Set queue specific interrupt */
470 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
471 }
472 /* Frame receive */
473 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
474 /* Disable FIFO full warning */
475 ravb_write(ndev, 0, RIC1);
476 /* Receive FIFO full error, descriptor empty */
477 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
478 /* Frame transmitted, timestamp FIFO updated */
479 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
480
481 /* Setting the control will start the AVB-DMAC process. */
482 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
483
484 return 0;
485}
486
487static void ravb_get_tx_tstamp(struct net_device *ndev)
488{
489 struct ravb_private *priv = netdev_priv(ndev);
490 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
491 struct skb_shared_hwtstamps shhwtstamps;
492 struct sk_buff *skb;
493 struct timespec64 ts;
494 u16 tag, tfa_tag;
495 int count;
496 u32 tfa2;
497
498 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
499 while (count--) {
500 tfa2 = ravb_read(ndev, TFA2);
501 tfa_tag = (tfa2 & TFA2_TST) >> 16;
502 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
503 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
504 ravb_read(ndev, TFA1);
505 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
506 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
507 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
508 list) {
509 skb = ts_skb->skb;
510 tag = ts_skb->tag;
511 list_del(&ts_skb->list);
512 kfree(ts_skb);
513 if (tag == tfa_tag) {
514 skb_tstamp_tx(skb, &shhwtstamps);
515 break;
516 }
517 }
518 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
519 }
520}
521
522/* Packet receive function for Ethernet AVB */
523static bool ravb_rx(struct net_device *ndev, int *quota, int q)
524{
525 struct ravb_private *priv = netdev_priv(ndev);
526 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
527 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
528 priv->cur_rx[q];
529 struct net_device_stats *stats = &priv->stats[q];
530 struct ravb_ex_rx_desc *desc;
531 struct sk_buff *skb;
532 dma_addr_t dma_addr;
533 struct timespec64 ts;
534 u8 desc_status;
535 u16 pkt_len;
536 int limit;
537
538 boguscnt = min(boguscnt, *quota);
539 limit = boguscnt;
540 desc = &priv->rx_ring[q][entry];
541 while (desc->die_dt != DT_FEMPTY) {
542 /* Descriptor type must be checked before all other reads */
543 dma_rmb();
544 desc_status = desc->msc;
545 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
546
547 if (--boguscnt < 0)
548 break;
549
550 /* We use 0-byte descriptors to mark the DMA mapping errors */
551 if (!pkt_len)
552 continue;
553
554 if (desc_status & MSC_MC)
555 stats->multicast++;
556
557 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
558 MSC_CEEF)) {
559 stats->rx_errors++;
560 if (desc_status & MSC_CRC)
561 stats->rx_crc_errors++;
562 if (desc_status & MSC_RFE)
563 stats->rx_frame_errors++;
564 if (desc_status & (MSC_RTLF | MSC_RTSF))
565 stats->rx_length_errors++;
566 if (desc_status & MSC_CEEF)
567 stats->rx_missed_errors++;
568 } else {
569 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
570
571 skb = priv->rx_skb[q][entry];
572 priv->rx_skb[q][entry] = NULL;
573 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
574 PKT_BUF_SZ,
575 DMA_FROM_DEVICE);
576 get_ts &= (q == RAVB_NC) ?
577 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
578 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
579 if (get_ts) {
580 struct skb_shared_hwtstamps *shhwtstamps;
581
582 shhwtstamps = skb_hwtstamps(skb);
583 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
584 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
585 32) | le32_to_cpu(desc->ts_sl);
586 ts.tv_nsec = le32_to_cpu(desc->ts_n);
587 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
588 }
589 skb_put(skb, pkt_len);
590 skb->protocol = eth_type_trans(skb, ndev);
591 napi_gro_receive(&priv->napi[q], skb);
592 stats->rx_packets++;
593 stats->rx_bytes += pkt_len;
594 }
595
596 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
597 desc = &priv->rx_ring[q][entry];
598 }
599
600 /* Refill the RX ring buffers. */
601 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
602 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
603 desc = &priv->rx_ring[q][entry];
604 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
605
606 if (!priv->rx_skb[q][entry]) {
607 skb = netdev_alloc_skb(ndev,
608 PKT_BUF_SZ + RAVB_ALIGN - 1);
609 if (!skb)
610 break; /* Better luck next round. */
611 ravb_set_buffer_align(skb);
612 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
613 le16_to_cpu(desc->ds_cc),
614 DMA_FROM_DEVICE);
615 skb_checksum_none_assert(skb);
616 /* We just set the data size to 0 for a failed mapping
617 * which should prevent DMA from happening...
618 */
619 if (dma_mapping_error(ndev->dev.parent, dma_addr))
620 desc->ds_cc = cpu_to_le16(0);
621 desc->dptr = cpu_to_le32(dma_addr);
622 priv->rx_skb[q][entry] = skb;
623 }
624 /* Descriptor type must be set after all the above writes */
625 dma_wmb();
626 desc->die_dt = DT_FEMPTY;
627 }
628
629 *quota -= limit - (++boguscnt);
630
631 return boguscnt <= 0;
632}
633
634static void ravb_rcv_snd_disable(struct net_device *ndev)
635{
636 /* Disable TX and RX */
637 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
638}
639
640static void ravb_rcv_snd_enable(struct net_device *ndev)
641{
642 /* Enable TX and RX */
643 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
644}
645
646/* function for waiting dma process finished */
647static int ravb_stop_dma(struct net_device *ndev)
648{
649 int error;
650
651 /* Wait for stopping the hardware TX process */
652 error = ravb_wait(ndev, TCCR,
653 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
654 if (error)
655 return error;
656
657 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
658 0);
659 if (error)
660 return error;
661
662 /* Stop the E-MAC's RX/TX processes. */
663 ravb_rcv_snd_disable(ndev);
664
665 /* Wait for stopping the RX DMA process */
666 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
667 if (error)
668 return error;
669
670 /* Stop AVB-DMAC process */
671 return ravb_config(ndev);
672}
673
674/* E-MAC interrupt handler */
675static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
676{
677 struct ravb_private *priv = netdev_priv(ndev);
678 u32 ecsr, psr;
679
680 ecsr = ravb_read(ndev, ECSR);
681 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
682 if (ecsr & ECSR_ICD)
683 ndev->stats.tx_carrier_errors++;
684 if (ecsr & ECSR_LCHNG) {
685 /* Link changed */
686 if (priv->no_avb_link)
687 return;
688 psr = ravb_read(ndev, PSR);
689 if (priv->avb_link_active_low)
690 psr ^= PSR_LMON;
691 if (!(psr & PSR_LMON)) {
692 /* DIsable RX and TX */
693 ravb_rcv_snd_disable(ndev);
694 } else {
695 /* Enable RX and TX */
696 ravb_rcv_snd_enable(ndev);
697 }
698 }
699}
700
701static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
702{
703 struct net_device *ndev = dev_id;
704 struct ravb_private *priv = netdev_priv(ndev);
705
706 spin_lock(&priv->lock);
707 ravb_emac_interrupt_unlocked(ndev);
708 mmiowb();
709 spin_unlock(&priv->lock);
710 return IRQ_HANDLED;
711}
712
713/* Error interrupt handler */
714static void ravb_error_interrupt(struct net_device *ndev)
715{
716 struct ravb_private *priv = netdev_priv(ndev);
717 u32 eis, ris2;
718
719 eis = ravb_read(ndev, EIS);
720 ravb_write(ndev, ~EIS_QFS, EIS);
721 if (eis & EIS_QFS) {
722 ris2 = ravb_read(ndev, RIS2);
723 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
724
725 /* Receive Descriptor Empty int */
726 if (ris2 & RIS2_QFF0)
727 priv->stats[RAVB_BE].rx_over_errors++;
728
729 /* Receive Descriptor Empty int */
730 if (ris2 & RIS2_QFF1)
731 priv->stats[RAVB_NC].rx_over_errors++;
732
733 /* Receive FIFO Overflow int */
734 if (ris2 & RIS2_RFFF)
735 priv->rx_fifo_errors++;
736 }
737}
738
739static bool ravb_queue_interrupt(struct net_device *ndev, int q)
740{
741 struct ravb_private *priv = netdev_priv(ndev);
742 u32 ris0 = ravb_read(ndev, RIS0);
743 u32 ric0 = ravb_read(ndev, RIC0);
744 u32 tis = ravb_read(ndev, TIS);
745 u32 tic = ravb_read(ndev, TIC);
746
747 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
748 if (napi_schedule_prep(&priv->napi[q])) {
749 /* Mask RX and TX interrupts */
750 if (priv->chip_id == RCAR_GEN2) {
751 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
752 ravb_write(ndev, tic & ~BIT(q), TIC);
753 } else {
754 ravb_write(ndev, BIT(q), RID0);
755 ravb_write(ndev, BIT(q), TID);
756 }
757 __napi_schedule(&priv->napi[q]);
758 } else {
759 netdev_warn(ndev,
760 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
761 ris0, ric0);
762 netdev_warn(ndev,
763 " tx status 0x%08x, tx mask 0x%08x.\n",
764 tis, tic);
765 }
766 return true;
767 }
768 return false;
769}
770
771static bool ravb_timestamp_interrupt(struct net_device *ndev)
772{
773 u32 tis = ravb_read(ndev, TIS);
774
775 if (tis & TIS_TFUF) {
776 ravb_write(ndev, ~TIS_TFUF, TIS);
777 ravb_get_tx_tstamp(ndev);
778 return true;
779 }
780 return false;
781}
782
783static irqreturn_t ravb_interrupt(int irq, void *dev_id)
784{
785 struct net_device *ndev = dev_id;
786 struct ravb_private *priv = netdev_priv(ndev);
787 irqreturn_t result = IRQ_NONE;
788 u32 iss;
789
790 spin_lock(&priv->lock);
791 /* Get interrupt status */
792 iss = ravb_read(ndev, ISS);
793
794 /* Received and transmitted interrupts */
795 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
796 int q;
797
798 /* Timestamp updated */
799 if (ravb_timestamp_interrupt(ndev))
800 result = IRQ_HANDLED;
801
802 /* Network control and best effort queue RX/TX */
803 for (q = RAVB_NC; q >= RAVB_BE; q--) {
804 if (ravb_queue_interrupt(ndev, q))
805 result = IRQ_HANDLED;
806 }
807 }
808
809 /* E-MAC status summary */
810 if (iss & ISS_MS) {
811 ravb_emac_interrupt_unlocked(ndev);
812 result = IRQ_HANDLED;
813 }
814
815 /* Error status summary */
816 if (iss & ISS_ES) {
817 ravb_error_interrupt(ndev);
818 result = IRQ_HANDLED;
819 }
820
821 /* gPTP interrupt status summary */
822 if (iss & ISS_CGIS) {
823 ravb_ptp_interrupt(ndev);
824 result = IRQ_HANDLED;
825 }
826
827 mmiowb();
828 spin_unlock(&priv->lock);
829 return result;
830}
831
832/* Timestamp/Error/gPTP interrupt handler */
833static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
834{
835 struct net_device *ndev = dev_id;
836 struct ravb_private *priv = netdev_priv(ndev);
837 irqreturn_t result = IRQ_NONE;
838 u32 iss;
839
840 spin_lock(&priv->lock);
841 /* Get interrupt status */
842 iss = ravb_read(ndev, ISS);
843
844 /* Timestamp updated */
845 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
846 result = IRQ_HANDLED;
847
848 /* Error status summary */
849 if (iss & ISS_ES) {
850 ravb_error_interrupt(ndev);
851 result = IRQ_HANDLED;
852 }
853
854 /* gPTP interrupt status summary */
855 if (iss & ISS_CGIS) {
856 ravb_ptp_interrupt(ndev);
857 result = IRQ_HANDLED;
858 }
859
860 mmiowb();
861 spin_unlock(&priv->lock);
862 return result;
863}
864
865static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
866{
867 struct net_device *ndev = dev_id;
868 struct ravb_private *priv = netdev_priv(ndev);
869 irqreturn_t result = IRQ_NONE;
870
871 spin_lock(&priv->lock);
872
873 /* Network control/Best effort queue RX/TX */
874 if (ravb_queue_interrupt(ndev, q))
875 result = IRQ_HANDLED;
876
877 mmiowb();
878 spin_unlock(&priv->lock);
879 return result;
880}
881
882static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
883{
884 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
885}
886
887static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
888{
889 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
890}
891
892static int ravb_poll(struct napi_struct *napi, int budget)
893{
894 struct net_device *ndev = napi->dev;
895 struct ravb_private *priv = netdev_priv(ndev);
896 unsigned long flags;
897 int q = napi - priv->napi;
898 int mask = BIT(q);
899 int quota = budget;
900 u32 ris0, tis;
901
902 for (;;) {
903 tis = ravb_read(ndev, TIS);
904 ris0 = ravb_read(ndev, RIS0);
905 if (!((ris0 & mask) || (tis & mask)))
906 break;
907
908 /* Processing RX Descriptor Ring */
909 if (ris0 & mask) {
910 /* Clear RX interrupt */
911 ravb_write(ndev, ~mask, RIS0);
912 if (ravb_rx(ndev, "a, q))
913 goto out;
914 }
915 /* Processing TX Descriptor Ring */
916 if (tis & mask) {
917 spin_lock_irqsave(&priv->lock, flags);
918 /* Clear TX interrupt */
919 ravb_write(ndev, ~mask, TIS);
920 ravb_tx_free(ndev, q, true);
921 netif_wake_subqueue(ndev, q);
922 mmiowb();
923 spin_unlock_irqrestore(&priv->lock, flags);
924 }
925 }
926
927 napi_complete(napi);
928
929 /* Re-enable RX/TX interrupts */
930 spin_lock_irqsave(&priv->lock, flags);
931 if (priv->chip_id == RCAR_GEN2) {
932 ravb_modify(ndev, RIC0, mask, mask);
933 ravb_modify(ndev, TIC, mask, mask);
934 } else {
935 ravb_write(ndev, mask, RIE0);
936 ravb_write(ndev, mask, TIE);
937 }
938 mmiowb();
939 spin_unlock_irqrestore(&priv->lock, flags);
940
941 /* Receive error message handling */
942 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
943 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
944 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
945 ndev->stats.rx_over_errors = priv->rx_over_errors;
946 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
947 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
948out:
949 return budget - quota;
950}
951
952/* PHY state control function */
953static void ravb_adjust_link(struct net_device *ndev)
954{
955 struct ravb_private *priv = netdev_priv(ndev);
956 struct phy_device *phydev = ndev->phydev;
957 bool new_state = false;
958
959 if (phydev->link) {
960 if (phydev->duplex != priv->duplex) {
961 new_state = true;
962 priv->duplex = phydev->duplex;
963 ravb_set_duplex(ndev);
964 }
965
966 if (phydev->speed != priv->speed) {
967 new_state = true;
968 priv->speed = phydev->speed;
969 ravb_set_rate(ndev);
970 }
971 if (!priv->link) {
972 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
973 new_state = true;
974 priv->link = phydev->link;
975 if (priv->no_avb_link)
976 ravb_rcv_snd_enable(ndev);
977 }
978 } else if (priv->link) {
979 new_state = true;
980 priv->link = 0;
981 priv->speed = 0;
982 priv->duplex = -1;
983 if (priv->no_avb_link)
984 ravb_rcv_snd_disable(ndev);
985 }
986
987 if (new_state && netif_msg_link(priv))
988 phy_print_status(phydev);
989}
990
991/* PHY init function */
992static int ravb_phy_init(struct net_device *ndev)
993{
994 struct device_node *np = ndev->dev.parent->of_node;
995 struct ravb_private *priv = netdev_priv(ndev);
996 struct phy_device *phydev;
997 struct device_node *pn;
998 int err;
999
1000 priv->link = 0;
1001 priv->speed = 0;
1002 priv->duplex = -1;
1003
1004 /* Try connecting to PHY */
1005 pn = of_parse_phandle(np, "phy-handle", 0);
1006 if (!pn) {
1007 /* In the case of a fixed PHY, the DT node associated
1008 * to the PHY is the Ethernet MAC DT node.
1009 */
1010 if (of_phy_is_fixed_link(np)) {
1011 err = of_phy_register_fixed_link(np);
1012 if (err)
1013 return err;
1014 }
1015 pn = of_node_get(np);
1016 }
1017 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1018 priv->phy_interface);
1019 of_node_put(pn);
1020 if (!phydev) {
1021 netdev_err(ndev, "failed to connect PHY\n");
1022 err = -ENOENT;
1023 goto err_deregister_fixed_link;
1024 }
1025
1026 /* This driver only support 10/100Mbit speeds on Gen3
1027 * at this time.
1028 */
1029 if (priv->chip_id == RCAR_GEN3) {
1030 err = phy_set_max_speed(phydev, SPEED_100);
1031 if (err) {
1032 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1033 goto err_phy_disconnect;
1034 }
1035
1036 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1037 }
1038
1039 /* 10BASE is not supported */
1040 phydev->supported &= ~PHY_10BT_FEATURES;
1041
1042 phy_attached_info(phydev);
1043
1044 return 0;
1045
1046err_phy_disconnect:
1047 phy_disconnect(phydev);
1048err_deregister_fixed_link:
1049 if (of_phy_is_fixed_link(np))
1050 of_phy_deregister_fixed_link(np);
1051
1052 return err;
1053}
1054
1055/* PHY control start function */
1056static int ravb_phy_start(struct net_device *ndev)
1057{
1058 int error;
1059
1060 error = ravb_phy_init(ndev);
1061 if (error)
1062 return error;
1063
1064 phy_start(ndev->phydev);
1065
1066 return 0;
1067}
1068
1069static int ravb_get_link_ksettings(struct net_device *ndev,
1070 struct ethtool_link_ksettings *cmd)
1071{
1072 struct ravb_private *priv = netdev_priv(ndev);
1073 int error = -ENODEV;
1074 unsigned long flags;
1075
1076 if (ndev->phydev) {
1077 spin_lock_irqsave(&priv->lock, flags);
1078 error = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1079 spin_unlock_irqrestore(&priv->lock, flags);
1080 }
1081
1082 return error;
1083}
1084
1085static int ravb_set_link_ksettings(struct net_device *ndev,
1086 const struct ethtool_link_ksettings *cmd)
1087{
1088 struct ravb_private *priv = netdev_priv(ndev);
1089 unsigned long flags;
1090 int error;
1091
1092 if (!ndev->phydev)
1093 return -ENODEV;
1094
1095 spin_lock_irqsave(&priv->lock, flags);
1096
1097 /* Disable TX and RX */
1098 ravb_rcv_snd_disable(ndev);
1099
1100 error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1101 if (error)
1102 goto error_exit;
1103
1104 if (cmd->base.duplex == DUPLEX_FULL)
1105 priv->duplex = 1;
1106 else
1107 priv->duplex = 0;
1108
1109 ravb_set_duplex(ndev);
1110
1111error_exit:
1112 mdelay(1);
1113
1114 /* Enable TX and RX */
1115 ravb_rcv_snd_enable(ndev);
1116
1117 mmiowb();
1118 spin_unlock_irqrestore(&priv->lock, flags);
1119
1120 return error;
1121}
1122
1123static int ravb_nway_reset(struct net_device *ndev)
1124{
1125 struct ravb_private *priv = netdev_priv(ndev);
1126 int error = -ENODEV;
1127 unsigned long flags;
1128
1129 if (ndev->phydev) {
1130 spin_lock_irqsave(&priv->lock, flags);
1131 error = phy_start_aneg(ndev->phydev);
1132 spin_unlock_irqrestore(&priv->lock, flags);
1133 }
1134
1135 return error;
1136}
1137
1138static u32 ravb_get_msglevel(struct net_device *ndev)
1139{
1140 struct ravb_private *priv = netdev_priv(ndev);
1141
1142 return priv->msg_enable;
1143}
1144
1145static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1146{
1147 struct ravb_private *priv = netdev_priv(ndev);
1148
1149 priv->msg_enable = value;
1150}
1151
1152static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1153 "rx_queue_0_current",
1154 "tx_queue_0_current",
1155 "rx_queue_0_dirty",
1156 "tx_queue_0_dirty",
1157 "rx_queue_0_packets",
1158 "tx_queue_0_packets",
1159 "rx_queue_0_bytes",
1160 "tx_queue_0_bytes",
1161 "rx_queue_0_mcast_packets",
1162 "rx_queue_0_errors",
1163 "rx_queue_0_crc_errors",
1164 "rx_queue_0_frame_errors",
1165 "rx_queue_0_length_errors",
1166 "rx_queue_0_missed_errors",
1167 "rx_queue_0_over_errors",
1168
1169 "rx_queue_1_current",
1170 "tx_queue_1_current",
1171 "rx_queue_1_dirty",
1172 "tx_queue_1_dirty",
1173 "rx_queue_1_packets",
1174 "tx_queue_1_packets",
1175 "rx_queue_1_bytes",
1176 "tx_queue_1_bytes",
1177 "rx_queue_1_mcast_packets",
1178 "rx_queue_1_errors",
1179 "rx_queue_1_crc_errors",
1180 "rx_queue_1_frame_errors",
1181 "rx_queue_1_length_errors",
1182 "rx_queue_1_missed_errors",
1183 "rx_queue_1_over_errors",
1184};
1185
1186#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1187
1188static int ravb_get_sset_count(struct net_device *netdev, int sset)
1189{
1190 switch (sset) {
1191 case ETH_SS_STATS:
1192 return RAVB_STATS_LEN;
1193 default:
1194 return -EOPNOTSUPP;
1195 }
1196}
1197
1198static void ravb_get_ethtool_stats(struct net_device *ndev,
1199 struct ethtool_stats *stats, u64 *data)
1200{
1201 struct ravb_private *priv = netdev_priv(ndev);
1202 int i = 0;
1203 int q;
1204
1205 /* Device-specific stats */
1206 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1207 struct net_device_stats *stats = &priv->stats[q];
1208
1209 data[i++] = priv->cur_rx[q];
1210 data[i++] = priv->cur_tx[q];
1211 data[i++] = priv->dirty_rx[q];
1212 data[i++] = priv->dirty_tx[q];
1213 data[i++] = stats->rx_packets;
1214 data[i++] = stats->tx_packets;
1215 data[i++] = stats->rx_bytes;
1216 data[i++] = stats->tx_bytes;
1217 data[i++] = stats->multicast;
1218 data[i++] = stats->rx_errors;
1219 data[i++] = stats->rx_crc_errors;
1220 data[i++] = stats->rx_frame_errors;
1221 data[i++] = stats->rx_length_errors;
1222 data[i++] = stats->rx_missed_errors;
1223 data[i++] = stats->rx_over_errors;
1224 }
1225}
1226
1227static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1228{
1229 switch (stringset) {
1230 case ETH_SS_STATS:
1231 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1232 break;
1233 }
1234}
1235
1236static void ravb_get_ringparam(struct net_device *ndev,
1237 struct ethtool_ringparam *ring)
1238{
1239 struct ravb_private *priv = netdev_priv(ndev);
1240
1241 ring->rx_max_pending = BE_RX_RING_MAX;
1242 ring->tx_max_pending = BE_TX_RING_MAX;
1243 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1244 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1245}
1246
1247static int ravb_set_ringparam(struct net_device *ndev,
1248 struct ethtool_ringparam *ring)
1249{
1250 struct ravb_private *priv = netdev_priv(ndev);
1251 int error;
1252
1253 if (ring->tx_pending > BE_TX_RING_MAX ||
1254 ring->rx_pending > BE_RX_RING_MAX ||
1255 ring->tx_pending < BE_TX_RING_MIN ||
1256 ring->rx_pending < BE_RX_RING_MIN)
1257 return -EINVAL;
1258 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1259 return -EINVAL;
1260
1261 if (netif_running(ndev)) {
1262 netif_device_detach(ndev);
1263 /* Stop PTP Clock driver */
1264 if (priv->chip_id == RCAR_GEN2)
1265 ravb_ptp_stop(ndev);
1266 /* Wait for DMA stopping */
1267 error = ravb_stop_dma(ndev);
1268 if (error) {
1269 netdev_err(ndev,
1270 "cannot set ringparam! Any AVB processes are still running?\n");
1271 return error;
1272 }
1273 synchronize_irq(ndev->irq);
1274
1275 /* Free all the skb's in the RX queue and the DMA buffers. */
1276 ravb_ring_free(ndev, RAVB_BE);
1277 ravb_ring_free(ndev, RAVB_NC);
1278 }
1279
1280 /* Set new parameters */
1281 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1282 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1283
1284 if (netif_running(ndev)) {
1285 error = ravb_dmac_init(ndev);
1286 if (error) {
1287 netdev_err(ndev,
1288 "%s: ravb_dmac_init() failed, error %d\n",
1289 __func__, error);
1290 return error;
1291 }
1292
1293 ravb_emac_init(ndev);
1294
1295 /* Initialise PTP Clock driver */
1296 if (priv->chip_id == RCAR_GEN2)
1297 ravb_ptp_init(ndev, priv->pdev);
1298
1299 netif_device_attach(ndev);
1300 }
1301
1302 return 0;
1303}
1304
1305static int ravb_get_ts_info(struct net_device *ndev,
1306 struct ethtool_ts_info *info)
1307{
1308 struct ravb_private *priv = netdev_priv(ndev);
1309
1310 info->so_timestamping =
1311 SOF_TIMESTAMPING_TX_SOFTWARE |
1312 SOF_TIMESTAMPING_RX_SOFTWARE |
1313 SOF_TIMESTAMPING_SOFTWARE |
1314 SOF_TIMESTAMPING_TX_HARDWARE |
1315 SOF_TIMESTAMPING_RX_HARDWARE |
1316 SOF_TIMESTAMPING_RAW_HARDWARE;
1317 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1318 info->rx_filters =
1319 (1 << HWTSTAMP_FILTER_NONE) |
1320 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1321 (1 << HWTSTAMP_FILTER_ALL);
1322 info->phc_index = ptp_clock_index(priv->ptp.clock);
1323
1324 return 0;
1325}
1326
1327static const struct ethtool_ops ravb_ethtool_ops = {
1328 .nway_reset = ravb_nway_reset,
1329 .get_msglevel = ravb_get_msglevel,
1330 .set_msglevel = ravb_set_msglevel,
1331 .get_link = ethtool_op_get_link,
1332 .get_strings = ravb_get_strings,
1333 .get_ethtool_stats = ravb_get_ethtool_stats,
1334 .get_sset_count = ravb_get_sset_count,
1335 .get_ringparam = ravb_get_ringparam,
1336 .set_ringparam = ravb_set_ringparam,
1337 .get_ts_info = ravb_get_ts_info,
1338 .get_link_ksettings = ravb_get_link_ksettings,
1339 .set_link_ksettings = ravb_set_link_ksettings,
1340};
1341
1342static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1343 struct net_device *ndev, struct device *dev,
1344 const char *ch)
1345{
1346 char *name;
1347 int error;
1348
1349 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1350 if (!name)
1351 return -ENOMEM;
1352 error = request_irq(irq, handler, 0, name, ndev);
1353 if (error)
1354 netdev_err(ndev, "cannot request IRQ %s\n", name);
1355
1356 return error;
1357}
1358
1359/* Network device open function for Ethernet AVB */
1360static int ravb_open(struct net_device *ndev)
1361{
1362 struct ravb_private *priv = netdev_priv(ndev);
1363 struct platform_device *pdev = priv->pdev;
1364 struct device *dev = &pdev->dev;
1365 int error;
1366
1367 napi_enable(&priv->napi[RAVB_BE]);
1368 napi_enable(&priv->napi[RAVB_NC]);
1369
1370 if (priv->chip_id == RCAR_GEN2) {
1371 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1372 ndev->name, ndev);
1373 if (error) {
1374 netdev_err(ndev, "cannot request IRQ\n");
1375 goto out_napi_off;
1376 }
1377 } else {
1378 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1379 dev, "ch22:multi");
1380 if (error)
1381 goto out_napi_off;
1382 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1383 dev, "ch24:emac");
1384 if (error)
1385 goto out_free_irq;
1386 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1387 ndev, dev, "ch0:rx_be");
1388 if (error)
1389 goto out_free_irq_emac;
1390 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1391 ndev, dev, "ch18:tx_be");
1392 if (error)
1393 goto out_free_irq_be_rx;
1394 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1395 ndev, dev, "ch1:rx_nc");
1396 if (error)
1397 goto out_free_irq_be_tx;
1398 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1399 ndev, dev, "ch19:tx_nc");
1400 if (error)
1401 goto out_free_irq_nc_rx;
1402 }
1403
1404 /* Device init */
1405 error = ravb_dmac_init(ndev);
1406 if (error)
1407 goto out_free_irq_nc_tx;
1408 ravb_emac_init(ndev);
1409
1410 /* Initialise PTP Clock driver */
1411 if (priv->chip_id == RCAR_GEN2)
1412 ravb_ptp_init(ndev, priv->pdev);
1413
1414 netif_tx_start_all_queues(ndev);
1415
1416 /* PHY control start */
1417 error = ravb_phy_start(ndev);
1418 if (error)
1419 goto out_ptp_stop;
1420
1421 return 0;
1422
1423out_ptp_stop:
1424 /* Stop PTP Clock driver */
1425 if (priv->chip_id == RCAR_GEN2)
1426 ravb_ptp_stop(ndev);
1427out_free_irq_nc_tx:
1428 if (priv->chip_id == RCAR_GEN2)
1429 goto out_free_irq;
1430 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1431out_free_irq_nc_rx:
1432 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1433out_free_irq_be_tx:
1434 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1435out_free_irq_be_rx:
1436 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1437out_free_irq_emac:
1438 free_irq(priv->emac_irq, ndev);
1439out_free_irq:
1440 free_irq(ndev->irq, ndev);
1441out_napi_off:
1442 napi_disable(&priv->napi[RAVB_NC]);
1443 napi_disable(&priv->napi[RAVB_BE]);
1444 return error;
1445}
1446
1447/* Timeout function for Ethernet AVB */
1448static void ravb_tx_timeout(struct net_device *ndev)
1449{
1450 struct ravb_private *priv = netdev_priv(ndev);
1451
1452 netif_err(priv, tx_err, ndev,
1453 "transmit timed out, status %08x, resetting...\n",
1454 ravb_read(ndev, ISS));
1455
1456 /* tx_errors count up */
1457 ndev->stats.tx_errors++;
1458
1459 schedule_work(&priv->work);
1460}
1461
1462static void ravb_tx_timeout_work(struct work_struct *work)
1463{
1464 struct ravb_private *priv = container_of(work, struct ravb_private,
1465 work);
1466 struct net_device *ndev = priv->ndev;
1467
1468 netif_tx_stop_all_queues(ndev);
1469
1470 /* Stop PTP Clock driver */
1471 if (priv->chip_id == RCAR_GEN2)
1472 ravb_ptp_stop(ndev);
1473
1474 /* Wait for DMA stopping */
1475 ravb_stop_dma(ndev);
1476
1477 ravb_ring_free(ndev, RAVB_BE);
1478 ravb_ring_free(ndev, RAVB_NC);
1479
1480 /* Device init */
1481 ravb_dmac_init(ndev);
1482 ravb_emac_init(ndev);
1483
1484 /* Initialise PTP Clock driver */
1485 if (priv->chip_id == RCAR_GEN2)
1486 ravb_ptp_init(ndev, priv->pdev);
1487
1488 netif_tx_start_all_queues(ndev);
1489}
1490
1491/* Packet transmit function for Ethernet AVB */
1492static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1493{
1494 struct ravb_private *priv = netdev_priv(ndev);
1495 u16 q = skb_get_queue_mapping(skb);
1496 struct ravb_tstamp_skb *ts_skb;
1497 struct ravb_tx_desc *desc;
1498 unsigned long flags;
1499 u32 dma_addr;
1500 void *buffer;
1501 u32 entry;
1502 u32 len;
1503
1504 spin_lock_irqsave(&priv->lock, flags);
1505 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1506 NUM_TX_DESC) {
1507 netif_err(priv, tx_queued, ndev,
1508 "still transmitting with the full ring!\n");
1509 netif_stop_subqueue(ndev, q);
1510 spin_unlock_irqrestore(&priv->lock, flags);
1511 return NETDEV_TX_BUSY;
1512 }
1513 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1514 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1515
1516 if (skb_put_padto(skb, ETH_ZLEN))
1517 goto drop;
1518
1519 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1520 entry / NUM_TX_DESC * DPTR_ALIGN;
1521 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1522 /* Zero length DMA descriptors are problematic as they seem to
1523 * terminate DMA transfers. Avoid them by simply using a length of
1524 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1525 *
1526 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1527 * data by the call to skb_put_padto() above this is safe with
1528 * respect to both the length of the first DMA descriptor (len)
1529 * overflowing the available data and the length of the second DMA
1530 * descriptor (skb->len - len) being negative.
1531 */
1532 if (len == 0)
1533 len = DPTR_ALIGN;
1534
1535 memcpy(buffer, skb->data, len);
1536 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1537 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1538 goto drop;
1539
1540 desc = &priv->tx_ring[q][entry];
1541 desc->ds_tagl = cpu_to_le16(len);
1542 desc->dptr = cpu_to_le32(dma_addr);
1543
1544 buffer = skb->data + len;
1545 len = skb->len - len;
1546 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1547 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1548 goto unmap;
1549
1550 desc++;
1551 desc->ds_tagl = cpu_to_le16(len);
1552 desc->dptr = cpu_to_le32(dma_addr);
1553
1554 /* TX timestamp required */
1555 if (q == RAVB_NC) {
1556 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1557 if (!ts_skb) {
1558 desc--;
1559 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1560 DMA_TO_DEVICE);
1561 goto unmap;
1562 }
1563 ts_skb->skb = skb;
1564 ts_skb->tag = priv->ts_skb_tag++;
1565 priv->ts_skb_tag &= 0x3ff;
1566 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1567
1568 /* TAG and timestamp required flag */
1569 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1570 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1571 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1572 }
1573
1574 skb_tx_timestamp(skb);
1575 /* Descriptor type must be set after all the above writes */
1576 dma_wmb();
1577 desc->die_dt = DT_FEND;
1578 desc--;
1579 desc->die_dt = DT_FSTART;
1580
1581 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1582
1583 priv->cur_tx[q] += NUM_TX_DESC;
1584 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1585 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1586 !ravb_tx_free(ndev, q, true))
1587 netif_stop_subqueue(ndev, q);
1588
1589exit:
1590 mmiowb();
1591 spin_unlock_irqrestore(&priv->lock, flags);
1592 return NETDEV_TX_OK;
1593
1594unmap:
1595 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1596 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1597drop:
1598 dev_kfree_skb_any(skb);
1599 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1600 goto exit;
1601}
1602
1603static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1604 void *accel_priv, select_queue_fallback_t fallback)
1605{
1606 /* If skb needs TX timestamp, it is handled in network control queue */
1607 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1608 RAVB_BE;
1609
1610}
1611
1612static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1613{
1614 struct ravb_private *priv = netdev_priv(ndev);
1615 struct net_device_stats *nstats, *stats0, *stats1;
1616
1617 nstats = &ndev->stats;
1618 stats0 = &priv->stats[RAVB_BE];
1619 stats1 = &priv->stats[RAVB_NC];
1620
1621 nstats->tx_dropped += ravb_read(ndev, TROCR);
1622 ravb_write(ndev, 0, TROCR); /* (write clear) */
1623 nstats->collisions += ravb_read(ndev, CDCR);
1624 ravb_write(ndev, 0, CDCR); /* (write clear) */
1625 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1626 ravb_write(ndev, 0, LCCR); /* (write clear) */
1627
1628 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1629 ravb_write(ndev, 0, CERCR); /* (write clear) */
1630 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1631 ravb_write(ndev, 0, CEECR); /* (write clear) */
1632
1633 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1634 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1635 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1636 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1637 nstats->multicast = stats0->multicast + stats1->multicast;
1638 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1639 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1640 nstats->rx_frame_errors =
1641 stats0->rx_frame_errors + stats1->rx_frame_errors;
1642 nstats->rx_length_errors =
1643 stats0->rx_length_errors + stats1->rx_length_errors;
1644 nstats->rx_missed_errors =
1645 stats0->rx_missed_errors + stats1->rx_missed_errors;
1646 nstats->rx_over_errors =
1647 stats0->rx_over_errors + stats1->rx_over_errors;
1648
1649 return nstats;
1650}
1651
1652/* Update promiscuous bit */
1653static void ravb_set_rx_mode(struct net_device *ndev)
1654{
1655 struct ravb_private *priv = netdev_priv(ndev);
1656 unsigned long flags;
1657
1658 spin_lock_irqsave(&priv->lock, flags);
1659 ravb_modify(ndev, ECMR, ECMR_PRM,
1660 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1661 mmiowb();
1662 spin_unlock_irqrestore(&priv->lock, flags);
1663}
1664
1665/* Device close function for Ethernet AVB */
1666static int ravb_close(struct net_device *ndev)
1667{
1668 struct device_node *np = ndev->dev.parent->of_node;
1669 struct ravb_private *priv = netdev_priv(ndev);
1670 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1671
1672 netif_tx_stop_all_queues(ndev);
1673
1674 /* Disable interrupts by clearing the interrupt masks. */
1675 ravb_write(ndev, 0, RIC0);
1676 ravb_write(ndev, 0, RIC2);
1677 ravb_write(ndev, 0, TIC);
1678
1679 /* Stop PTP Clock driver */
1680 if (priv->chip_id == RCAR_GEN2)
1681 ravb_ptp_stop(ndev);
1682
1683 /* Set the config mode to stop the AVB-DMAC's processes */
1684 if (ravb_stop_dma(ndev) < 0)
1685 netdev_err(ndev,
1686 "device will be stopped after h/w processes are done.\n");
1687
1688 /* Clear the timestamp list */
1689 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1690 list_del(&ts_skb->list);
1691 kfree(ts_skb);
1692 }
1693
1694 /* PHY disconnect */
1695 if (ndev->phydev) {
1696 phy_stop(ndev->phydev);
1697 phy_disconnect(ndev->phydev);
1698 if (of_phy_is_fixed_link(np))
1699 of_phy_deregister_fixed_link(np);
1700 }
1701
1702 if (priv->chip_id != RCAR_GEN2) {
1703 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1704 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1705 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1706 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1707 free_irq(priv->emac_irq, ndev);
1708 }
1709 free_irq(ndev->irq, ndev);
1710
1711 napi_disable(&priv->napi[RAVB_NC]);
1712 napi_disable(&priv->napi[RAVB_BE]);
1713
1714 /* Free all the skb's in the RX queue and the DMA buffers. */
1715 ravb_ring_free(ndev, RAVB_BE);
1716 ravb_ring_free(ndev, RAVB_NC);
1717
1718 return 0;
1719}
1720
1721static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1722{
1723 struct ravb_private *priv = netdev_priv(ndev);
1724 struct hwtstamp_config config;
1725
1726 config.flags = 0;
1727 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1728 HWTSTAMP_TX_OFF;
1729 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1730 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1731 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1732 config.rx_filter = HWTSTAMP_FILTER_ALL;
1733 else
1734 config.rx_filter = HWTSTAMP_FILTER_NONE;
1735
1736 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1737 -EFAULT : 0;
1738}
1739
1740/* Control hardware time stamping */
1741static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1742{
1743 struct ravb_private *priv = netdev_priv(ndev);
1744 struct hwtstamp_config config;
1745 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1746 u32 tstamp_tx_ctrl;
1747
1748 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1749 return -EFAULT;
1750
1751 /* Reserved for future extensions */
1752 if (config.flags)
1753 return -EINVAL;
1754
1755 switch (config.tx_type) {
1756 case HWTSTAMP_TX_OFF:
1757 tstamp_tx_ctrl = 0;
1758 break;
1759 case HWTSTAMP_TX_ON:
1760 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1761 break;
1762 default:
1763 return -ERANGE;
1764 }
1765
1766 switch (config.rx_filter) {
1767 case HWTSTAMP_FILTER_NONE:
1768 tstamp_rx_ctrl = 0;
1769 break;
1770 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1771 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1772 break;
1773 default:
1774 config.rx_filter = HWTSTAMP_FILTER_ALL;
1775 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1776 }
1777
1778 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1779 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1780
1781 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1782 -EFAULT : 0;
1783}
1784
1785/* ioctl to device function */
1786static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1787{
1788 struct phy_device *phydev = ndev->phydev;
1789
1790 if (!netif_running(ndev))
1791 return -EINVAL;
1792
1793 if (!phydev)
1794 return -ENODEV;
1795
1796 switch (cmd) {
1797 case SIOCGHWTSTAMP:
1798 return ravb_hwtstamp_get(ndev, req);
1799 case SIOCSHWTSTAMP:
1800 return ravb_hwtstamp_set(ndev, req);
1801 }
1802
1803 return phy_mii_ioctl(phydev, req, cmd);
1804}
1805
1806static const struct net_device_ops ravb_netdev_ops = {
1807 .ndo_open = ravb_open,
1808 .ndo_stop = ravb_close,
1809 .ndo_start_xmit = ravb_start_xmit,
1810 .ndo_select_queue = ravb_select_queue,
1811 .ndo_get_stats = ravb_get_stats,
1812 .ndo_set_rx_mode = ravb_set_rx_mode,
1813 .ndo_tx_timeout = ravb_tx_timeout,
1814 .ndo_do_ioctl = ravb_do_ioctl,
1815 .ndo_validate_addr = eth_validate_addr,
1816 .ndo_set_mac_address = eth_mac_addr,
1817};
1818
1819/* MDIO bus init function */
1820static int ravb_mdio_init(struct ravb_private *priv)
1821{
1822 struct platform_device *pdev = priv->pdev;
1823 struct device *dev = &pdev->dev;
1824 int error;
1825
1826 /* Bitbang init */
1827 priv->mdiobb.ops = &bb_ops;
1828
1829 /* MII controller setting */
1830 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1831 if (!priv->mii_bus)
1832 return -ENOMEM;
1833
1834 /* Hook up MII support for ethtool */
1835 priv->mii_bus->name = "ravb_mii";
1836 priv->mii_bus->parent = dev;
1837 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1838 pdev->name, pdev->id);
1839
1840 /* Register MDIO bus */
1841 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1842 if (error)
1843 goto out_free_bus;
1844
1845 return 0;
1846
1847out_free_bus:
1848 free_mdio_bitbang(priv->mii_bus);
1849 return error;
1850}
1851
1852/* MDIO bus release function */
1853static int ravb_mdio_release(struct ravb_private *priv)
1854{
1855 /* Unregister mdio bus */
1856 mdiobus_unregister(priv->mii_bus);
1857
1858 /* Free bitbang info */
1859 free_mdio_bitbang(priv->mii_bus);
1860
1861 return 0;
1862}
1863
1864static const struct of_device_id ravb_match_table[] = {
1865 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1866 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1867 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1868 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1869 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1870 { }
1871};
1872MODULE_DEVICE_TABLE(of, ravb_match_table);
1873
1874static int ravb_set_gti(struct net_device *ndev)
1875{
1876
1877 struct device *dev = ndev->dev.parent;
1878 struct device_node *np = dev->of_node;
1879 unsigned long rate;
1880 struct clk *clk;
1881 uint64_t inc;
1882
1883 clk = of_clk_get(np, 0);
1884 if (IS_ERR(clk)) {
1885 dev_err(dev, "could not get clock\n");
1886 return PTR_ERR(clk);
1887 }
1888
1889 rate = clk_get_rate(clk);
1890 clk_put(clk);
1891
1892 if (!rate)
1893 return -EINVAL;
1894
1895 inc = 1000000000ULL << 20;
1896 do_div(inc, rate);
1897
1898 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1899 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1900 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1901 return -EINVAL;
1902 }
1903
1904 ravb_write(ndev, inc, GTI);
1905
1906 return 0;
1907}
1908
1909static void ravb_set_config_mode(struct net_device *ndev)
1910{
1911 struct ravb_private *priv = netdev_priv(ndev);
1912
1913 if (priv->chip_id == RCAR_GEN2) {
1914 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1915 /* Set CSEL value */
1916 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1917 } else {
1918 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1919 CCC_GAC | CCC_CSEL_HPB);
1920 }
1921}
1922
1923static int ravb_probe(struct platform_device *pdev)
1924{
1925 struct device_node *np = pdev->dev.of_node;
1926 struct ravb_private *priv;
1927 enum ravb_chip_id chip_id;
1928 struct net_device *ndev;
1929 int error, irq, q;
1930 struct resource *res;
1931 int i;
1932
1933 if (!np) {
1934 dev_err(&pdev->dev,
1935 "this driver is required to be instantiated from device tree\n");
1936 return -EINVAL;
1937 }
1938
1939 /* Get base address */
1940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1941 if (!res) {
1942 dev_err(&pdev->dev, "invalid resource\n");
1943 return -EINVAL;
1944 }
1945
1946 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1947 NUM_TX_QUEUE, NUM_RX_QUEUE);
1948 if (!ndev)
1949 return -ENOMEM;
1950
1951 pm_runtime_enable(&pdev->dev);
1952 pm_runtime_get_sync(&pdev->dev);
1953
1954 /* The Ether-specific entries in the device structure. */
1955 ndev->base_addr = res->start;
1956
1957 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1958
1959 if (chip_id == RCAR_GEN3)
1960 irq = platform_get_irq_byname(pdev, "ch22");
1961 else
1962 irq = platform_get_irq(pdev, 0);
1963 if (irq < 0) {
1964 error = irq;
1965 goto out_release;
1966 }
1967 ndev->irq = irq;
1968
1969 SET_NETDEV_DEV(ndev, &pdev->dev);
1970
1971 priv = netdev_priv(ndev);
1972 priv->ndev = ndev;
1973 priv->pdev = pdev;
1974 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1975 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1976 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1977 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1978 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1979 if (IS_ERR(priv->addr)) {
1980 error = PTR_ERR(priv->addr);
1981 goto out_release;
1982 }
1983
1984 spin_lock_init(&priv->lock);
1985 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1986
1987 priv->phy_interface = of_get_phy_mode(np);
1988
1989 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1990 priv->avb_link_active_low =
1991 of_property_read_bool(np, "renesas,ether-link-active-low");
1992
1993 if (chip_id == RCAR_GEN3) {
1994 irq = platform_get_irq_byname(pdev, "ch24");
1995 if (irq < 0) {
1996 error = irq;
1997 goto out_release;
1998 }
1999 priv->emac_irq = irq;
2000 for (i = 0; i < NUM_RX_QUEUE; i++) {
2001 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2002 if (irq < 0) {
2003 error = irq;
2004 goto out_release;
2005 }
2006 priv->rx_irqs[i] = irq;
2007 }
2008 for (i = 0; i < NUM_TX_QUEUE; i++) {
2009 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2010 if (irq < 0) {
2011 error = irq;
2012 goto out_release;
2013 }
2014 priv->tx_irqs[i] = irq;
2015 }
2016 }
2017
2018 priv->chip_id = chip_id;
2019
2020 /* Set function */
2021 ndev->netdev_ops = &ravb_netdev_ops;
2022 ndev->ethtool_ops = &ravb_ethtool_ops;
2023
2024 /* Set AVB config mode */
2025 ravb_set_config_mode(ndev);
2026
2027 /* Set GTI value */
2028 error = ravb_set_gti(ndev);
2029 if (error)
2030 goto out_release;
2031
2032 /* Request GTI loading */
2033 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2034
2035 /* Allocate descriptor base address table */
2036 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2037 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2038 &priv->desc_bat_dma, GFP_KERNEL);
2039 if (!priv->desc_bat) {
2040 dev_err(&pdev->dev,
2041 "Cannot allocate desc base address table (size %d bytes)\n",
2042 priv->desc_bat_size);
2043 error = -ENOMEM;
2044 goto out_release;
2045 }
2046 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2047 priv->desc_bat[q].die_dt = DT_EOS;
2048 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2049
2050 /* Initialise HW timestamp list */
2051 INIT_LIST_HEAD(&priv->ts_skb_list);
2052
2053 /* Initialise PTP Clock driver */
2054 if (chip_id != RCAR_GEN2)
2055 ravb_ptp_init(ndev, pdev);
2056
2057 /* Debug message level */
2058 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2059
2060 /* Read and set MAC address */
2061 ravb_read_mac_address(ndev, of_get_mac_address(np));
2062 if (!is_valid_ether_addr(ndev->dev_addr)) {
2063 dev_warn(&pdev->dev,
2064 "no valid MAC address supplied, using a random one\n");
2065 eth_hw_addr_random(ndev);
2066 }
2067
2068 /* MDIO bus init */
2069 error = ravb_mdio_init(priv);
2070 if (error) {
2071 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2072 goto out_dma_free;
2073 }
2074
2075 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2076 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2077
2078 /* Network device register */
2079 error = register_netdev(ndev);
2080 if (error)
2081 goto out_napi_del;
2082
2083 /* Print device information */
2084 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2085 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2086
2087 platform_set_drvdata(pdev, ndev);
2088
2089 return 0;
2090
2091out_napi_del:
2092 netif_napi_del(&priv->napi[RAVB_NC]);
2093 netif_napi_del(&priv->napi[RAVB_BE]);
2094 ravb_mdio_release(priv);
2095out_dma_free:
2096 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2097 priv->desc_bat_dma);
2098
2099 /* Stop PTP Clock driver */
2100 if (chip_id != RCAR_GEN2)
2101 ravb_ptp_stop(ndev);
2102out_release:
2103 if (ndev)
2104 free_netdev(ndev);
2105
2106 pm_runtime_put(&pdev->dev);
2107 pm_runtime_disable(&pdev->dev);
2108 return error;
2109}
2110
2111static int ravb_remove(struct platform_device *pdev)
2112{
2113 struct net_device *ndev = platform_get_drvdata(pdev);
2114 struct ravb_private *priv = netdev_priv(ndev);
2115
2116 /* Stop PTP Clock driver */
2117 if (priv->chip_id != RCAR_GEN2)
2118 ravb_ptp_stop(ndev);
2119
2120 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2121 priv->desc_bat_dma);
2122 /* Set reset mode */
2123 ravb_write(ndev, CCC_OPC_RESET, CCC);
2124 pm_runtime_put_sync(&pdev->dev);
2125 unregister_netdev(ndev);
2126 netif_napi_del(&priv->napi[RAVB_NC]);
2127 netif_napi_del(&priv->napi[RAVB_BE]);
2128 ravb_mdio_release(priv);
2129 pm_runtime_disable(&pdev->dev);
2130 free_netdev(ndev);
2131 platform_set_drvdata(pdev, NULL);
2132
2133 return 0;
2134}
2135
2136static int __maybe_unused ravb_suspend(struct device *dev)
2137{
2138 struct net_device *ndev = dev_get_drvdata(dev);
2139 int ret = 0;
2140
2141 if (netif_running(ndev)) {
2142 netif_device_detach(ndev);
2143 ret = ravb_close(ndev);
2144 }
2145
2146 return ret;
2147}
2148
2149static int __maybe_unused ravb_resume(struct device *dev)
2150{
2151 struct net_device *ndev = dev_get_drvdata(dev);
2152 struct ravb_private *priv = netdev_priv(ndev);
2153 int ret = 0;
2154
2155 /* All register have been reset to default values.
2156 * Restore all registers which where setup at probe time and
2157 * reopen device if it was running before system suspended.
2158 */
2159
2160 /* Set AVB config mode */
2161 ravb_set_config_mode(ndev);
2162
2163 /* Set GTI value */
2164 ret = ravb_set_gti(ndev);
2165 if (ret)
2166 return ret;
2167
2168 /* Request GTI loading */
2169 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2170
2171 /* Restore descriptor base address table */
2172 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2173
2174 if (netif_running(ndev)) {
2175 ret = ravb_open(ndev);
2176 if (ret < 0)
2177 return ret;
2178 netif_device_attach(ndev);
2179 }
2180
2181 return ret;
2182}
2183
2184static int __maybe_unused ravb_runtime_nop(struct device *dev)
2185{
2186 /* Runtime PM callback shared between ->runtime_suspend()
2187 * and ->runtime_resume(). Simply returns success.
2188 *
2189 * This driver re-initializes all registers after
2190 * pm_runtime_get_sync() anyway so there is no need
2191 * to save and restore registers here.
2192 */
2193 return 0;
2194}
2195
2196static const struct dev_pm_ops ravb_dev_pm_ops = {
2197 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2198 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2199};
2200
2201static struct platform_driver ravb_driver = {
2202 .probe = ravb_probe,
2203 .remove = ravb_remove,
2204 .driver = {
2205 .name = "ravb",
2206 .pm = &ravb_dev_pm_ops,
2207 .of_match_table = ravb_match_table,
2208 },
2209};
2210
2211module_platform_driver(ravb_driver);
2212
2213MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2214MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2215MODULE_LICENSE("GPL v2");