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1// SPDX-License-Identifier: GPL-2.0
2/* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11#include <linux/cache.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/err.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_vlan.h>
19#include <linux/kernel.h>
20#include <linux/list.h>
21#include <linux/module.h>
22#include <linux/net_tstamp.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/of_irq.h>
26#include <linux/of_mdio.h>
27#include <linux/of_net.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/spinlock.h>
31#include <linux/sys_soc.h>
32
33#include <asm/div64.h>
34
35#include "ravb.h"
36
37#define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46};
47
48static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51};
52
53void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55{
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57}
58
59int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60{
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69}
70
71static int ravb_config(struct net_device *ndev)
72{
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83}
84
85static void ravb_set_rate(struct net_device *ndev)
86{
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97}
98
99static void ravb_set_buffer_align(struct sk_buff *skb)
100{
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105}
106
107/* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
112static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
113{
114 if (!IS_ERR(mac)) {
115 ether_addr_copy(ndev->dev_addr, mac);
116 } else {
117 u32 mahr = ravb_read(ndev, MAHR);
118 u32 malr = ravb_read(ndev, MALR);
119
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
124 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
125 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
126 }
127}
128
129static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
130{
131 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
132 mdiobb);
133
134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
135}
136
137/* MDC pin control */
138static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
139{
140 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
141}
142
143/* Data I/O pin control */
144static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
145{
146 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
147}
148
149/* Set data bit */
150static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
151{
152 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
153}
154
155/* Get data bit */
156static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
157{
158 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
159 mdiobb);
160
161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
162}
163
164/* MDIO bus control struct */
165static struct mdiobb_ops bb_ops = {
166 .owner = THIS_MODULE,
167 .set_mdc = ravb_set_mdc,
168 .set_mdio_dir = ravb_set_mdio_dir,
169 .set_mdio_data = ravb_set_mdio_data,
170 .get_mdio_data = ravb_get_mdio_data,
171};
172
173/* Free TX skb function for AVB-IP */
174static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
175{
176 struct ravb_private *priv = netdev_priv(ndev);
177 struct net_device_stats *stats = &priv->stats[q];
178 int num_tx_desc = priv->num_tx_desc;
179 struct ravb_tx_desc *desc;
180 int free_num = 0;
181 int entry;
182 u32 size;
183
184 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
185 bool txed;
186
187 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
188 num_tx_desc);
189 desc = &priv->tx_ring[q][entry];
190 txed = desc->die_dt == DT_FEMPTY;
191 if (free_txed_only && !txed)
192 break;
193 /* Descriptor type must be checked before all other reads */
194 dma_rmb();
195 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
196 /* Free the original skb. */
197 if (priv->tx_skb[q][entry / num_tx_desc]) {
198 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
199 size, DMA_TO_DEVICE);
200 /* Last packet descriptor? */
201 if (entry % num_tx_desc == num_tx_desc - 1) {
202 entry /= num_tx_desc;
203 dev_kfree_skb_any(priv->tx_skb[q][entry]);
204 priv->tx_skb[q][entry] = NULL;
205 if (txed)
206 stats->tx_packets++;
207 }
208 free_num++;
209 }
210 if (txed)
211 stats->tx_bytes += size;
212 desc->die_dt = DT_EEMPTY;
213 }
214 return free_num;
215}
216
217/* Free skb's and DMA buffers for Ethernet AVB */
218static void ravb_ring_free(struct net_device *ndev, int q)
219{
220 struct ravb_private *priv = netdev_priv(ndev);
221 int num_tx_desc = priv->num_tx_desc;
222 int ring_size;
223 int i;
224
225 if (priv->rx_ring[q]) {
226 for (i = 0; i < priv->num_rx_ring[q]; i++) {
227 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
228
229 if (!dma_mapping_error(ndev->dev.parent,
230 le32_to_cpu(desc->dptr)))
231 dma_unmap_single(ndev->dev.parent,
232 le32_to_cpu(desc->dptr),
233 RX_BUF_SZ,
234 DMA_FROM_DEVICE);
235 }
236 ring_size = sizeof(struct ravb_ex_rx_desc) *
237 (priv->num_rx_ring[q] + 1);
238 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
239 priv->rx_desc_dma[q]);
240 priv->rx_ring[q] = NULL;
241 }
242
243 if (priv->tx_ring[q]) {
244 ravb_tx_free(ndev, q, false);
245
246 ring_size = sizeof(struct ravb_tx_desc) *
247 (priv->num_tx_ring[q] * num_tx_desc + 1);
248 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
249 priv->tx_desc_dma[q]);
250 priv->tx_ring[q] = NULL;
251 }
252
253 /* Free RX skb ringbuffer */
254 if (priv->rx_skb[q]) {
255 for (i = 0; i < priv->num_rx_ring[q]; i++)
256 dev_kfree_skb(priv->rx_skb[q][i]);
257 }
258 kfree(priv->rx_skb[q]);
259 priv->rx_skb[q] = NULL;
260
261 /* Free aligned TX buffers */
262 kfree(priv->tx_align[q]);
263 priv->tx_align[q] = NULL;
264
265 /* Free TX skb ringbuffer.
266 * SKBs are freed by ravb_tx_free() call above.
267 */
268 kfree(priv->tx_skb[q]);
269 priv->tx_skb[q] = NULL;
270}
271
272/* Format skb and descriptor buffer for Ethernet AVB */
273static void ravb_ring_format(struct net_device *ndev, int q)
274{
275 struct ravb_private *priv = netdev_priv(ndev);
276 int num_tx_desc = priv->num_tx_desc;
277 struct ravb_ex_rx_desc *rx_desc;
278 struct ravb_tx_desc *tx_desc;
279 struct ravb_desc *desc;
280 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
281 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
282 num_tx_desc;
283 dma_addr_t dma_addr;
284 int i;
285
286 priv->cur_rx[q] = 0;
287 priv->cur_tx[q] = 0;
288 priv->dirty_rx[q] = 0;
289 priv->dirty_tx[q] = 0;
290
291 memset(priv->rx_ring[q], 0, rx_ring_size);
292 /* Build RX ring buffer */
293 for (i = 0; i < priv->num_rx_ring[q]; i++) {
294 /* RX descriptor */
295 rx_desc = &priv->rx_ring[q][i];
296 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
297 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
298 RX_BUF_SZ,
299 DMA_FROM_DEVICE);
300 /* We just set the data size to 0 for a failed mapping which
301 * should prevent DMA from happening...
302 */
303 if (dma_mapping_error(ndev->dev.parent, dma_addr))
304 rx_desc->ds_cc = cpu_to_le16(0);
305 rx_desc->dptr = cpu_to_le32(dma_addr);
306 rx_desc->die_dt = DT_FEMPTY;
307 }
308 rx_desc = &priv->rx_ring[q][i];
309 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
310 rx_desc->die_dt = DT_LINKFIX; /* type */
311
312 memset(priv->tx_ring[q], 0, tx_ring_size);
313 /* Build TX ring buffer */
314 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
315 i++, tx_desc++) {
316 tx_desc->die_dt = DT_EEMPTY;
317 if (num_tx_desc > 1) {
318 tx_desc++;
319 tx_desc->die_dt = DT_EEMPTY;
320 }
321 }
322 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
323 tx_desc->die_dt = DT_LINKFIX; /* type */
324
325 /* RX descriptor base address for best effort */
326 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
327 desc->die_dt = DT_LINKFIX; /* type */
328 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
329
330 /* TX descriptor base address for best effort */
331 desc = &priv->desc_bat[q];
332 desc->die_dt = DT_LINKFIX; /* type */
333 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
334}
335
336/* Init skb and descriptor buffer for Ethernet AVB */
337static int ravb_ring_init(struct net_device *ndev, int q)
338{
339 struct ravb_private *priv = netdev_priv(ndev);
340 int num_tx_desc = priv->num_tx_desc;
341 struct sk_buff *skb;
342 int ring_size;
343 int i;
344
345 /* Allocate RX and TX skb rings */
346 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
347 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
348 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
349 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
350 if (!priv->rx_skb[q] || !priv->tx_skb[q])
351 goto error;
352
353 for (i = 0; i < priv->num_rx_ring[q]; i++) {
354 skb = netdev_alloc_skb(ndev, RX_BUF_SZ + RAVB_ALIGN - 1);
355 if (!skb)
356 goto error;
357 ravb_set_buffer_align(skb);
358 priv->rx_skb[q][i] = skb;
359 }
360
361 if (num_tx_desc > 1) {
362 /* Allocate rings for the aligned buffers */
363 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
364 DPTR_ALIGN - 1, GFP_KERNEL);
365 if (!priv->tx_align[q])
366 goto error;
367 }
368
369 /* Allocate all RX descriptors. */
370 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
371 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
372 &priv->rx_desc_dma[q],
373 GFP_KERNEL);
374 if (!priv->rx_ring[q])
375 goto error;
376
377 priv->dirty_rx[q] = 0;
378
379 /* Allocate all TX descriptors. */
380 ring_size = sizeof(struct ravb_tx_desc) *
381 (priv->num_tx_ring[q] * num_tx_desc + 1);
382 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
383 &priv->tx_desc_dma[q],
384 GFP_KERNEL);
385 if (!priv->tx_ring[q])
386 goto error;
387
388 return 0;
389
390error:
391 ravb_ring_free(ndev, q);
392
393 return -ENOMEM;
394}
395
396/* E-MAC init function */
397static void ravb_emac_init(struct net_device *ndev)
398{
399 /* Receive frame limit set register */
400 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
401
402 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
403 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
404 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
405 ECMR_TE | ECMR_RE, ECMR);
406
407 ravb_set_rate(ndev);
408
409 /* Set MAC address */
410 ravb_write(ndev,
411 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
412 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
413 ravb_write(ndev,
414 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
415
416 /* E-MAC status register clear */
417 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
418
419 /* E-MAC interrupt enable register */
420 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
421}
422
423/* Device init function for Ethernet AVB */
424static int ravb_dmac_init(struct net_device *ndev)
425{
426 struct ravb_private *priv = netdev_priv(ndev);
427 int error;
428
429 /* Set CONFIG mode */
430 error = ravb_config(ndev);
431 if (error)
432 return error;
433
434 error = ravb_ring_init(ndev, RAVB_BE);
435 if (error)
436 return error;
437 error = ravb_ring_init(ndev, RAVB_NC);
438 if (error) {
439 ravb_ring_free(ndev, RAVB_BE);
440 return error;
441 }
442
443 /* Descriptor format */
444 ravb_ring_format(ndev, RAVB_BE);
445 ravb_ring_format(ndev, RAVB_NC);
446
447 /* Set AVB RX */
448 ravb_write(ndev,
449 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
450
451 /* Set FIFO size */
452 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
453
454 /* Timestamp enable */
455 ravb_write(ndev, TCCR_TFEN, TCCR);
456
457 /* Interrupt init: */
458 if (priv->chip_id == RCAR_GEN3) {
459 /* Clear DIL.DPLx */
460 ravb_write(ndev, 0, DIL);
461 /* Set queue specific interrupt */
462 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
463 }
464 /* Frame receive */
465 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
466 /* Disable FIFO full warning */
467 ravb_write(ndev, 0, RIC1);
468 /* Receive FIFO full error, descriptor empty */
469 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
470 /* Frame transmitted, timestamp FIFO updated */
471 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
472
473 /* Setting the control will start the AVB-DMAC process. */
474 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
475
476 return 0;
477}
478
479static void ravb_get_tx_tstamp(struct net_device *ndev)
480{
481 struct ravb_private *priv = netdev_priv(ndev);
482 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
483 struct skb_shared_hwtstamps shhwtstamps;
484 struct sk_buff *skb;
485 struct timespec64 ts;
486 u16 tag, tfa_tag;
487 int count;
488 u32 tfa2;
489
490 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
491 while (count--) {
492 tfa2 = ravb_read(ndev, TFA2);
493 tfa_tag = (tfa2 & TFA2_TST) >> 16;
494 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
495 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
496 ravb_read(ndev, TFA1);
497 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
498 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
499 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
500 list) {
501 skb = ts_skb->skb;
502 tag = ts_skb->tag;
503 list_del(&ts_skb->list);
504 kfree(ts_skb);
505 if (tag == tfa_tag) {
506 skb_tstamp_tx(skb, &shhwtstamps);
507 dev_consume_skb_any(skb);
508 break;
509 } else {
510 dev_kfree_skb_any(skb);
511 }
512 }
513 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
514 }
515}
516
517static void ravb_rx_csum(struct sk_buff *skb)
518{
519 u8 *hw_csum;
520
521 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
522 * appended to packet data
523 */
524 if (unlikely(skb->len < sizeof(__sum16)))
525 return;
526 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
527 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
528 skb->ip_summed = CHECKSUM_COMPLETE;
529 skb_trim(skb, skb->len - sizeof(__sum16));
530}
531
532/* Packet receive function for Ethernet AVB */
533static bool ravb_rx(struct net_device *ndev, int *quota, int q)
534{
535 struct ravb_private *priv = netdev_priv(ndev);
536 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
537 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
538 priv->cur_rx[q];
539 struct net_device_stats *stats = &priv->stats[q];
540 struct ravb_ex_rx_desc *desc;
541 struct sk_buff *skb;
542 dma_addr_t dma_addr;
543 struct timespec64 ts;
544 u8 desc_status;
545 u16 pkt_len;
546 int limit;
547
548 boguscnt = min(boguscnt, *quota);
549 limit = boguscnt;
550 desc = &priv->rx_ring[q][entry];
551 while (desc->die_dt != DT_FEMPTY) {
552 /* Descriptor type must be checked before all other reads */
553 dma_rmb();
554 desc_status = desc->msc;
555 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
556
557 if (--boguscnt < 0)
558 break;
559
560 /* We use 0-byte descriptors to mark the DMA mapping errors */
561 if (!pkt_len)
562 continue;
563
564 if (desc_status & MSC_MC)
565 stats->multicast++;
566
567 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
568 MSC_CEEF)) {
569 stats->rx_errors++;
570 if (desc_status & MSC_CRC)
571 stats->rx_crc_errors++;
572 if (desc_status & MSC_RFE)
573 stats->rx_frame_errors++;
574 if (desc_status & (MSC_RTLF | MSC_RTSF))
575 stats->rx_length_errors++;
576 if (desc_status & MSC_CEEF)
577 stats->rx_missed_errors++;
578 } else {
579 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
580
581 skb = priv->rx_skb[q][entry];
582 priv->rx_skb[q][entry] = NULL;
583 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
584 RX_BUF_SZ,
585 DMA_FROM_DEVICE);
586 get_ts &= (q == RAVB_NC) ?
587 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
588 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
589 if (get_ts) {
590 struct skb_shared_hwtstamps *shhwtstamps;
591
592 shhwtstamps = skb_hwtstamps(skb);
593 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
594 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
595 32) | le32_to_cpu(desc->ts_sl);
596 ts.tv_nsec = le32_to_cpu(desc->ts_n);
597 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
598 }
599
600 skb_put(skb, pkt_len);
601 skb->protocol = eth_type_trans(skb, ndev);
602 if (ndev->features & NETIF_F_RXCSUM)
603 ravb_rx_csum(skb);
604 napi_gro_receive(&priv->napi[q], skb);
605 stats->rx_packets++;
606 stats->rx_bytes += pkt_len;
607 }
608
609 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
610 desc = &priv->rx_ring[q][entry];
611 }
612
613 /* Refill the RX ring buffers. */
614 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
615 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
616 desc = &priv->rx_ring[q][entry];
617 desc->ds_cc = cpu_to_le16(RX_BUF_SZ);
618
619 if (!priv->rx_skb[q][entry]) {
620 skb = netdev_alloc_skb(ndev,
621 RX_BUF_SZ +
622 RAVB_ALIGN - 1);
623 if (!skb)
624 break; /* Better luck next round. */
625 ravb_set_buffer_align(skb);
626 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
627 le16_to_cpu(desc->ds_cc),
628 DMA_FROM_DEVICE);
629 skb_checksum_none_assert(skb);
630 /* We just set the data size to 0 for a failed mapping
631 * which should prevent DMA from happening...
632 */
633 if (dma_mapping_error(ndev->dev.parent, dma_addr))
634 desc->ds_cc = cpu_to_le16(0);
635 desc->dptr = cpu_to_le32(dma_addr);
636 priv->rx_skb[q][entry] = skb;
637 }
638 /* Descriptor type must be set after all the above writes */
639 dma_wmb();
640 desc->die_dt = DT_FEMPTY;
641 }
642
643 *quota -= limit - (++boguscnt);
644
645 return boguscnt <= 0;
646}
647
648static void ravb_rcv_snd_disable(struct net_device *ndev)
649{
650 /* Disable TX and RX */
651 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
652}
653
654static void ravb_rcv_snd_enable(struct net_device *ndev)
655{
656 /* Enable TX and RX */
657 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
658}
659
660/* function for waiting dma process finished */
661static int ravb_stop_dma(struct net_device *ndev)
662{
663 int error;
664
665 /* Wait for stopping the hardware TX process */
666 error = ravb_wait(ndev, TCCR,
667 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
668 if (error)
669 return error;
670
671 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
672 0);
673 if (error)
674 return error;
675
676 /* Stop the E-MAC's RX/TX processes. */
677 ravb_rcv_snd_disable(ndev);
678
679 /* Wait for stopping the RX DMA process */
680 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
681 if (error)
682 return error;
683
684 /* Stop AVB-DMAC process */
685 return ravb_config(ndev);
686}
687
688/* E-MAC interrupt handler */
689static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
690{
691 struct ravb_private *priv = netdev_priv(ndev);
692 u32 ecsr, psr;
693
694 ecsr = ravb_read(ndev, ECSR);
695 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
696
697 if (ecsr & ECSR_MPD)
698 pm_wakeup_event(&priv->pdev->dev, 0);
699 if (ecsr & ECSR_ICD)
700 ndev->stats.tx_carrier_errors++;
701 if (ecsr & ECSR_LCHNG) {
702 /* Link changed */
703 if (priv->no_avb_link)
704 return;
705 psr = ravb_read(ndev, PSR);
706 if (priv->avb_link_active_low)
707 psr ^= PSR_LMON;
708 if (!(psr & PSR_LMON)) {
709 /* DIsable RX and TX */
710 ravb_rcv_snd_disable(ndev);
711 } else {
712 /* Enable RX and TX */
713 ravb_rcv_snd_enable(ndev);
714 }
715 }
716}
717
718static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
719{
720 struct net_device *ndev = dev_id;
721 struct ravb_private *priv = netdev_priv(ndev);
722
723 spin_lock(&priv->lock);
724 ravb_emac_interrupt_unlocked(ndev);
725 spin_unlock(&priv->lock);
726 return IRQ_HANDLED;
727}
728
729/* Error interrupt handler */
730static void ravb_error_interrupt(struct net_device *ndev)
731{
732 struct ravb_private *priv = netdev_priv(ndev);
733 u32 eis, ris2;
734
735 eis = ravb_read(ndev, EIS);
736 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
737 if (eis & EIS_QFS) {
738 ris2 = ravb_read(ndev, RIS2);
739 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
740 RIS2);
741
742 /* Receive Descriptor Empty int */
743 if (ris2 & RIS2_QFF0)
744 priv->stats[RAVB_BE].rx_over_errors++;
745
746 /* Receive Descriptor Empty int */
747 if (ris2 & RIS2_QFF1)
748 priv->stats[RAVB_NC].rx_over_errors++;
749
750 /* Receive FIFO Overflow int */
751 if (ris2 & RIS2_RFFF)
752 priv->rx_fifo_errors++;
753 }
754}
755
756static bool ravb_queue_interrupt(struct net_device *ndev, int q)
757{
758 struct ravb_private *priv = netdev_priv(ndev);
759 u32 ris0 = ravb_read(ndev, RIS0);
760 u32 ric0 = ravb_read(ndev, RIC0);
761 u32 tis = ravb_read(ndev, TIS);
762 u32 tic = ravb_read(ndev, TIC);
763
764 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
765 if (napi_schedule_prep(&priv->napi[q])) {
766 /* Mask RX and TX interrupts */
767 if (priv->chip_id == RCAR_GEN2) {
768 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
769 ravb_write(ndev, tic & ~BIT(q), TIC);
770 } else {
771 ravb_write(ndev, BIT(q), RID0);
772 ravb_write(ndev, BIT(q), TID);
773 }
774 __napi_schedule(&priv->napi[q]);
775 } else {
776 netdev_warn(ndev,
777 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
778 ris0, ric0);
779 netdev_warn(ndev,
780 " tx status 0x%08x, tx mask 0x%08x.\n",
781 tis, tic);
782 }
783 return true;
784 }
785 return false;
786}
787
788static bool ravb_timestamp_interrupt(struct net_device *ndev)
789{
790 u32 tis = ravb_read(ndev, TIS);
791
792 if (tis & TIS_TFUF) {
793 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
794 ravb_get_tx_tstamp(ndev);
795 return true;
796 }
797 return false;
798}
799
800static irqreturn_t ravb_interrupt(int irq, void *dev_id)
801{
802 struct net_device *ndev = dev_id;
803 struct ravb_private *priv = netdev_priv(ndev);
804 irqreturn_t result = IRQ_NONE;
805 u32 iss;
806
807 spin_lock(&priv->lock);
808 /* Get interrupt status */
809 iss = ravb_read(ndev, ISS);
810
811 /* Received and transmitted interrupts */
812 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
813 int q;
814
815 /* Timestamp updated */
816 if (ravb_timestamp_interrupt(ndev))
817 result = IRQ_HANDLED;
818
819 /* Network control and best effort queue RX/TX */
820 for (q = RAVB_NC; q >= RAVB_BE; q--) {
821 if (ravb_queue_interrupt(ndev, q))
822 result = IRQ_HANDLED;
823 }
824 }
825
826 /* E-MAC status summary */
827 if (iss & ISS_MS) {
828 ravb_emac_interrupt_unlocked(ndev);
829 result = IRQ_HANDLED;
830 }
831
832 /* Error status summary */
833 if (iss & ISS_ES) {
834 ravb_error_interrupt(ndev);
835 result = IRQ_HANDLED;
836 }
837
838 /* gPTP interrupt status summary */
839 if (iss & ISS_CGIS) {
840 ravb_ptp_interrupt(ndev);
841 result = IRQ_HANDLED;
842 }
843
844 spin_unlock(&priv->lock);
845 return result;
846}
847
848/* Timestamp/Error/gPTP interrupt handler */
849static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
850{
851 struct net_device *ndev = dev_id;
852 struct ravb_private *priv = netdev_priv(ndev);
853 irqreturn_t result = IRQ_NONE;
854 u32 iss;
855
856 spin_lock(&priv->lock);
857 /* Get interrupt status */
858 iss = ravb_read(ndev, ISS);
859
860 /* Timestamp updated */
861 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
862 result = IRQ_HANDLED;
863
864 /* Error status summary */
865 if (iss & ISS_ES) {
866 ravb_error_interrupt(ndev);
867 result = IRQ_HANDLED;
868 }
869
870 /* gPTP interrupt status summary */
871 if (iss & ISS_CGIS) {
872 ravb_ptp_interrupt(ndev);
873 result = IRQ_HANDLED;
874 }
875
876 spin_unlock(&priv->lock);
877 return result;
878}
879
880static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
881{
882 struct net_device *ndev = dev_id;
883 struct ravb_private *priv = netdev_priv(ndev);
884 irqreturn_t result = IRQ_NONE;
885
886 spin_lock(&priv->lock);
887
888 /* Network control/Best effort queue RX/TX */
889 if (ravb_queue_interrupt(ndev, q))
890 result = IRQ_HANDLED;
891
892 spin_unlock(&priv->lock);
893 return result;
894}
895
896static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
897{
898 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
899}
900
901static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
902{
903 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
904}
905
906static int ravb_poll(struct napi_struct *napi, int budget)
907{
908 struct net_device *ndev = napi->dev;
909 struct ravb_private *priv = netdev_priv(ndev);
910 unsigned long flags;
911 int q = napi - priv->napi;
912 int mask = BIT(q);
913 int quota = budget;
914 u32 ris0, tis;
915
916 for (;;) {
917 tis = ravb_read(ndev, TIS);
918 ris0 = ravb_read(ndev, RIS0);
919 if (!((ris0 & mask) || (tis & mask)))
920 break;
921
922 /* Processing RX Descriptor Ring */
923 if (ris0 & mask) {
924 /* Clear RX interrupt */
925 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
926 if (ravb_rx(ndev, "a, q))
927 goto out;
928 }
929 /* Processing TX Descriptor Ring */
930 if (tis & mask) {
931 spin_lock_irqsave(&priv->lock, flags);
932 /* Clear TX interrupt */
933 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
934 ravb_tx_free(ndev, q, true);
935 netif_wake_subqueue(ndev, q);
936 spin_unlock_irqrestore(&priv->lock, flags);
937 }
938 }
939
940 napi_complete(napi);
941
942 /* Re-enable RX/TX interrupts */
943 spin_lock_irqsave(&priv->lock, flags);
944 if (priv->chip_id == RCAR_GEN2) {
945 ravb_modify(ndev, RIC0, mask, mask);
946 ravb_modify(ndev, TIC, mask, mask);
947 } else {
948 ravb_write(ndev, mask, RIE0);
949 ravb_write(ndev, mask, TIE);
950 }
951 spin_unlock_irqrestore(&priv->lock, flags);
952
953 /* Receive error message handling */
954 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
955 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
956 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
957 ndev->stats.rx_over_errors = priv->rx_over_errors;
958 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
959 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
960out:
961 return budget - quota;
962}
963
964/* PHY state control function */
965static void ravb_adjust_link(struct net_device *ndev)
966{
967 struct ravb_private *priv = netdev_priv(ndev);
968 struct phy_device *phydev = ndev->phydev;
969 bool new_state = false;
970 unsigned long flags;
971
972 spin_lock_irqsave(&priv->lock, flags);
973
974 /* Disable TX and RX right over here, if E-MAC change is ignored */
975 if (priv->no_avb_link)
976 ravb_rcv_snd_disable(ndev);
977
978 if (phydev->link) {
979 if (phydev->speed != priv->speed) {
980 new_state = true;
981 priv->speed = phydev->speed;
982 ravb_set_rate(ndev);
983 }
984 if (!priv->link) {
985 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
986 new_state = true;
987 priv->link = phydev->link;
988 }
989 } else if (priv->link) {
990 new_state = true;
991 priv->link = 0;
992 priv->speed = 0;
993 }
994
995 /* Enable TX and RX right over here, if E-MAC change is ignored */
996 if (priv->no_avb_link && phydev->link)
997 ravb_rcv_snd_enable(ndev);
998
999 spin_unlock_irqrestore(&priv->lock, flags);
1000
1001 if (new_state && netif_msg_link(priv))
1002 phy_print_status(phydev);
1003}
1004
1005static const struct soc_device_attribute r8a7795es10[] = {
1006 { .soc_id = "r8a7795", .revision = "ES1.0", },
1007 { /* sentinel */ }
1008};
1009
1010/* PHY init function */
1011static int ravb_phy_init(struct net_device *ndev)
1012{
1013 struct device_node *np = ndev->dev.parent->of_node;
1014 struct ravb_private *priv = netdev_priv(ndev);
1015 struct phy_device *phydev;
1016 struct device_node *pn;
1017 phy_interface_t iface;
1018 int err;
1019
1020 priv->link = 0;
1021 priv->speed = 0;
1022
1023 /* Try connecting to PHY */
1024 pn = of_parse_phandle(np, "phy-handle", 0);
1025 if (!pn) {
1026 /* In the case of a fixed PHY, the DT node associated
1027 * to the PHY is the Ethernet MAC DT node.
1028 */
1029 if (of_phy_is_fixed_link(np)) {
1030 err = of_phy_register_fixed_link(np);
1031 if (err)
1032 return err;
1033 }
1034 pn = of_node_get(np);
1035 }
1036
1037 iface = priv->phy_interface;
1038 if (priv->chip_id != RCAR_GEN2 && phy_interface_mode_is_rgmii(iface)) {
1039 /* ravb_set_delay_mode() takes care of internal delay mode */
1040 iface = PHY_INTERFACE_MODE_RGMII;
1041 }
1042 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface);
1043 of_node_put(pn);
1044 if (!phydev) {
1045 netdev_err(ndev, "failed to connect PHY\n");
1046 err = -ENOENT;
1047 goto err_deregister_fixed_link;
1048 }
1049
1050 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1051 * at this time.
1052 */
1053 if (soc_device_match(r8a7795es10)) {
1054 err = phy_set_max_speed(phydev, SPEED_100);
1055 if (err) {
1056 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1057 goto err_phy_disconnect;
1058 }
1059
1060 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1061 }
1062
1063 /* 10BASE, Pause and Asym Pause is not supported */
1064 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT);
1065 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT);
1066 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT);
1067 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT);
1068
1069 /* Half Duplex is not supported */
1070 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1071 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT);
1072
1073 phy_attached_info(phydev);
1074
1075 return 0;
1076
1077err_phy_disconnect:
1078 phy_disconnect(phydev);
1079err_deregister_fixed_link:
1080 if (of_phy_is_fixed_link(np))
1081 of_phy_deregister_fixed_link(np);
1082
1083 return err;
1084}
1085
1086/* PHY control start function */
1087static int ravb_phy_start(struct net_device *ndev)
1088{
1089 int error;
1090
1091 error = ravb_phy_init(ndev);
1092 if (error)
1093 return error;
1094
1095 phy_start(ndev->phydev);
1096
1097 return 0;
1098}
1099
1100static u32 ravb_get_msglevel(struct net_device *ndev)
1101{
1102 struct ravb_private *priv = netdev_priv(ndev);
1103
1104 return priv->msg_enable;
1105}
1106
1107static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1108{
1109 struct ravb_private *priv = netdev_priv(ndev);
1110
1111 priv->msg_enable = value;
1112}
1113
1114static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1115 "rx_queue_0_current",
1116 "tx_queue_0_current",
1117 "rx_queue_0_dirty",
1118 "tx_queue_0_dirty",
1119 "rx_queue_0_packets",
1120 "tx_queue_0_packets",
1121 "rx_queue_0_bytes",
1122 "tx_queue_0_bytes",
1123 "rx_queue_0_mcast_packets",
1124 "rx_queue_0_errors",
1125 "rx_queue_0_crc_errors",
1126 "rx_queue_0_frame_errors",
1127 "rx_queue_0_length_errors",
1128 "rx_queue_0_missed_errors",
1129 "rx_queue_0_over_errors",
1130
1131 "rx_queue_1_current",
1132 "tx_queue_1_current",
1133 "rx_queue_1_dirty",
1134 "tx_queue_1_dirty",
1135 "rx_queue_1_packets",
1136 "tx_queue_1_packets",
1137 "rx_queue_1_bytes",
1138 "tx_queue_1_bytes",
1139 "rx_queue_1_mcast_packets",
1140 "rx_queue_1_errors",
1141 "rx_queue_1_crc_errors",
1142 "rx_queue_1_frame_errors",
1143 "rx_queue_1_length_errors",
1144 "rx_queue_1_missed_errors",
1145 "rx_queue_1_over_errors",
1146};
1147
1148#define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1149
1150static int ravb_get_sset_count(struct net_device *netdev, int sset)
1151{
1152 switch (sset) {
1153 case ETH_SS_STATS:
1154 return RAVB_STATS_LEN;
1155 default:
1156 return -EOPNOTSUPP;
1157 }
1158}
1159
1160static void ravb_get_ethtool_stats(struct net_device *ndev,
1161 struct ethtool_stats *estats, u64 *data)
1162{
1163 struct ravb_private *priv = netdev_priv(ndev);
1164 int i = 0;
1165 int q;
1166
1167 /* Device-specific stats */
1168 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1169 struct net_device_stats *stats = &priv->stats[q];
1170
1171 data[i++] = priv->cur_rx[q];
1172 data[i++] = priv->cur_tx[q];
1173 data[i++] = priv->dirty_rx[q];
1174 data[i++] = priv->dirty_tx[q];
1175 data[i++] = stats->rx_packets;
1176 data[i++] = stats->tx_packets;
1177 data[i++] = stats->rx_bytes;
1178 data[i++] = stats->tx_bytes;
1179 data[i++] = stats->multicast;
1180 data[i++] = stats->rx_errors;
1181 data[i++] = stats->rx_crc_errors;
1182 data[i++] = stats->rx_frame_errors;
1183 data[i++] = stats->rx_length_errors;
1184 data[i++] = stats->rx_missed_errors;
1185 data[i++] = stats->rx_over_errors;
1186 }
1187}
1188
1189static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1190{
1191 switch (stringset) {
1192 case ETH_SS_STATS:
1193 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1194 break;
1195 }
1196}
1197
1198static void ravb_get_ringparam(struct net_device *ndev,
1199 struct ethtool_ringparam *ring)
1200{
1201 struct ravb_private *priv = netdev_priv(ndev);
1202
1203 ring->rx_max_pending = BE_RX_RING_MAX;
1204 ring->tx_max_pending = BE_TX_RING_MAX;
1205 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1206 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1207}
1208
1209static int ravb_set_ringparam(struct net_device *ndev,
1210 struct ethtool_ringparam *ring)
1211{
1212 struct ravb_private *priv = netdev_priv(ndev);
1213 int error;
1214
1215 if (ring->tx_pending > BE_TX_RING_MAX ||
1216 ring->rx_pending > BE_RX_RING_MAX ||
1217 ring->tx_pending < BE_TX_RING_MIN ||
1218 ring->rx_pending < BE_RX_RING_MIN)
1219 return -EINVAL;
1220 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1221 return -EINVAL;
1222
1223 if (netif_running(ndev)) {
1224 netif_device_detach(ndev);
1225 /* Stop PTP Clock driver */
1226 if (priv->chip_id == RCAR_GEN2)
1227 ravb_ptp_stop(ndev);
1228 /* Wait for DMA stopping */
1229 error = ravb_stop_dma(ndev);
1230 if (error) {
1231 netdev_err(ndev,
1232 "cannot set ringparam! Any AVB processes are still running?\n");
1233 return error;
1234 }
1235 synchronize_irq(ndev->irq);
1236
1237 /* Free all the skb's in the RX queue and the DMA buffers. */
1238 ravb_ring_free(ndev, RAVB_BE);
1239 ravb_ring_free(ndev, RAVB_NC);
1240 }
1241
1242 /* Set new parameters */
1243 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1244 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1245
1246 if (netif_running(ndev)) {
1247 error = ravb_dmac_init(ndev);
1248 if (error) {
1249 netdev_err(ndev,
1250 "%s: ravb_dmac_init() failed, error %d\n",
1251 __func__, error);
1252 return error;
1253 }
1254
1255 ravb_emac_init(ndev);
1256
1257 /* Initialise PTP Clock driver */
1258 if (priv->chip_id == RCAR_GEN2)
1259 ravb_ptp_init(ndev, priv->pdev);
1260
1261 netif_device_attach(ndev);
1262 }
1263
1264 return 0;
1265}
1266
1267static int ravb_get_ts_info(struct net_device *ndev,
1268 struct ethtool_ts_info *info)
1269{
1270 struct ravb_private *priv = netdev_priv(ndev);
1271
1272 info->so_timestamping =
1273 SOF_TIMESTAMPING_TX_SOFTWARE |
1274 SOF_TIMESTAMPING_RX_SOFTWARE |
1275 SOF_TIMESTAMPING_SOFTWARE |
1276 SOF_TIMESTAMPING_TX_HARDWARE |
1277 SOF_TIMESTAMPING_RX_HARDWARE |
1278 SOF_TIMESTAMPING_RAW_HARDWARE;
1279 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1280 info->rx_filters =
1281 (1 << HWTSTAMP_FILTER_NONE) |
1282 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1283 (1 << HWTSTAMP_FILTER_ALL);
1284 info->phc_index = ptp_clock_index(priv->ptp.clock);
1285
1286 return 0;
1287}
1288
1289static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1290{
1291 struct ravb_private *priv = netdev_priv(ndev);
1292
1293 wol->supported = WAKE_MAGIC;
1294 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1295}
1296
1297static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1298{
1299 struct ravb_private *priv = netdev_priv(ndev);
1300
1301 if (wol->wolopts & ~WAKE_MAGIC)
1302 return -EOPNOTSUPP;
1303
1304 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1305
1306 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1307
1308 return 0;
1309}
1310
1311static const struct ethtool_ops ravb_ethtool_ops = {
1312 .nway_reset = phy_ethtool_nway_reset,
1313 .get_msglevel = ravb_get_msglevel,
1314 .set_msglevel = ravb_set_msglevel,
1315 .get_link = ethtool_op_get_link,
1316 .get_strings = ravb_get_strings,
1317 .get_ethtool_stats = ravb_get_ethtool_stats,
1318 .get_sset_count = ravb_get_sset_count,
1319 .get_ringparam = ravb_get_ringparam,
1320 .set_ringparam = ravb_set_ringparam,
1321 .get_ts_info = ravb_get_ts_info,
1322 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1323 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1324 .get_wol = ravb_get_wol,
1325 .set_wol = ravb_set_wol,
1326};
1327
1328static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1329 struct net_device *ndev, struct device *dev,
1330 const char *ch)
1331{
1332 char *name;
1333 int error;
1334
1335 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1336 if (!name)
1337 return -ENOMEM;
1338 error = request_irq(irq, handler, 0, name, ndev);
1339 if (error)
1340 netdev_err(ndev, "cannot request IRQ %s\n", name);
1341
1342 return error;
1343}
1344
1345/* Network device open function for Ethernet AVB */
1346static int ravb_open(struct net_device *ndev)
1347{
1348 struct ravb_private *priv = netdev_priv(ndev);
1349 struct platform_device *pdev = priv->pdev;
1350 struct device *dev = &pdev->dev;
1351 int error;
1352
1353 napi_enable(&priv->napi[RAVB_BE]);
1354 napi_enable(&priv->napi[RAVB_NC]);
1355
1356 if (priv->chip_id == RCAR_GEN2) {
1357 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1358 ndev->name, ndev);
1359 if (error) {
1360 netdev_err(ndev, "cannot request IRQ\n");
1361 goto out_napi_off;
1362 }
1363 } else {
1364 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1365 dev, "ch22:multi");
1366 if (error)
1367 goto out_napi_off;
1368 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1369 dev, "ch24:emac");
1370 if (error)
1371 goto out_free_irq;
1372 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1373 ndev, dev, "ch0:rx_be");
1374 if (error)
1375 goto out_free_irq_emac;
1376 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1377 ndev, dev, "ch18:tx_be");
1378 if (error)
1379 goto out_free_irq_be_rx;
1380 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1381 ndev, dev, "ch1:rx_nc");
1382 if (error)
1383 goto out_free_irq_be_tx;
1384 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1385 ndev, dev, "ch19:tx_nc");
1386 if (error)
1387 goto out_free_irq_nc_rx;
1388 }
1389
1390 /* Device init */
1391 error = ravb_dmac_init(ndev);
1392 if (error)
1393 goto out_free_irq_nc_tx;
1394 ravb_emac_init(ndev);
1395
1396 /* Initialise PTP Clock driver */
1397 if (priv->chip_id == RCAR_GEN2)
1398 ravb_ptp_init(ndev, priv->pdev);
1399
1400 netif_tx_start_all_queues(ndev);
1401
1402 /* PHY control start */
1403 error = ravb_phy_start(ndev);
1404 if (error)
1405 goto out_ptp_stop;
1406
1407 return 0;
1408
1409out_ptp_stop:
1410 /* Stop PTP Clock driver */
1411 if (priv->chip_id == RCAR_GEN2)
1412 ravb_ptp_stop(ndev);
1413out_free_irq_nc_tx:
1414 if (priv->chip_id == RCAR_GEN2)
1415 goto out_free_irq;
1416 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1417out_free_irq_nc_rx:
1418 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1419out_free_irq_be_tx:
1420 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1421out_free_irq_be_rx:
1422 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1423out_free_irq_emac:
1424 free_irq(priv->emac_irq, ndev);
1425out_free_irq:
1426 free_irq(ndev->irq, ndev);
1427out_napi_off:
1428 napi_disable(&priv->napi[RAVB_NC]);
1429 napi_disable(&priv->napi[RAVB_BE]);
1430 return error;
1431}
1432
1433/* Timeout function for Ethernet AVB */
1434static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1435{
1436 struct ravb_private *priv = netdev_priv(ndev);
1437
1438 netif_err(priv, tx_err, ndev,
1439 "transmit timed out, status %08x, resetting...\n",
1440 ravb_read(ndev, ISS));
1441
1442 /* tx_errors count up */
1443 ndev->stats.tx_errors++;
1444
1445 schedule_work(&priv->work);
1446}
1447
1448static void ravb_tx_timeout_work(struct work_struct *work)
1449{
1450 struct ravb_private *priv = container_of(work, struct ravb_private,
1451 work);
1452 struct net_device *ndev = priv->ndev;
1453 int error;
1454
1455 netif_tx_stop_all_queues(ndev);
1456
1457 /* Stop PTP Clock driver */
1458 if (priv->chip_id == RCAR_GEN2)
1459 ravb_ptp_stop(ndev);
1460
1461 /* Wait for DMA stopping */
1462 if (ravb_stop_dma(ndev)) {
1463 /* If ravb_stop_dma() fails, the hardware is still operating
1464 * for TX and/or RX. So, this should not call the following
1465 * functions because ravb_dmac_init() is possible to fail too.
1466 * Also, this should not retry ravb_stop_dma() again and again
1467 * here because it's possible to wait forever. So, this just
1468 * re-enables the TX and RX and skip the following
1469 * re-initialization procedure.
1470 */
1471 ravb_rcv_snd_enable(ndev);
1472 goto out;
1473 }
1474
1475 ravb_ring_free(ndev, RAVB_BE);
1476 ravb_ring_free(ndev, RAVB_NC);
1477
1478 /* Device init */
1479 error = ravb_dmac_init(ndev);
1480 if (error) {
1481 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1482 * should return here to avoid re-enabling the TX and RX in
1483 * ravb_emac_init().
1484 */
1485 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1486 __func__, error);
1487 return;
1488 }
1489 ravb_emac_init(ndev);
1490
1491out:
1492 /* Initialise PTP Clock driver */
1493 if (priv->chip_id == RCAR_GEN2)
1494 ravb_ptp_init(ndev, priv->pdev);
1495
1496 netif_tx_start_all_queues(ndev);
1497}
1498
1499/* Packet transmit function for Ethernet AVB */
1500static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1501{
1502 struct ravb_private *priv = netdev_priv(ndev);
1503 int num_tx_desc = priv->num_tx_desc;
1504 u16 q = skb_get_queue_mapping(skb);
1505 struct ravb_tstamp_skb *ts_skb;
1506 struct ravb_tx_desc *desc;
1507 unsigned long flags;
1508 u32 dma_addr;
1509 void *buffer;
1510 u32 entry;
1511 u32 len;
1512
1513 spin_lock_irqsave(&priv->lock, flags);
1514 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1515 num_tx_desc) {
1516 netif_err(priv, tx_queued, ndev,
1517 "still transmitting with the full ring!\n");
1518 netif_stop_subqueue(ndev, q);
1519 spin_unlock_irqrestore(&priv->lock, flags);
1520 return NETDEV_TX_BUSY;
1521 }
1522
1523 if (skb_put_padto(skb, ETH_ZLEN))
1524 goto exit;
1525
1526 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc);
1527 priv->tx_skb[q][entry / num_tx_desc] = skb;
1528
1529 if (num_tx_desc > 1) {
1530 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1531 entry / num_tx_desc * DPTR_ALIGN;
1532 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1533
1534 /* Zero length DMA descriptors are problematic as they seem
1535 * to terminate DMA transfers. Avoid them by simply using a
1536 * length of DPTR_ALIGN (4) when skb data is aligned to
1537 * DPTR_ALIGN.
1538 *
1539 * As skb is guaranteed to have at least ETH_ZLEN (60)
1540 * bytes of data by the call to skb_put_padto() above this
1541 * is safe with respect to both the length of the first DMA
1542 * descriptor (len) overflowing the available data and the
1543 * length of the second DMA descriptor (skb->len - len)
1544 * being negative.
1545 */
1546 if (len == 0)
1547 len = DPTR_ALIGN;
1548
1549 memcpy(buffer, skb->data, len);
1550 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1551 DMA_TO_DEVICE);
1552 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1553 goto drop;
1554
1555 desc = &priv->tx_ring[q][entry];
1556 desc->ds_tagl = cpu_to_le16(len);
1557 desc->dptr = cpu_to_le32(dma_addr);
1558
1559 buffer = skb->data + len;
1560 len = skb->len - len;
1561 dma_addr = dma_map_single(ndev->dev.parent, buffer, len,
1562 DMA_TO_DEVICE);
1563 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1564 goto unmap;
1565
1566 desc++;
1567 } else {
1568 desc = &priv->tx_ring[q][entry];
1569 len = skb->len;
1570 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len,
1571 DMA_TO_DEVICE);
1572 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1573 goto drop;
1574 }
1575 desc->ds_tagl = cpu_to_le16(len);
1576 desc->dptr = cpu_to_le32(dma_addr);
1577
1578 /* TX timestamp required */
1579 if (q == RAVB_NC) {
1580 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1581 if (!ts_skb) {
1582 if (num_tx_desc > 1) {
1583 desc--;
1584 dma_unmap_single(ndev->dev.parent, dma_addr,
1585 len, DMA_TO_DEVICE);
1586 }
1587 goto unmap;
1588 }
1589 ts_skb->skb = skb_get(skb);
1590 ts_skb->tag = priv->ts_skb_tag++;
1591 priv->ts_skb_tag &= 0x3ff;
1592 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1593
1594 /* TAG and timestamp required flag */
1595 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1596 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1597 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1598 }
1599
1600 skb_tx_timestamp(skb);
1601 /* Descriptor type must be set after all the above writes */
1602 dma_wmb();
1603 if (num_tx_desc > 1) {
1604 desc->die_dt = DT_FEND;
1605 desc--;
1606 desc->die_dt = DT_FSTART;
1607 } else {
1608 desc->die_dt = DT_FSINGLE;
1609 }
1610 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1611
1612 priv->cur_tx[q] += num_tx_desc;
1613 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1614 (priv->num_tx_ring[q] - 1) * num_tx_desc &&
1615 !ravb_tx_free(ndev, q, true))
1616 netif_stop_subqueue(ndev, q);
1617
1618exit:
1619 spin_unlock_irqrestore(&priv->lock, flags);
1620 return NETDEV_TX_OK;
1621
1622unmap:
1623 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1624 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1625drop:
1626 dev_kfree_skb_any(skb);
1627 priv->tx_skb[q][entry / num_tx_desc] = NULL;
1628 goto exit;
1629}
1630
1631static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1632 struct net_device *sb_dev)
1633{
1634 /* If skb needs TX timestamp, it is handled in network control queue */
1635 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1636 RAVB_BE;
1637
1638}
1639
1640static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1641{
1642 struct ravb_private *priv = netdev_priv(ndev);
1643 struct net_device_stats *nstats, *stats0, *stats1;
1644
1645 nstats = &ndev->stats;
1646 stats0 = &priv->stats[RAVB_BE];
1647 stats1 = &priv->stats[RAVB_NC];
1648
1649 if (priv->chip_id == RCAR_GEN3) {
1650 nstats->tx_dropped += ravb_read(ndev, TROCR);
1651 ravb_write(ndev, 0, TROCR); /* (write clear) */
1652 }
1653
1654 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1655 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1656 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1657 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1658 nstats->multicast = stats0->multicast + stats1->multicast;
1659 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1660 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1661 nstats->rx_frame_errors =
1662 stats0->rx_frame_errors + stats1->rx_frame_errors;
1663 nstats->rx_length_errors =
1664 stats0->rx_length_errors + stats1->rx_length_errors;
1665 nstats->rx_missed_errors =
1666 stats0->rx_missed_errors + stats1->rx_missed_errors;
1667 nstats->rx_over_errors =
1668 stats0->rx_over_errors + stats1->rx_over_errors;
1669
1670 return nstats;
1671}
1672
1673/* Update promiscuous bit */
1674static void ravb_set_rx_mode(struct net_device *ndev)
1675{
1676 struct ravb_private *priv = netdev_priv(ndev);
1677 unsigned long flags;
1678
1679 spin_lock_irqsave(&priv->lock, flags);
1680 ravb_modify(ndev, ECMR, ECMR_PRM,
1681 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1682 spin_unlock_irqrestore(&priv->lock, flags);
1683}
1684
1685/* Device close function for Ethernet AVB */
1686static int ravb_close(struct net_device *ndev)
1687{
1688 struct device_node *np = ndev->dev.parent->of_node;
1689 struct ravb_private *priv = netdev_priv(ndev);
1690 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1691
1692 netif_tx_stop_all_queues(ndev);
1693
1694 /* Disable interrupts by clearing the interrupt masks. */
1695 ravb_write(ndev, 0, RIC0);
1696 ravb_write(ndev, 0, RIC2);
1697 ravb_write(ndev, 0, TIC);
1698
1699 /* Stop PTP Clock driver */
1700 if (priv->chip_id == RCAR_GEN2)
1701 ravb_ptp_stop(ndev);
1702
1703 /* Set the config mode to stop the AVB-DMAC's processes */
1704 if (ravb_stop_dma(ndev) < 0)
1705 netdev_err(ndev,
1706 "device will be stopped after h/w processes are done.\n");
1707
1708 /* Clear the timestamp list */
1709 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1710 list_del(&ts_skb->list);
1711 kfree_skb(ts_skb->skb);
1712 kfree(ts_skb);
1713 }
1714
1715 /* PHY disconnect */
1716 if (ndev->phydev) {
1717 phy_stop(ndev->phydev);
1718 phy_disconnect(ndev->phydev);
1719 if (of_phy_is_fixed_link(np))
1720 of_phy_deregister_fixed_link(np);
1721 }
1722
1723 if (priv->chip_id != RCAR_GEN2) {
1724 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1725 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1726 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1727 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1728 free_irq(priv->emac_irq, ndev);
1729 }
1730 free_irq(ndev->irq, ndev);
1731
1732 napi_disable(&priv->napi[RAVB_NC]);
1733 napi_disable(&priv->napi[RAVB_BE]);
1734
1735 /* Free all the skb's in the RX queue and the DMA buffers. */
1736 ravb_ring_free(ndev, RAVB_BE);
1737 ravb_ring_free(ndev, RAVB_NC);
1738
1739 return 0;
1740}
1741
1742static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1743{
1744 struct ravb_private *priv = netdev_priv(ndev);
1745 struct hwtstamp_config config;
1746
1747 config.flags = 0;
1748 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1749 HWTSTAMP_TX_OFF;
1750 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1752 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1753 config.rx_filter = HWTSTAMP_FILTER_ALL;
1754 else
1755 config.rx_filter = HWTSTAMP_FILTER_NONE;
1756
1757 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1758 -EFAULT : 0;
1759}
1760
1761/* Control hardware time stamping */
1762static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1763{
1764 struct ravb_private *priv = netdev_priv(ndev);
1765 struct hwtstamp_config config;
1766 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1767 u32 tstamp_tx_ctrl;
1768
1769 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1770 return -EFAULT;
1771
1772 /* Reserved for future extensions */
1773 if (config.flags)
1774 return -EINVAL;
1775
1776 switch (config.tx_type) {
1777 case HWTSTAMP_TX_OFF:
1778 tstamp_tx_ctrl = 0;
1779 break;
1780 case HWTSTAMP_TX_ON:
1781 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1782 break;
1783 default:
1784 return -ERANGE;
1785 }
1786
1787 switch (config.rx_filter) {
1788 case HWTSTAMP_FILTER_NONE:
1789 tstamp_rx_ctrl = 0;
1790 break;
1791 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1792 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1793 break;
1794 default:
1795 config.rx_filter = HWTSTAMP_FILTER_ALL;
1796 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1797 }
1798
1799 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1800 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1801
1802 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1803 -EFAULT : 0;
1804}
1805
1806/* ioctl to device function */
1807static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1808{
1809 struct phy_device *phydev = ndev->phydev;
1810
1811 if (!netif_running(ndev))
1812 return -EINVAL;
1813
1814 if (!phydev)
1815 return -ENODEV;
1816
1817 switch (cmd) {
1818 case SIOCGHWTSTAMP:
1819 return ravb_hwtstamp_get(ndev, req);
1820 case SIOCSHWTSTAMP:
1821 return ravb_hwtstamp_set(ndev, req);
1822 }
1823
1824 return phy_mii_ioctl(phydev, req, cmd);
1825}
1826
1827static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1828{
1829 struct ravb_private *priv = netdev_priv(ndev);
1830
1831 ndev->mtu = new_mtu;
1832
1833 if (netif_running(ndev)) {
1834 synchronize_irq(priv->emac_irq);
1835 ravb_emac_init(ndev);
1836 }
1837
1838 netdev_update_features(ndev);
1839
1840 return 0;
1841}
1842
1843static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1844{
1845 struct ravb_private *priv = netdev_priv(ndev);
1846 unsigned long flags;
1847
1848 spin_lock_irqsave(&priv->lock, flags);
1849
1850 /* Disable TX and RX */
1851 ravb_rcv_snd_disable(ndev);
1852
1853 /* Modify RX Checksum setting */
1854 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1855
1856 /* Enable TX and RX */
1857 ravb_rcv_snd_enable(ndev);
1858
1859 spin_unlock_irqrestore(&priv->lock, flags);
1860}
1861
1862static int ravb_set_features(struct net_device *ndev,
1863 netdev_features_t features)
1864{
1865 netdev_features_t changed = ndev->features ^ features;
1866
1867 if (changed & NETIF_F_RXCSUM)
1868 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1869
1870 ndev->features = features;
1871
1872 return 0;
1873}
1874
1875static const struct net_device_ops ravb_netdev_ops = {
1876 .ndo_open = ravb_open,
1877 .ndo_stop = ravb_close,
1878 .ndo_start_xmit = ravb_start_xmit,
1879 .ndo_select_queue = ravb_select_queue,
1880 .ndo_get_stats = ravb_get_stats,
1881 .ndo_set_rx_mode = ravb_set_rx_mode,
1882 .ndo_tx_timeout = ravb_tx_timeout,
1883 .ndo_do_ioctl = ravb_do_ioctl,
1884 .ndo_change_mtu = ravb_change_mtu,
1885 .ndo_validate_addr = eth_validate_addr,
1886 .ndo_set_mac_address = eth_mac_addr,
1887 .ndo_set_features = ravb_set_features,
1888};
1889
1890/* MDIO bus init function */
1891static int ravb_mdio_init(struct ravb_private *priv)
1892{
1893 struct platform_device *pdev = priv->pdev;
1894 struct device *dev = &pdev->dev;
1895 int error;
1896
1897 /* Bitbang init */
1898 priv->mdiobb.ops = &bb_ops;
1899
1900 /* MII controller setting */
1901 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1902 if (!priv->mii_bus)
1903 return -ENOMEM;
1904
1905 /* Hook up MII support for ethtool */
1906 priv->mii_bus->name = "ravb_mii";
1907 priv->mii_bus->parent = dev;
1908 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1909 pdev->name, pdev->id);
1910
1911 /* Register MDIO bus */
1912 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1913 if (error)
1914 goto out_free_bus;
1915
1916 return 0;
1917
1918out_free_bus:
1919 free_mdio_bitbang(priv->mii_bus);
1920 return error;
1921}
1922
1923/* MDIO bus release function */
1924static int ravb_mdio_release(struct ravb_private *priv)
1925{
1926 /* Unregister mdio bus */
1927 mdiobus_unregister(priv->mii_bus);
1928
1929 /* Free bitbang info */
1930 free_mdio_bitbang(priv->mii_bus);
1931
1932 return 0;
1933}
1934
1935static const struct of_device_id ravb_match_table[] = {
1936 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1937 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1938 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1939 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1940 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1941 { }
1942};
1943MODULE_DEVICE_TABLE(of, ravb_match_table);
1944
1945static int ravb_set_gti(struct net_device *ndev)
1946{
1947 struct ravb_private *priv = netdev_priv(ndev);
1948 struct device *dev = ndev->dev.parent;
1949 unsigned long rate;
1950 uint64_t inc;
1951
1952 rate = clk_get_rate(priv->clk);
1953 if (!rate)
1954 return -EINVAL;
1955
1956 inc = 1000000000ULL << 20;
1957 do_div(inc, rate);
1958
1959 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1960 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1961 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1962 return -EINVAL;
1963 }
1964
1965 ravb_write(ndev, inc, GTI);
1966
1967 return 0;
1968}
1969
1970static void ravb_set_config_mode(struct net_device *ndev)
1971{
1972 struct ravb_private *priv = netdev_priv(ndev);
1973
1974 if (priv->chip_id == RCAR_GEN2) {
1975 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1976 /* Set CSEL value */
1977 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1978 } else {
1979 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1980 CCC_GAC | CCC_CSEL_HPB);
1981 }
1982}
1983
1984static const struct soc_device_attribute ravb_delay_mode_quirk_match[] = {
1985 { .soc_id = "r8a774c0" },
1986 { .soc_id = "r8a77990" },
1987 { .soc_id = "r8a77995" },
1988 { /* sentinel */ }
1989};
1990
1991/* Set tx and rx clock internal delay modes */
1992static void ravb_set_delay_mode(struct net_device *ndev)
1993{
1994 struct ravb_private *priv = netdev_priv(ndev);
1995 int set = 0;
1996
1997 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1998 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1999 set |= APSR_DM_RDM;
2000
2001 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
2002 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) {
2003 if (!WARN(soc_device_match(ravb_delay_mode_quirk_match),
2004 "phy-mode %s requires TX clock internal delay mode which is not supported by this hardware revision. Please update device tree",
2005 phy_modes(priv->phy_interface)))
2006 set |= APSR_DM_TDM;
2007 }
2008
2009 ravb_modify(ndev, APSR, APSR_DM, set);
2010}
2011
2012static int ravb_probe(struct platform_device *pdev)
2013{
2014 struct device_node *np = pdev->dev.of_node;
2015 struct ravb_private *priv;
2016 enum ravb_chip_id chip_id;
2017 struct net_device *ndev;
2018 int error, irq, q;
2019 struct resource *res;
2020 int i;
2021
2022 if (!np) {
2023 dev_err(&pdev->dev,
2024 "this driver is required to be instantiated from device tree\n");
2025 return -EINVAL;
2026 }
2027
2028 /* Get base address */
2029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2030 if (!res) {
2031 dev_err(&pdev->dev, "invalid resource\n");
2032 return -EINVAL;
2033 }
2034
2035 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2036 NUM_TX_QUEUE, NUM_RX_QUEUE);
2037 if (!ndev)
2038 return -ENOMEM;
2039
2040 ndev->features = NETIF_F_RXCSUM;
2041 ndev->hw_features = NETIF_F_RXCSUM;
2042
2043 pm_runtime_enable(&pdev->dev);
2044 pm_runtime_get_sync(&pdev->dev);
2045
2046 /* The Ether-specific entries in the device structure. */
2047 ndev->base_addr = res->start;
2048
2049 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2050
2051 if (chip_id == RCAR_GEN3)
2052 irq = platform_get_irq_byname(pdev, "ch22");
2053 else
2054 irq = platform_get_irq(pdev, 0);
2055 if (irq < 0) {
2056 error = irq;
2057 goto out_release;
2058 }
2059 ndev->irq = irq;
2060
2061 SET_NETDEV_DEV(ndev, &pdev->dev);
2062
2063 priv = netdev_priv(ndev);
2064 priv->ndev = ndev;
2065 priv->pdev = pdev;
2066 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2067 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2068 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2069 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2070 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2071 if (IS_ERR(priv->addr)) {
2072 error = PTR_ERR(priv->addr);
2073 goto out_release;
2074 }
2075
2076 spin_lock_init(&priv->lock);
2077 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2078
2079 error = of_get_phy_mode(np, &priv->phy_interface);
2080 if (error && error != -ENODEV)
2081 goto out_release;
2082
2083 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2084 priv->avb_link_active_low =
2085 of_property_read_bool(np, "renesas,ether-link-active-low");
2086
2087 if (chip_id == RCAR_GEN3) {
2088 irq = platform_get_irq_byname(pdev, "ch24");
2089 if (irq < 0) {
2090 error = irq;
2091 goto out_release;
2092 }
2093 priv->emac_irq = irq;
2094 for (i = 0; i < NUM_RX_QUEUE; i++) {
2095 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2096 if (irq < 0) {
2097 error = irq;
2098 goto out_release;
2099 }
2100 priv->rx_irqs[i] = irq;
2101 }
2102 for (i = 0; i < NUM_TX_QUEUE; i++) {
2103 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2104 if (irq < 0) {
2105 error = irq;
2106 goto out_release;
2107 }
2108 priv->tx_irqs[i] = irq;
2109 }
2110 }
2111
2112 priv->chip_id = chip_id;
2113
2114 priv->clk = devm_clk_get(&pdev->dev, NULL);
2115 if (IS_ERR(priv->clk)) {
2116 error = PTR_ERR(priv->clk);
2117 goto out_release;
2118 }
2119
2120 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2121 ndev->min_mtu = ETH_MIN_MTU;
2122
2123 priv->num_tx_desc = chip_id == RCAR_GEN2 ?
2124 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3;
2125
2126 /* Set function */
2127 ndev->netdev_ops = &ravb_netdev_ops;
2128 ndev->ethtool_ops = &ravb_ethtool_ops;
2129
2130 /* Set AVB config mode */
2131 ravb_set_config_mode(ndev);
2132
2133 /* Set GTI value */
2134 error = ravb_set_gti(ndev);
2135 if (error)
2136 goto out_release;
2137
2138 /* Request GTI loading */
2139 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2140
2141 if (priv->chip_id != RCAR_GEN2)
2142 ravb_set_delay_mode(ndev);
2143
2144 /* Allocate descriptor base address table */
2145 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2146 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2147 &priv->desc_bat_dma, GFP_KERNEL);
2148 if (!priv->desc_bat) {
2149 dev_err(&pdev->dev,
2150 "Cannot allocate desc base address table (size %d bytes)\n",
2151 priv->desc_bat_size);
2152 error = -ENOMEM;
2153 goto out_release;
2154 }
2155 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2156 priv->desc_bat[q].die_dt = DT_EOS;
2157 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2158
2159 /* Initialise HW timestamp list */
2160 INIT_LIST_HEAD(&priv->ts_skb_list);
2161
2162 /* Initialise PTP Clock driver */
2163 if (chip_id != RCAR_GEN2)
2164 ravb_ptp_init(ndev, pdev);
2165
2166 /* Debug message level */
2167 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2168
2169 /* Read and set MAC address */
2170 ravb_read_mac_address(ndev, of_get_mac_address(np));
2171 if (!is_valid_ether_addr(ndev->dev_addr)) {
2172 dev_warn(&pdev->dev,
2173 "no valid MAC address supplied, using a random one\n");
2174 eth_hw_addr_random(ndev);
2175 }
2176
2177 /* MDIO bus init */
2178 error = ravb_mdio_init(priv);
2179 if (error) {
2180 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2181 goto out_dma_free;
2182 }
2183
2184 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2185 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2186
2187 /* Network device register */
2188 error = register_netdev(ndev);
2189 if (error)
2190 goto out_napi_del;
2191
2192 device_set_wakeup_capable(&pdev->dev, 1);
2193
2194 /* Print device information */
2195 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2196 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2197
2198 platform_set_drvdata(pdev, ndev);
2199
2200 return 0;
2201
2202out_napi_del:
2203 netif_napi_del(&priv->napi[RAVB_NC]);
2204 netif_napi_del(&priv->napi[RAVB_BE]);
2205 ravb_mdio_release(priv);
2206out_dma_free:
2207 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2208 priv->desc_bat_dma);
2209
2210 /* Stop PTP Clock driver */
2211 if (chip_id != RCAR_GEN2)
2212 ravb_ptp_stop(ndev);
2213out_release:
2214 free_netdev(ndev);
2215
2216 pm_runtime_put(&pdev->dev);
2217 pm_runtime_disable(&pdev->dev);
2218 return error;
2219}
2220
2221static int ravb_remove(struct platform_device *pdev)
2222{
2223 struct net_device *ndev = platform_get_drvdata(pdev);
2224 struct ravb_private *priv = netdev_priv(ndev);
2225
2226 /* Stop PTP Clock driver */
2227 if (priv->chip_id != RCAR_GEN2)
2228 ravb_ptp_stop(ndev);
2229
2230 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2231 priv->desc_bat_dma);
2232 /* Set reset mode */
2233 ravb_write(ndev, CCC_OPC_RESET, CCC);
2234 pm_runtime_put_sync(&pdev->dev);
2235 unregister_netdev(ndev);
2236 netif_napi_del(&priv->napi[RAVB_NC]);
2237 netif_napi_del(&priv->napi[RAVB_BE]);
2238 ravb_mdio_release(priv);
2239 pm_runtime_disable(&pdev->dev);
2240 free_netdev(ndev);
2241 platform_set_drvdata(pdev, NULL);
2242
2243 return 0;
2244}
2245
2246static int ravb_wol_setup(struct net_device *ndev)
2247{
2248 struct ravb_private *priv = netdev_priv(ndev);
2249
2250 /* Disable interrupts by clearing the interrupt masks. */
2251 ravb_write(ndev, 0, RIC0);
2252 ravb_write(ndev, 0, RIC2);
2253 ravb_write(ndev, 0, TIC);
2254
2255 /* Only allow ECI interrupts */
2256 synchronize_irq(priv->emac_irq);
2257 napi_disable(&priv->napi[RAVB_NC]);
2258 napi_disable(&priv->napi[RAVB_BE]);
2259 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2260
2261 /* Enable MagicPacket */
2262 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2263
2264 return enable_irq_wake(priv->emac_irq);
2265}
2266
2267static int ravb_wol_restore(struct net_device *ndev)
2268{
2269 struct ravb_private *priv = netdev_priv(ndev);
2270 int ret;
2271
2272 napi_enable(&priv->napi[RAVB_NC]);
2273 napi_enable(&priv->napi[RAVB_BE]);
2274
2275 /* Disable MagicPacket */
2276 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2277
2278 ret = ravb_close(ndev);
2279 if (ret < 0)
2280 return ret;
2281
2282 return disable_irq_wake(priv->emac_irq);
2283}
2284
2285static int __maybe_unused ravb_suspend(struct device *dev)
2286{
2287 struct net_device *ndev = dev_get_drvdata(dev);
2288 struct ravb_private *priv = netdev_priv(ndev);
2289 int ret;
2290
2291 if (!netif_running(ndev))
2292 return 0;
2293
2294 netif_device_detach(ndev);
2295
2296 if (priv->wol_enabled)
2297 ret = ravb_wol_setup(ndev);
2298 else
2299 ret = ravb_close(ndev);
2300
2301 return ret;
2302}
2303
2304static int __maybe_unused ravb_resume(struct device *dev)
2305{
2306 struct net_device *ndev = dev_get_drvdata(dev);
2307 struct ravb_private *priv = netdev_priv(ndev);
2308 int ret = 0;
2309
2310 /* If WoL is enabled set reset mode to rearm the WoL logic */
2311 if (priv->wol_enabled)
2312 ravb_write(ndev, CCC_OPC_RESET, CCC);
2313
2314 /* All register have been reset to default values.
2315 * Restore all registers which where setup at probe time and
2316 * reopen device if it was running before system suspended.
2317 */
2318
2319 /* Set AVB config mode */
2320 ravb_set_config_mode(ndev);
2321
2322 /* Set GTI value */
2323 ret = ravb_set_gti(ndev);
2324 if (ret)
2325 return ret;
2326
2327 /* Request GTI loading */
2328 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2329
2330 if (priv->chip_id != RCAR_GEN2)
2331 ravb_set_delay_mode(ndev);
2332
2333 /* Restore descriptor base address table */
2334 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2335
2336 if (netif_running(ndev)) {
2337 if (priv->wol_enabled) {
2338 ret = ravb_wol_restore(ndev);
2339 if (ret)
2340 return ret;
2341 }
2342 ret = ravb_open(ndev);
2343 if (ret < 0)
2344 return ret;
2345 netif_device_attach(ndev);
2346 }
2347
2348 return ret;
2349}
2350
2351static int __maybe_unused ravb_runtime_nop(struct device *dev)
2352{
2353 /* Runtime PM callback shared between ->runtime_suspend()
2354 * and ->runtime_resume(). Simply returns success.
2355 *
2356 * This driver re-initializes all registers after
2357 * pm_runtime_get_sync() anyway so there is no need
2358 * to save and restore registers here.
2359 */
2360 return 0;
2361}
2362
2363static const struct dev_pm_ops ravb_dev_pm_ops = {
2364 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2365 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2366};
2367
2368static struct platform_driver ravb_driver = {
2369 .probe = ravb_probe,
2370 .remove = ravb_remove,
2371 .driver = {
2372 .name = "ravb",
2373 .pm = &ravb_dev_pm_ops,
2374 .of_match_table = ravb_match_table,
2375 },
2376};
2377
2378module_platform_driver(ravb_driver);
2379
2380MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2381MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2382MODULE_LICENSE("GPL v2");