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1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 */
34
35/** Includes *******************************************************************
36*******************************************************************************/
37
38#include <linux/init.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/errno.h>
42#include <linux/err.h>
43#include <linux/interrupt.h>
44#include <linux/delay.h>
45#include <linux/i2c.h>
46#include <linux/io.h>
47#include <linux/sched.h>
48#include <linux/platform_device.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51
52#include <mach/irqs.h>
53#include <mach/hardware.h>
54#include <mach/i2c.h>
55
56/** Defines ********************************************************************
57*******************************************************************************/
58
59/* This will be the driver name the kernel reports */
60#define DRIVER_NAME "imx-i2c"
61
62/* Default value */
63#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
64
65/* IMX I2C registers */
66#define IMX_I2C_IADR 0x00 /* i2c slave address */
67#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
68#define IMX_I2C_I2CR 0x08 /* i2c control */
69#define IMX_I2C_I2SR 0x0C /* i2c status */
70#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
71
72/* Bits of IMX I2C registers */
73#define I2SR_RXAK 0x01
74#define I2SR_IIF 0x02
75#define I2SR_SRW 0x04
76#define I2SR_IAL 0x10
77#define I2SR_IBB 0x20
78#define I2SR_IAAS 0x40
79#define I2SR_ICF 0x80
80#define I2CR_RSTA 0x04
81#define I2CR_TXAK 0x08
82#define I2CR_MTX 0x10
83#define I2CR_MSTA 0x20
84#define I2CR_IIEN 0x40
85#define I2CR_IEN 0x80
86
87/** Variables ******************************************************************
88*******************************************************************************/
89
90/*
91 * sorted list of clock divider, register value pairs
92 * taken from table 26-5, p.26-9, Freescale i.MX
93 * Integrated Portable System Processor Reference Manual
94 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
95 *
96 * Duplicated divider values removed from list
97 */
98
99static u16 __initdata i2c_clk_div[50][2] = {
100 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
101 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
102 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
103 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
104 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
105 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
106 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
107 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
108 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
109 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
110 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
111 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
112 { 3072, 0x1E }, { 3840, 0x1F }
113};
114
115struct imx_i2c_struct {
116 struct i2c_adapter adapter;
117 struct resource *res;
118 struct clk *clk;
119 void __iomem *base;
120 int irq;
121 wait_queue_head_t queue;
122 unsigned long i2csr;
123 unsigned int disable_delay;
124 int stopped;
125 unsigned int ifdr; /* IMX_I2C_IFDR */
126};
127
128/** Functions for IMX I2C adapter driver ***************************************
129*******************************************************************************/
130
131static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
132{
133 unsigned long orig_jiffies = jiffies;
134 unsigned int temp;
135
136 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
137
138 while (1) {
139 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
140 if (for_busy && (temp & I2SR_IBB))
141 break;
142 if (!for_busy && !(temp & I2SR_IBB))
143 break;
144 if (signal_pending(current)) {
145 dev_dbg(&i2c_imx->adapter.dev,
146 "<%s> I2C Interrupted\n", __func__);
147 return -EINTR;
148 }
149 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
150 dev_dbg(&i2c_imx->adapter.dev,
151 "<%s> I2C bus is busy\n", __func__);
152 return -ETIMEDOUT;
153 }
154 schedule();
155 }
156
157 return 0;
158}
159
160static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
161{
162 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
163
164 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
165 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
166 return -ETIMEDOUT;
167 }
168 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
169 i2c_imx->i2csr = 0;
170 return 0;
171}
172
173static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
174{
175 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
176 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
177 return -EIO; /* No ACK */
178 }
179
180 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
181 return 0;
182}
183
184static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
185{
186 unsigned int temp = 0;
187 int result;
188
189 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
190
191 clk_enable(i2c_imx->clk);
192 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
193 /* Enable I2C controller */
194 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
195 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
196
197 /* Wait controller to be stable */
198 udelay(50);
199
200 /* Start I2C transaction */
201 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
202 temp |= I2CR_MSTA;
203 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
204 result = i2c_imx_bus_busy(i2c_imx, 1);
205 if (result)
206 return result;
207 i2c_imx->stopped = 0;
208
209 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
210 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
211 return result;
212}
213
214static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
215{
216 unsigned int temp = 0;
217
218 if (!i2c_imx->stopped) {
219 /* Stop I2C transaction */
220 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
221 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
222 temp &= ~(I2CR_MSTA | I2CR_MTX);
223 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
224 }
225 if (cpu_is_mx1()) {
226 /*
227 * This delay caused by an i.MXL hardware bug.
228 * If no (or too short) delay, no "STOP" bit will be generated.
229 */
230 udelay(i2c_imx->disable_delay);
231 }
232
233 if (!i2c_imx->stopped) {
234 i2c_imx_bus_busy(i2c_imx, 0);
235 i2c_imx->stopped = 1;
236 }
237
238 /* Disable I2C controller */
239 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
240 clk_disable(i2c_imx->clk);
241}
242
243static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
244 unsigned int rate)
245{
246 unsigned int i2c_clk_rate;
247 unsigned int div;
248 int i;
249
250 /* Divider value calculation */
251 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
252 div = (i2c_clk_rate + rate - 1) / rate;
253 if (div < i2c_clk_div[0][0])
254 i = 0;
255 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
256 i = ARRAY_SIZE(i2c_clk_div) - 1;
257 else
258 for (i = 0; i2c_clk_div[i][0] < div; i++);
259
260 /* Store divider value */
261 i2c_imx->ifdr = i2c_clk_div[i][1];
262
263 /*
264 * There dummy delay is calculated.
265 * It should be about one I2C clock period long.
266 * This delay is used in I2C bus disable function
267 * to fix chip hardware bug.
268 */
269 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
270 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
271
272 /* dev_dbg() can't be used, because adapter is not yet registered */
273#ifdef CONFIG_I2C_DEBUG_BUS
274 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
275 __func__, i2c_clk_rate, div);
276 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
277 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
278#endif
279}
280
281static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
282{
283 struct imx_i2c_struct *i2c_imx = dev_id;
284 unsigned int temp;
285
286 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
287 if (temp & I2SR_IIF) {
288 /* save status register */
289 i2c_imx->i2csr = temp;
290 temp &= ~I2SR_IIF;
291 writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
292 wake_up(&i2c_imx->queue);
293 return IRQ_HANDLED;
294 }
295
296 return IRQ_NONE;
297}
298
299static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
300{
301 int i, result;
302
303 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
304 __func__, msgs->addr << 1);
305
306 /* write slave address */
307 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
308 result = i2c_imx_trx_complete(i2c_imx);
309 if (result)
310 return result;
311 result = i2c_imx_acked(i2c_imx);
312 if (result)
313 return result;
314 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
315
316 /* write data */
317 for (i = 0; i < msgs->len; i++) {
318 dev_dbg(&i2c_imx->adapter.dev,
319 "<%s> write byte: B%d=0x%X\n",
320 __func__, i, msgs->buf[i]);
321 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
322 result = i2c_imx_trx_complete(i2c_imx);
323 if (result)
324 return result;
325 result = i2c_imx_acked(i2c_imx);
326 if (result)
327 return result;
328 }
329 return 0;
330}
331
332static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
333{
334 int i, result;
335 unsigned int temp;
336
337 dev_dbg(&i2c_imx->adapter.dev,
338 "<%s> write slave address: addr=0x%x\n",
339 __func__, (msgs->addr << 1) | 0x01);
340
341 /* write slave address */
342 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
343 result = i2c_imx_trx_complete(i2c_imx);
344 if (result)
345 return result;
346 result = i2c_imx_acked(i2c_imx);
347 if (result)
348 return result;
349
350 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
351
352 /* setup bus to read data */
353 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
354 temp &= ~I2CR_MTX;
355 if (msgs->len - 1)
356 temp &= ~I2CR_TXAK;
357 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
358 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
359
360 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
361
362 /* read data */
363 for (i = 0; i < msgs->len; i++) {
364 result = i2c_imx_trx_complete(i2c_imx);
365 if (result)
366 return result;
367 if (i == (msgs->len - 1)) {
368 /* It must generate STOP before read I2DR to prevent
369 controller from generating another clock cycle */
370 dev_dbg(&i2c_imx->adapter.dev,
371 "<%s> clear MSTA\n", __func__);
372 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
373 temp &= ~(I2CR_MSTA | I2CR_MTX);
374 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
375 i2c_imx_bus_busy(i2c_imx, 0);
376 i2c_imx->stopped = 1;
377 } else if (i == (msgs->len - 2)) {
378 dev_dbg(&i2c_imx->adapter.dev,
379 "<%s> set TXAK\n", __func__);
380 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
381 temp |= I2CR_TXAK;
382 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
383 }
384 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
385 dev_dbg(&i2c_imx->adapter.dev,
386 "<%s> read byte: B%d=0x%X\n",
387 __func__, i, msgs->buf[i]);
388 }
389 return 0;
390}
391
392static int i2c_imx_xfer(struct i2c_adapter *adapter,
393 struct i2c_msg *msgs, int num)
394{
395 unsigned int i, temp;
396 int result;
397 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
398
399 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
400
401 /* Start I2C transfer */
402 result = i2c_imx_start(i2c_imx);
403 if (result)
404 goto fail0;
405
406 /* read/write data */
407 for (i = 0; i < num; i++) {
408 if (i) {
409 dev_dbg(&i2c_imx->adapter.dev,
410 "<%s> repeated start\n", __func__);
411 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
412 temp |= I2CR_RSTA;
413 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
414 result = i2c_imx_bus_busy(i2c_imx, 1);
415 if (result)
416 goto fail0;
417 }
418 dev_dbg(&i2c_imx->adapter.dev,
419 "<%s> transfer message: %d\n", __func__, i);
420 /* write/read data */
421#ifdef CONFIG_I2C_DEBUG_BUS
422 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
423 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
424 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
425 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
426 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
427 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
428 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
429 dev_dbg(&i2c_imx->adapter.dev,
430 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
431 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
432 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
433 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
434 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
435 (temp & I2SR_RXAK ? 1 : 0));
436#endif
437 if (msgs[i].flags & I2C_M_RD)
438 result = i2c_imx_read(i2c_imx, &msgs[i]);
439 else
440 result = i2c_imx_write(i2c_imx, &msgs[i]);
441 if (result)
442 goto fail0;
443 }
444
445fail0:
446 /* Stop I2C transfer */
447 i2c_imx_stop(i2c_imx);
448
449 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
450 (result < 0) ? "error" : "success msg",
451 (result < 0) ? result : num);
452 return (result < 0) ? result : num;
453}
454
455static u32 i2c_imx_func(struct i2c_adapter *adapter)
456{
457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
458}
459
460static struct i2c_algorithm i2c_imx_algo = {
461 .master_xfer = i2c_imx_xfer,
462 .functionality = i2c_imx_func,
463};
464
465static int __init i2c_imx_probe(struct platform_device *pdev)
466{
467 struct imx_i2c_struct *i2c_imx;
468 struct resource *res;
469 struct imxi2c_platform_data *pdata;
470 void __iomem *base;
471 resource_size_t res_size;
472 int irq;
473 int ret;
474
475 dev_dbg(&pdev->dev, "<%s>\n", __func__);
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 if (!res) {
479 dev_err(&pdev->dev, "can't get device resources\n");
480 return -ENOENT;
481 }
482 irq = platform_get_irq(pdev, 0);
483 if (irq < 0) {
484 dev_err(&pdev->dev, "can't get irq number\n");
485 return -ENOENT;
486 }
487
488 pdata = pdev->dev.platform_data;
489
490 if (pdata && pdata->init) {
491 ret = pdata->init(&pdev->dev);
492 if (ret)
493 return ret;
494 }
495
496 res_size = resource_size(res);
497
498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
499 ret = -EBUSY;
500 goto fail0;
501 }
502
503 base = ioremap(res->start, res_size);
504 if (!base) {
505 dev_err(&pdev->dev, "ioremap failed\n");
506 ret = -EIO;
507 goto fail1;
508 }
509
510 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
511 if (!i2c_imx) {
512 dev_err(&pdev->dev, "can't allocate interface\n");
513 ret = -ENOMEM;
514 goto fail2;
515 }
516
517 /* Setup i2c_imx driver structure */
518 strcpy(i2c_imx->adapter.name, pdev->name);
519 i2c_imx->adapter.owner = THIS_MODULE;
520 i2c_imx->adapter.algo = &i2c_imx_algo;
521 i2c_imx->adapter.dev.parent = &pdev->dev;
522 i2c_imx->adapter.nr = pdev->id;
523 i2c_imx->irq = irq;
524 i2c_imx->base = base;
525 i2c_imx->res = res;
526
527 /* Get I2C clock */
528 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
529 if (IS_ERR(i2c_imx->clk)) {
530 ret = PTR_ERR(i2c_imx->clk);
531 dev_err(&pdev->dev, "can't get I2C clock\n");
532 goto fail3;
533 }
534
535 /* Request IRQ */
536 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
537 if (ret) {
538 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
539 goto fail4;
540 }
541
542 /* Init queue */
543 init_waitqueue_head(&i2c_imx->queue);
544
545 /* Set up adapter data */
546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
547
548 /* Set up clock divider */
549 if (pdata && pdata->bitrate)
550 i2c_imx_set_clk(i2c_imx, pdata->bitrate);
551 else
552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
553
554 /* Set up chip registers to defaults */
555 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
556 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
557
558 /* Add I2C adapter */
559 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
560 if (ret < 0) {
561 dev_err(&pdev->dev, "registration failed\n");
562 goto fail5;
563 }
564
565 /* Set up platform driver data */
566 platform_set_drvdata(pdev, i2c_imx);
567
568 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
569 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
570 i2c_imx->res->start, i2c_imx->res->end);
571 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
572 res_size, i2c_imx->res->start);
573 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
574 i2c_imx->adapter.name);
575 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
576
577 return 0; /* Return OK */
578
579fail5:
580 free_irq(i2c_imx->irq, i2c_imx);
581fail4:
582 clk_put(i2c_imx->clk);
583fail3:
584 kfree(i2c_imx);
585fail2:
586 iounmap(base);
587fail1:
588 release_mem_region(res->start, resource_size(res));
589fail0:
590 if (pdata && pdata->exit)
591 pdata->exit(&pdev->dev);
592 return ret; /* Return error number */
593}
594
595static int __exit i2c_imx_remove(struct platform_device *pdev)
596{
597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
599
600 /* remove adapter */
601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
602 i2c_del_adapter(&i2c_imx->adapter);
603 platform_set_drvdata(pdev, NULL);
604
605 /* free interrupt */
606 free_irq(i2c_imx->irq, i2c_imx);
607
608 /* setup chip registers to defaults */
609 writeb(0, i2c_imx->base + IMX_I2C_IADR);
610 writeb(0, i2c_imx->base + IMX_I2C_IFDR);
611 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
612 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
613
614 /* Shut down hardware */
615 if (pdata && pdata->exit)
616 pdata->exit(&pdev->dev);
617
618 clk_put(i2c_imx->clk);
619
620 iounmap(i2c_imx->base);
621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
622 kfree(i2c_imx);
623 return 0;
624}
625
626static struct platform_driver i2c_imx_driver = {
627 .remove = __exit_p(i2c_imx_remove),
628 .driver = {
629 .name = DRIVER_NAME,
630 .owner = THIS_MODULE,
631 }
632};
633
634static int __init i2c_adap_imx_init(void)
635{
636 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
637}
638subsys_initcall(i2c_adap_imx_init);
639
640static void __exit i2c_adap_imx_exit(void)
641{
642 platform_driver_unregister(&i2c_imx_driver);
643}
644module_exit(i2c_adap_imx_exit);
645
646MODULE_LICENSE("GPL");
647MODULE_AUTHOR("Darius Augulis");
648MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
649MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 * Copyright 2020 NXP
21 *
22 */
23
24#include <linux/acpi.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmaengine.h>
30#include <linux/dmapool.h>
31#include <linux/err.h>
32#include <linux/errno.h>
33#include <linux/gpio/consumer.h>
34#include <linux/i2c.h>
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/io.h>
38#include <linux/iopoll.h>
39#include <linux/kernel.h>
40#include <linux/spinlock.h>
41#include <linux/hrtimer.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/of_device.h>
45#include <linux/of_dma.h>
46#include <linux/pinctrl/consumer.h>
47#include <linux/platform_data/i2c-imx.h>
48#include <linux/platform_device.h>
49#include <linux/pm_runtime.h>
50#include <linux/sched.h>
51#include <linux/slab.h>
52
53/* This will be the driver name the kernel reports */
54#define DRIVER_NAME "imx-i2c"
55
56#define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
57
58/*
59 * Enable DMA if transfer byte size is bigger than this threshold.
60 * As the hardware request, it must bigger than 4 bytes.\
61 * I have set '16' here, maybe it's not the best but I think it's
62 * the appropriate.
63 */
64#define DMA_THRESHOLD 16
65#define DMA_TIMEOUT 1000
66
67/* IMX I2C registers:
68 * the I2C register offset is different between SoCs,
69 * to provide support for all these chips, split the
70 * register offset into a fixed base address and a
71 * variable shift value, then the full register offset
72 * will be calculated by
73 * reg_off = ( reg_base_addr << reg_shift)
74 */
75#define IMX_I2C_IADR 0x00 /* i2c slave address */
76#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
77#define IMX_I2C_I2CR 0x02 /* i2c control */
78#define IMX_I2C_I2SR 0x03 /* i2c status */
79#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
80
81/*
82 * All of the layerscape series SoCs support IBIC register.
83 */
84#define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
85
86#define IMX_I2C_REGSHIFT 2
87#define VF610_I2C_REGSHIFT 0
88
89/* Bits of IMX I2C registers */
90#define I2SR_RXAK 0x01
91#define I2SR_IIF 0x02
92#define I2SR_SRW 0x04
93#define I2SR_IAL 0x10
94#define I2SR_IBB 0x20
95#define I2SR_IAAS 0x40
96#define I2SR_ICF 0x80
97#define I2CR_DMAEN 0x02
98#define I2CR_RSTA 0x04
99#define I2CR_TXAK 0x08
100#define I2CR_MTX 0x10
101#define I2CR_MSTA 0x20
102#define I2CR_IIEN 0x40
103#define I2CR_IEN 0x80
104#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
105
106/* register bits different operating codes definition:
107 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
108 * - write zero to clear(w0c) INT flag on i.MX,
109 * - but write one to clear(w1c) INT flag on Vybrid.
110 * 2) I2CR: I2C module enable operation also differ between SoCs:
111 * - set I2CR_IEN bit enable the module on i.MX,
112 * - but clear I2CR_IEN bit enable the module on Vybrid.
113 */
114#define I2SR_CLR_OPCODE_W0C 0x0
115#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
116#define I2CR_IEN_OPCODE_0 0x0
117#define I2CR_IEN_OPCODE_1 I2CR_IEN
118
119#define I2C_PM_TIMEOUT 10 /* ms */
120
121/*
122 * sorted list of clock divider, register value pairs
123 * taken from table 26-5, p.26-9, Freescale i.MX
124 * Integrated Portable System Processor Reference Manual
125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
126 *
127 * Duplicated divider values removed from list
128 */
129struct imx_i2c_clk_pair {
130 u16 div;
131 u16 val;
132};
133
134static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
147 { 3072, 0x1E }, { 3840, 0x1F }
148};
149
150/* Vybrid VF610 clock divider, register value pairs */
151static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
167};
168
169enum imx_i2c_type {
170 IMX1_I2C,
171 IMX21_I2C,
172 VF610_I2C,
173};
174
175struct imx_i2c_hwdata {
176 enum imx_i2c_type devtype;
177 unsigned int regshift;
178 struct imx_i2c_clk_pair *clk_div;
179 unsigned int ndivs;
180 unsigned int i2sr_clr_opcode;
181 unsigned int i2cr_ien_opcode;
182 /*
183 * Errata ERR007805 or e7805:
184 * I2C: When the I2C clock speed is configured for 400 kHz,
185 * the SCL low period violates the I2C spec of 1.3 uS min.
186 */
187 bool has_err007805;
188};
189
190struct imx_i2c_dma {
191 struct dma_chan *chan_tx;
192 struct dma_chan *chan_rx;
193 struct dma_chan *chan_using;
194 struct completion cmd_complete;
195 dma_addr_t dma_buf;
196 unsigned int dma_len;
197 enum dma_transfer_direction dma_transfer_dir;
198 enum dma_data_direction dma_data_dir;
199};
200
201struct imx_i2c_struct {
202 struct i2c_adapter adapter;
203 struct clk *clk;
204 struct notifier_block clk_change_nb;
205 void __iomem *base;
206 wait_queue_head_t queue;
207 unsigned long i2csr;
208 unsigned int disable_delay;
209 int stopped;
210 unsigned int ifdr; /* IMX_I2C_IFDR */
211 unsigned int cur_clk;
212 unsigned int bitrate;
213 const struct imx_i2c_hwdata *hwdata;
214 struct i2c_bus_recovery_info rinfo;
215
216 struct pinctrl *pinctrl;
217 struct pinctrl_state *pinctrl_pins_default;
218 struct pinctrl_state *pinctrl_pins_gpio;
219
220 struct imx_i2c_dma *dma;
221 struct i2c_client *slave;
222 enum i2c_slave_event last_slave_event;
223
224 /* For checking slave events. */
225 spinlock_t slave_lock;
226 struct hrtimer slave_timer;
227};
228
229static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
230 .devtype = IMX1_I2C,
231 .regshift = IMX_I2C_REGSHIFT,
232 .clk_div = imx_i2c_clk_div,
233 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
234 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
235 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
236
237};
238
239static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
240 .devtype = IMX21_I2C,
241 .regshift = IMX_I2C_REGSHIFT,
242 .clk_div = imx_i2c_clk_div,
243 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
244 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
245 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
246
247};
248
249static const struct imx_i2c_hwdata imx6_i2c_hwdata = {
250 .devtype = IMX21_I2C,
251 .regshift = IMX_I2C_REGSHIFT,
252 .clk_div = imx_i2c_clk_div,
253 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
254 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
255 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
256 .has_err007805 = true,
257};
258
259static struct imx_i2c_hwdata vf610_i2c_hwdata = {
260 .devtype = VF610_I2C,
261 .regshift = VF610_I2C_REGSHIFT,
262 .clk_div = vf610_i2c_clk_div,
263 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
264 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
265 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
266
267};
268
269static const struct platform_device_id imx_i2c_devtype[] = {
270 {
271 .name = "imx1-i2c",
272 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
273 }, {
274 .name = "imx21-i2c",
275 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
276 }, {
277 /* sentinel */
278 }
279};
280MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
281
282static const struct of_device_id i2c_imx_dt_ids[] = {
283 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
284 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
285 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
286 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
287 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
288 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
289 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
290 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
291 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
292 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
293 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
294 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
295 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
296 { /* sentinel */ }
297};
298MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
299
300static const struct acpi_device_id i2c_imx_acpi_ids[] = {
301 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
302 { }
303};
304MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
305
306static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
307{
308 return i2c_imx->hwdata->devtype == IMX1_I2C;
309}
310
311static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
312{
313 return i2c_imx->hwdata->devtype == VF610_I2C;
314}
315
316static inline void imx_i2c_write_reg(unsigned int val,
317 struct imx_i2c_struct *i2c_imx, unsigned int reg)
318{
319 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
320}
321
322static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
323 unsigned int reg)
324{
325 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
326}
327
328static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
329{
330 unsigned int temp;
331
332 /*
333 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
334 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
335 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
336 */
337 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
338 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
339}
340
341/* Set up i2c controller register and i2c status register to default value. */
342static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
343{
344 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
345 i2c_imx, IMX_I2C_I2CR);
346 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
347}
348
349/* Functions for DMA support */
350static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
351 dma_addr_t phy_addr)
352{
353 struct imx_i2c_dma *dma;
354 struct dma_slave_config dma_sconfig;
355 struct device *dev = &i2c_imx->adapter.dev;
356 int ret;
357
358 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
359 if (!dma)
360 return;
361
362 dma->chan_tx = dma_request_chan(dev, "tx");
363 if (IS_ERR(dma->chan_tx)) {
364 ret = PTR_ERR(dma->chan_tx);
365 if (ret != -ENODEV && ret != -EPROBE_DEFER)
366 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
367 goto fail_al;
368 }
369
370 dma_sconfig.dst_addr = phy_addr +
371 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
372 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
373 dma_sconfig.dst_maxburst = 1;
374 dma_sconfig.direction = DMA_MEM_TO_DEV;
375 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
376 if (ret < 0) {
377 dev_err(dev, "can't configure tx channel (%d)\n", ret);
378 goto fail_tx;
379 }
380
381 dma->chan_rx = dma_request_chan(dev, "rx");
382 if (IS_ERR(dma->chan_rx)) {
383 ret = PTR_ERR(dma->chan_rx);
384 if (ret != -ENODEV && ret != -EPROBE_DEFER)
385 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
386 goto fail_tx;
387 }
388
389 dma_sconfig.src_addr = phy_addr +
390 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
391 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
392 dma_sconfig.src_maxburst = 1;
393 dma_sconfig.direction = DMA_DEV_TO_MEM;
394 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
395 if (ret < 0) {
396 dev_err(dev, "can't configure rx channel (%d)\n", ret);
397 goto fail_rx;
398 }
399
400 i2c_imx->dma = dma;
401 init_completion(&dma->cmd_complete);
402 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
403 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
404
405 return;
406
407fail_rx:
408 dma_release_channel(dma->chan_rx);
409fail_tx:
410 dma_release_channel(dma->chan_tx);
411fail_al:
412 devm_kfree(dev, dma);
413}
414
415static void i2c_imx_dma_callback(void *arg)
416{
417 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
418 struct imx_i2c_dma *dma = i2c_imx->dma;
419
420 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
421 dma->dma_len, dma->dma_data_dir);
422 complete(&dma->cmd_complete);
423}
424
425static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
426 struct i2c_msg *msgs)
427{
428 struct imx_i2c_dma *dma = i2c_imx->dma;
429 struct dma_async_tx_descriptor *txdesc;
430 struct device *dev = &i2c_imx->adapter.dev;
431 struct device *chan_dev = dma->chan_using->device->dev;
432
433 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
434 dma->dma_len, dma->dma_data_dir);
435 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
436 dev_err(dev, "DMA mapping failed\n");
437 goto err_map;
438 }
439
440 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
441 dma->dma_len, dma->dma_transfer_dir,
442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
443 if (!txdesc) {
444 dev_err(dev, "Not able to get desc for DMA xfer\n");
445 goto err_desc;
446 }
447
448 reinit_completion(&dma->cmd_complete);
449 txdesc->callback = i2c_imx_dma_callback;
450 txdesc->callback_param = i2c_imx;
451 if (dma_submit_error(dmaengine_submit(txdesc))) {
452 dev_err(dev, "DMA submit failed\n");
453 goto err_submit;
454 }
455
456 dma_async_issue_pending(dma->chan_using);
457 return 0;
458
459err_submit:
460 dmaengine_terminate_sync(dma->chan_using);
461err_desc:
462 dma_unmap_single(chan_dev, dma->dma_buf,
463 dma->dma_len, dma->dma_data_dir);
464err_map:
465 return -EINVAL;
466}
467
468static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
469{
470 struct imx_i2c_dma *dma = i2c_imx->dma;
471
472 dma->dma_buf = 0;
473 dma->dma_len = 0;
474
475 dma_release_channel(dma->chan_tx);
476 dma->chan_tx = NULL;
477
478 dma_release_channel(dma->chan_rx);
479 dma->chan_rx = NULL;
480
481 dma->chan_using = NULL;
482}
483
484static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
485{
486 unsigned long orig_jiffies = jiffies;
487 unsigned int temp;
488
489 while (1) {
490 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
491
492 /* check for arbitration lost */
493 if (temp & I2SR_IAL) {
494 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
495 return -EAGAIN;
496 }
497
498 if (for_busy && (temp & I2SR_IBB)) {
499 i2c_imx->stopped = 0;
500 break;
501 }
502 if (!for_busy && !(temp & I2SR_IBB)) {
503 i2c_imx->stopped = 1;
504 break;
505 }
506 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
507 dev_dbg(&i2c_imx->adapter.dev,
508 "<%s> I2C bus is busy\n", __func__);
509 return -ETIMEDOUT;
510 }
511 if (atomic)
512 udelay(100);
513 else
514 schedule();
515 }
516
517 return 0;
518}
519
520static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
521{
522 if (atomic) {
523 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
524 unsigned int regval;
525
526 /*
527 * The formula for the poll timeout is documented in the RM
528 * Rev.5 on page 1878:
529 * T_min = 10/F_scl
530 * Set the value hard as it is done for the non-atomic use-case.
531 * Use 10 kHz for the calculation since this is the minimum
532 * allowed SMBus frequency. Also add an offset of 100us since it
533 * turned out that the I2SR_IIF bit isn't set correctly within
534 * the minimum timeout in polling mode.
535 */
536 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
537 i2c_imx->i2csr = regval;
538 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
539 } else {
540 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
541 }
542
543 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
544 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
545 return -ETIMEDOUT;
546 }
547
548 /* check for arbitration lost */
549 if (i2c_imx->i2csr & I2SR_IAL) {
550 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
551 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
552
553 i2c_imx->i2csr = 0;
554 return -EAGAIN;
555 }
556
557 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
558 i2c_imx->i2csr = 0;
559 return 0;
560}
561
562static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
563{
564 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
565 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
566 return -ENXIO; /* No ACK */
567 }
568
569 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
570 return 0;
571}
572
573static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
574 unsigned int i2c_clk_rate)
575{
576 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
577 unsigned int div;
578 int i;
579
580 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
581 dev_dbg(&i2c_imx->adapter.dev,
582 "SoC errata ERR007805 or e7805 applies, bus frequency limited from %d Hz to 384000 Hz.\n",
583 i2c_imx->bitrate);
584 i2c_imx->bitrate = 384000;
585 }
586
587 /* Divider value calculation */
588 if (i2c_imx->cur_clk == i2c_clk_rate)
589 return;
590
591 i2c_imx->cur_clk = i2c_clk_rate;
592
593 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
594 if (div < i2c_clk_div[0].div)
595 i = 0;
596 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
597 i = i2c_imx->hwdata->ndivs - 1;
598 else
599 for (i = 0; i2c_clk_div[i].div < div; i++)
600 ;
601
602 /* Store divider value */
603 i2c_imx->ifdr = i2c_clk_div[i].val;
604
605 /*
606 * There dummy delay is calculated.
607 * It should be about one I2C clock period long.
608 * This delay is used in I2C bus disable function
609 * to fix chip hardware bug.
610 */
611 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
612 i2c_clk_rate / 2);
613
614#ifdef CONFIG_I2C_DEBUG_BUS
615 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
616 i2c_clk_rate, div);
617 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
618 i2c_clk_div[i].val, i2c_clk_div[i].div);
619#endif
620}
621
622static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
623 unsigned long action, void *data)
624{
625 struct clk_notifier_data *ndata = data;
626 struct imx_i2c_struct *i2c_imx = container_of(nb,
627 struct imx_i2c_struct,
628 clk_change_nb);
629
630 if (action & POST_RATE_CHANGE)
631 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
632
633 return NOTIFY_OK;
634}
635
636static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
637{
638 unsigned int temp = 0;
639 int result;
640
641 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
642 /* Enable I2C controller */
643 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
644 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
645
646 /* Wait controller to be stable */
647 if (atomic)
648 udelay(50);
649 else
650 usleep_range(50, 150);
651
652 /* Start I2C transaction */
653 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
654 temp |= I2CR_MSTA;
655 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
656 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
657 if (result)
658 return result;
659
660 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
661 if (atomic)
662 temp &= ~I2CR_IIEN; /* Disable interrupt */
663
664 temp &= ~I2CR_DMAEN;
665 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
666 return result;
667}
668
669static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
670{
671 unsigned int temp = 0;
672
673 if (!i2c_imx->stopped) {
674 /* Stop I2C transaction */
675 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
676 if (!(temp & I2CR_MSTA))
677 i2c_imx->stopped = 1;
678 temp &= ~(I2CR_MSTA | I2CR_MTX);
679 if (i2c_imx->dma)
680 temp &= ~I2CR_DMAEN;
681 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
682 }
683 if (is_imx1_i2c(i2c_imx)) {
684 /*
685 * This delay caused by an i.MXL hardware bug.
686 * If no (or too short) delay, no "STOP" bit will be generated.
687 */
688 udelay(i2c_imx->disable_delay);
689 }
690
691 if (!i2c_imx->stopped)
692 i2c_imx_bus_busy(i2c_imx, 0, atomic);
693
694 /* Disable I2C controller */
695 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
696 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
697}
698
699/*
700 * Enable bus idle interrupts
701 * Note: IBIC register will be cleared after disabled i2c module.
702 * All of layerscape series SoCs support IBIC register.
703 */
704static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
705{
706 if (is_vf610_i2c(i2c_imx)) {
707 unsigned int temp;
708
709 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
710 temp |= IBIC_BIIE;
711 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
712 }
713}
714
715static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
716 enum i2c_slave_event event, u8 *val)
717{
718 i2c_slave_event(i2c_imx->slave, event, val);
719 i2c_imx->last_slave_event = event;
720}
721
722static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
723{
724 u8 val = 0;
725
726 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
727 switch (i2c_imx->last_slave_event) {
728 case I2C_SLAVE_READ_REQUESTED:
729 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
730 &val);
731 break;
732
733 case I2C_SLAVE_WRITE_REQUESTED:
734 case I2C_SLAVE_READ_PROCESSED:
735 case I2C_SLAVE_WRITE_RECEIVED:
736 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
737 break;
738
739 case I2C_SLAVE_STOP:
740 break;
741 }
742 }
743}
744
745/* Returns true if the timer should be restarted, false if not. */
746static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
747 unsigned int status, unsigned int ctl)
748{
749 u8 value = 0;
750
751 if (status & I2SR_IAL) { /* Arbitration lost */
752 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
753 if (!(status & I2SR_IAAS))
754 return IRQ_HANDLED;
755 }
756
757 if (!(status & I2SR_IBB)) {
758 /* No master on the bus, that could mean a stop condition. */
759 i2c_imx_slave_finish_op(i2c_imx);
760 return IRQ_HANDLED;
761 }
762
763 if (!(status & I2SR_ICF))
764 /* Data transfer still in progress, ignore this. */
765 goto out;
766
767 if (status & I2SR_IAAS) { /* Addressed as a slave */
768 i2c_imx_slave_finish_op(i2c_imx);
769 if (status & I2SR_SRW) { /* Master wants to read from us*/
770 dev_dbg(&i2c_imx->adapter.dev, "read requested");
771 i2c_imx_slave_event(i2c_imx,
772 I2C_SLAVE_READ_REQUESTED, &value);
773
774 /* Slave transmit */
775 ctl |= I2CR_MTX;
776 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
777
778 /* Send data */
779 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
780 } else { /* Master wants to write to us */
781 dev_dbg(&i2c_imx->adapter.dev, "write requested");
782 i2c_imx_slave_event(i2c_imx,
783 I2C_SLAVE_WRITE_REQUESTED, &value);
784
785 /* Slave receive */
786 ctl &= ~I2CR_MTX;
787 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
788 /* Dummy read */
789 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
790 }
791 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
792 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
793 i2c_imx_slave_event(i2c_imx,
794 I2C_SLAVE_WRITE_RECEIVED, &value);
795 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
796 ctl |= I2CR_MTX;
797 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
798
799 i2c_imx_slave_event(i2c_imx,
800 I2C_SLAVE_READ_PROCESSED, &value);
801
802 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
803 } else { /* Transmit mode received NAK, operation is done */
804 ctl &= ~I2CR_MTX;
805 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
806 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
807 i2c_imx_slave_finish_op(i2c_imx);
808 return IRQ_HANDLED;
809 }
810
811out:
812 /*
813 * No need to check the return value here. If it returns 0 or
814 * 1, then everything is fine. If it returns -1, then the
815 * timer is running in the handler. This will still work,
816 * though it may be redone (or already have been done) by the
817 * timer function.
818 */
819 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
820 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
821 hrtimer_restart(&i2c_imx->slave_timer);
822 return IRQ_HANDLED;
823}
824
825static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
826{
827 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
828 slave_timer);
829 unsigned int ctl, status;
830 unsigned long flags;
831
832 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
833 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
834 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
835 i2c_imx_slave_handle(i2c_imx, status, ctl);
836 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
837 return HRTIMER_NORESTART;
838}
839
840static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
841{
842 int temp;
843
844 /* Set slave addr. */
845 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
846
847 i2c_imx_reset_regs(i2c_imx);
848
849 /* Enable module */
850 temp = i2c_imx->hwdata->i2cr_ien_opcode;
851 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
852
853 /* Enable interrupt from i2c module */
854 temp |= I2CR_IIEN;
855 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
856
857 i2c_imx_enable_bus_idle(i2c_imx);
858}
859
860static int i2c_imx_reg_slave(struct i2c_client *client)
861{
862 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
863 int ret;
864
865 if (i2c_imx->slave)
866 return -EBUSY;
867
868 i2c_imx->slave = client;
869 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
870
871 /* Resume */
872 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
873 if (ret < 0) {
874 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
875 return ret;
876 }
877
878 i2c_imx_slave_init(i2c_imx);
879
880 return 0;
881}
882
883static int i2c_imx_unreg_slave(struct i2c_client *client)
884{
885 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
886 int ret;
887
888 if (!i2c_imx->slave)
889 return -EINVAL;
890
891 /* Reset slave address. */
892 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
893
894 i2c_imx_reset_regs(i2c_imx);
895
896 i2c_imx->slave = NULL;
897
898 /* Suspend */
899 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
900 if (ret < 0)
901 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
902
903 return ret;
904}
905
906static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
907{
908 /* save status register */
909 i2c_imx->i2csr = status;
910 wake_up(&i2c_imx->queue);
911
912 return IRQ_HANDLED;
913}
914
915static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
916{
917 struct imx_i2c_struct *i2c_imx = dev_id;
918 unsigned int ctl, status;
919 unsigned long flags;
920
921 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
922 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
923 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
924
925 if (status & I2SR_IIF) {
926 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
927 if (i2c_imx->slave) {
928 if (!(ctl & I2CR_MSTA)) {
929 irqreturn_t ret;
930
931 ret = i2c_imx_slave_handle(i2c_imx,
932 status, ctl);
933 spin_unlock_irqrestore(&i2c_imx->slave_lock,
934 flags);
935 return ret;
936 }
937 i2c_imx_slave_finish_op(i2c_imx);
938 }
939 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
940 return i2c_imx_master_isr(i2c_imx, status);
941 }
942 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
943
944 return IRQ_NONE;
945}
946
947static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
948 struct i2c_msg *msgs)
949{
950 int result;
951 unsigned long time_left;
952 unsigned int temp = 0;
953 unsigned long orig_jiffies = jiffies;
954 struct imx_i2c_dma *dma = i2c_imx->dma;
955 struct device *dev = &i2c_imx->adapter.dev;
956
957 dma->chan_using = dma->chan_tx;
958 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
959 dma->dma_data_dir = DMA_TO_DEVICE;
960 dma->dma_len = msgs->len - 1;
961 result = i2c_imx_dma_xfer(i2c_imx, msgs);
962 if (result)
963 return result;
964
965 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
966 temp |= I2CR_DMAEN;
967 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
968
969 /*
970 * Write slave address.
971 * The first byte must be transmitted by the CPU.
972 */
973 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
974 time_left = wait_for_completion_timeout(
975 &i2c_imx->dma->cmd_complete,
976 msecs_to_jiffies(DMA_TIMEOUT));
977 if (time_left == 0) {
978 dmaengine_terminate_sync(dma->chan_using);
979 return -ETIMEDOUT;
980 }
981
982 /* Waiting for transfer complete. */
983 while (1) {
984 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
985 if (temp & I2SR_ICF)
986 break;
987 if (time_after(jiffies, orig_jiffies +
988 msecs_to_jiffies(DMA_TIMEOUT))) {
989 dev_dbg(dev, "<%s> Timeout\n", __func__);
990 return -ETIMEDOUT;
991 }
992 schedule();
993 }
994
995 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
996 temp &= ~I2CR_DMAEN;
997 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
998
999 /* The last data byte must be transferred by the CPU. */
1000 imx_i2c_write_reg(msgs->buf[msgs->len-1],
1001 i2c_imx, IMX_I2C_I2DR);
1002 result = i2c_imx_trx_complete(i2c_imx, false);
1003 if (result)
1004 return result;
1005
1006 return i2c_imx_acked(i2c_imx);
1007}
1008
1009static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
1010 struct i2c_msg *msgs, bool is_lastmsg)
1011{
1012 int result;
1013 unsigned long time_left;
1014 unsigned int temp;
1015 unsigned long orig_jiffies = jiffies;
1016 struct imx_i2c_dma *dma = i2c_imx->dma;
1017 struct device *dev = &i2c_imx->adapter.dev;
1018
1019
1020 dma->chan_using = dma->chan_rx;
1021 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1022 dma->dma_data_dir = DMA_FROM_DEVICE;
1023 /* The last two data bytes must be transferred by the CPU. */
1024 dma->dma_len = msgs->len - 2;
1025 result = i2c_imx_dma_xfer(i2c_imx, msgs);
1026 if (result)
1027 return result;
1028
1029 time_left = wait_for_completion_timeout(
1030 &i2c_imx->dma->cmd_complete,
1031 msecs_to_jiffies(DMA_TIMEOUT));
1032 if (time_left == 0) {
1033 dmaengine_terminate_sync(dma->chan_using);
1034 return -ETIMEDOUT;
1035 }
1036
1037 /* waiting for transfer complete. */
1038 while (1) {
1039 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1040 if (temp & I2SR_ICF)
1041 break;
1042 if (time_after(jiffies, orig_jiffies +
1043 msecs_to_jiffies(DMA_TIMEOUT))) {
1044 dev_dbg(dev, "<%s> Timeout\n", __func__);
1045 return -ETIMEDOUT;
1046 }
1047 schedule();
1048 }
1049
1050 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1051 temp &= ~I2CR_DMAEN;
1052 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1053
1054 /* read n-1 byte data */
1055 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1056 temp |= I2CR_TXAK;
1057 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1058
1059 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1060 /* read n byte data */
1061 result = i2c_imx_trx_complete(i2c_imx, false);
1062 if (result)
1063 return result;
1064
1065 if (is_lastmsg) {
1066 /*
1067 * It must generate STOP before read I2DR to prevent
1068 * controller from generating another clock cycle
1069 */
1070 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1071 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1072 if (!(temp & I2CR_MSTA))
1073 i2c_imx->stopped = 1;
1074 temp &= ~(I2CR_MSTA | I2CR_MTX);
1075 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1076 if (!i2c_imx->stopped)
1077 i2c_imx_bus_busy(i2c_imx, 0, false);
1078 } else {
1079 /*
1080 * For i2c master receiver repeat restart operation like:
1081 * read -> repeat MSTA -> read/write
1082 * The controller must set MTX before read the last byte in
1083 * the first read operation, otherwise the first read cost
1084 * one extra clock cycle.
1085 */
1086 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1087 temp |= I2CR_MTX;
1088 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1089 }
1090 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1091
1092 return 0;
1093}
1094
1095static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1096 bool atomic)
1097{
1098 int i, result;
1099
1100 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1101 __func__, i2c_8bit_addr_from_msg(msgs));
1102
1103 /* write slave address */
1104 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1105 result = i2c_imx_trx_complete(i2c_imx, atomic);
1106 if (result)
1107 return result;
1108 result = i2c_imx_acked(i2c_imx);
1109 if (result)
1110 return result;
1111 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1112
1113 /* write data */
1114 for (i = 0; i < msgs->len; i++) {
1115 dev_dbg(&i2c_imx->adapter.dev,
1116 "<%s> write byte: B%d=0x%X\n",
1117 __func__, i, msgs->buf[i]);
1118 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1119 result = i2c_imx_trx_complete(i2c_imx, atomic);
1120 if (result)
1121 return result;
1122 result = i2c_imx_acked(i2c_imx);
1123 if (result)
1124 return result;
1125 }
1126 return 0;
1127}
1128
1129static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1130 bool is_lastmsg, bool atomic)
1131{
1132 int i, result;
1133 unsigned int temp;
1134 int block_data = msgs->flags & I2C_M_RECV_LEN;
1135 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&
1136 msgs->len >= DMA_THRESHOLD && !block_data;
1137
1138 dev_dbg(&i2c_imx->adapter.dev,
1139 "<%s> write slave address: addr=0x%x\n",
1140 __func__, i2c_8bit_addr_from_msg(msgs));
1141
1142 /* write slave address */
1143 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1144 result = i2c_imx_trx_complete(i2c_imx, atomic);
1145 if (result)
1146 return result;
1147 result = i2c_imx_acked(i2c_imx);
1148 if (result)
1149 return result;
1150
1151 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1152
1153 /* setup bus to read data */
1154 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1155 temp &= ~I2CR_MTX;
1156
1157 /*
1158 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1159 * length is unknown
1160 */
1161 if ((msgs->len - 1) || block_data)
1162 temp &= ~I2CR_TXAK;
1163 if (use_dma)
1164 temp |= I2CR_DMAEN;
1165 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1166 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1167
1168 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1169
1170 if (use_dma)
1171 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
1172
1173 /* read data */
1174 for (i = 0; i < msgs->len; i++) {
1175 u8 len = 0;
1176
1177 result = i2c_imx_trx_complete(i2c_imx, atomic);
1178 if (result)
1179 return result;
1180 /*
1181 * First byte is the length of remaining packet
1182 * in the SMBus block data read. Add it to
1183 * msgs->len.
1184 */
1185 if ((!i) && block_data) {
1186 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1187 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1188 return -EPROTO;
1189 dev_dbg(&i2c_imx->adapter.dev,
1190 "<%s> read length: 0x%X\n",
1191 __func__, len);
1192 msgs->len += len;
1193 }
1194 if (i == (msgs->len - 1)) {
1195 if (is_lastmsg) {
1196 /*
1197 * It must generate STOP before read I2DR to prevent
1198 * controller from generating another clock cycle
1199 */
1200 dev_dbg(&i2c_imx->adapter.dev,
1201 "<%s> clear MSTA\n", __func__);
1202 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1203 if (!(temp & I2CR_MSTA))
1204 i2c_imx->stopped = 1;
1205 temp &= ~(I2CR_MSTA | I2CR_MTX);
1206 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1207 if (!i2c_imx->stopped)
1208 i2c_imx_bus_busy(i2c_imx, 0, atomic);
1209 } else {
1210 /*
1211 * For i2c master receiver repeat restart operation like:
1212 * read -> repeat MSTA -> read/write
1213 * The controller must set MTX before read the last byte in
1214 * the first read operation, otherwise the first read cost
1215 * one extra clock cycle.
1216 */
1217 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1218 temp |= I2CR_MTX;
1219 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1220 }
1221 } else if (i == (msgs->len - 2)) {
1222 dev_dbg(&i2c_imx->adapter.dev,
1223 "<%s> set TXAK\n", __func__);
1224 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1225 temp |= I2CR_TXAK;
1226 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1227 }
1228 if ((!i) && block_data)
1229 msgs->buf[0] = len;
1230 else
1231 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1232 dev_dbg(&i2c_imx->adapter.dev,
1233 "<%s> read byte: B%d=0x%X\n",
1234 __func__, i, msgs->buf[i]);
1235 }
1236 return 0;
1237}
1238
1239static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1240 struct i2c_msg *msgs, int num, bool atomic)
1241{
1242 unsigned int i, temp;
1243 int result;
1244 bool is_lastmsg = false;
1245 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1246
1247 /* Start I2C transfer */
1248 result = i2c_imx_start(i2c_imx, atomic);
1249 if (result) {
1250 /*
1251 * Bus recovery uses gpiod_get_value_cansleep() which is not
1252 * allowed within atomic context.
1253 */
1254 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1255 i2c_recover_bus(&i2c_imx->adapter);
1256 result = i2c_imx_start(i2c_imx, atomic);
1257 }
1258 }
1259
1260 if (result)
1261 goto fail0;
1262
1263 /* read/write data */
1264 for (i = 0; i < num; i++) {
1265 if (i == num - 1)
1266 is_lastmsg = true;
1267
1268 if (i) {
1269 dev_dbg(&i2c_imx->adapter.dev,
1270 "<%s> repeated start\n", __func__);
1271 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1272 temp |= I2CR_RSTA;
1273 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1274 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1275 if (result)
1276 goto fail0;
1277 }
1278 dev_dbg(&i2c_imx->adapter.dev,
1279 "<%s> transfer message: %d\n", __func__, i);
1280 /* write/read data */
1281#ifdef CONFIG_I2C_DEBUG_BUS
1282 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1283 dev_dbg(&i2c_imx->adapter.dev,
1284 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1285 __func__,
1286 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1287 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1288 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1289 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1290 dev_dbg(&i2c_imx->adapter.dev,
1291 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1292 __func__,
1293 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1294 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1295 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1296 (temp & I2SR_RXAK ? 1 : 0));
1297#endif
1298 if (msgs[i].flags & I2C_M_RD) {
1299 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
1300 } else {
1301 if (!atomic &&
1302 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1303 msgs[i].flags & I2C_M_DMA_SAFE)
1304 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1305 else
1306 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1307 }
1308 if (result)
1309 goto fail0;
1310 }
1311
1312fail0:
1313 /* Stop I2C transfer */
1314 i2c_imx_stop(i2c_imx, atomic);
1315
1316 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1317 (result < 0) ? "error" : "success msg",
1318 (result < 0) ? result : num);
1319 /* After data is transferred, switch to slave mode(as a receiver) */
1320 if (i2c_imx->slave)
1321 i2c_imx_slave_init(i2c_imx);
1322
1323 return (result < 0) ? result : num;
1324}
1325
1326static int i2c_imx_xfer(struct i2c_adapter *adapter,
1327 struct i2c_msg *msgs, int num)
1328{
1329 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1330 int result;
1331
1332 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1333 if (result < 0)
1334 return result;
1335
1336 result = i2c_imx_xfer_common(adapter, msgs, num, false);
1337
1338 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1339 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1340
1341 return result;
1342}
1343
1344static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1345 struct i2c_msg *msgs, int num)
1346{
1347 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1348 int result;
1349
1350 result = clk_enable(i2c_imx->clk);
1351 if (result)
1352 return result;
1353
1354 result = i2c_imx_xfer_common(adapter, msgs, num, true);
1355
1356 clk_disable(i2c_imx->clk);
1357
1358 return result;
1359}
1360
1361static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1362{
1363 struct imx_i2c_struct *i2c_imx;
1364
1365 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1366
1367 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1368}
1369
1370static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1371{
1372 struct imx_i2c_struct *i2c_imx;
1373
1374 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1375
1376 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1377}
1378
1379/*
1380 * We switch SCL and SDA to their GPIO function and do some bitbanging
1381 * for bus recovery. These alternative pinmux settings can be
1382 * described in the device tree by a separate pinctrl state "gpio". If
1383 * this is missing this is not a big problem, the only implication is
1384 * that we can't do bus recovery.
1385 */
1386static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1387 struct platform_device *pdev)
1388{
1389 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1390
1391 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1392 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1393 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1394 return PTR_ERR(i2c_imx->pinctrl);
1395 }
1396
1397 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1398 PINCTRL_STATE_DEFAULT);
1399 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1400 "gpio");
1401 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1402 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1403
1404 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1405 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1406 return -EPROBE_DEFER;
1407 } else if (IS_ERR(rinfo->sda_gpiod) ||
1408 IS_ERR(rinfo->scl_gpiod) ||
1409 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1410 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1411 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1412 return 0;
1413 }
1414
1415 dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1416 rinfo->sda_gpiod ? ",sda" : "");
1417
1418 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1419 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1420 rinfo->recover_bus = i2c_generic_scl_recovery;
1421 i2c_imx->adapter.bus_recovery_info = rinfo;
1422
1423 return 0;
1424}
1425
1426static u32 i2c_imx_func(struct i2c_adapter *adapter)
1427{
1428 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1429 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1430}
1431
1432static const struct i2c_algorithm i2c_imx_algo = {
1433 .master_xfer = i2c_imx_xfer,
1434 .master_xfer_atomic = i2c_imx_xfer_atomic,
1435 .functionality = i2c_imx_func,
1436 .reg_slave = i2c_imx_reg_slave,
1437 .unreg_slave = i2c_imx_unreg_slave,
1438};
1439
1440static int i2c_imx_probe(struct platform_device *pdev)
1441{
1442 struct imx_i2c_struct *i2c_imx;
1443 struct resource *res;
1444 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1445 void __iomem *base;
1446 int irq, ret;
1447 dma_addr_t phy_addr;
1448 const struct imx_i2c_hwdata *match;
1449
1450 irq = platform_get_irq(pdev, 0);
1451 if (irq < 0)
1452 return irq;
1453
1454 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1455 if (IS_ERR(base))
1456 return PTR_ERR(base);
1457
1458 phy_addr = (dma_addr_t)res->start;
1459 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1460 if (!i2c_imx)
1461 return -ENOMEM;
1462
1463 spin_lock_init(&i2c_imx->slave_lock);
1464 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1465 i2c_imx->slave_timer.function = i2c_imx_slave_timeout;
1466
1467 match = device_get_match_data(&pdev->dev);
1468 if (match)
1469 i2c_imx->hwdata = match;
1470 else
1471 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1472 platform_get_device_id(pdev)->driver_data;
1473
1474 /* Setup i2c_imx driver structure */
1475 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1476 i2c_imx->adapter.owner = THIS_MODULE;
1477 i2c_imx->adapter.algo = &i2c_imx_algo;
1478 i2c_imx->adapter.dev.parent = &pdev->dev;
1479 i2c_imx->adapter.nr = pdev->id;
1480 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1481 i2c_imx->base = base;
1482 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1483
1484 /* Get I2C clock */
1485 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1486 if (IS_ERR(i2c_imx->clk))
1487 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1488 "can't get I2C clock\n");
1489
1490 ret = clk_prepare_enable(i2c_imx->clk);
1491 if (ret) {
1492 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1493 return ret;
1494 }
1495
1496 /* Init queue */
1497 init_waitqueue_head(&i2c_imx->queue);
1498
1499 /* Set up adapter data */
1500 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1501
1502 /* Set up platform driver data */
1503 platform_set_drvdata(pdev, i2c_imx);
1504
1505 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1506 pm_runtime_use_autosuspend(&pdev->dev);
1507 pm_runtime_set_active(&pdev->dev);
1508 pm_runtime_enable(&pdev->dev);
1509
1510 ret = pm_runtime_get_sync(&pdev->dev);
1511 if (ret < 0)
1512 goto rpm_disable;
1513
1514 /* Request IRQ */
1515 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1516 pdev->name, i2c_imx);
1517 if (ret) {
1518 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1519 goto rpm_disable;
1520 }
1521
1522 /* Set up clock divider */
1523 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1524 ret = of_property_read_u32(pdev->dev.of_node,
1525 "clock-frequency", &i2c_imx->bitrate);
1526 if (ret < 0 && pdata && pdata->bitrate)
1527 i2c_imx->bitrate = pdata->bitrate;
1528 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1529 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1530 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1531
1532 i2c_imx_reset_regs(i2c_imx);
1533
1534 /* Init optional bus recovery function */
1535 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1536 /* Give it another chance if pinctrl used is not ready yet */
1537 if (ret == -EPROBE_DEFER)
1538 goto clk_notifier_unregister;
1539
1540 /* Add I2C adapter */
1541 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1542 if (ret < 0)
1543 goto clk_notifier_unregister;
1544
1545 pm_runtime_mark_last_busy(&pdev->dev);
1546 pm_runtime_put_autosuspend(&pdev->dev);
1547
1548 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1549 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1550 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1551 i2c_imx->adapter.name);
1552 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1553
1554 /* Init DMA config if supported */
1555 i2c_imx_dma_request(i2c_imx, phy_addr);
1556
1557 return 0; /* Return OK */
1558
1559clk_notifier_unregister:
1560 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1561 free_irq(irq, i2c_imx);
1562rpm_disable:
1563 pm_runtime_put_noidle(&pdev->dev);
1564 pm_runtime_disable(&pdev->dev);
1565 pm_runtime_set_suspended(&pdev->dev);
1566 pm_runtime_dont_use_autosuspend(&pdev->dev);
1567 clk_disable_unprepare(i2c_imx->clk);
1568 return ret;
1569}
1570
1571static int i2c_imx_remove(struct platform_device *pdev)
1572{
1573 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1574 int irq, ret;
1575
1576 ret = pm_runtime_get_sync(&pdev->dev);
1577
1578 hrtimer_cancel(&i2c_imx->slave_timer);
1579
1580 /* remove adapter */
1581 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1582 i2c_del_adapter(&i2c_imx->adapter);
1583
1584 if (i2c_imx->dma)
1585 i2c_imx_dma_free(i2c_imx);
1586
1587 if (ret >= 0) {
1588 /* setup chip registers to defaults */
1589 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1590 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1591 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1592 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1593 clk_disable(i2c_imx->clk);
1594 }
1595
1596 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1597 irq = platform_get_irq(pdev, 0);
1598 if (irq >= 0)
1599 free_irq(irq, i2c_imx);
1600
1601 clk_unprepare(i2c_imx->clk);
1602
1603 pm_runtime_put_noidle(&pdev->dev);
1604 pm_runtime_disable(&pdev->dev);
1605
1606 return 0;
1607}
1608
1609static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1610{
1611 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1612
1613 clk_disable(i2c_imx->clk);
1614
1615 return 0;
1616}
1617
1618static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1619{
1620 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1621 int ret;
1622
1623 ret = clk_enable(i2c_imx->clk);
1624 if (ret)
1625 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1626
1627 return ret;
1628}
1629
1630static const struct dev_pm_ops i2c_imx_pm_ops = {
1631 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1632 i2c_imx_runtime_resume, NULL)
1633};
1634
1635static struct platform_driver i2c_imx_driver = {
1636 .probe = i2c_imx_probe,
1637 .remove = i2c_imx_remove,
1638 .driver = {
1639 .name = DRIVER_NAME,
1640 .pm = &i2c_imx_pm_ops,
1641 .of_match_table = i2c_imx_dt_ids,
1642 .acpi_match_table = i2c_imx_acpi_ids,
1643 },
1644 .id_table = imx_i2c_devtype,
1645};
1646
1647static int __init i2c_adap_imx_init(void)
1648{
1649 return platform_driver_register(&i2c_imx_driver);
1650}
1651subsys_initcall(i2c_adap_imx_init);
1652
1653static void __exit i2c_adap_imx_exit(void)
1654{
1655 platform_driver_unregister(&i2c_imx_driver);
1656}
1657module_exit(i2c_adap_imx_exit);
1658
1659MODULE_LICENSE("GPL");
1660MODULE_AUTHOR("Darius Augulis");
1661MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1662MODULE_ALIAS("platform:" DRIVER_NAME);