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1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 */
34
35/** Includes *******************************************************************
36*******************************************************************************/
37
38#include <linux/init.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/errno.h>
42#include <linux/err.h>
43#include <linux/interrupt.h>
44#include <linux/delay.h>
45#include <linux/i2c.h>
46#include <linux/io.h>
47#include <linux/sched.h>
48#include <linux/platform_device.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51
52#include <mach/irqs.h>
53#include <mach/hardware.h>
54#include <mach/i2c.h>
55
56/** Defines ********************************************************************
57*******************************************************************************/
58
59/* This will be the driver name the kernel reports */
60#define DRIVER_NAME "imx-i2c"
61
62/* Default value */
63#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
64
65/* IMX I2C registers */
66#define IMX_I2C_IADR 0x00 /* i2c slave address */
67#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
68#define IMX_I2C_I2CR 0x08 /* i2c control */
69#define IMX_I2C_I2SR 0x0C /* i2c status */
70#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
71
72/* Bits of IMX I2C registers */
73#define I2SR_RXAK 0x01
74#define I2SR_IIF 0x02
75#define I2SR_SRW 0x04
76#define I2SR_IAL 0x10
77#define I2SR_IBB 0x20
78#define I2SR_IAAS 0x40
79#define I2SR_ICF 0x80
80#define I2CR_RSTA 0x04
81#define I2CR_TXAK 0x08
82#define I2CR_MTX 0x10
83#define I2CR_MSTA 0x20
84#define I2CR_IIEN 0x40
85#define I2CR_IEN 0x80
86
87/** Variables ******************************************************************
88*******************************************************************************/
89
90/*
91 * sorted list of clock divider, register value pairs
92 * taken from table 26-5, p.26-9, Freescale i.MX
93 * Integrated Portable System Processor Reference Manual
94 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
95 *
96 * Duplicated divider values removed from list
97 */
98
99static u16 __initdata i2c_clk_div[50][2] = {
100 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
101 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
102 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
103 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
104 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
105 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
106 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
107 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
108 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
109 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
110 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
111 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
112 { 3072, 0x1E }, { 3840, 0x1F }
113};
114
115struct imx_i2c_struct {
116 struct i2c_adapter adapter;
117 struct resource *res;
118 struct clk *clk;
119 void __iomem *base;
120 int irq;
121 wait_queue_head_t queue;
122 unsigned long i2csr;
123 unsigned int disable_delay;
124 int stopped;
125 unsigned int ifdr; /* IMX_I2C_IFDR */
126};
127
128/** Functions for IMX I2C adapter driver ***************************************
129*******************************************************************************/
130
131static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
132{
133 unsigned long orig_jiffies = jiffies;
134 unsigned int temp;
135
136 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
137
138 while (1) {
139 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
140 if (for_busy && (temp & I2SR_IBB))
141 break;
142 if (!for_busy && !(temp & I2SR_IBB))
143 break;
144 if (signal_pending(current)) {
145 dev_dbg(&i2c_imx->adapter.dev,
146 "<%s> I2C Interrupted\n", __func__);
147 return -EINTR;
148 }
149 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
150 dev_dbg(&i2c_imx->adapter.dev,
151 "<%s> I2C bus is busy\n", __func__);
152 return -ETIMEDOUT;
153 }
154 schedule();
155 }
156
157 return 0;
158}
159
160static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
161{
162 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
163
164 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
165 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
166 return -ETIMEDOUT;
167 }
168 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
169 i2c_imx->i2csr = 0;
170 return 0;
171}
172
173static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
174{
175 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
176 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
177 return -EIO; /* No ACK */
178 }
179
180 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
181 return 0;
182}
183
184static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
185{
186 unsigned int temp = 0;
187 int result;
188
189 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
190
191 clk_enable(i2c_imx->clk);
192 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
193 /* Enable I2C controller */
194 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
195 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
196
197 /* Wait controller to be stable */
198 udelay(50);
199
200 /* Start I2C transaction */
201 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
202 temp |= I2CR_MSTA;
203 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
204 result = i2c_imx_bus_busy(i2c_imx, 1);
205 if (result)
206 return result;
207 i2c_imx->stopped = 0;
208
209 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
210 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
211 return result;
212}
213
214static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
215{
216 unsigned int temp = 0;
217
218 if (!i2c_imx->stopped) {
219 /* Stop I2C transaction */
220 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
221 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
222 temp &= ~(I2CR_MSTA | I2CR_MTX);
223 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
224 }
225 if (cpu_is_mx1()) {
226 /*
227 * This delay caused by an i.MXL hardware bug.
228 * If no (or too short) delay, no "STOP" bit will be generated.
229 */
230 udelay(i2c_imx->disable_delay);
231 }
232
233 if (!i2c_imx->stopped) {
234 i2c_imx_bus_busy(i2c_imx, 0);
235 i2c_imx->stopped = 1;
236 }
237
238 /* Disable I2C controller */
239 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
240 clk_disable(i2c_imx->clk);
241}
242
243static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
244 unsigned int rate)
245{
246 unsigned int i2c_clk_rate;
247 unsigned int div;
248 int i;
249
250 /* Divider value calculation */
251 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
252 div = (i2c_clk_rate + rate - 1) / rate;
253 if (div < i2c_clk_div[0][0])
254 i = 0;
255 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
256 i = ARRAY_SIZE(i2c_clk_div) - 1;
257 else
258 for (i = 0; i2c_clk_div[i][0] < div; i++);
259
260 /* Store divider value */
261 i2c_imx->ifdr = i2c_clk_div[i][1];
262
263 /*
264 * There dummy delay is calculated.
265 * It should be about one I2C clock period long.
266 * This delay is used in I2C bus disable function
267 * to fix chip hardware bug.
268 */
269 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
270 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
271
272 /* dev_dbg() can't be used, because adapter is not yet registered */
273#ifdef CONFIG_I2C_DEBUG_BUS
274 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
275 __func__, i2c_clk_rate, div);
276 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
277 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
278#endif
279}
280
281static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
282{
283 struct imx_i2c_struct *i2c_imx = dev_id;
284 unsigned int temp;
285
286 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
287 if (temp & I2SR_IIF) {
288 /* save status register */
289 i2c_imx->i2csr = temp;
290 temp &= ~I2SR_IIF;
291 writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
292 wake_up(&i2c_imx->queue);
293 return IRQ_HANDLED;
294 }
295
296 return IRQ_NONE;
297}
298
299static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
300{
301 int i, result;
302
303 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
304 __func__, msgs->addr << 1);
305
306 /* write slave address */
307 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
308 result = i2c_imx_trx_complete(i2c_imx);
309 if (result)
310 return result;
311 result = i2c_imx_acked(i2c_imx);
312 if (result)
313 return result;
314 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
315
316 /* write data */
317 for (i = 0; i < msgs->len; i++) {
318 dev_dbg(&i2c_imx->adapter.dev,
319 "<%s> write byte: B%d=0x%X\n",
320 __func__, i, msgs->buf[i]);
321 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
322 result = i2c_imx_trx_complete(i2c_imx);
323 if (result)
324 return result;
325 result = i2c_imx_acked(i2c_imx);
326 if (result)
327 return result;
328 }
329 return 0;
330}
331
332static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
333{
334 int i, result;
335 unsigned int temp;
336
337 dev_dbg(&i2c_imx->adapter.dev,
338 "<%s> write slave address: addr=0x%x\n",
339 __func__, (msgs->addr << 1) | 0x01);
340
341 /* write slave address */
342 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
343 result = i2c_imx_trx_complete(i2c_imx);
344 if (result)
345 return result;
346 result = i2c_imx_acked(i2c_imx);
347 if (result)
348 return result;
349
350 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
351
352 /* setup bus to read data */
353 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
354 temp &= ~I2CR_MTX;
355 if (msgs->len - 1)
356 temp &= ~I2CR_TXAK;
357 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
358 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
359
360 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
361
362 /* read data */
363 for (i = 0; i < msgs->len; i++) {
364 result = i2c_imx_trx_complete(i2c_imx);
365 if (result)
366 return result;
367 if (i == (msgs->len - 1)) {
368 /* It must generate STOP before read I2DR to prevent
369 controller from generating another clock cycle */
370 dev_dbg(&i2c_imx->adapter.dev,
371 "<%s> clear MSTA\n", __func__);
372 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
373 temp &= ~(I2CR_MSTA | I2CR_MTX);
374 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
375 i2c_imx_bus_busy(i2c_imx, 0);
376 i2c_imx->stopped = 1;
377 } else if (i == (msgs->len - 2)) {
378 dev_dbg(&i2c_imx->adapter.dev,
379 "<%s> set TXAK\n", __func__);
380 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
381 temp |= I2CR_TXAK;
382 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
383 }
384 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
385 dev_dbg(&i2c_imx->adapter.dev,
386 "<%s> read byte: B%d=0x%X\n",
387 __func__, i, msgs->buf[i]);
388 }
389 return 0;
390}
391
392static int i2c_imx_xfer(struct i2c_adapter *adapter,
393 struct i2c_msg *msgs, int num)
394{
395 unsigned int i, temp;
396 int result;
397 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
398
399 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
400
401 /* Start I2C transfer */
402 result = i2c_imx_start(i2c_imx);
403 if (result)
404 goto fail0;
405
406 /* read/write data */
407 for (i = 0; i < num; i++) {
408 if (i) {
409 dev_dbg(&i2c_imx->adapter.dev,
410 "<%s> repeated start\n", __func__);
411 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
412 temp |= I2CR_RSTA;
413 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
414 result = i2c_imx_bus_busy(i2c_imx, 1);
415 if (result)
416 goto fail0;
417 }
418 dev_dbg(&i2c_imx->adapter.dev,
419 "<%s> transfer message: %d\n", __func__, i);
420 /* write/read data */
421#ifdef CONFIG_I2C_DEBUG_BUS
422 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
423 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
424 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
425 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
426 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
427 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
428 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
429 dev_dbg(&i2c_imx->adapter.dev,
430 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
431 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
432 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
433 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
434 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
435 (temp & I2SR_RXAK ? 1 : 0));
436#endif
437 if (msgs[i].flags & I2C_M_RD)
438 result = i2c_imx_read(i2c_imx, &msgs[i]);
439 else
440 result = i2c_imx_write(i2c_imx, &msgs[i]);
441 if (result)
442 goto fail0;
443 }
444
445fail0:
446 /* Stop I2C transfer */
447 i2c_imx_stop(i2c_imx);
448
449 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
450 (result < 0) ? "error" : "success msg",
451 (result < 0) ? result : num);
452 return (result < 0) ? result : num;
453}
454
455static u32 i2c_imx_func(struct i2c_adapter *adapter)
456{
457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
458}
459
460static struct i2c_algorithm i2c_imx_algo = {
461 .master_xfer = i2c_imx_xfer,
462 .functionality = i2c_imx_func,
463};
464
465static int __init i2c_imx_probe(struct platform_device *pdev)
466{
467 struct imx_i2c_struct *i2c_imx;
468 struct resource *res;
469 struct imxi2c_platform_data *pdata;
470 void __iomem *base;
471 resource_size_t res_size;
472 int irq;
473 int ret;
474
475 dev_dbg(&pdev->dev, "<%s>\n", __func__);
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 if (!res) {
479 dev_err(&pdev->dev, "can't get device resources\n");
480 return -ENOENT;
481 }
482 irq = platform_get_irq(pdev, 0);
483 if (irq < 0) {
484 dev_err(&pdev->dev, "can't get irq number\n");
485 return -ENOENT;
486 }
487
488 pdata = pdev->dev.platform_data;
489
490 if (pdata && pdata->init) {
491 ret = pdata->init(&pdev->dev);
492 if (ret)
493 return ret;
494 }
495
496 res_size = resource_size(res);
497
498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
499 ret = -EBUSY;
500 goto fail0;
501 }
502
503 base = ioremap(res->start, res_size);
504 if (!base) {
505 dev_err(&pdev->dev, "ioremap failed\n");
506 ret = -EIO;
507 goto fail1;
508 }
509
510 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
511 if (!i2c_imx) {
512 dev_err(&pdev->dev, "can't allocate interface\n");
513 ret = -ENOMEM;
514 goto fail2;
515 }
516
517 /* Setup i2c_imx driver structure */
518 strcpy(i2c_imx->adapter.name, pdev->name);
519 i2c_imx->adapter.owner = THIS_MODULE;
520 i2c_imx->adapter.algo = &i2c_imx_algo;
521 i2c_imx->adapter.dev.parent = &pdev->dev;
522 i2c_imx->adapter.nr = pdev->id;
523 i2c_imx->irq = irq;
524 i2c_imx->base = base;
525 i2c_imx->res = res;
526
527 /* Get I2C clock */
528 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
529 if (IS_ERR(i2c_imx->clk)) {
530 ret = PTR_ERR(i2c_imx->clk);
531 dev_err(&pdev->dev, "can't get I2C clock\n");
532 goto fail3;
533 }
534
535 /* Request IRQ */
536 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
537 if (ret) {
538 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
539 goto fail4;
540 }
541
542 /* Init queue */
543 init_waitqueue_head(&i2c_imx->queue);
544
545 /* Set up adapter data */
546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
547
548 /* Set up clock divider */
549 if (pdata && pdata->bitrate)
550 i2c_imx_set_clk(i2c_imx, pdata->bitrate);
551 else
552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
553
554 /* Set up chip registers to defaults */
555 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
556 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
557
558 /* Add I2C adapter */
559 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
560 if (ret < 0) {
561 dev_err(&pdev->dev, "registration failed\n");
562 goto fail5;
563 }
564
565 /* Set up platform driver data */
566 platform_set_drvdata(pdev, i2c_imx);
567
568 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
569 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
570 i2c_imx->res->start, i2c_imx->res->end);
571 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
572 res_size, i2c_imx->res->start);
573 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
574 i2c_imx->adapter.name);
575 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
576
577 return 0; /* Return OK */
578
579fail5:
580 free_irq(i2c_imx->irq, i2c_imx);
581fail4:
582 clk_put(i2c_imx->clk);
583fail3:
584 kfree(i2c_imx);
585fail2:
586 iounmap(base);
587fail1:
588 release_mem_region(res->start, resource_size(res));
589fail0:
590 if (pdata && pdata->exit)
591 pdata->exit(&pdev->dev);
592 return ret; /* Return error number */
593}
594
595static int __exit i2c_imx_remove(struct platform_device *pdev)
596{
597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
599
600 /* remove adapter */
601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
602 i2c_del_adapter(&i2c_imx->adapter);
603 platform_set_drvdata(pdev, NULL);
604
605 /* free interrupt */
606 free_irq(i2c_imx->irq, i2c_imx);
607
608 /* setup chip registers to defaults */
609 writeb(0, i2c_imx->base + IMX_I2C_IADR);
610 writeb(0, i2c_imx->base + IMX_I2C_IFDR);
611 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
612 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
613
614 /* Shut down hardware */
615 if (pdata && pdata->exit)
616 pdata->exit(&pdev->dev);
617
618 clk_put(i2c_imx->clk);
619
620 iounmap(i2c_imx->base);
621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
622 kfree(i2c_imx);
623 return 0;
624}
625
626static struct platform_driver i2c_imx_driver = {
627 .remove = __exit_p(i2c_imx_remove),
628 .driver = {
629 .name = DRIVER_NAME,
630 .owner = THIS_MODULE,
631 }
632};
633
634static int __init i2c_adap_imx_init(void)
635{
636 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
637}
638subsys_initcall(i2c_adap_imx_init);
639
640static void __exit i2c_adap_imx_exit(void)
641{
642 platform_driver_unregister(&i2c_imx_driver);
643}
644module_exit(i2c_adap_imx_exit);
645
646MODULE_LICENSE("GPL");
647MODULE_AUTHOR("Darius Augulis");
648MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
649MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 * Copyright 2013 Freescale Semiconductor, Inc.
34 *
35 */
36
37/** Includes *******************************************************************
38*******************************************************************************/
39
40#include <linux/init.h>
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/errno.h>
44#include <linux/err.h>
45#include <linux/interrupt.h>
46#include <linux/delay.h>
47#include <linux/i2c.h>
48#include <linux/io.h>
49#include <linux/sched.h>
50#include <linux/platform_device.h>
51#include <linux/clk.h>
52#include <linux/slab.h>
53#include <linux/of.h>
54#include <linux/of_device.h>
55#include <linux/platform_data/i2c-imx.h>
56
57/** Defines ********************************************************************
58*******************************************************************************/
59
60/* This will be the driver name the kernel reports */
61#define DRIVER_NAME "imx-i2c"
62
63/* Default value */
64#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
65
66/* IMX I2C registers:
67 * the I2C register offset is different between SoCs,
68 * to provid support for all these chips, split the
69 * register offset into a fixed base address and a
70 * variable shift value, then the full register offset
71 * will be calculated by
72 * reg_off = ( reg_base_addr << reg_shift)
73 */
74#define IMX_I2C_IADR 0x00 /* i2c slave address */
75#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
76#define IMX_I2C_I2CR 0x02 /* i2c control */
77#define IMX_I2C_I2SR 0x03 /* i2c status */
78#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
79
80#define IMX_I2C_REGSHIFT 2
81#define VF610_I2C_REGSHIFT 0
82
83/* Bits of IMX I2C registers */
84#define I2SR_RXAK 0x01
85#define I2SR_IIF 0x02
86#define I2SR_SRW 0x04
87#define I2SR_IAL 0x10
88#define I2SR_IBB 0x20
89#define I2SR_IAAS 0x40
90#define I2SR_ICF 0x80
91#define I2CR_RSTA 0x04
92#define I2CR_TXAK 0x08
93#define I2CR_MTX 0x10
94#define I2CR_MSTA 0x20
95#define I2CR_IIEN 0x40
96#define I2CR_IEN 0x80
97
98/* register bits different operating codes definition:
99 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
100 * - write zero to clear(w0c) INT flag on i.MX,
101 * - but write one to clear(w1c) INT flag on Vybrid.
102 * 2) I2CR: I2C module enable operation also differ between SoCs:
103 * - set I2CR_IEN bit enable the module on i.MX,
104 * - but clear I2CR_IEN bit enable the module on Vybrid.
105 */
106#define I2SR_CLR_OPCODE_W0C 0x0
107#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
108#define I2CR_IEN_OPCODE_0 0x0
109#define I2CR_IEN_OPCODE_1 I2CR_IEN
110
111/** Variables ******************************************************************
112*******************************************************************************/
113
114/*
115 * sorted list of clock divider, register value pairs
116 * taken from table 26-5, p.26-9, Freescale i.MX
117 * Integrated Portable System Processor Reference Manual
118 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
119 *
120 * Duplicated divider values removed from list
121 */
122struct imx_i2c_clk_pair {
123 u16 div;
124 u16 val;
125};
126
127static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
128 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
129 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
130 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
131 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
132 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
133 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
134 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
135 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
136 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
137 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
138 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
139 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
140 { 3072, 0x1E }, { 3840, 0x1F }
141};
142
143/* Vybrid VF610 clock divider, register value pairs */
144static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
145 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
146 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
147 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
148 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
149 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
150 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
151 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
152 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
153 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
154 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
155 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
156 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
157 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
158 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
159 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
160};
161
162enum imx_i2c_type {
163 IMX1_I2C,
164 IMX21_I2C,
165 VF610_I2C,
166};
167
168struct imx_i2c_hwdata {
169 enum imx_i2c_type devtype;
170 unsigned regshift;
171 struct imx_i2c_clk_pair *clk_div;
172 unsigned ndivs;
173 unsigned i2sr_clr_opcode;
174 unsigned i2cr_ien_opcode;
175};
176
177struct imx_i2c_struct {
178 struct i2c_adapter adapter;
179 struct clk *clk;
180 void __iomem *base;
181 wait_queue_head_t queue;
182 unsigned long i2csr;
183 unsigned int disable_delay;
184 int stopped;
185 unsigned int ifdr; /* IMX_I2C_IFDR */
186 const struct imx_i2c_hwdata *hwdata;
187};
188
189static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
190 .devtype = IMX1_I2C,
191 .regshift = IMX_I2C_REGSHIFT,
192 .clk_div = imx_i2c_clk_div,
193 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
194 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
195 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
196
197};
198
199static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
200 .devtype = IMX21_I2C,
201 .regshift = IMX_I2C_REGSHIFT,
202 .clk_div = imx_i2c_clk_div,
203 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
204 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
205 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
206
207};
208
209static struct imx_i2c_hwdata vf610_i2c_hwdata = {
210 .devtype = VF610_I2C,
211 .regshift = VF610_I2C_REGSHIFT,
212 .clk_div = vf610_i2c_clk_div,
213 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
214 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
215 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
216
217};
218
219static struct platform_device_id imx_i2c_devtype[] = {
220 {
221 .name = "imx1-i2c",
222 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
223 }, {
224 .name = "imx21-i2c",
225 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
226 }, {
227 /* sentinel */
228 }
229};
230MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
231
232static const struct of_device_id i2c_imx_dt_ids[] = {
233 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
234 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
235 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
236 { /* sentinel */ }
237};
238MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
239
240static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
241{
242 return i2c_imx->hwdata->devtype == IMX1_I2C;
243}
244
245static inline void imx_i2c_write_reg(unsigned int val,
246 struct imx_i2c_struct *i2c_imx, unsigned int reg)
247{
248 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
249}
250
251static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
252 unsigned int reg)
253{
254 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
255}
256
257/** Functions for IMX I2C adapter driver ***************************************
258*******************************************************************************/
259
260static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
261{
262 unsigned long orig_jiffies = jiffies;
263 unsigned int temp;
264
265 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
266
267 while (1) {
268 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
269 if (for_busy && (temp & I2SR_IBB))
270 break;
271 if (!for_busy && !(temp & I2SR_IBB))
272 break;
273 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
274 dev_dbg(&i2c_imx->adapter.dev,
275 "<%s> I2C bus is busy\n", __func__);
276 return -ETIMEDOUT;
277 }
278 schedule();
279 }
280
281 return 0;
282}
283
284static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
285{
286 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
287
288 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
289 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
290 return -ETIMEDOUT;
291 }
292 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
293 i2c_imx->i2csr = 0;
294 return 0;
295}
296
297static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
298{
299 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
300 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
301 return -EIO; /* No ACK */
302 }
303
304 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
305 return 0;
306}
307
308static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
309{
310 unsigned int temp = 0;
311 int result;
312
313 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
314
315 result = clk_prepare_enable(i2c_imx->clk);
316 if (result)
317 return result;
318 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
319 /* Enable I2C controller */
320 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
321 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
322
323 /* Wait controller to be stable */
324 udelay(50);
325
326 /* Start I2C transaction */
327 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
328 temp |= I2CR_MSTA;
329 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
330 result = i2c_imx_bus_busy(i2c_imx, 1);
331 if (result)
332 return result;
333 i2c_imx->stopped = 0;
334
335 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
336 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
337 return result;
338}
339
340static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
341{
342 unsigned int temp = 0;
343
344 if (!i2c_imx->stopped) {
345 /* Stop I2C transaction */
346 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
347 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
348 temp &= ~(I2CR_MSTA | I2CR_MTX);
349 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
350 }
351 if (is_imx1_i2c(i2c_imx)) {
352 /*
353 * This delay caused by an i.MXL hardware bug.
354 * If no (or too short) delay, no "STOP" bit will be generated.
355 */
356 udelay(i2c_imx->disable_delay);
357 }
358
359 if (!i2c_imx->stopped) {
360 i2c_imx_bus_busy(i2c_imx, 0);
361 i2c_imx->stopped = 1;
362 }
363
364 /* Disable I2C controller */
365 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
366 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
367 clk_disable_unprepare(i2c_imx->clk);
368}
369
370static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
371 unsigned int rate)
372{
373 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
374 unsigned int i2c_clk_rate;
375 unsigned int div;
376 int i;
377
378 /* Divider value calculation */
379 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
380 div = (i2c_clk_rate + rate - 1) / rate;
381 if (div < i2c_clk_div[0].div)
382 i = 0;
383 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
384 i = i2c_imx->hwdata->ndivs - 1;
385 else
386 for (i = 0; i2c_clk_div[i].div < div; i++);
387
388 /* Store divider value */
389 i2c_imx->ifdr = i2c_clk_div[i].val;
390
391 /*
392 * There dummy delay is calculated.
393 * It should be about one I2C clock period long.
394 * This delay is used in I2C bus disable function
395 * to fix chip hardware bug.
396 */
397 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
398 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
399
400 /* dev_dbg() can't be used, because adapter is not yet registered */
401#ifdef CONFIG_I2C_DEBUG_BUS
402 dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
403 __func__, i2c_clk_rate, div);
404 dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
405 __func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
406#endif
407}
408
409static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
410{
411 struct imx_i2c_struct *i2c_imx = dev_id;
412 unsigned int temp;
413
414 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
415 if (temp & I2SR_IIF) {
416 /* save status register */
417 i2c_imx->i2csr = temp;
418 temp &= ~I2SR_IIF;
419 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
420 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
421 wake_up(&i2c_imx->queue);
422 return IRQ_HANDLED;
423 }
424
425 return IRQ_NONE;
426}
427
428static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
429{
430 int i, result;
431
432 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
433 __func__, msgs->addr << 1);
434
435 /* write slave address */
436 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
437 result = i2c_imx_trx_complete(i2c_imx);
438 if (result)
439 return result;
440 result = i2c_imx_acked(i2c_imx);
441 if (result)
442 return result;
443 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
444
445 /* write data */
446 for (i = 0; i < msgs->len; i++) {
447 dev_dbg(&i2c_imx->adapter.dev,
448 "<%s> write byte: B%d=0x%X\n",
449 __func__, i, msgs->buf[i]);
450 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
451 result = i2c_imx_trx_complete(i2c_imx);
452 if (result)
453 return result;
454 result = i2c_imx_acked(i2c_imx);
455 if (result)
456 return result;
457 }
458 return 0;
459}
460
461static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
462{
463 int i, result;
464 unsigned int temp;
465
466 dev_dbg(&i2c_imx->adapter.dev,
467 "<%s> write slave address: addr=0x%x\n",
468 __func__, (msgs->addr << 1) | 0x01);
469
470 /* write slave address */
471 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
472 result = i2c_imx_trx_complete(i2c_imx);
473 if (result)
474 return result;
475 result = i2c_imx_acked(i2c_imx);
476 if (result)
477 return result;
478
479 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
480
481 /* setup bus to read data */
482 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
483 temp &= ~I2CR_MTX;
484 if (msgs->len - 1)
485 temp &= ~I2CR_TXAK;
486 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
487 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
488
489 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
490
491 /* read data */
492 for (i = 0; i < msgs->len; i++) {
493 result = i2c_imx_trx_complete(i2c_imx);
494 if (result)
495 return result;
496 if (i == (msgs->len - 1)) {
497 /* It must generate STOP before read I2DR to prevent
498 controller from generating another clock cycle */
499 dev_dbg(&i2c_imx->adapter.dev,
500 "<%s> clear MSTA\n", __func__);
501 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
502 temp &= ~(I2CR_MSTA | I2CR_MTX);
503 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
504 i2c_imx_bus_busy(i2c_imx, 0);
505 i2c_imx->stopped = 1;
506 } else if (i == (msgs->len - 2)) {
507 dev_dbg(&i2c_imx->adapter.dev,
508 "<%s> set TXAK\n", __func__);
509 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
510 temp |= I2CR_TXAK;
511 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
512 }
513 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
514 dev_dbg(&i2c_imx->adapter.dev,
515 "<%s> read byte: B%d=0x%X\n",
516 __func__, i, msgs->buf[i]);
517 }
518 return 0;
519}
520
521static int i2c_imx_xfer(struct i2c_adapter *adapter,
522 struct i2c_msg *msgs, int num)
523{
524 unsigned int i, temp;
525 int result;
526 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
527
528 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
529
530 /* Start I2C transfer */
531 result = i2c_imx_start(i2c_imx);
532 if (result)
533 goto fail0;
534
535 /* read/write data */
536 for (i = 0; i < num; i++) {
537 if (i) {
538 dev_dbg(&i2c_imx->adapter.dev,
539 "<%s> repeated start\n", __func__);
540 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
541 temp |= I2CR_RSTA;
542 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
543 result = i2c_imx_bus_busy(i2c_imx, 1);
544 if (result)
545 goto fail0;
546 }
547 dev_dbg(&i2c_imx->adapter.dev,
548 "<%s> transfer message: %d\n", __func__, i);
549 /* write/read data */
550#ifdef CONFIG_I2C_DEBUG_BUS
551 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
552 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
553 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
554 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
555 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
556 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
557 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
558 dev_dbg(&i2c_imx->adapter.dev,
559 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
560 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
561 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
562 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
563 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
564 (temp & I2SR_RXAK ? 1 : 0));
565#endif
566 if (msgs[i].flags & I2C_M_RD)
567 result = i2c_imx_read(i2c_imx, &msgs[i]);
568 else
569 result = i2c_imx_write(i2c_imx, &msgs[i]);
570 if (result)
571 goto fail0;
572 }
573
574fail0:
575 /* Stop I2C transfer */
576 i2c_imx_stop(i2c_imx);
577
578 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
579 (result < 0) ? "error" : "success msg",
580 (result < 0) ? result : num);
581 return (result < 0) ? result : num;
582}
583
584static u32 i2c_imx_func(struct i2c_adapter *adapter)
585{
586 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
587}
588
589static struct i2c_algorithm i2c_imx_algo = {
590 .master_xfer = i2c_imx_xfer,
591 .functionality = i2c_imx_func,
592};
593
594static int i2c_imx_probe(struct platform_device *pdev)
595{
596 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
597 &pdev->dev);
598 struct imx_i2c_struct *i2c_imx;
599 struct resource *res;
600 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
601 void __iomem *base;
602 int irq, ret;
603 u32 bitrate;
604
605 dev_dbg(&pdev->dev, "<%s>\n", __func__);
606
607 irq = platform_get_irq(pdev, 0);
608 if (irq < 0) {
609 dev_err(&pdev->dev, "can't get irq number\n");
610 return irq;
611 }
612
613 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
614 base = devm_ioremap_resource(&pdev->dev, res);
615 if (IS_ERR(base))
616 return PTR_ERR(base);
617
618 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
619 GFP_KERNEL);
620 if (!i2c_imx) {
621 dev_err(&pdev->dev, "can't allocate interface\n");
622 return -ENOMEM;
623 }
624
625 if (of_id)
626 i2c_imx->hwdata = of_id->data;
627 else
628 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
629 platform_get_device_id(pdev)->driver_data;
630
631 /* Setup i2c_imx driver structure */
632 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
633 i2c_imx->adapter.owner = THIS_MODULE;
634 i2c_imx->adapter.algo = &i2c_imx_algo;
635 i2c_imx->adapter.dev.parent = &pdev->dev;
636 i2c_imx->adapter.nr = pdev->id;
637 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
638 i2c_imx->base = base;
639
640 /* Get I2C clock */
641 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
642 if (IS_ERR(i2c_imx->clk)) {
643 dev_err(&pdev->dev, "can't get I2C clock\n");
644 return PTR_ERR(i2c_imx->clk);
645 }
646
647 ret = clk_prepare_enable(i2c_imx->clk);
648 if (ret) {
649 dev_err(&pdev->dev, "can't enable I2C clock\n");
650 return ret;
651 }
652 /* Request IRQ */
653 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
654 pdev->name, i2c_imx);
655 if (ret) {
656 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
657 return ret;
658 }
659
660 /* Init queue */
661 init_waitqueue_head(&i2c_imx->queue);
662
663 /* Set up adapter data */
664 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
665
666 /* Set up clock divider */
667 bitrate = IMX_I2C_BIT_RATE;
668 ret = of_property_read_u32(pdev->dev.of_node,
669 "clock-frequency", &bitrate);
670 if (ret < 0 && pdata && pdata->bitrate)
671 bitrate = pdata->bitrate;
672 i2c_imx_set_clk(i2c_imx, bitrate);
673
674 /* Set up chip registers to defaults */
675 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
676 i2c_imx, IMX_I2C_I2CR);
677 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
678
679 /* Add I2C adapter */
680 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
681 if (ret < 0) {
682 dev_err(&pdev->dev, "registration failed\n");
683 return ret;
684 }
685
686 /* Set up platform driver data */
687 platform_set_drvdata(pdev, i2c_imx);
688 clk_disable_unprepare(i2c_imx->clk);
689
690 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
691 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
692 res->start, res->end);
693 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
694 resource_size(res), res->start);
695 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
696 i2c_imx->adapter.name);
697 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
698
699 return 0; /* Return OK */
700}
701
702static int i2c_imx_remove(struct platform_device *pdev)
703{
704 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
705
706 /* remove adapter */
707 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
708 i2c_del_adapter(&i2c_imx->adapter);
709
710 /* setup chip registers to defaults */
711 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
712 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
713 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
714 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
715
716 return 0;
717}
718
719static struct platform_driver i2c_imx_driver = {
720 .probe = i2c_imx_probe,
721 .remove = i2c_imx_remove,
722 .driver = {
723 .name = DRIVER_NAME,
724 .owner = THIS_MODULE,
725 .of_match_table = i2c_imx_dt_ids,
726 },
727 .id_table = imx_i2c_devtype,
728};
729
730static int __init i2c_adap_imx_init(void)
731{
732 return platform_driver_register(&i2c_imx_driver);
733}
734subsys_initcall(i2c_adap_imx_init);
735
736static void __exit i2c_adap_imx_exit(void)
737{
738 platform_driver_unregister(&i2c_imx_driver);
739}
740module_exit(i2c_adap_imx_exit);
741
742MODULE_LICENSE("GPL");
743MODULE_AUTHOR("Darius Augulis");
744MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
745MODULE_ALIAS("platform:" DRIVER_NAME);