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1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 */
34
35/** Includes *******************************************************************
36*******************************************************************************/
37
38#include <linux/init.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/errno.h>
42#include <linux/err.h>
43#include <linux/interrupt.h>
44#include <linux/delay.h>
45#include <linux/i2c.h>
46#include <linux/io.h>
47#include <linux/sched.h>
48#include <linux/platform_device.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51#include <linux/of.h>
52#include <linux/of_device.h>
53#include <linux/of_i2c.h>
54#include <linux/pinctrl/consumer.h>
55
56#include <mach/irqs.h>
57#include <mach/hardware.h>
58#include <mach/i2c.h>
59
60/** Defines ********************************************************************
61*******************************************************************************/
62
63/* This will be the driver name the kernel reports */
64#define DRIVER_NAME "imx-i2c"
65
66/* Default value */
67#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
68
69/* IMX I2C registers */
70#define IMX_I2C_IADR 0x00 /* i2c slave address */
71#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
72#define IMX_I2C_I2CR 0x08 /* i2c control */
73#define IMX_I2C_I2SR 0x0C /* i2c status */
74#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
75
76/* Bits of IMX I2C registers */
77#define I2SR_RXAK 0x01
78#define I2SR_IIF 0x02
79#define I2SR_SRW 0x04
80#define I2SR_IAL 0x10
81#define I2SR_IBB 0x20
82#define I2SR_IAAS 0x40
83#define I2SR_ICF 0x80
84#define I2CR_RSTA 0x04
85#define I2CR_TXAK 0x08
86#define I2CR_MTX 0x10
87#define I2CR_MSTA 0x20
88#define I2CR_IIEN 0x40
89#define I2CR_IEN 0x80
90
91/** Variables ******************************************************************
92*******************************************************************************/
93
94/*
95 * sorted list of clock divider, register value pairs
96 * taken from table 26-5, p.26-9, Freescale i.MX
97 * Integrated Portable System Processor Reference Manual
98 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
99 *
100 * Duplicated divider values removed from list
101 */
102
103static u16 __initdata i2c_clk_div[50][2] = {
104 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
105 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
106 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
107 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
108 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
109 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
110 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
111 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
112 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
113 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
114 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
115 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
116 { 3072, 0x1E }, { 3840, 0x1F }
117};
118
119struct imx_i2c_struct {
120 struct i2c_adapter adapter;
121 struct resource *res;
122 struct clk *clk;
123 void __iomem *base;
124 int irq;
125 wait_queue_head_t queue;
126 unsigned long i2csr;
127 unsigned int disable_delay;
128 int stopped;
129 unsigned int ifdr; /* IMX_I2C_IFDR */
130};
131
132static const struct of_device_id i2c_imx_dt_ids[] = {
133 { .compatible = "fsl,imx1-i2c", },
134 { /* sentinel */ }
135};
136
137/** Functions for IMX I2C adapter driver ***************************************
138*******************************************************************************/
139
140static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
141{
142 unsigned long orig_jiffies = jiffies;
143 unsigned int temp;
144
145 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
146
147 while (1) {
148 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
149 if (for_busy && (temp & I2SR_IBB))
150 break;
151 if (!for_busy && !(temp & I2SR_IBB))
152 break;
153 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
154 dev_dbg(&i2c_imx->adapter.dev,
155 "<%s> I2C bus is busy\n", __func__);
156 return -ETIMEDOUT;
157 }
158 schedule();
159 }
160
161 return 0;
162}
163
164static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
165{
166 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
167
168 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
169 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
170 return -ETIMEDOUT;
171 }
172 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
173 i2c_imx->i2csr = 0;
174 return 0;
175}
176
177static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
178{
179 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
180 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
181 return -EIO; /* No ACK */
182 }
183
184 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
185 return 0;
186}
187
188static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
189{
190 unsigned int temp = 0;
191 int result;
192
193 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
194
195 clk_prepare_enable(i2c_imx->clk);
196 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
197 /* Enable I2C controller */
198 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
199 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
200
201 /* Wait controller to be stable */
202 udelay(50);
203
204 /* Start I2C transaction */
205 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
206 temp |= I2CR_MSTA;
207 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
208 result = i2c_imx_bus_busy(i2c_imx, 1);
209 if (result)
210 return result;
211 i2c_imx->stopped = 0;
212
213 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
214 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
215 return result;
216}
217
218static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
219{
220 unsigned int temp = 0;
221
222 if (!i2c_imx->stopped) {
223 /* Stop I2C transaction */
224 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
225 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
226 temp &= ~(I2CR_MSTA | I2CR_MTX);
227 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
228 }
229 if (cpu_is_mx1()) {
230 /*
231 * This delay caused by an i.MXL hardware bug.
232 * If no (or too short) delay, no "STOP" bit will be generated.
233 */
234 udelay(i2c_imx->disable_delay);
235 }
236
237 if (!i2c_imx->stopped) {
238 i2c_imx_bus_busy(i2c_imx, 0);
239 i2c_imx->stopped = 1;
240 }
241
242 /* Disable I2C controller */
243 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
244 clk_disable_unprepare(i2c_imx->clk);
245}
246
247static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
248 unsigned int rate)
249{
250 unsigned int i2c_clk_rate;
251 unsigned int div;
252 int i;
253
254 /* Divider value calculation */
255 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
256 div = (i2c_clk_rate + rate - 1) / rate;
257 if (div < i2c_clk_div[0][0])
258 i = 0;
259 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
260 i = ARRAY_SIZE(i2c_clk_div) - 1;
261 else
262 for (i = 0; i2c_clk_div[i][0] < div; i++);
263
264 /* Store divider value */
265 i2c_imx->ifdr = i2c_clk_div[i][1];
266
267 /*
268 * There dummy delay is calculated.
269 * It should be about one I2C clock period long.
270 * This delay is used in I2C bus disable function
271 * to fix chip hardware bug.
272 */
273 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
274 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
275
276 /* dev_dbg() can't be used, because adapter is not yet registered */
277#ifdef CONFIG_I2C_DEBUG_BUS
278 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
279 __func__, i2c_clk_rate, div);
280 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
281 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
282#endif
283}
284
285static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
286{
287 struct imx_i2c_struct *i2c_imx = dev_id;
288 unsigned int temp;
289
290 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
291 if (temp & I2SR_IIF) {
292 /* save status register */
293 i2c_imx->i2csr = temp;
294 temp &= ~I2SR_IIF;
295 writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
296 wake_up(&i2c_imx->queue);
297 return IRQ_HANDLED;
298 }
299
300 return IRQ_NONE;
301}
302
303static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
304{
305 int i, result;
306
307 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
308 __func__, msgs->addr << 1);
309
310 /* write slave address */
311 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
312 result = i2c_imx_trx_complete(i2c_imx);
313 if (result)
314 return result;
315 result = i2c_imx_acked(i2c_imx);
316 if (result)
317 return result;
318 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
319
320 /* write data */
321 for (i = 0; i < msgs->len; i++) {
322 dev_dbg(&i2c_imx->adapter.dev,
323 "<%s> write byte: B%d=0x%X\n",
324 __func__, i, msgs->buf[i]);
325 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
326 result = i2c_imx_trx_complete(i2c_imx);
327 if (result)
328 return result;
329 result = i2c_imx_acked(i2c_imx);
330 if (result)
331 return result;
332 }
333 return 0;
334}
335
336static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
337{
338 int i, result;
339 unsigned int temp;
340
341 dev_dbg(&i2c_imx->adapter.dev,
342 "<%s> write slave address: addr=0x%x\n",
343 __func__, (msgs->addr << 1) | 0x01);
344
345 /* write slave address */
346 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
347 result = i2c_imx_trx_complete(i2c_imx);
348 if (result)
349 return result;
350 result = i2c_imx_acked(i2c_imx);
351 if (result)
352 return result;
353
354 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
355
356 /* setup bus to read data */
357 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
358 temp &= ~I2CR_MTX;
359 if (msgs->len - 1)
360 temp &= ~I2CR_TXAK;
361 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
362 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
363
364 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
365
366 /* read data */
367 for (i = 0; i < msgs->len; i++) {
368 result = i2c_imx_trx_complete(i2c_imx);
369 if (result)
370 return result;
371 if (i == (msgs->len - 1)) {
372 /* It must generate STOP before read I2DR to prevent
373 controller from generating another clock cycle */
374 dev_dbg(&i2c_imx->adapter.dev,
375 "<%s> clear MSTA\n", __func__);
376 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
377 temp &= ~(I2CR_MSTA | I2CR_MTX);
378 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
379 i2c_imx_bus_busy(i2c_imx, 0);
380 i2c_imx->stopped = 1;
381 } else if (i == (msgs->len - 2)) {
382 dev_dbg(&i2c_imx->adapter.dev,
383 "<%s> set TXAK\n", __func__);
384 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
385 temp |= I2CR_TXAK;
386 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
387 }
388 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
389 dev_dbg(&i2c_imx->adapter.dev,
390 "<%s> read byte: B%d=0x%X\n",
391 __func__, i, msgs->buf[i]);
392 }
393 return 0;
394}
395
396static int i2c_imx_xfer(struct i2c_adapter *adapter,
397 struct i2c_msg *msgs, int num)
398{
399 unsigned int i, temp;
400 int result;
401 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
402
403 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
404
405 /* Start I2C transfer */
406 result = i2c_imx_start(i2c_imx);
407 if (result)
408 goto fail0;
409
410 /* read/write data */
411 for (i = 0; i < num; i++) {
412 if (i) {
413 dev_dbg(&i2c_imx->adapter.dev,
414 "<%s> repeated start\n", __func__);
415 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
416 temp |= I2CR_RSTA;
417 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
418 result = i2c_imx_bus_busy(i2c_imx, 1);
419 if (result)
420 goto fail0;
421 }
422 dev_dbg(&i2c_imx->adapter.dev,
423 "<%s> transfer message: %d\n", __func__, i);
424 /* write/read data */
425#ifdef CONFIG_I2C_DEBUG_BUS
426 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
427 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
428 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
429 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
430 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
431 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
432 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
433 dev_dbg(&i2c_imx->adapter.dev,
434 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
435 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
436 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
437 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
438 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
439 (temp & I2SR_RXAK ? 1 : 0));
440#endif
441 if (msgs[i].flags & I2C_M_RD)
442 result = i2c_imx_read(i2c_imx, &msgs[i]);
443 else
444 result = i2c_imx_write(i2c_imx, &msgs[i]);
445 if (result)
446 goto fail0;
447 }
448
449fail0:
450 /* Stop I2C transfer */
451 i2c_imx_stop(i2c_imx);
452
453 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
454 (result < 0) ? "error" : "success msg",
455 (result < 0) ? result : num);
456 return (result < 0) ? result : num;
457}
458
459static u32 i2c_imx_func(struct i2c_adapter *adapter)
460{
461 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
462}
463
464static struct i2c_algorithm i2c_imx_algo = {
465 .master_xfer = i2c_imx_xfer,
466 .functionality = i2c_imx_func,
467};
468
469static int __init i2c_imx_probe(struct platform_device *pdev)
470{
471 struct imx_i2c_struct *i2c_imx;
472 struct resource *res;
473 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
474 struct pinctrl *pinctrl;
475 void __iomem *base;
476 resource_size_t res_size;
477 int irq, bitrate;
478 int ret;
479
480 dev_dbg(&pdev->dev, "<%s>\n", __func__);
481
482 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
483 if (!res) {
484 dev_err(&pdev->dev, "can't get device resources\n");
485 return -ENOENT;
486 }
487 irq = platform_get_irq(pdev, 0);
488 if (irq < 0) {
489 dev_err(&pdev->dev, "can't get irq number\n");
490 return -ENOENT;
491 }
492
493 res_size = resource_size(res);
494
495 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
496 dev_err(&pdev->dev, "request_mem_region failed\n");
497 return -EBUSY;
498 }
499
500 base = ioremap(res->start, res_size);
501 if (!base) {
502 dev_err(&pdev->dev, "ioremap failed\n");
503 ret = -EIO;
504 goto fail1;
505 }
506
507 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
508 if (!i2c_imx) {
509 dev_err(&pdev->dev, "can't allocate interface\n");
510 ret = -ENOMEM;
511 goto fail2;
512 }
513
514 /* Setup i2c_imx driver structure */
515 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
516 i2c_imx->adapter.owner = THIS_MODULE;
517 i2c_imx->adapter.algo = &i2c_imx_algo;
518 i2c_imx->adapter.dev.parent = &pdev->dev;
519 i2c_imx->adapter.nr = pdev->id;
520 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
521 i2c_imx->irq = irq;
522 i2c_imx->base = base;
523 i2c_imx->res = res;
524
525 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
526 if (IS_ERR(pinctrl)) {
527 ret = PTR_ERR(pinctrl);
528 goto fail3;
529 }
530
531 /* Get I2C clock */
532 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
533 if (IS_ERR(i2c_imx->clk)) {
534 ret = PTR_ERR(i2c_imx->clk);
535 dev_err(&pdev->dev, "can't get I2C clock\n");
536 goto fail3;
537 }
538
539 /* Request IRQ */
540 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
541 if (ret) {
542 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
543 goto fail4;
544 }
545
546 /* Init queue */
547 init_waitqueue_head(&i2c_imx->queue);
548
549 /* Set up adapter data */
550 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
551
552 /* Set up clock divider */
553 bitrate = IMX_I2C_BIT_RATE;
554 ret = of_property_read_u32(pdev->dev.of_node,
555 "clock-frequency", &bitrate);
556 if (ret < 0 && pdata && pdata->bitrate)
557 bitrate = pdata->bitrate;
558 i2c_imx_set_clk(i2c_imx, bitrate);
559
560 /* Set up chip registers to defaults */
561 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
562 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
563
564 /* Add I2C adapter */
565 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
566 if (ret < 0) {
567 dev_err(&pdev->dev, "registration failed\n");
568 goto fail5;
569 }
570
571 of_i2c_register_devices(&i2c_imx->adapter);
572
573 /* Set up platform driver data */
574 platform_set_drvdata(pdev, i2c_imx);
575
576 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
577 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
578 i2c_imx->res->start, i2c_imx->res->end);
579 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
580 res_size, i2c_imx->res->start);
581 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
582 i2c_imx->adapter.name);
583 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
584
585 return 0; /* Return OK */
586
587fail5:
588 free_irq(i2c_imx->irq, i2c_imx);
589fail4:
590 clk_put(i2c_imx->clk);
591fail3:
592 kfree(i2c_imx);
593fail2:
594 iounmap(base);
595fail1:
596 release_mem_region(res->start, resource_size(res));
597 return ret; /* Return error number */
598}
599
600static int __exit i2c_imx_remove(struct platform_device *pdev)
601{
602 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
603
604 /* remove adapter */
605 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
606 i2c_del_adapter(&i2c_imx->adapter);
607 platform_set_drvdata(pdev, NULL);
608
609 /* free interrupt */
610 free_irq(i2c_imx->irq, i2c_imx);
611
612 /* setup chip registers to defaults */
613 writeb(0, i2c_imx->base + IMX_I2C_IADR);
614 writeb(0, i2c_imx->base + IMX_I2C_IFDR);
615 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
616 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
617
618 clk_put(i2c_imx->clk);
619
620 iounmap(i2c_imx->base);
621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
622 kfree(i2c_imx);
623 return 0;
624}
625
626static struct platform_driver i2c_imx_driver = {
627 .remove = __exit_p(i2c_imx_remove),
628 .driver = {
629 .name = DRIVER_NAME,
630 .owner = THIS_MODULE,
631 .of_match_table = i2c_imx_dt_ids,
632 }
633};
634
635static int __init i2c_adap_imx_init(void)
636{
637 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
638}
639subsys_initcall(i2c_adap_imx_init);
640
641static void __exit i2c_adap_imx_exit(void)
642{
643 platform_driver_unregister(&i2c_imx_driver);
644}
645module_exit(i2c_adap_imx_exit);
646
647MODULE_LICENSE("GPL");
648MODULE_AUTHOR("Darius Augulis");
649MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
650MODULE_ALIAS("platform:" DRIVER_NAME);