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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167}
168
169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
261 radeon_crtc->enabled = false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
264 break;
265 }
266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
270 struct drm_display_mode *mode)
271{
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
277 u16 misc = 0;
278
279 memset(&args, 0, sizeof(args));
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
281 args.usH_Blanking_Time =
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
284 args.usV_Blanking_Time =
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
286 args.usH_SyncOffset =
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
310
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312}
313
314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
316{
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
322 u16 misc = 0;
323
324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
354
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356}
357
358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
401union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
407};
408
409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
413{
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args;
418
419 memset(&args, 0, sizeof(args));
420
421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v3.ucEnable = enable;
444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
446 } else if (ASIC_IS_DCE4(rdev)) {
447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
449 switch (pll_id) {
450 case ATOM_PPLL1:
451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
454 break;
455 case ATOM_PPLL2:
456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
459 break;
460 case ATOM_DCPLL:
461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
464 break;
465 case ATOM_PPLL_INVALID:
466 return;
467 }
468 args.v2.ucEnable = enable;
469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
470 args.v2.ucEnable = ATOM_DISABLE;
471 } else if (ASIC_IS_DCE3(rdev)) {
472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 args.v1.ucSpreadSpectrumStep = ss->step;
475 args.v1.ucSpreadSpectrumDelay = ss->delay;
476 args.v1.ucSpreadSpectrumRange = ss->range;
477 args.v1.ucPpll = pll_id;
478 args.v1.ucEnable = enable;
479 } else if (ASIC_IS_AVIVO(rdev)) {
480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
482 atombios_disable_ss(crtc);
483 return;
484 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
490 args.lvds_ss_2.ucEnable = enable;
491 } else {
492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
494 atombios_disable_ss(crtc);
495 return;
496 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
501 args.lvds_ss.ucEnable = enable;
502 }
503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
504}
505
506union adjust_pixel_clock {
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
509};
510
511static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct drm_display_mode *mode,
513 struct radeon_pll *pll,
514 bool ss_enabled,
515 struct radeon_atom_ss *ss)
516{
517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct drm_encoder *encoder = NULL;
520 struct radeon_encoder *radeon_encoder = NULL;
521 struct drm_connector *connector = NULL;
522 u32 adjusted_clock = mode->clock;
523 int encoder_mode = 0;
524 u32 dp_clock = mode->clock;
525 int bpc = 8;
526
527 /* reset the pll flags */
528 pll->flags = 0;
529
530 if (ASIC_IS_AVIVO(rdev)) {
531 if ((rdev->family == CHIP_RS600) ||
532 (rdev->family == CHIP_RS690) ||
533 (rdev->family == CHIP_RS740))
534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
535 RADEON_PLL_PREFER_CLOSEST_LOWER);
536
537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 if (rdev->family < CHIP_RV770)
543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
544 } else {
545 pll->flags |= RADEON_PLL_LEGACY;
546
547 if (mode->clock > 200000) /* range limits??? */
548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
549 else
550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
551 }
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
554 if (encoder->crtc == crtc) {
555 radeon_encoder = to_radeon_encoder(encoder);
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (connector)
558 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 radeon_encoder_is_dp_bridge(encoder)) {
562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector =
565 radeon_connector->con_priv;
566
567 dp_clock = dig_connector->dp_clock;
568 }
569 }
570
571 /* use recommended ref_div for ss */
572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573 if (ss_enabled) {
574 if (ss->refdiv) {
575 pll->flags |= RADEON_PLL_USE_REF_DIV;
576 pll->reference_div = ss->refdiv;
577 if (ASIC_IS_AVIVO(rdev))
578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
579 }
580 }
581 }
582
583 if (ASIC_IS_AVIVO(rdev)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
586 adjusted_clock = mode->clock * 2;
587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
590 pll->flags |= RADEON_PLL_IS_LCD;
591 } else {
592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
595 pll->flags |= RADEON_PLL_USE_REF_DIV;
596 }
597 break;
598 }
599 }
600
601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
604 */
605 if (ASIC_IS_DCE3(rdev)) {
606 union adjust_pixel_clock args;
607 u8 frev, crev;
608 int index;
609
610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
612 &crev))
613 return adjusted_clock;
614
615 memset(&args, 0, sizeof(args));
616
617 switch (frev) {
618 case 1:
619 switch (crev) {
620 case 1:
621 case 2:
622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
624 args.v1.ucEncodeMode = encoder_mode;
625 if (ss_enabled && ss->percentage)
626 args.v1.ucConfig |=
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
628
629 atom_execute_table(rdev->mode_info.atom_context,
630 index, (uint32_t *)&args);
631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
632 break;
633 case 3:
634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
636 args.v3.sInput.ucEncodeMode = encoder_mode;
637 args.v3.sInput.ucDispPllConfig = 0;
638 if (ss_enabled && ss->percentage)
639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE;
641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642 radeon_encoder_is_dp_bridge(encoder)) {
643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
645 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE;
647 /* 16200 or 27000 */
648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649 } else {
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 /* deep color support */
652 args.v3.sInput.usPixelClock =
653 cpu_to_le16((mode->clock * bpc / 8) / 10);
654 }
655 if (dig->coherent_mode)
656 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_COHERENT_MODE;
658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE;
666 /* 16200 or 27000 */
667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669 if (mode->clock > 165000)
670 args.v3.sInput.ucDispPllConfig |=
671 DISPPLL_CONFIG_DUAL_LINK;
672 }
673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
681 atom_execute_table(rdev->mode_info.atom_context,
682 index, (uint32_t *)&args);
683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
684 if (args.v3.sOutput.ucRefDiv) {
685 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
686 pll->flags |= RADEON_PLL_USE_REF_DIV;
687 pll->reference_div = args.v3.sOutput.ucRefDiv;
688 }
689 if (args.v3.sOutput.ucPostDiv) {
690 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
691 pll->flags |= RADEON_PLL_USE_POST_DIV;
692 pll->post_div = args.v3.sOutput.ucPostDiv;
693 }
694 break;
695 default:
696 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 return adjusted_clock;
698 }
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
702 return adjusted_clock;
703 }
704 }
705 return adjusted_clock;
706}
707
708union set_pixel_clock {
709 SET_PIXEL_CLOCK_PS_ALLOCATION base;
710 PIXEL_CLOCK_PARAMETERS v1;
711 PIXEL_CLOCK_PARAMETERS_V2 v2;
712 PIXEL_CLOCK_PARAMETERS_V3 v3;
713 PIXEL_CLOCK_PARAMETERS_V5 v5;
714 PIXEL_CLOCK_PARAMETERS_V6 v6;
715};
716
717/* on DCE5, make sure the voltage is high enough to support the
718 * required disp clk.
719 */
720static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
721 u32 dispclk)
722{
723 struct drm_device *dev = crtc->dev;
724 struct radeon_device *rdev = dev->dev_private;
725 u8 frev, crev;
726 int index;
727 union set_pixel_clock args;
728
729 memset(&args, 0, sizeof(args));
730
731 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
733 &crev))
734 return;
735
736 switch (frev) {
737 case 1:
738 switch (crev) {
739 case 5:
740 /* if the default dcpll clock is specified,
741 * SetPixelClock provides the dividers
742 */
743 args.v5.ucCRTC = ATOM_CRTC_INVALID;
744 args.v5.usPixelClock = cpu_to_le16(dispclk);
745 args.v5.ucPpll = ATOM_DCPLL;
746 break;
747 case 6:
748 /* if the default dcpll clock is specified,
749 * SetPixelClock provides the dividers
750 */
751 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
752 args.v6.ucPpll = ATOM_DCPLL;
753 break;
754 default:
755 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
756 return;
757 }
758 break;
759 default:
760 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
761 return;
762 }
763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
764}
765
766static void atombios_crtc_program_pll(struct drm_crtc *crtc,
767 u32 crtc_id,
768 int pll_id,
769 u32 encoder_mode,
770 u32 encoder_id,
771 u32 clock,
772 u32 ref_div,
773 u32 fb_div,
774 u32 frac_fb_div,
775 u32 post_div,
776 int bpc,
777 bool ss_enabled,
778 struct radeon_atom_ss *ss)
779{
780 struct drm_device *dev = crtc->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 u8 frev, crev;
783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
784 union set_pixel_clock args;
785
786 memset(&args, 0, sizeof(args));
787
788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
789 &crev))
790 return;
791
792 switch (frev) {
793 case 1:
794 switch (crev) {
795 case 1:
796 if (clock == ATOM_DISABLE)
797 return;
798 args.v1.usPixelClock = cpu_to_le16(clock / 10);
799 args.v1.usRefDiv = cpu_to_le16(ref_div);
800 args.v1.usFbDiv = cpu_to_le16(fb_div);
801 args.v1.ucFracFbDiv = frac_fb_div;
802 args.v1.ucPostDiv = post_div;
803 args.v1.ucPpll = pll_id;
804 args.v1.ucCRTC = crtc_id;
805 args.v1.ucRefDivSrc = 1;
806 break;
807 case 2:
808 args.v2.usPixelClock = cpu_to_le16(clock / 10);
809 args.v2.usRefDiv = cpu_to_le16(ref_div);
810 args.v2.usFbDiv = cpu_to_le16(fb_div);
811 args.v2.ucFracFbDiv = frac_fb_div;
812 args.v2.ucPostDiv = post_div;
813 args.v2.ucPpll = pll_id;
814 args.v2.ucCRTC = crtc_id;
815 args.v2.ucRefDivSrc = 1;
816 break;
817 case 3:
818 args.v3.usPixelClock = cpu_to_le16(clock / 10);
819 args.v3.usRefDiv = cpu_to_le16(ref_div);
820 args.v3.usFbDiv = cpu_to_le16(fb_div);
821 args.v3.ucFracFbDiv = frac_fb_div;
822 args.v3.ucPostDiv = post_div;
823 args.v3.ucPpll = pll_id;
824 args.v3.ucMiscInfo = (pll_id << 2);
825 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
826 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
827 args.v3.ucTransmitterId = encoder_id;
828 args.v3.ucEncoderMode = encoder_mode;
829 break;
830 case 5:
831 args.v5.ucCRTC = crtc_id;
832 args.v5.usPixelClock = cpu_to_le16(clock / 10);
833 args.v5.ucRefDiv = ref_div;
834 args.v5.usFbDiv = cpu_to_le16(fb_div);
835 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
836 args.v5.ucPostDiv = post_div;
837 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
838 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
840 switch (bpc) {
841 case 8:
842 default:
843 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
844 break;
845 case 10:
846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
847 break;
848 }
849 args.v5.ucTransmitterID = encoder_id;
850 args.v5.ucEncoderMode = encoder_mode;
851 args.v5.ucPpll = pll_id;
852 break;
853 case 6:
854 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
855 args.v6.ucRefDiv = ref_div;
856 args.v6.usFbDiv = cpu_to_le16(fb_div);
857 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
858 args.v6.ucPostDiv = post_div;
859 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
860 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
861 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
862 switch (bpc) {
863 case 8:
864 default:
865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
866 break;
867 case 10:
868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
869 break;
870 case 12:
871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
872 break;
873 case 16:
874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
875 break;
876 }
877 args.v6.ucTransmitterID = encoder_id;
878 args.v6.ucEncoderMode = encoder_mode;
879 args.v6.ucPpll = pll_id;
880 break;
881 default:
882 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
883 return;
884 }
885 break;
886 default:
887 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
888 return;
889 }
890
891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
892}
893
894static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
895{
896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
897 struct drm_device *dev = crtc->dev;
898 struct radeon_device *rdev = dev->dev_private;
899 struct drm_encoder *encoder = NULL;
900 struct radeon_encoder *radeon_encoder = NULL;
901 u32 pll_clock = mode->clock;
902 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
903 struct radeon_pll *pll;
904 u32 adjusted_clock;
905 int encoder_mode = 0;
906 struct radeon_atom_ss ss;
907 bool ss_enabled = false;
908 int bpc = 8;
909
910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
911 if (encoder->crtc == crtc) {
912 radeon_encoder = to_radeon_encoder(encoder);
913 encoder_mode = atombios_get_encoder_mode(encoder);
914 break;
915 }
916 }
917
918 if (!radeon_encoder)
919 return;
920
921 switch (radeon_crtc->pll_id) {
922 case ATOM_PPLL1:
923 pll = &rdev->clock.p1pll;
924 break;
925 case ATOM_PPLL2:
926 pll = &rdev->clock.p2pll;
927 break;
928 case ATOM_DCPLL:
929 case ATOM_PPLL_INVALID:
930 default:
931 pll = &rdev->clock.dcpll;
932 break;
933 }
934
935 if (radeon_encoder->active_device &
936 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector =
939 radeon_get_connector_for_encoder(encoder);
940 struct radeon_connector *radeon_connector =
941 to_radeon_connector(connector);
942 struct radeon_connector_atom_dig *dig_connector =
943 radeon_connector->con_priv;
944 int dp_clock;
945 bpc = connector->display_info.bpc;
946
947 switch (encoder_mode) {
948 case ATOM_ENCODER_MODE_DP:
949 /* DP/eDP */
950 dp_clock = dig_connector->dp_clock / 10;
951 if (ASIC_IS_DCE4(rdev))
952 ss_enabled =
953 radeon_atombios_get_asic_ss_info(rdev, &ss,
954 ASIC_INTERNAL_SS_ON_DP,
955 dp_clock);
956 else {
957 if (dp_clock == 16200) {
958 ss_enabled =
959 radeon_atombios_get_ppll_ss_info(rdev, &ss,
960 ATOM_DP_SS_ID2);
961 if (!ss_enabled)
962 ss_enabled =
963 radeon_atombios_get_ppll_ss_info(rdev, &ss,
964 ATOM_DP_SS_ID1);
965 } else
966 ss_enabled =
967 radeon_atombios_get_ppll_ss_info(rdev, &ss,
968 ATOM_DP_SS_ID1);
969 }
970 break;
971 case ATOM_ENCODER_MODE_LVDS:
972 if (ASIC_IS_DCE4(rdev))
973 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
974 dig->lcd_ss_id,
975 mode->clock / 10);
976 else
977 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
978 dig->lcd_ss_id);
979 break;
980 case ATOM_ENCODER_MODE_DVI:
981 if (ASIC_IS_DCE4(rdev))
982 ss_enabled =
983 radeon_atombios_get_asic_ss_info(rdev, &ss,
984 ASIC_INTERNAL_SS_ON_TMDS,
985 mode->clock / 10);
986 break;
987 case ATOM_ENCODER_MODE_HDMI:
988 if (ASIC_IS_DCE4(rdev))
989 ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev, &ss,
991 ASIC_INTERNAL_SS_ON_HDMI,
992 mode->clock / 10);
993 break;
994 default:
995 break;
996 }
997 }
998
999 /* adjust pixel clock as needed */
1000 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1001
1002 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1003 /* TV seems to prefer the legacy algo on some boards */
1004 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1005 &ref_div, &post_div);
1006 else if (ASIC_IS_AVIVO(rdev))
1007 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1008 &ref_div, &post_div);
1009 else
1010 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1011 &ref_div, &post_div);
1012
1013 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1014
1015 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1016 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1017 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1018
1019 if (ss_enabled) {
1020 /* calculate ss amount and step size */
1021 if (ASIC_IS_DCE4(rdev)) {
1022 u32 step_size;
1023 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1024 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1025 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1026 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1027 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1028 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1029 (125 * 25 * pll->reference_freq / 100);
1030 else
1031 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1032 (125 * 25 * pll->reference_freq / 100);
1033 ss.step = step_size;
1034 }
1035
1036 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1037 }
1038}
1039
1040static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1041 struct drm_framebuffer *fb,
1042 int x, int y, int atomic)
1043{
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 struct drm_device *dev = crtc->dev;
1046 struct radeon_device *rdev = dev->dev_private;
1047 struct radeon_framebuffer *radeon_fb;
1048 struct drm_framebuffer *target_fb;
1049 struct drm_gem_object *obj;
1050 struct radeon_bo *rbo;
1051 uint64_t fb_location;
1052 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1053 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1054 u32 tmp, viewport_w, viewport_h;
1055 int r;
1056
1057 /* no fb bound */
1058 if (!atomic && !crtc->fb) {
1059 DRM_DEBUG_KMS("No FB bound\n");
1060 return 0;
1061 }
1062
1063 if (atomic) {
1064 radeon_fb = to_radeon_framebuffer(fb);
1065 target_fb = fb;
1066 }
1067 else {
1068 radeon_fb = to_radeon_framebuffer(crtc->fb);
1069 target_fb = crtc->fb;
1070 }
1071
1072 /* If atomic, assume fb object is pinned & idle & fenced and
1073 * just update base pointers
1074 */
1075 obj = radeon_fb->obj;
1076 rbo = gem_to_radeon_bo(obj);
1077 r = radeon_bo_reserve(rbo, false);
1078 if (unlikely(r != 0))
1079 return r;
1080
1081 if (atomic)
1082 fb_location = radeon_bo_gpu_offset(rbo);
1083 else {
1084 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1085 if (unlikely(r != 0)) {
1086 radeon_bo_unreserve(rbo);
1087 return -EINVAL;
1088 }
1089 }
1090
1091 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1092 radeon_bo_unreserve(rbo);
1093
1094 switch (target_fb->bits_per_pixel) {
1095 case 8:
1096 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1097 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1098 break;
1099 case 15:
1100 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1101 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1102 break;
1103 case 16:
1104 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1105 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1106#ifdef __BIG_ENDIAN
1107 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1108#endif
1109 break;
1110 case 24:
1111 case 32:
1112 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1113 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1114#ifdef __BIG_ENDIAN
1115 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1116#endif
1117 break;
1118 default:
1119 DRM_ERROR("Unsupported screen depth %d\n",
1120 target_fb->bits_per_pixel);
1121 return -EINVAL;
1122 }
1123
1124 if (tiling_flags & RADEON_TILING_MACRO)
1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 else if (tiling_flags & RADEON_TILING_MICRO)
1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1128
1129 switch (radeon_crtc->crtc_id) {
1130 case 0:
1131 WREG32(AVIVO_D1VGA_CONTROL, 0);
1132 break;
1133 case 1:
1134 WREG32(AVIVO_D2VGA_CONTROL, 0);
1135 break;
1136 case 2:
1137 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1138 break;
1139 case 3:
1140 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1141 break;
1142 case 4:
1143 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1144 break;
1145 case 5:
1146 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1147 break;
1148 default:
1149 break;
1150 }
1151
1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1153 upper_32_bits(fb_location));
1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1155 upper_32_bits(fb_location));
1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1157 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1159 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1160 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1161 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1162
1163 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1164 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1165 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1166 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1167 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1168 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1169
1170 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1171 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1172 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1173
1174 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1175 crtc->mode.vdisplay);
1176 x &= ~3;
1177 y &= ~1;
1178 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1179 (x << 16) | y);
1180 viewport_w = crtc->mode.hdisplay;
1181 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1182 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1183 (viewport_w << 16) | viewport_h);
1184
1185 /* pageflip setup */
1186 /* make sure flip is at vb rather than hb */
1187 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1188 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1189 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1190
1191 /* set pageflip to happen anywhere in vblank interval */
1192 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1193
1194 if (!atomic && fb && fb != crtc->fb) {
1195 radeon_fb = to_radeon_framebuffer(fb);
1196 rbo = gem_to_radeon_bo(radeon_fb->obj);
1197 r = radeon_bo_reserve(rbo, false);
1198 if (unlikely(r != 0))
1199 return r;
1200 radeon_bo_unpin(rbo);
1201 radeon_bo_unreserve(rbo);
1202 }
1203
1204 /* Bytes per pixel may have changed */
1205 radeon_bandwidth_update(rdev);
1206
1207 return 0;
1208}
1209
1210static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1211 struct drm_framebuffer *fb,
1212 int x, int y, int atomic)
1213{
1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1215 struct drm_device *dev = crtc->dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_framebuffer *radeon_fb;
1218 struct drm_gem_object *obj;
1219 struct radeon_bo *rbo;
1220 struct drm_framebuffer *target_fb;
1221 uint64_t fb_location;
1222 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1223 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1224 u32 tmp, viewport_w, viewport_h;
1225 int r;
1226
1227 /* no fb bound */
1228 if (!atomic && !crtc->fb) {
1229 DRM_DEBUG_KMS("No FB bound\n");
1230 return 0;
1231 }
1232
1233 if (atomic) {
1234 radeon_fb = to_radeon_framebuffer(fb);
1235 target_fb = fb;
1236 }
1237 else {
1238 radeon_fb = to_radeon_framebuffer(crtc->fb);
1239 target_fb = crtc->fb;
1240 }
1241
1242 obj = radeon_fb->obj;
1243 rbo = gem_to_radeon_bo(obj);
1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1246 return r;
1247
1248 /* If atomic, assume fb object is pinned & idle & fenced and
1249 * just update base pointers
1250 */
1251 if (atomic)
1252 fb_location = radeon_bo_gpu_offset(rbo);
1253 else {
1254 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1255 if (unlikely(r != 0)) {
1256 radeon_bo_unreserve(rbo);
1257 return -EINVAL;
1258 }
1259 }
1260 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1261 radeon_bo_unreserve(rbo);
1262
1263 switch (target_fb->bits_per_pixel) {
1264 case 8:
1265 fb_format =
1266 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1267 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1268 break;
1269 case 15:
1270 fb_format =
1271 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1272 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1273 break;
1274 case 16:
1275 fb_format =
1276 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1277 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1278#ifdef __BIG_ENDIAN
1279 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1280#endif
1281 break;
1282 case 24:
1283 case 32:
1284 fb_format =
1285 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1286 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1287#ifdef __BIG_ENDIAN
1288 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1289#endif
1290 break;
1291 default:
1292 DRM_ERROR("Unsupported screen depth %d\n",
1293 target_fb->bits_per_pixel);
1294 return -EINVAL;
1295 }
1296
1297 if (rdev->family >= CHIP_R600) {
1298 if (tiling_flags & RADEON_TILING_MACRO)
1299 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1300 else if (tiling_flags & RADEON_TILING_MICRO)
1301 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1302 } else {
1303 if (tiling_flags & RADEON_TILING_MACRO)
1304 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1305
1306 if (tiling_flags & RADEON_TILING_MICRO)
1307 fb_format |= AVIVO_D1GRPH_TILED;
1308 }
1309
1310 if (radeon_crtc->crtc_id == 0)
1311 WREG32(AVIVO_D1VGA_CONTROL, 0);
1312 else
1313 WREG32(AVIVO_D2VGA_CONTROL, 0);
1314
1315 if (rdev->family >= CHIP_RV770) {
1316 if (radeon_crtc->crtc_id) {
1317 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1318 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1319 } else {
1320 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1321 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1322 }
1323 }
1324 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1325 (u32) fb_location);
1326 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1327 radeon_crtc->crtc_offset, (u32) fb_location);
1328 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1329 if (rdev->family >= CHIP_R600)
1330 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331
1332 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1335 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1336 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1337 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1338
1339 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1340 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1341 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1342
1343 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1344 crtc->mode.vdisplay);
1345 x &= ~3;
1346 y &= ~1;
1347 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1348 (x << 16) | y);
1349 viewport_w = crtc->mode.hdisplay;
1350 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1351 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1352 (viewport_w << 16) | viewport_h);
1353
1354 /* pageflip setup */
1355 /* make sure flip is at vb rather than hb */
1356 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1357 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1358 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1359
1360 /* set pageflip to happen anywhere in vblank interval */
1361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1362
1363 if (!atomic && fb && fb != crtc->fb) {
1364 radeon_fb = to_radeon_framebuffer(fb);
1365 rbo = gem_to_radeon_bo(radeon_fb->obj);
1366 r = radeon_bo_reserve(rbo, false);
1367 if (unlikely(r != 0))
1368 return r;
1369 radeon_bo_unpin(rbo);
1370 radeon_bo_unreserve(rbo);
1371 }
1372
1373 /* Bytes per pixel may have changed */
1374 radeon_bandwidth_update(rdev);
1375
1376 return 0;
1377}
1378
1379int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1380 struct drm_framebuffer *old_fb)
1381{
1382 struct drm_device *dev = crtc->dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384
1385 if (ASIC_IS_DCE4(rdev))
1386 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1387 else if (ASIC_IS_AVIVO(rdev))
1388 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1389 else
1390 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1391}
1392
1393int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1394 struct drm_framebuffer *fb,
1395 int x, int y, enum mode_set_atomic state)
1396{
1397 struct drm_device *dev = crtc->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399
1400 if (ASIC_IS_DCE4(rdev))
1401 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1402 else if (ASIC_IS_AVIVO(rdev))
1403 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1404 else
1405 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1406}
1407
1408/* properly set additional regs when using atombios */
1409static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct radeon_device *rdev = dev->dev_private;
1413 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1414 u32 disp_merge_cntl;
1415
1416 switch (radeon_crtc->crtc_id) {
1417 case 0:
1418 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1419 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1420 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1421 break;
1422 case 1:
1423 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1424 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1425 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1426 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1427 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1428 break;
1429 }
1430}
1431
1432static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1433{
1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1435 struct drm_device *dev = crtc->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1437 struct drm_encoder *test_encoder;
1438 struct drm_crtc *test_crtc;
1439 uint32_t pll_in_use = 0;
1440
1441 if (ASIC_IS_DCE4(rdev)) {
1442 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1443 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1444 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1445 * depending on the asic:
1446 * DCE4: PPLL or ext clock
1447 * DCE5: DCPLL or ext clock
1448 *
1449 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1450 * PPLL/DCPLL programming and only program the DP DTO for the
1451 * crtc virtual pixel clock.
1452 */
1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1455 return ATOM_PPLL_INVALID;
1456 }
1457 }
1458 }
1459
1460 /* otherwise, pick one of the plls */
1461 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1462 struct radeon_crtc *radeon_test_crtc;
1463
1464 if (crtc == test_crtc)
1465 continue;
1466
1467 radeon_test_crtc = to_radeon_crtc(test_crtc);
1468 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1469 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1470 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1471 }
1472 if (!(pll_in_use & 1))
1473 return ATOM_PPLL1;
1474 return ATOM_PPLL2;
1475 } else
1476 return radeon_crtc->crtc_id;
1477
1478}
1479
1480int atombios_crtc_mode_set(struct drm_crtc *crtc,
1481 struct drm_display_mode *mode,
1482 struct drm_display_mode *adjusted_mode,
1483 int x, int y, struct drm_framebuffer *old_fb)
1484{
1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1486 struct drm_device *dev = crtc->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct drm_encoder *encoder;
1489 bool is_tvcv = false;
1490
1491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1492 /* find tv std */
1493 if (encoder->crtc == crtc) {
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 if (radeon_encoder->active_device &
1496 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1497 is_tvcv = true;
1498 }
1499 }
1500
1501 /* always set DCPLL */
1502 if (ASIC_IS_DCE4(rdev)) {
1503 struct radeon_atom_ss ss;
1504 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1505 ASIC_INTERNAL_SS_ON_DCPLL,
1506 rdev->clock.default_dispclk);
1507 if (ss_enabled)
1508 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1509 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1510 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1511 if (ss_enabled)
1512 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1513 }
1514 atombios_crtc_set_pll(crtc, adjusted_mode);
1515
1516 if (ASIC_IS_DCE4(rdev))
1517 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1518 else if (ASIC_IS_AVIVO(rdev)) {
1519 if (is_tvcv)
1520 atombios_crtc_set_timing(crtc, adjusted_mode);
1521 else
1522 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1523 } else {
1524 atombios_crtc_set_timing(crtc, adjusted_mode);
1525 if (radeon_crtc->crtc_id == 0)
1526 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1527 radeon_legacy_atom_fixup(crtc);
1528 }
1529 atombios_crtc_set_base(crtc, x, y, old_fb);
1530 atombios_overscan_setup(crtc, mode, adjusted_mode);
1531 atombios_scaler_setup(crtc);
1532 return 0;
1533}
1534
1535static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1536 struct drm_display_mode *mode,
1537 struct drm_display_mode *adjusted_mode)
1538{
1539 struct drm_device *dev = crtc->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541
1542 /* adjust pm to upcoming mode change */
1543 radeon_pm_compute_clocks(rdev);
1544
1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1546 return false;
1547 return true;
1548}
1549
1550static void atombios_crtc_prepare(struct drm_crtc *crtc)
1551{
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553
1554 /* pick pll */
1555 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1556
1557 atombios_lock_crtc(crtc, ATOM_ENABLE);
1558 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1559}
1560
1561static void atombios_crtc_commit(struct drm_crtc *crtc)
1562{
1563 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1564 atombios_lock_crtc(crtc, ATOM_DISABLE);
1565}
1566
1567static void atombios_crtc_disable(struct drm_crtc *crtc)
1568{
1569 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1570 struct radeon_atom_ss ss;
1571
1572 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1573
1574 switch (radeon_crtc->pll_id) {
1575 case ATOM_PPLL1:
1576 case ATOM_PPLL2:
1577 /* disable the ppll */
1578 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1580 break;
1581 default:
1582 break;
1583 }
1584 radeon_crtc->pll_id = -1;
1585}
1586
1587static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1588 .dpms = atombios_crtc_dpms,
1589 .mode_fixup = atombios_crtc_mode_fixup,
1590 .mode_set = atombios_crtc_mode_set,
1591 .mode_set_base = atombios_crtc_set_base,
1592 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1593 .prepare = atombios_crtc_prepare,
1594 .commit = atombios_crtc_commit,
1595 .load_lut = radeon_crtc_load_lut,
1596 .disable = atombios_crtc_disable,
1597};
1598
1599void radeon_atombios_init_crtc(struct drm_device *dev,
1600 struct radeon_crtc *radeon_crtc)
1601{
1602 struct radeon_device *rdev = dev->dev_private;
1603
1604 if (ASIC_IS_DCE4(rdev)) {
1605 switch (radeon_crtc->crtc_id) {
1606 case 0:
1607 default:
1608 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1609 break;
1610 case 1:
1611 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1612 break;
1613 case 2:
1614 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1615 break;
1616 case 3:
1617 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1618 break;
1619 case 4:
1620 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1621 break;
1622 case 5:
1623 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1624 break;
1625 }
1626 } else {
1627 if (radeon_crtc->crtc_id == 1)
1628 radeon_crtc->crtc_offset =
1629 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1630 else
1631 radeon_crtc->crtc_offset = 0;
1632 }
1633 radeon_crtc->pll_id = -1;
1634 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1635}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_fb_helper.h>
29#include <drm/drm_fixed.h>
30#include <drm/drm_fourcc.h>
31#include <drm/drm_framebuffer.h>
32#include <drm/drm_vblank.h>
33#include <drm/radeon_drm.h>
34
35#include "radeon.h"
36#include "atom.h"
37#include "atom-bits.h"
38
39static void atombios_overscan_setup(struct drm_crtc *crtc,
40 struct drm_display_mode *mode,
41 struct drm_display_mode *adjusted_mode)
42{
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
46 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
47 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
48 int a1, a2;
49
50 memset(&args, 0, sizeof(args));
51
52 args.ucCRTC = radeon_crtc->crtc_id;
53
54 switch (radeon_crtc->rmx_type) {
55 case RMX_CENTER:
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
67 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
68 } else if (a2 > a1) {
69 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
71 }
72 break;
73 case RMX_FULL:
74 default:
75 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
76 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
77 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
78 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
79 break;
80 }
81 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
82}
83
84static void atombios_scaler_setup(struct drm_crtc *crtc)
85{
86 struct drm_device *dev = crtc->dev;
87 struct radeon_device *rdev = dev->dev_private;
88 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
89 ENABLE_SCALER_PS_ALLOCATION args;
90 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
91 struct radeon_encoder *radeon_encoder =
92 to_radeon_encoder(radeon_crtc->encoder);
93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
95 bool is_tv = false, is_cv = false;
96
97 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
98 return;
99
100 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
101 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
102 tv_std = tv_dac->tv_std;
103 is_tv = true;
104 }
105
106 memset(&args, 0, sizeof(args));
107
108 args.ucScaler = radeon_crtc->crtc_id;
109
110 if (is_tv) {
111 switch (tv_std) {
112 case TV_STD_NTSC:
113 default:
114 args.ucTVStandard = ATOM_TV_NTSC;
115 break;
116 case TV_STD_PAL:
117 args.ucTVStandard = ATOM_TV_PAL;
118 break;
119 case TV_STD_PAL_M:
120 args.ucTVStandard = ATOM_TV_PALM;
121 break;
122 case TV_STD_PAL_60:
123 args.ucTVStandard = ATOM_TV_PAL60;
124 break;
125 case TV_STD_NTSC_J:
126 args.ucTVStandard = ATOM_TV_NTSCJ;
127 break;
128 case TV_STD_SCART_PAL:
129 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
130 break;
131 case TV_STD_SECAM:
132 args.ucTVStandard = ATOM_TV_SECAM;
133 break;
134 case TV_STD_PAL_CN:
135 args.ucTVStandard = ATOM_TV_PALCN;
136 break;
137 }
138 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
139 } else if (is_cv) {
140 args.ucTVStandard = ATOM_TV_CV;
141 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
142 } else {
143 switch (radeon_crtc->rmx_type) {
144 case RMX_FULL:
145 args.ucEnable = ATOM_SCALER_EXPANSION;
146 break;
147 case RMX_CENTER:
148 args.ucEnable = ATOM_SCALER_CENTER;
149 break;
150 case RMX_ASPECT:
151 args.ucEnable = ATOM_SCALER_EXPANSION;
152 break;
153 default:
154 if (ASIC_IS_AVIVO(rdev))
155 args.ucEnable = ATOM_SCALER_DISABLE;
156 else
157 args.ucEnable = ATOM_SCALER_CENTER;
158 break;
159 }
160 }
161 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
162 if ((is_tv || is_cv)
163 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
164 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
165 }
166}
167
168static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
169{
170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
171 struct drm_device *dev = crtc->dev;
172 struct radeon_device *rdev = dev->dev_private;
173 int index =
174 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
175 ENABLE_CRTC_PS_ALLOCATION args;
176
177 memset(&args, 0, sizeof(args));
178
179 args.ucCRTC = radeon_crtc->crtc_id;
180 args.ucEnable = lock;
181
182 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
183}
184
185static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
186{
187 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
188 struct drm_device *dev = crtc->dev;
189 struct radeon_device *rdev = dev->dev_private;
190 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
191 ENABLE_CRTC_PS_ALLOCATION args;
192
193 memset(&args, 0, sizeof(args));
194
195 args.ucCRTC = radeon_crtc->crtc_id;
196 args.ucEnable = state;
197
198 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
199}
200
201static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
202{
203 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
204 struct drm_device *dev = crtc->dev;
205 struct radeon_device *rdev = dev->dev_private;
206 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
207 ENABLE_CRTC_PS_ALLOCATION args;
208
209 memset(&args, 0, sizeof(args));
210
211 args.ucCRTC = radeon_crtc->crtc_id;
212 args.ucEnable = state;
213
214 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
215}
216
217static const u32 vga_control_regs[6] =
218{
219 AVIVO_D1VGA_CONTROL,
220 AVIVO_D2VGA_CONTROL,
221 EVERGREEN_D3VGA_CONTROL,
222 EVERGREEN_D4VGA_CONTROL,
223 EVERGREEN_D5VGA_CONTROL,
224 EVERGREEN_D6VGA_CONTROL,
225};
226
227static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
228{
229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
230 struct drm_device *dev = crtc->dev;
231 struct radeon_device *rdev = dev->dev_private;
232 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
233 BLANK_CRTC_PS_ALLOCATION args;
234 u32 vga_control = 0;
235
236 memset(&args, 0, sizeof(args));
237
238 if (ASIC_IS_DCE8(rdev)) {
239 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
240 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
241 }
242
243 args.ucCRTC = radeon_crtc->crtc_id;
244 args.ucBlanking = state;
245
246 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
247
248 if (ASIC_IS_DCE8(rdev))
249 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
250}
251
252static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
253{
254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255 struct drm_device *dev = crtc->dev;
256 struct radeon_device *rdev = dev->dev_private;
257 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
258 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
259
260 memset(&args, 0, sizeof(args));
261
262 args.ucDispPipeId = radeon_crtc->crtc_id;
263 args.ucEnable = state;
264
265 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
266}
267
268void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
269{
270 struct drm_device *dev = crtc->dev;
271 struct radeon_device *rdev = dev->dev_private;
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273
274 switch (mode) {
275 case DRM_MODE_DPMS_ON:
276 radeon_crtc->enabled = true;
277 atombios_enable_crtc(crtc, ATOM_ENABLE);
278 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
279 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
280 atombios_blank_crtc(crtc, ATOM_DISABLE);
281 if (dev->num_crtcs > radeon_crtc->crtc_id)
282 drm_crtc_vblank_on(crtc);
283 radeon_crtc_load_lut(crtc);
284 break;
285 case DRM_MODE_DPMS_STANDBY:
286 case DRM_MODE_DPMS_SUSPEND:
287 case DRM_MODE_DPMS_OFF:
288 if (dev->num_crtcs > radeon_crtc->crtc_id)
289 drm_crtc_vblank_off(crtc);
290 if (radeon_crtc->enabled)
291 atombios_blank_crtc(crtc, ATOM_ENABLE);
292 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
293 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
294 atombios_enable_crtc(crtc, ATOM_DISABLE);
295 radeon_crtc->enabled = false;
296 break;
297 }
298 /* adjust pm to dpms */
299 radeon_pm_compute_clocks(rdev);
300}
301
302static void
303atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
304 struct drm_display_mode *mode)
305{
306 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
307 struct drm_device *dev = crtc->dev;
308 struct radeon_device *rdev = dev->dev_private;
309 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
310 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
311 u16 misc = 0;
312
313 memset(&args, 0, sizeof(args));
314 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
315 args.usH_Blanking_Time =
316 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
317 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
318 args.usV_Blanking_Time =
319 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
320 args.usH_SyncOffset =
321 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
322 args.usH_SyncWidth =
323 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
324 args.usV_SyncOffset =
325 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
326 args.usV_SyncWidth =
327 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
328 args.ucH_Border = radeon_crtc->h_border;
329 args.ucV_Border = radeon_crtc->v_border;
330
331 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
332 misc |= ATOM_VSYNC_POLARITY;
333 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
334 misc |= ATOM_HSYNC_POLARITY;
335 if (mode->flags & DRM_MODE_FLAG_CSYNC)
336 misc |= ATOM_COMPOSITESYNC;
337 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
338 misc |= ATOM_INTERLACE;
339 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
340 misc |= ATOM_DOUBLE_CLOCK_MODE;
341 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
342 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
343
344 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
345 args.ucCRTC = radeon_crtc->crtc_id;
346
347 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
348}
349
350static void atombios_crtc_set_timing(struct drm_crtc *crtc,
351 struct drm_display_mode *mode)
352{
353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 struct drm_device *dev = crtc->dev;
355 struct radeon_device *rdev = dev->dev_private;
356 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
357 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
358 u16 misc = 0;
359
360 memset(&args, 0, sizeof(args));
361 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
362 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
363 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
364 args.usH_SyncWidth =
365 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
366 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
367 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
368 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
369 args.usV_SyncWidth =
370 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
371
372 args.ucOverscanRight = radeon_crtc->h_border;
373 args.ucOverscanLeft = radeon_crtc->h_border;
374 args.ucOverscanBottom = radeon_crtc->v_border;
375 args.ucOverscanTop = radeon_crtc->v_border;
376
377 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
378 misc |= ATOM_VSYNC_POLARITY;
379 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
380 misc |= ATOM_HSYNC_POLARITY;
381 if (mode->flags & DRM_MODE_FLAG_CSYNC)
382 misc |= ATOM_COMPOSITESYNC;
383 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
384 misc |= ATOM_INTERLACE;
385 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
386 misc |= ATOM_DOUBLE_CLOCK_MODE;
387 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
388 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
389
390 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
391 args.ucCRTC = radeon_crtc->crtc_id;
392
393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
394}
395
396static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
397{
398 u32 ss_cntl;
399
400 if (ASIC_IS_DCE4(rdev)) {
401 switch (pll_id) {
402 case ATOM_PPLL1:
403 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
404 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
405 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
406 break;
407 case ATOM_PPLL2:
408 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
409 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
410 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
411 break;
412 case ATOM_DCPLL:
413 case ATOM_PPLL_INVALID:
414 return;
415 }
416 } else if (ASIC_IS_AVIVO(rdev)) {
417 switch (pll_id) {
418 case ATOM_PPLL1:
419 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
420 ss_cntl &= ~1;
421 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
422 break;
423 case ATOM_PPLL2:
424 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
425 ss_cntl &= ~1;
426 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
427 break;
428 case ATOM_DCPLL:
429 case ATOM_PPLL_INVALID:
430 return;
431 }
432 }
433}
434
435
436union atom_enable_ss {
437 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
438 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
439 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
441 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
442};
443
444static void atombios_crtc_program_ss(struct radeon_device *rdev,
445 int enable,
446 int pll_id,
447 int crtc_id,
448 struct radeon_atom_ss *ss)
449{
450 unsigned i;
451 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
452 union atom_enable_ss args;
453
454 if (enable) {
455 /* Don't mess with SS if percentage is 0 or external ss.
456 * SS is already disabled previously, and disabling it
457 * again can cause display problems if the pll is already
458 * programmed.
459 */
460 if (ss->percentage == 0)
461 return;
462 if (ss->type & ATOM_EXTERNAL_SS_MASK)
463 return;
464 } else {
465 for (i = 0; i < rdev->num_crtc; i++) {
466 if (rdev->mode_info.crtcs[i] &&
467 rdev->mode_info.crtcs[i]->enabled &&
468 i != crtc_id &&
469 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
470 /* one other crtc is using this pll don't turn
471 * off spread spectrum as it might turn off
472 * display on active crtc
473 */
474 return;
475 }
476 }
477 }
478
479 memset(&args, 0, sizeof(args));
480
481 if (ASIC_IS_DCE5(rdev)) {
482 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
483 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
484 switch (pll_id) {
485 case ATOM_PPLL1:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
487 break;
488 case ATOM_PPLL2:
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
490 break;
491 case ATOM_DCPLL:
492 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
493 break;
494 case ATOM_PPLL_INVALID:
495 return;
496 }
497 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
498 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
499 args.v3.ucEnable = enable;
500 } else if (ASIC_IS_DCE4(rdev)) {
501 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
502 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
503 switch (pll_id) {
504 case ATOM_PPLL1:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
506 break;
507 case ATOM_PPLL2:
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
509 break;
510 case ATOM_DCPLL:
511 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
512 break;
513 case ATOM_PPLL_INVALID:
514 return;
515 }
516 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
517 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
518 args.v2.ucEnable = enable;
519 } else if (ASIC_IS_DCE3(rdev)) {
520 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
521 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
522 args.v1.ucSpreadSpectrumStep = ss->step;
523 args.v1.ucSpreadSpectrumDelay = ss->delay;
524 args.v1.ucSpreadSpectrumRange = ss->range;
525 args.v1.ucPpll = pll_id;
526 args.v1.ucEnable = enable;
527 } else if (ASIC_IS_AVIVO(rdev)) {
528 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
529 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
530 atombios_disable_ss(rdev, pll_id);
531 return;
532 }
533 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
534 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
535 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
536 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
537 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
538 args.lvds_ss_2.ucEnable = enable;
539 } else {
540 if (enable == ATOM_DISABLE) {
541 atombios_disable_ss(rdev, pll_id);
542 return;
543 }
544 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
545 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
547 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
548 args.lvds_ss.ucEnable = enable;
549 }
550 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
551}
552
553union adjust_pixel_clock {
554 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
555 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
556};
557
558static u32 atombios_adjust_pll(struct drm_crtc *crtc,
559 struct drm_display_mode *mode)
560{
561 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
562 struct drm_device *dev = crtc->dev;
563 struct radeon_device *rdev = dev->dev_private;
564 struct drm_encoder *encoder = radeon_crtc->encoder;
565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
566 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
567 u32 adjusted_clock = mode->clock;
568 int encoder_mode = atombios_get_encoder_mode(encoder);
569 u32 dp_clock = mode->clock;
570 u32 clock = mode->clock;
571 int bpc = radeon_crtc->bpc;
572 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
573
574 /* reset the pll flags */
575 radeon_crtc->pll_flags = 0;
576
577 if (ASIC_IS_AVIVO(rdev)) {
578 if ((rdev->family == CHIP_RS600) ||
579 (rdev->family == CHIP_RS690) ||
580 (rdev->family == CHIP_RS740))
581 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
582 RADEON_PLL_PREFER_CLOSEST_LOWER);
583
584 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
585 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
586 else
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
588
589 if (rdev->family < CHIP_RV770)
590 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
591 /* use frac fb div on APUs */
592 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
594 /* use frac fb div on RS780/RS880 */
595 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
596 && !radeon_crtc->ss_enabled)
597 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
598 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
599 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
600 } else {
601 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
602
603 if (mode->clock > 200000) /* range limits??? */
604 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
605 else
606 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
607 }
608
609 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
610 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
611 if (connector) {
612 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
613 struct radeon_connector_atom_dig *dig_connector =
614 radeon_connector->con_priv;
615
616 dp_clock = dig_connector->dp_clock;
617 }
618 }
619
620 /* use recommended ref_div for ss */
621 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
622 if (radeon_crtc->ss_enabled) {
623 if (radeon_crtc->ss.refdiv) {
624 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
625 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
626 if (ASIC_IS_AVIVO(rdev) &&
627 rdev->family != CHIP_RS780 &&
628 rdev->family != CHIP_RS880)
629 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
630 }
631 }
632 }
633
634 if (ASIC_IS_AVIVO(rdev)) {
635 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
636 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
637 adjusted_clock = mode->clock * 2;
638 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
639 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
641 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
642 } else {
643 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
644 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
645 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
646 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
647 }
648
649 /* adjust pll for deep color modes */
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 switch (bpc) {
652 case 8:
653 default:
654 break;
655 case 10:
656 clock = (clock * 5) / 4;
657 break;
658 case 12:
659 clock = (clock * 3) / 2;
660 break;
661 case 16:
662 clock = clock * 2;
663 break;
664 }
665 }
666
667 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
668 * accordingly based on the encoder/transmitter to work around
669 * special hw requirements.
670 */
671 if (ASIC_IS_DCE3(rdev)) {
672 union adjust_pixel_clock args;
673 u8 frev, crev;
674 int index;
675
676 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
677 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
678 &crev))
679 return adjusted_clock;
680
681 memset(&args, 0, sizeof(args));
682
683 switch (frev) {
684 case 1:
685 switch (crev) {
686 case 1:
687 case 2:
688 args.v1.usPixelClock = cpu_to_le16(clock / 10);
689 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
690 args.v1.ucEncodeMode = encoder_mode;
691 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
692 args.v1.ucConfig |=
693 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
694
695 atom_execute_table(rdev->mode_info.atom_context,
696 index, (uint32_t *)&args);
697 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
698 break;
699 case 3:
700 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
701 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
702 args.v3.sInput.ucEncodeMode = encoder_mode;
703 args.v3.sInput.ucDispPllConfig = 0;
704 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
705 args.v3.sInput.ucDispPllConfig |=
706 DISPPLL_CONFIG_SS_ENABLE;
707 if (ENCODER_MODE_IS_DP(encoder_mode)) {
708 args.v3.sInput.ucDispPllConfig |=
709 DISPPLL_CONFIG_COHERENT_MODE;
710 /* 16200 or 27000 */
711 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
712 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
713 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
714 if (dig->coherent_mode)
715 args.v3.sInput.ucDispPllConfig |=
716 DISPPLL_CONFIG_COHERENT_MODE;
717 if (is_duallink)
718 args.v3.sInput.ucDispPllConfig |=
719 DISPPLL_CONFIG_DUAL_LINK;
720 }
721 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
722 ENCODER_OBJECT_ID_NONE)
723 args.v3.sInput.ucExtTransmitterID =
724 radeon_encoder_get_dp_bridge_encoder_id(encoder);
725 else
726 args.v3.sInput.ucExtTransmitterID = 0;
727
728 atom_execute_table(rdev->mode_info.atom_context,
729 index, (uint32_t *)&args);
730 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
731 if (args.v3.sOutput.ucRefDiv) {
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
733 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
734 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
735 }
736 if (args.v3.sOutput.ucPostDiv) {
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
739 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
740 }
741 break;
742 default:
743 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
744 return adjusted_clock;
745 }
746 break;
747 default:
748 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
749 return adjusted_clock;
750 }
751 }
752 return adjusted_clock;
753}
754
755union set_pixel_clock {
756 SET_PIXEL_CLOCK_PS_ALLOCATION base;
757 PIXEL_CLOCK_PARAMETERS v1;
758 PIXEL_CLOCK_PARAMETERS_V2 v2;
759 PIXEL_CLOCK_PARAMETERS_V3 v3;
760 PIXEL_CLOCK_PARAMETERS_V5 v5;
761 PIXEL_CLOCK_PARAMETERS_V6 v6;
762};
763
764/* on DCE5, make sure the voltage is high enough to support the
765 * required disp clk.
766 */
767static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
768 u32 dispclk)
769{
770 u8 frev, crev;
771 int index;
772 union set_pixel_clock args;
773
774 memset(&args, 0, sizeof(args));
775
776 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
777 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
778 &crev))
779 return;
780
781 switch (frev) {
782 case 1:
783 switch (crev) {
784 case 5:
785 /* if the default dcpll clock is specified,
786 * SetPixelClock provides the dividers
787 */
788 args.v5.ucCRTC = ATOM_CRTC_INVALID;
789 args.v5.usPixelClock = cpu_to_le16(dispclk);
790 args.v5.ucPpll = ATOM_DCPLL;
791 break;
792 case 6:
793 /* if the default dcpll clock is specified,
794 * SetPixelClock provides the dividers
795 */
796 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
797 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
798 args.v6.ucPpll = ATOM_EXT_PLL1;
799 else if (ASIC_IS_DCE6(rdev))
800 args.v6.ucPpll = ATOM_PPLL0;
801 else
802 args.v6.ucPpll = ATOM_DCPLL;
803 break;
804 default:
805 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
806 return;
807 }
808 break;
809 default:
810 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
811 return;
812 }
813 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
814}
815
816static void atombios_crtc_program_pll(struct drm_crtc *crtc,
817 u32 crtc_id,
818 int pll_id,
819 u32 encoder_mode,
820 u32 encoder_id,
821 u32 clock,
822 u32 ref_div,
823 u32 fb_div,
824 u32 frac_fb_div,
825 u32 post_div,
826 int bpc,
827 bool ss_enabled,
828 struct radeon_atom_ss *ss)
829{
830 struct drm_device *dev = crtc->dev;
831 struct radeon_device *rdev = dev->dev_private;
832 u8 frev, crev;
833 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
834 union set_pixel_clock args;
835
836 memset(&args, 0, sizeof(args));
837
838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
839 &crev))
840 return;
841
842 switch (frev) {
843 case 1:
844 switch (crev) {
845 case 1:
846 if (clock == ATOM_DISABLE)
847 return;
848 args.v1.usPixelClock = cpu_to_le16(clock / 10);
849 args.v1.usRefDiv = cpu_to_le16(ref_div);
850 args.v1.usFbDiv = cpu_to_le16(fb_div);
851 args.v1.ucFracFbDiv = frac_fb_div;
852 args.v1.ucPostDiv = post_div;
853 args.v1.ucPpll = pll_id;
854 args.v1.ucCRTC = crtc_id;
855 args.v1.ucRefDivSrc = 1;
856 break;
857 case 2:
858 args.v2.usPixelClock = cpu_to_le16(clock / 10);
859 args.v2.usRefDiv = cpu_to_le16(ref_div);
860 args.v2.usFbDiv = cpu_to_le16(fb_div);
861 args.v2.ucFracFbDiv = frac_fb_div;
862 args.v2.ucPostDiv = post_div;
863 args.v2.ucPpll = pll_id;
864 args.v2.ucCRTC = crtc_id;
865 args.v2.ucRefDivSrc = 1;
866 break;
867 case 3:
868 args.v3.usPixelClock = cpu_to_le16(clock / 10);
869 args.v3.usRefDiv = cpu_to_le16(ref_div);
870 args.v3.usFbDiv = cpu_to_le16(fb_div);
871 args.v3.ucFracFbDiv = frac_fb_div;
872 args.v3.ucPostDiv = post_div;
873 args.v3.ucPpll = pll_id;
874 if (crtc_id == ATOM_CRTC2)
875 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
876 else
877 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
878 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
879 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
880 args.v3.ucTransmitterId = encoder_id;
881 args.v3.ucEncoderMode = encoder_mode;
882 break;
883 case 5:
884 args.v5.ucCRTC = crtc_id;
885 args.v5.usPixelClock = cpu_to_le16(clock / 10);
886 args.v5.ucRefDiv = ref_div;
887 args.v5.usFbDiv = cpu_to_le16(fb_div);
888 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
889 args.v5.ucPostDiv = post_div;
890 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
891 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
892 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
893 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
894 switch (bpc) {
895 case 8:
896 default:
897 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
898 break;
899 case 10:
900 /* yes this is correct, the atom define is wrong */
901 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
902 break;
903 case 12:
904 /* yes this is correct, the atom define is wrong */
905 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
906 break;
907 }
908 }
909 args.v5.ucTransmitterID = encoder_id;
910 args.v5.ucEncoderMode = encoder_mode;
911 args.v5.ucPpll = pll_id;
912 break;
913 case 6:
914 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
915 args.v6.ucRefDiv = ref_div;
916 args.v6.usFbDiv = cpu_to_le16(fb_div);
917 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
918 args.v6.ucPostDiv = post_div;
919 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
920 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
921 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
922 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
923 switch (bpc) {
924 case 8:
925 default:
926 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
927 break;
928 case 10:
929 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
930 break;
931 case 12:
932 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
933 break;
934 case 16:
935 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
936 break;
937 }
938 }
939 args.v6.ucTransmitterID = encoder_id;
940 args.v6.ucEncoderMode = encoder_mode;
941 args.v6.ucPpll = pll_id;
942 break;
943 default:
944 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
945 return;
946 }
947 break;
948 default:
949 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
950 return;
951 }
952
953 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
954}
955
956static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
957{
958 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
959 struct drm_device *dev = crtc->dev;
960 struct radeon_device *rdev = dev->dev_private;
961 struct radeon_encoder *radeon_encoder =
962 to_radeon_encoder(radeon_crtc->encoder);
963 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
964
965 radeon_crtc->bpc = 8;
966 radeon_crtc->ss_enabled = false;
967
968 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
969 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
970 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
971 struct drm_connector *connector =
972 radeon_get_connector_for_encoder(radeon_crtc->encoder);
973 struct radeon_connector *radeon_connector =
974 to_radeon_connector(connector);
975 struct radeon_connector_atom_dig *dig_connector =
976 radeon_connector->con_priv;
977 int dp_clock;
978
979 /* Assign mode clock for hdmi deep color max clock limit check */
980 radeon_connector->pixelclock_for_modeset = mode->clock;
981 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
982
983 switch (encoder_mode) {
984 case ATOM_ENCODER_MODE_DP_MST:
985 case ATOM_ENCODER_MODE_DP:
986 /* DP/eDP */
987 dp_clock = dig_connector->dp_clock / 10;
988 if (ASIC_IS_DCE4(rdev))
989 radeon_crtc->ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
991 ASIC_INTERNAL_SS_ON_DP,
992 dp_clock);
993 else {
994 if (dp_clock == 16200) {
995 radeon_crtc->ss_enabled =
996 radeon_atombios_get_ppll_ss_info(rdev,
997 &radeon_crtc->ss,
998 ATOM_DP_SS_ID2);
999 if (!radeon_crtc->ss_enabled)
1000 radeon_crtc->ss_enabled =
1001 radeon_atombios_get_ppll_ss_info(rdev,
1002 &radeon_crtc->ss,
1003 ATOM_DP_SS_ID1);
1004 } else {
1005 radeon_crtc->ss_enabled =
1006 radeon_atombios_get_ppll_ss_info(rdev,
1007 &radeon_crtc->ss,
1008 ATOM_DP_SS_ID1);
1009 }
1010 /* disable spread spectrum on DCE3 DP */
1011 radeon_crtc->ss_enabled = false;
1012 }
1013 break;
1014 case ATOM_ENCODER_MODE_LVDS:
1015 if (ASIC_IS_DCE4(rdev))
1016 radeon_crtc->ss_enabled =
1017 radeon_atombios_get_asic_ss_info(rdev,
1018 &radeon_crtc->ss,
1019 dig->lcd_ss_id,
1020 mode->clock / 10);
1021 else
1022 radeon_crtc->ss_enabled =
1023 radeon_atombios_get_ppll_ss_info(rdev,
1024 &radeon_crtc->ss,
1025 dig->lcd_ss_id);
1026 break;
1027 case ATOM_ENCODER_MODE_DVI:
1028 if (ASIC_IS_DCE4(rdev))
1029 radeon_crtc->ss_enabled =
1030 radeon_atombios_get_asic_ss_info(rdev,
1031 &radeon_crtc->ss,
1032 ASIC_INTERNAL_SS_ON_TMDS,
1033 mode->clock / 10);
1034 break;
1035 case ATOM_ENCODER_MODE_HDMI:
1036 if (ASIC_IS_DCE4(rdev))
1037 radeon_crtc->ss_enabled =
1038 radeon_atombios_get_asic_ss_info(rdev,
1039 &radeon_crtc->ss,
1040 ASIC_INTERNAL_SS_ON_HDMI,
1041 mode->clock / 10);
1042 break;
1043 default:
1044 break;
1045 }
1046 }
1047
1048 /* adjust pixel clock as needed */
1049 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1050
1051 return true;
1052}
1053
1054static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1055{
1056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1057 struct drm_device *dev = crtc->dev;
1058 struct radeon_device *rdev = dev->dev_private;
1059 struct radeon_encoder *radeon_encoder =
1060 to_radeon_encoder(radeon_crtc->encoder);
1061 u32 pll_clock = mode->clock;
1062 u32 clock = mode->clock;
1063 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1064 struct radeon_pll *pll;
1065 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1066
1067 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1068 if (ASIC_IS_DCE5(rdev) &&
1069 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1070 (radeon_crtc->bpc > 8))
1071 clock = radeon_crtc->adjusted_clock;
1072
1073 switch (radeon_crtc->pll_id) {
1074 case ATOM_PPLL1:
1075 pll = &rdev->clock.p1pll;
1076 break;
1077 case ATOM_PPLL2:
1078 pll = &rdev->clock.p2pll;
1079 break;
1080 case ATOM_DCPLL:
1081 case ATOM_PPLL_INVALID:
1082 default:
1083 pll = &rdev->clock.dcpll;
1084 break;
1085 }
1086
1087 /* update pll params */
1088 pll->flags = radeon_crtc->pll_flags;
1089 pll->reference_div = radeon_crtc->pll_reference_div;
1090 pll->post_div = radeon_crtc->pll_post_div;
1091
1092 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1093 /* TV seems to prefer the legacy algo on some boards */
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1095 &fb_div, &frac_fb_div, &ref_div, &post_div);
1096 else if (ASIC_IS_AVIVO(rdev))
1097 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1098 &fb_div, &frac_fb_div, &ref_div, &post_div);
1099 else
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101 &fb_div, &frac_fb_div, &ref_div, &post_div);
1102
1103 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1104 radeon_crtc->crtc_id, &radeon_crtc->ss);
1105
1106 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1107 encoder_mode, radeon_encoder->encoder_id, clock,
1108 ref_div, fb_div, frac_fb_div, post_div,
1109 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1110
1111 if (radeon_crtc->ss_enabled) {
1112 /* calculate ss amount and step size */
1113 if (ASIC_IS_DCE4(rdev)) {
1114 u32 step_size;
1115 u32 amount = (((fb_div * 10) + frac_fb_div) *
1116 (u32)radeon_crtc->ss.percentage) /
1117 (100 * (u32)radeon_crtc->ss.percentage_divider);
1118 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1119 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1120 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1121 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1122 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1123 (125 * 25 * pll->reference_freq / 100);
1124 else
1125 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1126 (125 * 25 * pll->reference_freq / 100);
1127 radeon_crtc->ss.step = step_size;
1128 }
1129
1130 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1131 radeon_crtc->crtc_id, &radeon_crtc->ss);
1132 }
1133}
1134
1135static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1136 struct drm_framebuffer *fb,
1137 int x, int y, int atomic)
1138{
1139 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1140 struct drm_device *dev = crtc->dev;
1141 struct radeon_device *rdev = dev->dev_private;
1142 struct drm_framebuffer *target_fb;
1143 struct drm_gem_object *obj;
1144 struct radeon_bo *rbo;
1145 uint64_t fb_location;
1146 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1147 unsigned bankw, bankh, mtaspect, tile_split;
1148 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1149 u32 tmp, viewport_w, viewport_h;
1150 int r;
1151 bool bypass_lut = false;
1152
1153 /* no fb bound */
1154 if (!atomic && !crtc->primary->fb) {
1155 DRM_DEBUG_KMS("No FB bound\n");
1156 return 0;
1157 }
1158
1159 if (atomic)
1160 target_fb = fb;
1161 else
1162 target_fb = crtc->primary->fb;
1163
1164 /* If atomic, assume fb object is pinned & idle & fenced and
1165 * just update base pointers
1166 */
1167 obj = target_fb->obj[0];
1168 rbo = gem_to_radeon_bo(obj);
1169 r = radeon_bo_reserve(rbo, false);
1170 if (unlikely(r != 0))
1171 return r;
1172
1173 if (atomic)
1174 fb_location = radeon_bo_gpu_offset(rbo);
1175 else {
1176 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1177 if (unlikely(r != 0)) {
1178 radeon_bo_unreserve(rbo);
1179 return -EINVAL;
1180 }
1181 }
1182
1183 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1184 radeon_bo_unreserve(rbo);
1185
1186 switch (target_fb->format->format) {
1187 case DRM_FORMAT_C8:
1188 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1189 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1190 break;
1191 case DRM_FORMAT_XRGB4444:
1192 case DRM_FORMAT_ARGB4444:
1193 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1194 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1195#ifdef __BIG_ENDIAN
1196 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1197#endif
1198 break;
1199 case DRM_FORMAT_XRGB1555:
1200 case DRM_FORMAT_ARGB1555:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1203#ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205#endif
1206 break;
1207 case DRM_FORMAT_BGRX5551:
1208 case DRM_FORMAT_BGRA5551:
1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1211#ifdef __BIG_ENDIAN
1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1213#endif
1214 break;
1215 case DRM_FORMAT_RGB565:
1216 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1217 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1218#ifdef __BIG_ENDIAN
1219 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1220#endif
1221 break;
1222 case DRM_FORMAT_XRGB8888:
1223 case DRM_FORMAT_ARGB8888:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1226#ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1228#endif
1229 break;
1230 case DRM_FORMAT_XRGB2101010:
1231 case DRM_FORMAT_ARGB2101010:
1232 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1233 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1234#ifdef __BIG_ENDIAN
1235 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1236#endif
1237 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1238 bypass_lut = true;
1239 break;
1240 case DRM_FORMAT_BGRX1010102:
1241 case DRM_FORMAT_BGRA1010102:
1242 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1243 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1244#ifdef __BIG_ENDIAN
1245 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1246#endif
1247 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1248 bypass_lut = true;
1249 break;
1250 case DRM_FORMAT_XBGR8888:
1251 case DRM_FORMAT_ABGR8888:
1252 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1253 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1254 fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
1255 EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
1256#ifdef __BIG_ENDIAN
1257 fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1258#endif
1259 break;
1260 default:
1261 DRM_ERROR("Unsupported screen format %p4cc\n",
1262 &target_fb->format->format);
1263 return -EINVAL;
1264 }
1265
1266 if (tiling_flags & RADEON_TILING_MACRO) {
1267 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1268
1269 /* Set NUM_BANKS. */
1270 if (rdev->family >= CHIP_TAHITI) {
1271 unsigned index, num_banks;
1272
1273 if (rdev->family >= CHIP_BONAIRE) {
1274 unsigned tileb, tile_split_bytes;
1275
1276 /* Calculate the macrotile mode index. */
1277 tile_split_bytes = 64 << tile_split;
1278 tileb = 8 * 8 * target_fb->format->cpp[0];
1279 tileb = min(tile_split_bytes, tileb);
1280
1281 for (index = 0; tileb > 64; index++)
1282 tileb >>= 1;
1283
1284 if (index >= 16) {
1285 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1286 target_fb->format->cpp[0] * 8,
1287 tile_split);
1288 return -EINVAL;
1289 }
1290
1291 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1292 } else {
1293 switch (target_fb->format->cpp[0] * 8) {
1294 case 8:
1295 index = 10;
1296 break;
1297 case 16:
1298 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1299 break;
1300 default:
1301 case 32:
1302 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1303 break;
1304 }
1305
1306 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1307 }
1308
1309 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1310 } else {
1311 /* NI and older. */
1312 if (rdev->family >= CHIP_CAYMAN)
1313 tmp = rdev->config.cayman.tile_config;
1314 else
1315 tmp = rdev->config.evergreen.tile_config;
1316
1317 switch ((tmp & 0xf0) >> 4) {
1318 case 0: /* 4 banks */
1319 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1320 break;
1321 case 1: /* 8 banks */
1322 default:
1323 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1324 break;
1325 case 2: /* 16 banks */
1326 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1327 break;
1328 }
1329 }
1330
1331 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1332 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1333 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1334 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1335 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1336 if (rdev->family >= CHIP_BONAIRE) {
1337 /* XXX need to know more about the surface tiling mode */
1338 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1339 }
1340 } else if (tiling_flags & RADEON_TILING_MICRO)
1341 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1342
1343 if (rdev->family >= CHIP_BONAIRE) {
1344 /* Read the pipe config from the 2D TILED SCANOUT mode.
1345 * It should be the same for the other modes too, but not all
1346 * modes set the pipe config field. */
1347 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1348
1349 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1350 } else if ((rdev->family == CHIP_TAHITI) ||
1351 (rdev->family == CHIP_PITCAIRN))
1352 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1353 else if ((rdev->family == CHIP_VERDE) ||
1354 (rdev->family == CHIP_OLAND) ||
1355 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1356 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1357
1358 switch (radeon_crtc->crtc_id) {
1359 case 0:
1360 WREG32(AVIVO_D1VGA_CONTROL, 0);
1361 break;
1362 case 1:
1363 WREG32(AVIVO_D2VGA_CONTROL, 0);
1364 break;
1365 case 2:
1366 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1367 break;
1368 case 3:
1369 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1370 break;
1371 case 4:
1372 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1373 break;
1374 case 5:
1375 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1376 break;
1377 default:
1378 break;
1379 }
1380
1381 /* Make sure surface address is updated at vertical blank rather than
1382 * horizontal blank
1383 */
1384 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1385
1386 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1387 upper_32_bits(fb_location));
1388 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1389 upper_32_bits(fb_location));
1390 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1391 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1392 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1393 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1394 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1395 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1396
1397 /*
1398 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1399 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1400 * retain the full precision throughout the pipeline.
1401 */
1402 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1403 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1404 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1405
1406 if (bypass_lut)
1407 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1408
1409 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1410 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1411 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1412 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1413 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1414 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1415
1416 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1417 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1418 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1419
1420 if (rdev->family >= CHIP_BONAIRE)
1421 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1422 target_fb->height);
1423 else
1424 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1425 target_fb->height);
1426 x &= ~3;
1427 y &= ~1;
1428 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1429 (x << 16) | y);
1430 viewport_w = crtc->mode.hdisplay;
1431 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1432 if ((rdev->family >= CHIP_BONAIRE) &&
1433 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1434 viewport_h *= 2;
1435 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1436 (viewport_w << 16) | viewport_h);
1437
1438 /* set pageflip to happen anywhere in vblank interval */
1439 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1440
1441 if (!atomic && fb && fb != crtc->primary->fb) {
1442 rbo = gem_to_radeon_bo(fb->obj[0]);
1443 r = radeon_bo_reserve(rbo, false);
1444 if (unlikely(r != 0))
1445 return r;
1446 radeon_bo_unpin(rbo);
1447 radeon_bo_unreserve(rbo);
1448 }
1449
1450 /* Bytes per pixel may have changed */
1451 radeon_bandwidth_update(rdev);
1452
1453 return 0;
1454}
1455
1456static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1457 struct drm_framebuffer *fb,
1458 int x, int y, int atomic)
1459{
1460 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1461 struct drm_device *dev = crtc->dev;
1462 struct radeon_device *rdev = dev->dev_private;
1463 struct drm_gem_object *obj;
1464 struct radeon_bo *rbo;
1465 struct drm_framebuffer *target_fb;
1466 uint64_t fb_location;
1467 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1468 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1469 u32 viewport_w, viewport_h;
1470 int r;
1471 bool bypass_lut = false;
1472
1473 /* no fb bound */
1474 if (!atomic && !crtc->primary->fb) {
1475 DRM_DEBUG_KMS("No FB bound\n");
1476 return 0;
1477 }
1478
1479 if (atomic)
1480 target_fb = fb;
1481 else
1482 target_fb = crtc->primary->fb;
1483
1484 obj = target_fb->obj[0];
1485 rbo = gem_to_radeon_bo(obj);
1486 r = radeon_bo_reserve(rbo, false);
1487 if (unlikely(r != 0))
1488 return r;
1489
1490 /* If atomic, assume fb object is pinned & idle & fenced and
1491 * just update base pointers
1492 */
1493 if (atomic)
1494 fb_location = radeon_bo_gpu_offset(rbo);
1495 else {
1496 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1497 if (unlikely(r != 0)) {
1498 radeon_bo_unreserve(rbo);
1499 return -EINVAL;
1500 }
1501 }
1502 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1503 radeon_bo_unreserve(rbo);
1504
1505 switch (target_fb->format->format) {
1506 case DRM_FORMAT_C8:
1507 fb_format =
1508 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1509 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1510 break;
1511 case DRM_FORMAT_XRGB4444:
1512 case DRM_FORMAT_ARGB4444:
1513 fb_format =
1514 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1515 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1516#ifdef __BIG_ENDIAN
1517 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1518#endif
1519 break;
1520 case DRM_FORMAT_XRGB1555:
1521 fb_format =
1522 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1523 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1524#ifdef __BIG_ENDIAN
1525 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1526#endif
1527 break;
1528 case DRM_FORMAT_RGB565:
1529 fb_format =
1530 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1531 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1532#ifdef __BIG_ENDIAN
1533 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1534#endif
1535 break;
1536 case DRM_FORMAT_XRGB8888:
1537 case DRM_FORMAT_ARGB8888:
1538 fb_format =
1539 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1540 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1541#ifdef __BIG_ENDIAN
1542 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1543#endif
1544 break;
1545 case DRM_FORMAT_XRGB2101010:
1546 case DRM_FORMAT_ARGB2101010:
1547 fb_format =
1548 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1549 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1550#ifdef __BIG_ENDIAN
1551 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1552#endif
1553 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1554 bypass_lut = true;
1555 break;
1556 case DRM_FORMAT_XBGR8888:
1557 case DRM_FORMAT_ABGR8888:
1558 fb_format =
1559 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1560 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1561 if (rdev->family >= CHIP_R600)
1562 fb_swap =
1563 (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
1564 R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
1565 else /* DCE1 (R5xx) */
1566 fb_format |= AVIVO_D1GRPH_SWAP_RB;
1567#ifdef __BIG_ENDIAN
1568 fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
1569#endif
1570 break;
1571 default:
1572 DRM_ERROR("Unsupported screen format %p4cc\n",
1573 &target_fb->format->format);
1574 return -EINVAL;
1575 }
1576
1577 if (rdev->family >= CHIP_R600) {
1578 if (tiling_flags & RADEON_TILING_MACRO)
1579 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1580 else if (tiling_flags & RADEON_TILING_MICRO)
1581 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1582 } else {
1583 if (tiling_flags & RADEON_TILING_MACRO)
1584 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1585
1586 if (tiling_flags & RADEON_TILING_MICRO)
1587 fb_format |= AVIVO_D1GRPH_TILED;
1588 }
1589
1590 if (radeon_crtc->crtc_id == 0)
1591 WREG32(AVIVO_D1VGA_CONTROL, 0);
1592 else
1593 WREG32(AVIVO_D2VGA_CONTROL, 0);
1594
1595 /* Make sure surface address is update at vertical blank rather than
1596 * horizontal blank
1597 */
1598 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1599
1600 if (rdev->family >= CHIP_RV770) {
1601 if (radeon_crtc->crtc_id) {
1602 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1603 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1604 } else {
1605 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1606 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1607 }
1608 }
1609 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1610 (u32) fb_location);
1611 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1612 radeon_crtc->crtc_offset, (u32) fb_location);
1613 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1614 if (rdev->family >= CHIP_R600)
1615 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1616
1617 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1618 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1619 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1620
1621 if (bypass_lut)
1622 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1623
1624 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1625 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1626 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1627 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1628 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1629 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1630
1631 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1632 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1633 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1634
1635 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1636 target_fb->height);
1637 x &= ~3;
1638 y &= ~1;
1639 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1640 (x << 16) | y);
1641 viewport_w = crtc->mode.hdisplay;
1642 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1643 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1644 (viewport_w << 16) | viewport_h);
1645
1646 /* set pageflip to happen only at start of vblank interval (front porch) */
1647 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1648
1649 if (!atomic && fb && fb != crtc->primary->fb) {
1650 rbo = gem_to_radeon_bo(fb->obj[0]);
1651 r = radeon_bo_reserve(rbo, false);
1652 if (unlikely(r != 0))
1653 return r;
1654 radeon_bo_unpin(rbo);
1655 radeon_bo_unreserve(rbo);
1656 }
1657
1658 /* Bytes per pixel may have changed */
1659 radeon_bandwidth_update(rdev);
1660
1661 return 0;
1662}
1663
1664int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1665 struct drm_framebuffer *old_fb)
1666{
1667 struct drm_device *dev = crtc->dev;
1668 struct radeon_device *rdev = dev->dev_private;
1669
1670 if (ASIC_IS_DCE4(rdev))
1671 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1672 else if (ASIC_IS_AVIVO(rdev))
1673 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1674 else
1675 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1676}
1677
1678int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1679 struct drm_framebuffer *fb,
1680 int x, int y, enum mode_set_atomic state)
1681{
1682 struct drm_device *dev = crtc->dev;
1683 struct radeon_device *rdev = dev->dev_private;
1684
1685 if (ASIC_IS_DCE4(rdev))
1686 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1687 else if (ASIC_IS_AVIVO(rdev))
1688 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1689 else
1690 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1691}
1692
1693/* properly set additional regs when using atombios */
1694static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1695{
1696 struct drm_device *dev = crtc->dev;
1697 struct radeon_device *rdev = dev->dev_private;
1698 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1699 u32 disp_merge_cntl;
1700
1701 switch (radeon_crtc->crtc_id) {
1702 case 0:
1703 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1704 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1705 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1706 break;
1707 case 1:
1708 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1709 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1710 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1711 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1712 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1713 break;
1714 }
1715}
1716
1717/**
1718 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1719 *
1720 * @crtc: drm crtc
1721 *
1722 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1723 */
1724static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1725{
1726 struct drm_device *dev = crtc->dev;
1727 struct drm_crtc *test_crtc;
1728 struct radeon_crtc *test_radeon_crtc;
1729 u32 pll_in_use = 0;
1730
1731 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1732 if (crtc == test_crtc)
1733 continue;
1734
1735 test_radeon_crtc = to_radeon_crtc(test_crtc);
1736 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1737 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1738 }
1739 return pll_in_use;
1740}
1741
1742/**
1743 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1744 *
1745 * @crtc: drm crtc
1746 *
1747 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1748 * also in DP mode. For DP, a single PPLL can be used for all DP
1749 * crtcs/encoders.
1750 */
1751static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1752{
1753 struct drm_device *dev = crtc->dev;
1754 struct radeon_device *rdev = dev->dev_private;
1755 struct drm_crtc *test_crtc;
1756 struct radeon_crtc *test_radeon_crtc;
1757
1758 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1759 if (crtc == test_crtc)
1760 continue;
1761 test_radeon_crtc = to_radeon_crtc(test_crtc);
1762 if (test_radeon_crtc->encoder &&
1763 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1764 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1765 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1766 test_radeon_crtc->pll_id == ATOM_PPLL2)
1767 continue;
1768 /* for DP use the same PLL for all */
1769 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1770 return test_radeon_crtc->pll_id;
1771 }
1772 }
1773 return ATOM_PPLL_INVALID;
1774}
1775
1776/**
1777 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1778 *
1779 * @crtc: drm crtc
1780 *
1781 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1782 * be shared (i.e., same clock).
1783 */
1784static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1785{
1786 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1787 struct drm_device *dev = crtc->dev;
1788 struct radeon_device *rdev = dev->dev_private;
1789 struct drm_crtc *test_crtc;
1790 struct radeon_crtc *test_radeon_crtc;
1791 u32 adjusted_clock, test_adjusted_clock;
1792
1793 adjusted_clock = radeon_crtc->adjusted_clock;
1794
1795 if (adjusted_clock == 0)
1796 return ATOM_PPLL_INVALID;
1797
1798 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1799 if (crtc == test_crtc)
1800 continue;
1801 test_radeon_crtc = to_radeon_crtc(test_crtc);
1802 if (test_radeon_crtc->encoder &&
1803 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1804 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1805 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1806 test_radeon_crtc->pll_id == ATOM_PPLL2)
1807 continue;
1808 /* check if we are already driving this connector with another crtc */
1809 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1810 /* if we are, return that pll */
1811 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1812 return test_radeon_crtc->pll_id;
1813 }
1814 /* for non-DP check the clock */
1815 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1816 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1817 (adjusted_clock == test_adjusted_clock) &&
1818 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1819 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1820 return test_radeon_crtc->pll_id;
1821 }
1822 }
1823 return ATOM_PPLL_INVALID;
1824}
1825
1826/**
1827 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1828 *
1829 * @crtc: drm crtc
1830 *
1831 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1832 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1833 * monitors a dedicated PPLL must be used. If a particular board has
1834 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1835 * as there is no need to program the PLL itself. If we are not able to
1836 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1837 * avoid messing up an existing monitor.
1838 *
1839 * Asic specific PLL information
1840 *
1841 * DCE 8.x
1842 * KB/KV
1843 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1844 * CI
1845 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1846 *
1847 * DCE 6.1
1848 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1849 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1850 *
1851 * DCE 6.0
1852 * - PPLL0 is available to all UNIPHY (DP only)
1853 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1854 *
1855 * DCE 5.0
1856 * - DCPLL is available to all UNIPHY (DP only)
1857 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1858 *
1859 * DCE 3.0/4.0/4.1
1860 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1861 *
1862 */
1863static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1864{
1865 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1866 struct drm_device *dev = crtc->dev;
1867 struct radeon_device *rdev = dev->dev_private;
1868 struct radeon_encoder *radeon_encoder =
1869 to_radeon_encoder(radeon_crtc->encoder);
1870 u32 pll_in_use;
1871 int pll;
1872
1873 if (ASIC_IS_DCE8(rdev)) {
1874 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1875 if (rdev->clock.dp_extclk)
1876 /* skip PPLL programming if using ext clock */
1877 return ATOM_PPLL_INVALID;
1878 else {
1879 /* use the same PPLL for all DP monitors */
1880 pll = radeon_get_shared_dp_ppll(crtc);
1881 if (pll != ATOM_PPLL_INVALID)
1882 return pll;
1883 }
1884 } else {
1885 /* use the same PPLL for all monitors with the same clock */
1886 pll = radeon_get_shared_nondp_ppll(crtc);
1887 if (pll != ATOM_PPLL_INVALID)
1888 return pll;
1889 }
1890 /* otherwise, pick one of the plls */
1891 if ((rdev->family == CHIP_KABINI) ||
1892 (rdev->family == CHIP_MULLINS)) {
1893 /* KB/ML has PPLL1 and PPLL2 */
1894 pll_in_use = radeon_get_pll_use_mask(crtc);
1895 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1896 return ATOM_PPLL2;
1897 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1898 return ATOM_PPLL1;
1899 DRM_ERROR("unable to allocate a PPLL\n");
1900 return ATOM_PPLL_INVALID;
1901 } else {
1902 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1903 pll_in_use = radeon_get_pll_use_mask(crtc);
1904 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1905 return ATOM_PPLL2;
1906 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1907 return ATOM_PPLL1;
1908 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1909 return ATOM_PPLL0;
1910 DRM_ERROR("unable to allocate a PPLL\n");
1911 return ATOM_PPLL_INVALID;
1912 }
1913 } else if (ASIC_IS_DCE61(rdev)) {
1914 struct radeon_encoder_atom_dig *dig =
1915 radeon_encoder->enc_priv;
1916
1917 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1918 (dig->linkb == false))
1919 /* UNIPHY A uses PPLL2 */
1920 return ATOM_PPLL2;
1921 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1922 /* UNIPHY B/C/D/E/F */
1923 if (rdev->clock.dp_extclk)
1924 /* skip PPLL programming if using ext clock */
1925 return ATOM_PPLL_INVALID;
1926 else {
1927 /* use the same PPLL for all DP monitors */
1928 pll = radeon_get_shared_dp_ppll(crtc);
1929 if (pll != ATOM_PPLL_INVALID)
1930 return pll;
1931 }
1932 } else {
1933 /* use the same PPLL for all monitors with the same clock */
1934 pll = radeon_get_shared_nondp_ppll(crtc);
1935 if (pll != ATOM_PPLL_INVALID)
1936 return pll;
1937 }
1938 /* UNIPHY B/C/D/E/F */
1939 pll_in_use = radeon_get_pll_use_mask(crtc);
1940 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1941 return ATOM_PPLL0;
1942 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1943 return ATOM_PPLL1;
1944 DRM_ERROR("unable to allocate a PPLL\n");
1945 return ATOM_PPLL_INVALID;
1946 } else if (ASIC_IS_DCE41(rdev)) {
1947 /* Don't share PLLs on DCE4.1 chips */
1948 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1949 if (rdev->clock.dp_extclk)
1950 /* skip PPLL programming if using ext clock */
1951 return ATOM_PPLL_INVALID;
1952 }
1953 pll_in_use = radeon_get_pll_use_mask(crtc);
1954 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1955 return ATOM_PPLL1;
1956 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1957 return ATOM_PPLL2;
1958 DRM_ERROR("unable to allocate a PPLL\n");
1959 return ATOM_PPLL_INVALID;
1960 } else if (ASIC_IS_DCE4(rdev)) {
1961 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1962 * depending on the asic:
1963 * DCE4: PPLL or ext clock
1964 * DCE5: PPLL, DCPLL, or ext clock
1965 * DCE6: PPLL, PPLL0, or ext clock
1966 *
1967 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1968 * PPLL/DCPLL programming and only program the DP DTO for the
1969 * crtc virtual pixel clock.
1970 */
1971 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1972 if (rdev->clock.dp_extclk)
1973 /* skip PPLL programming if using ext clock */
1974 return ATOM_PPLL_INVALID;
1975 else if (ASIC_IS_DCE6(rdev))
1976 /* use PPLL0 for all DP */
1977 return ATOM_PPLL0;
1978 else if (ASIC_IS_DCE5(rdev))
1979 /* use DCPLL for all DP */
1980 return ATOM_DCPLL;
1981 else {
1982 /* use the same PPLL for all DP monitors */
1983 pll = radeon_get_shared_dp_ppll(crtc);
1984 if (pll != ATOM_PPLL_INVALID)
1985 return pll;
1986 }
1987 } else {
1988 /* use the same PPLL for all monitors with the same clock */
1989 pll = radeon_get_shared_nondp_ppll(crtc);
1990 if (pll != ATOM_PPLL_INVALID)
1991 return pll;
1992 }
1993 /* all other cases */
1994 pll_in_use = radeon_get_pll_use_mask(crtc);
1995 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1996 return ATOM_PPLL1;
1997 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1998 return ATOM_PPLL2;
1999 DRM_ERROR("unable to allocate a PPLL\n");
2000 return ATOM_PPLL_INVALID;
2001 } else {
2002 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
2003 /* some atombios (observed in some DCE2/DCE3) code have a bug,
2004 * the matching btw pll and crtc is done through
2005 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
2006 * pll (1 or 2) to select which register to write. ie if using
2007 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
2008 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
2009 * choose which value to write. Which is reverse order from
2010 * register logic. So only case that works is when pllid is
2011 * same as crtcid or when both pll and crtc are enabled and
2012 * both use same clock.
2013 *
2014 * So just return crtc id as if crtc and pll were hard linked
2015 * together even if they aren't
2016 */
2017 return radeon_crtc->crtc_id;
2018 }
2019}
2020
2021void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2022{
2023 /* always set DCPLL */
2024 if (ASIC_IS_DCE6(rdev))
2025 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2026 else if (ASIC_IS_DCE4(rdev)) {
2027 struct radeon_atom_ss ss;
2028 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2029 ASIC_INTERNAL_SS_ON_DCPLL,
2030 rdev->clock.default_dispclk);
2031 if (ss_enabled)
2032 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2033 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2034 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2035 if (ss_enabled)
2036 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2037 }
2038
2039}
2040
2041int atombios_crtc_mode_set(struct drm_crtc *crtc,
2042 struct drm_display_mode *mode,
2043 struct drm_display_mode *adjusted_mode,
2044 int x, int y, struct drm_framebuffer *old_fb)
2045{
2046 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2047 struct drm_device *dev = crtc->dev;
2048 struct radeon_device *rdev = dev->dev_private;
2049 struct radeon_encoder *radeon_encoder =
2050 to_radeon_encoder(radeon_crtc->encoder);
2051 bool is_tvcv = false;
2052
2053 if (radeon_encoder->active_device &
2054 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2055 is_tvcv = true;
2056
2057 if (!radeon_crtc->adjusted_clock)
2058 return -EINVAL;
2059
2060 atombios_crtc_set_pll(crtc, adjusted_mode);
2061
2062 if (ASIC_IS_DCE4(rdev))
2063 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2064 else if (ASIC_IS_AVIVO(rdev)) {
2065 if (is_tvcv)
2066 atombios_crtc_set_timing(crtc, adjusted_mode);
2067 else
2068 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2069 } else {
2070 atombios_crtc_set_timing(crtc, adjusted_mode);
2071 if (radeon_crtc->crtc_id == 0)
2072 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2073 radeon_legacy_atom_fixup(crtc);
2074 }
2075 atombios_crtc_set_base(crtc, x, y, old_fb);
2076 atombios_overscan_setup(crtc, mode, adjusted_mode);
2077 atombios_scaler_setup(crtc);
2078 radeon_cursor_reset(crtc);
2079 /* update the hw version fpr dpm */
2080 radeon_crtc->hw_mode = *adjusted_mode;
2081
2082 return 0;
2083}
2084
2085static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2086 const struct drm_display_mode *mode,
2087 struct drm_display_mode *adjusted_mode)
2088{
2089 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2090 struct drm_device *dev = crtc->dev;
2091 struct drm_encoder *encoder;
2092
2093 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2095 if (encoder->crtc == crtc) {
2096 radeon_crtc->encoder = encoder;
2097 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2098 break;
2099 }
2100 }
2101 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2102 radeon_crtc->encoder = NULL;
2103 radeon_crtc->connector = NULL;
2104 return false;
2105 }
2106 if (radeon_crtc->encoder) {
2107 struct radeon_encoder *radeon_encoder =
2108 to_radeon_encoder(radeon_crtc->encoder);
2109
2110 radeon_crtc->output_csc = radeon_encoder->output_csc;
2111 }
2112 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2113 return false;
2114 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2115 return false;
2116 /* pick pll */
2117 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2118 /* if we can't get a PPLL for a non-DP encoder, fail */
2119 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2120 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2121 return false;
2122
2123 return true;
2124}
2125
2126static void atombios_crtc_prepare(struct drm_crtc *crtc)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct radeon_device *rdev = dev->dev_private;
2130
2131 /* disable crtc pair power gating before programming */
2132 if (ASIC_IS_DCE6(rdev))
2133 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2134
2135 atombios_lock_crtc(crtc, ATOM_ENABLE);
2136 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2137}
2138
2139static void atombios_crtc_commit(struct drm_crtc *crtc)
2140{
2141 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2142 atombios_lock_crtc(crtc, ATOM_DISABLE);
2143}
2144
2145static void atombios_crtc_disable(struct drm_crtc *crtc)
2146{
2147 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2148 struct drm_device *dev = crtc->dev;
2149 struct radeon_device *rdev = dev->dev_private;
2150 struct radeon_atom_ss ss;
2151 int i;
2152
2153 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2154 if (crtc->primary->fb) {
2155 int r;
2156 struct radeon_bo *rbo;
2157
2158 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
2159 r = radeon_bo_reserve(rbo, false);
2160 if (unlikely(r))
2161 DRM_ERROR("failed to reserve rbo before unpin\n");
2162 else {
2163 radeon_bo_unpin(rbo);
2164 radeon_bo_unreserve(rbo);
2165 }
2166 }
2167 /* disable the GRPH */
2168 if (ASIC_IS_DCE4(rdev))
2169 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2170 else if (ASIC_IS_AVIVO(rdev))
2171 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2172
2173 if (ASIC_IS_DCE6(rdev))
2174 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2175
2176 for (i = 0; i < rdev->num_crtc; i++) {
2177 if (rdev->mode_info.crtcs[i] &&
2178 rdev->mode_info.crtcs[i]->enabled &&
2179 i != radeon_crtc->crtc_id &&
2180 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2181 /* one other crtc is using this pll don't turn
2182 * off the pll
2183 */
2184 goto done;
2185 }
2186 }
2187
2188 switch (radeon_crtc->pll_id) {
2189 case ATOM_PPLL1:
2190 case ATOM_PPLL2:
2191 /* disable the ppll */
2192 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2193 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2194 break;
2195 case ATOM_PPLL0:
2196 /* disable the ppll */
2197 if ((rdev->family == CHIP_ARUBA) ||
2198 (rdev->family == CHIP_KAVERI) ||
2199 (rdev->family == CHIP_BONAIRE) ||
2200 (rdev->family == CHIP_HAWAII))
2201 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2202 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2203 break;
2204 default:
2205 break;
2206 }
2207done:
2208 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2209 radeon_crtc->adjusted_clock = 0;
2210 radeon_crtc->encoder = NULL;
2211 radeon_crtc->connector = NULL;
2212}
2213
2214static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2215 .dpms = atombios_crtc_dpms,
2216 .mode_fixup = atombios_crtc_mode_fixup,
2217 .mode_set = atombios_crtc_mode_set,
2218 .mode_set_base = atombios_crtc_set_base,
2219 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2220 .prepare = atombios_crtc_prepare,
2221 .commit = atombios_crtc_commit,
2222 .disable = atombios_crtc_disable,
2223 .get_scanout_position = radeon_get_crtc_scanout_position,
2224};
2225
2226void radeon_atombios_init_crtc(struct drm_device *dev,
2227 struct radeon_crtc *radeon_crtc)
2228{
2229 struct radeon_device *rdev = dev->dev_private;
2230
2231 if (ASIC_IS_DCE4(rdev)) {
2232 switch (radeon_crtc->crtc_id) {
2233 case 0:
2234 default:
2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2236 break;
2237 case 1:
2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2239 break;
2240 case 2:
2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2242 break;
2243 case 3:
2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2245 break;
2246 case 4:
2247 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2248 break;
2249 case 5:
2250 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2251 break;
2252 }
2253 } else {
2254 if (radeon_crtc->crtc_id == 1)
2255 radeon_crtc->crtc_offset =
2256 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2257 else
2258 radeon_crtc->crtc_offset = 0;
2259 }
2260 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2261 radeon_crtc->adjusted_clock = 0;
2262 radeon_crtc->encoder = NULL;
2263 radeon_crtc->connector = NULL;
2264 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2265}