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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167}
168
169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
261 radeon_crtc->enabled = false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
264 break;
265 }
266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
270 struct drm_display_mode *mode)
271{
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
277 u16 misc = 0;
278
279 memset(&args, 0, sizeof(args));
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
281 args.usH_Blanking_Time =
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
284 args.usV_Blanking_Time =
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
286 args.usH_SyncOffset =
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
310
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312}
313
314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
316{
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
322 u16 misc = 0;
323
324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
354
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356}
357
358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
401union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
407};
408
409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
413{
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args;
418
419 memset(&args, 0, sizeof(args));
420
421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v3.ucEnable = enable;
444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
446 } else if (ASIC_IS_DCE4(rdev)) {
447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
449 switch (pll_id) {
450 case ATOM_PPLL1:
451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
454 break;
455 case ATOM_PPLL2:
456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
459 break;
460 case ATOM_DCPLL:
461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
464 break;
465 case ATOM_PPLL_INVALID:
466 return;
467 }
468 args.v2.ucEnable = enable;
469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
470 args.v2.ucEnable = ATOM_DISABLE;
471 } else if (ASIC_IS_DCE3(rdev)) {
472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 args.v1.ucSpreadSpectrumStep = ss->step;
475 args.v1.ucSpreadSpectrumDelay = ss->delay;
476 args.v1.ucSpreadSpectrumRange = ss->range;
477 args.v1.ucPpll = pll_id;
478 args.v1.ucEnable = enable;
479 } else if (ASIC_IS_AVIVO(rdev)) {
480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
482 atombios_disable_ss(crtc);
483 return;
484 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
490 args.lvds_ss_2.ucEnable = enable;
491 } else {
492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
494 atombios_disable_ss(crtc);
495 return;
496 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
501 args.lvds_ss.ucEnable = enable;
502 }
503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
504}
505
506union adjust_pixel_clock {
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
509};
510
511static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct drm_display_mode *mode,
513 struct radeon_pll *pll,
514 bool ss_enabled,
515 struct radeon_atom_ss *ss)
516{
517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct drm_encoder *encoder = NULL;
520 struct radeon_encoder *radeon_encoder = NULL;
521 struct drm_connector *connector = NULL;
522 u32 adjusted_clock = mode->clock;
523 int encoder_mode = 0;
524 u32 dp_clock = mode->clock;
525 int bpc = 8;
526
527 /* reset the pll flags */
528 pll->flags = 0;
529
530 if (ASIC_IS_AVIVO(rdev)) {
531 if ((rdev->family == CHIP_RS600) ||
532 (rdev->family == CHIP_RS690) ||
533 (rdev->family == CHIP_RS740))
534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
535 RADEON_PLL_PREFER_CLOSEST_LOWER);
536
537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 if (rdev->family < CHIP_RV770)
543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
544 } else {
545 pll->flags |= RADEON_PLL_LEGACY;
546
547 if (mode->clock > 200000) /* range limits??? */
548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
549 else
550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
551 }
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
554 if (encoder->crtc == crtc) {
555 radeon_encoder = to_radeon_encoder(encoder);
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (connector)
558 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 radeon_encoder_is_dp_bridge(encoder)) {
562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector =
565 radeon_connector->con_priv;
566
567 dp_clock = dig_connector->dp_clock;
568 }
569 }
570
571 /* use recommended ref_div for ss */
572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573 if (ss_enabled) {
574 if (ss->refdiv) {
575 pll->flags |= RADEON_PLL_USE_REF_DIV;
576 pll->reference_div = ss->refdiv;
577 if (ASIC_IS_AVIVO(rdev))
578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
579 }
580 }
581 }
582
583 if (ASIC_IS_AVIVO(rdev)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
586 adjusted_clock = mode->clock * 2;
587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
590 pll->flags |= RADEON_PLL_IS_LCD;
591 } else {
592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
595 pll->flags |= RADEON_PLL_USE_REF_DIV;
596 }
597 break;
598 }
599 }
600
601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
604 */
605 if (ASIC_IS_DCE3(rdev)) {
606 union adjust_pixel_clock args;
607 u8 frev, crev;
608 int index;
609
610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
612 &crev))
613 return adjusted_clock;
614
615 memset(&args, 0, sizeof(args));
616
617 switch (frev) {
618 case 1:
619 switch (crev) {
620 case 1:
621 case 2:
622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
624 args.v1.ucEncodeMode = encoder_mode;
625 if (ss_enabled && ss->percentage)
626 args.v1.ucConfig |=
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
628
629 atom_execute_table(rdev->mode_info.atom_context,
630 index, (uint32_t *)&args);
631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
632 break;
633 case 3:
634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
636 args.v3.sInput.ucEncodeMode = encoder_mode;
637 args.v3.sInput.ucDispPllConfig = 0;
638 if (ss_enabled && ss->percentage)
639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE;
641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642 radeon_encoder_is_dp_bridge(encoder)) {
643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
645 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE;
647 /* 16200 or 27000 */
648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649 } else {
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 /* deep color support */
652 args.v3.sInput.usPixelClock =
653 cpu_to_le16((mode->clock * bpc / 8) / 10);
654 }
655 if (dig->coherent_mode)
656 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_COHERENT_MODE;
658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE;
666 /* 16200 or 27000 */
667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669 if (mode->clock > 165000)
670 args.v3.sInput.ucDispPllConfig |=
671 DISPPLL_CONFIG_DUAL_LINK;
672 }
673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
681 atom_execute_table(rdev->mode_info.atom_context,
682 index, (uint32_t *)&args);
683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
684 if (args.v3.sOutput.ucRefDiv) {
685 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
686 pll->flags |= RADEON_PLL_USE_REF_DIV;
687 pll->reference_div = args.v3.sOutput.ucRefDiv;
688 }
689 if (args.v3.sOutput.ucPostDiv) {
690 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
691 pll->flags |= RADEON_PLL_USE_POST_DIV;
692 pll->post_div = args.v3.sOutput.ucPostDiv;
693 }
694 break;
695 default:
696 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 return adjusted_clock;
698 }
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
702 return adjusted_clock;
703 }
704 }
705 return adjusted_clock;
706}
707
708union set_pixel_clock {
709 SET_PIXEL_CLOCK_PS_ALLOCATION base;
710 PIXEL_CLOCK_PARAMETERS v1;
711 PIXEL_CLOCK_PARAMETERS_V2 v2;
712 PIXEL_CLOCK_PARAMETERS_V3 v3;
713 PIXEL_CLOCK_PARAMETERS_V5 v5;
714 PIXEL_CLOCK_PARAMETERS_V6 v6;
715};
716
717/* on DCE5, make sure the voltage is high enough to support the
718 * required disp clk.
719 */
720static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
721 u32 dispclk)
722{
723 struct drm_device *dev = crtc->dev;
724 struct radeon_device *rdev = dev->dev_private;
725 u8 frev, crev;
726 int index;
727 union set_pixel_clock args;
728
729 memset(&args, 0, sizeof(args));
730
731 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
733 &crev))
734 return;
735
736 switch (frev) {
737 case 1:
738 switch (crev) {
739 case 5:
740 /* if the default dcpll clock is specified,
741 * SetPixelClock provides the dividers
742 */
743 args.v5.ucCRTC = ATOM_CRTC_INVALID;
744 args.v5.usPixelClock = cpu_to_le16(dispclk);
745 args.v5.ucPpll = ATOM_DCPLL;
746 break;
747 case 6:
748 /* if the default dcpll clock is specified,
749 * SetPixelClock provides the dividers
750 */
751 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
752 args.v6.ucPpll = ATOM_DCPLL;
753 break;
754 default:
755 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
756 return;
757 }
758 break;
759 default:
760 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
761 return;
762 }
763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
764}
765
766static void atombios_crtc_program_pll(struct drm_crtc *crtc,
767 u32 crtc_id,
768 int pll_id,
769 u32 encoder_mode,
770 u32 encoder_id,
771 u32 clock,
772 u32 ref_div,
773 u32 fb_div,
774 u32 frac_fb_div,
775 u32 post_div,
776 int bpc,
777 bool ss_enabled,
778 struct radeon_atom_ss *ss)
779{
780 struct drm_device *dev = crtc->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 u8 frev, crev;
783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
784 union set_pixel_clock args;
785
786 memset(&args, 0, sizeof(args));
787
788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
789 &crev))
790 return;
791
792 switch (frev) {
793 case 1:
794 switch (crev) {
795 case 1:
796 if (clock == ATOM_DISABLE)
797 return;
798 args.v1.usPixelClock = cpu_to_le16(clock / 10);
799 args.v1.usRefDiv = cpu_to_le16(ref_div);
800 args.v1.usFbDiv = cpu_to_le16(fb_div);
801 args.v1.ucFracFbDiv = frac_fb_div;
802 args.v1.ucPostDiv = post_div;
803 args.v1.ucPpll = pll_id;
804 args.v1.ucCRTC = crtc_id;
805 args.v1.ucRefDivSrc = 1;
806 break;
807 case 2:
808 args.v2.usPixelClock = cpu_to_le16(clock / 10);
809 args.v2.usRefDiv = cpu_to_le16(ref_div);
810 args.v2.usFbDiv = cpu_to_le16(fb_div);
811 args.v2.ucFracFbDiv = frac_fb_div;
812 args.v2.ucPostDiv = post_div;
813 args.v2.ucPpll = pll_id;
814 args.v2.ucCRTC = crtc_id;
815 args.v2.ucRefDivSrc = 1;
816 break;
817 case 3:
818 args.v3.usPixelClock = cpu_to_le16(clock / 10);
819 args.v3.usRefDiv = cpu_to_le16(ref_div);
820 args.v3.usFbDiv = cpu_to_le16(fb_div);
821 args.v3.ucFracFbDiv = frac_fb_div;
822 args.v3.ucPostDiv = post_div;
823 args.v3.ucPpll = pll_id;
824 args.v3.ucMiscInfo = (pll_id << 2);
825 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
826 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
827 args.v3.ucTransmitterId = encoder_id;
828 args.v3.ucEncoderMode = encoder_mode;
829 break;
830 case 5:
831 args.v5.ucCRTC = crtc_id;
832 args.v5.usPixelClock = cpu_to_le16(clock / 10);
833 args.v5.ucRefDiv = ref_div;
834 args.v5.usFbDiv = cpu_to_le16(fb_div);
835 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
836 args.v5.ucPostDiv = post_div;
837 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
838 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
840 switch (bpc) {
841 case 8:
842 default:
843 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
844 break;
845 case 10:
846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
847 break;
848 }
849 args.v5.ucTransmitterID = encoder_id;
850 args.v5.ucEncoderMode = encoder_mode;
851 args.v5.ucPpll = pll_id;
852 break;
853 case 6:
854 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
855 args.v6.ucRefDiv = ref_div;
856 args.v6.usFbDiv = cpu_to_le16(fb_div);
857 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
858 args.v6.ucPostDiv = post_div;
859 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
860 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
861 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
862 switch (bpc) {
863 case 8:
864 default:
865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
866 break;
867 case 10:
868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
869 break;
870 case 12:
871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
872 break;
873 case 16:
874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
875 break;
876 }
877 args.v6.ucTransmitterID = encoder_id;
878 args.v6.ucEncoderMode = encoder_mode;
879 args.v6.ucPpll = pll_id;
880 break;
881 default:
882 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
883 return;
884 }
885 break;
886 default:
887 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
888 return;
889 }
890
891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
892}
893
894static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
895{
896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
897 struct drm_device *dev = crtc->dev;
898 struct radeon_device *rdev = dev->dev_private;
899 struct drm_encoder *encoder = NULL;
900 struct radeon_encoder *radeon_encoder = NULL;
901 u32 pll_clock = mode->clock;
902 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
903 struct radeon_pll *pll;
904 u32 adjusted_clock;
905 int encoder_mode = 0;
906 struct radeon_atom_ss ss;
907 bool ss_enabled = false;
908 int bpc = 8;
909
910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
911 if (encoder->crtc == crtc) {
912 radeon_encoder = to_radeon_encoder(encoder);
913 encoder_mode = atombios_get_encoder_mode(encoder);
914 break;
915 }
916 }
917
918 if (!radeon_encoder)
919 return;
920
921 switch (radeon_crtc->pll_id) {
922 case ATOM_PPLL1:
923 pll = &rdev->clock.p1pll;
924 break;
925 case ATOM_PPLL2:
926 pll = &rdev->clock.p2pll;
927 break;
928 case ATOM_DCPLL:
929 case ATOM_PPLL_INVALID:
930 default:
931 pll = &rdev->clock.dcpll;
932 break;
933 }
934
935 if (radeon_encoder->active_device &
936 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector =
939 radeon_get_connector_for_encoder(encoder);
940 struct radeon_connector *radeon_connector =
941 to_radeon_connector(connector);
942 struct radeon_connector_atom_dig *dig_connector =
943 radeon_connector->con_priv;
944 int dp_clock;
945 bpc = connector->display_info.bpc;
946
947 switch (encoder_mode) {
948 case ATOM_ENCODER_MODE_DP:
949 /* DP/eDP */
950 dp_clock = dig_connector->dp_clock / 10;
951 if (ASIC_IS_DCE4(rdev))
952 ss_enabled =
953 radeon_atombios_get_asic_ss_info(rdev, &ss,
954 ASIC_INTERNAL_SS_ON_DP,
955 dp_clock);
956 else {
957 if (dp_clock == 16200) {
958 ss_enabled =
959 radeon_atombios_get_ppll_ss_info(rdev, &ss,
960 ATOM_DP_SS_ID2);
961 if (!ss_enabled)
962 ss_enabled =
963 radeon_atombios_get_ppll_ss_info(rdev, &ss,
964 ATOM_DP_SS_ID1);
965 } else
966 ss_enabled =
967 radeon_atombios_get_ppll_ss_info(rdev, &ss,
968 ATOM_DP_SS_ID1);
969 }
970 break;
971 case ATOM_ENCODER_MODE_LVDS:
972 if (ASIC_IS_DCE4(rdev))
973 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
974 dig->lcd_ss_id,
975 mode->clock / 10);
976 else
977 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
978 dig->lcd_ss_id);
979 break;
980 case ATOM_ENCODER_MODE_DVI:
981 if (ASIC_IS_DCE4(rdev))
982 ss_enabled =
983 radeon_atombios_get_asic_ss_info(rdev, &ss,
984 ASIC_INTERNAL_SS_ON_TMDS,
985 mode->clock / 10);
986 break;
987 case ATOM_ENCODER_MODE_HDMI:
988 if (ASIC_IS_DCE4(rdev))
989 ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev, &ss,
991 ASIC_INTERNAL_SS_ON_HDMI,
992 mode->clock / 10);
993 break;
994 default:
995 break;
996 }
997 }
998
999 /* adjust pixel clock as needed */
1000 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1001
1002 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1003 /* TV seems to prefer the legacy algo on some boards */
1004 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1005 &ref_div, &post_div);
1006 else if (ASIC_IS_AVIVO(rdev))
1007 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1008 &ref_div, &post_div);
1009 else
1010 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1011 &ref_div, &post_div);
1012
1013 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1014
1015 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1016 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1017 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1018
1019 if (ss_enabled) {
1020 /* calculate ss amount and step size */
1021 if (ASIC_IS_DCE4(rdev)) {
1022 u32 step_size;
1023 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1024 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1025 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1026 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1027 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1028 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1029 (125 * 25 * pll->reference_freq / 100);
1030 else
1031 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1032 (125 * 25 * pll->reference_freq / 100);
1033 ss.step = step_size;
1034 }
1035
1036 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1037 }
1038}
1039
1040static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1041 struct drm_framebuffer *fb,
1042 int x, int y, int atomic)
1043{
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 struct drm_device *dev = crtc->dev;
1046 struct radeon_device *rdev = dev->dev_private;
1047 struct radeon_framebuffer *radeon_fb;
1048 struct drm_framebuffer *target_fb;
1049 struct drm_gem_object *obj;
1050 struct radeon_bo *rbo;
1051 uint64_t fb_location;
1052 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1053 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1054 u32 tmp, viewport_w, viewport_h;
1055 int r;
1056
1057 /* no fb bound */
1058 if (!atomic && !crtc->fb) {
1059 DRM_DEBUG_KMS("No FB bound\n");
1060 return 0;
1061 }
1062
1063 if (atomic) {
1064 radeon_fb = to_radeon_framebuffer(fb);
1065 target_fb = fb;
1066 }
1067 else {
1068 radeon_fb = to_radeon_framebuffer(crtc->fb);
1069 target_fb = crtc->fb;
1070 }
1071
1072 /* If atomic, assume fb object is pinned & idle & fenced and
1073 * just update base pointers
1074 */
1075 obj = radeon_fb->obj;
1076 rbo = gem_to_radeon_bo(obj);
1077 r = radeon_bo_reserve(rbo, false);
1078 if (unlikely(r != 0))
1079 return r;
1080
1081 if (atomic)
1082 fb_location = radeon_bo_gpu_offset(rbo);
1083 else {
1084 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1085 if (unlikely(r != 0)) {
1086 radeon_bo_unreserve(rbo);
1087 return -EINVAL;
1088 }
1089 }
1090
1091 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1092 radeon_bo_unreserve(rbo);
1093
1094 switch (target_fb->bits_per_pixel) {
1095 case 8:
1096 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1097 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1098 break;
1099 case 15:
1100 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1101 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1102 break;
1103 case 16:
1104 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1105 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1106#ifdef __BIG_ENDIAN
1107 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1108#endif
1109 break;
1110 case 24:
1111 case 32:
1112 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1113 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1114#ifdef __BIG_ENDIAN
1115 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1116#endif
1117 break;
1118 default:
1119 DRM_ERROR("Unsupported screen depth %d\n",
1120 target_fb->bits_per_pixel);
1121 return -EINVAL;
1122 }
1123
1124 if (tiling_flags & RADEON_TILING_MACRO)
1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 else if (tiling_flags & RADEON_TILING_MICRO)
1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1128
1129 switch (radeon_crtc->crtc_id) {
1130 case 0:
1131 WREG32(AVIVO_D1VGA_CONTROL, 0);
1132 break;
1133 case 1:
1134 WREG32(AVIVO_D2VGA_CONTROL, 0);
1135 break;
1136 case 2:
1137 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1138 break;
1139 case 3:
1140 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1141 break;
1142 case 4:
1143 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1144 break;
1145 case 5:
1146 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1147 break;
1148 default:
1149 break;
1150 }
1151
1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1153 upper_32_bits(fb_location));
1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1155 upper_32_bits(fb_location));
1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1157 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1159 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1160 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1161 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1162
1163 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1164 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1165 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1166 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1167 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1168 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1169
1170 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1171 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1172 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1173
1174 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1175 crtc->mode.vdisplay);
1176 x &= ~3;
1177 y &= ~1;
1178 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1179 (x << 16) | y);
1180 viewport_w = crtc->mode.hdisplay;
1181 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1182 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1183 (viewport_w << 16) | viewport_h);
1184
1185 /* pageflip setup */
1186 /* make sure flip is at vb rather than hb */
1187 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1188 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1189 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1190
1191 /* set pageflip to happen anywhere in vblank interval */
1192 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1193
1194 if (!atomic && fb && fb != crtc->fb) {
1195 radeon_fb = to_radeon_framebuffer(fb);
1196 rbo = gem_to_radeon_bo(radeon_fb->obj);
1197 r = radeon_bo_reserve(rbo, false);
1198 if (unlikely(r != 0))
1199 return r;
1200 radeon_bo_unpin(rbo);
1201 radeon_bo_unreserve(rbo);
1202 }
1203
1204 /* Bytes per pixel may have changed */
1205 radeon_bandwidth_update(rdev);
1206
1207 return 0;
1208}
1209
1210static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1211 struct drm_framebuffer *fb,
1212 int x, int y, int atomic)
1213{
1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1215 struct drm_device *dev = crtc->dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_framebuffer *radeon_fb;
1218 struct drm_gem_object *obj;
1219 struct radeon_bo *rbo;
1220 struct drm_framebuffer *target_fb;
1221 uint64_t fb_location;
1222 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1223 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1224 u32 tmp, viewport_w, viewport_h;
1225 int r;
1226
1227 /* no fb bound */
1228 if (!atomic && !crtc->fb) {
1229 DRM_DEBUG_KMS("No FB bound\n");
1230 return 0;
1231 }
1232
1233 if (atomic) {
1234 radeon_fb = to_radeon_framebuffer(fb);
1235 target_fb = fb;
1236 }
1237 else {
1238 radeon_fb = to_radeon_framebuffer(crtc->fb);
1239 target_fb = crtc->fb;
1240 }
1241
1242 obj = radeon_fb->obj;
1243 rbo = gem_to_radeon_bo(obj);
1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1246 return r;
1247
1248 /* If atomic, assume fb object is pinned & idle & fenced and
1249 * just update base pointers
1250 */
1251 if (atomic)
1252 fb_location = radeon_bo_gpu_offset(rbo);
1253 else {
1254 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1255 if (unlikely(r != 0)) {
1256 radeon_bo_unreserve(rbo);
1257 return -EINVAL;
1258 }
1259 }
1260 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1261 radeon_bo_unreserve(rbo);
1262
1263 switch (target_fb->bits_per_pixel) {
1264 case 8:
1265 fb_format =
1266 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1267 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1268 break;
1269 case 15:
1270 fb_format =
1271 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1272 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1273 break;
1274 case 16:
1275 fb_format =
1276 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1277 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1278#ifdef __BIG_ENDIAN
1279 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1280#endif
1281 break;
1282 case 24:
1283 case 32:
1284 fb_format =
1285 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1286 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1287#ifdef __BIG_ENDIAN
1288 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1289#endif
1290 break;
1291 default:
1292 DRM_ERROR("Unsupported screen depth %d\n",
1293 target_fb->bits_per_pixel);
1294 return -EINVAL;
1295 }
1296
1297 if (rdev->family >= CHIP_R600) {
1298 if (tiling_flags & RADEON_TILING_MACRO)
1299 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1300 else if (tiling_flags & RADEON_TILING_MICRO)
1301 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1302 } else {
1303 if (tiling_flags & RADEON_TILING_MACRO)
1304 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1305
1306 if (tiling_flags & RADEON_TILING_MICRO)
1307 fb_format |= AVIVO_D1GRPH_TILED;
1308 }
1309
1310 if (radeon_crtc->crtc_id == 0)
1311 WREG32(AVIVO_D1VGA_CONTROL, 0);
1312 else
1313 WREG32(AVIVO_D2VGA_CONTROL, 0);
1314
1315 if (rdev->family >= CHIP_RV770) {
1316 if (radeon_crtc->crtc_id) {
1317 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1318 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1319 } else {
1320 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1321 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1322 }
1323 }
1324 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1325 (u32) fb_location);
1326 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1327 radeon_crtc->crtc_offset, (u32) fb_location);
1328 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1329 if (rdev->family >= CHIP_R600)
1330 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331
1332 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1335 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1336 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1337 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1338
1339 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1340 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1341 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1342
1343 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1344 crtc->mode.vdisplay);
1345 x &= ~3;
1346 y &= ~1;
1347 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1348 (x << 16) | y);
1349 viewport_w = crtc->mode.hdisplay;
1350 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1351 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1352 (viewport_w << 16) | viewport_h);
1353
1354 /* pageflip setup */
1355 /* make sure flip is at vb rather than hb */
1356 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1357 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1358 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1359
1360 /* set pageflip to happen anywhere in vblank interval */
1361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1362
1363 if (!atomic && fb && fb != crtc->fb) {
1364 radeon_fb = to_radeon_framebuffer(fb);
1365 rbo = gem_to_radeon_bo(radeon_fb->obj);
1366 r = radeon_bo_reserve(rbo, false);
1367 if (unlikely(r != 0))
1368 return r;
1369 radeon_bo_unpin(rbo);
1370 radeon_bo_unreserve(rbo);
1371 }
1372
1373 /* Bytes per pixel may have changed */
1374 radeon_bandwidth_update(rdev);
1375
1376 return 0;
1377}
1378
1379int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1380 struct drm_framebuffer *old_fb)
1381{
1382 struct drm_device *dev = crtc->dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384
1385 if (ASIC_IS_DCE4(rdev))
1386 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1387 else if (ASIC_IS_AVIVO(rdev))
1388 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1389 else
1390 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1391}
1392
1393int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1394 struct drm_framebuffer *fb,
1395 int x, int y, enum mode_set_atomic state)
1396{
1397 struct drm_device *dev = crtc->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399
1400 if (ASIC_IS_DCE4(rdev))
1401 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1402 else if (ASIC_IS_AVIVO(rdev))
1403 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1404 else
1405 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1406}
1407
1408/* properly set additional regs when using atombios */
1409static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct radeon_device *rdev = dev->dev_private;
1413 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1414 u32 disp_merge_cntl;
1415
1416 switch (radeon_crtc->crtc_id) {
1417 case 0:
1418 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1419 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1420 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1421 break;
1422 case 1:
1423 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1424 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1425 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1426 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1427 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1428 break;
1429 }
1430}
1431
1432static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1433{
1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1435 struct drm_device *dev = crtc->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1437 struct drm_encoder *test_encoder;
1438 struct drm_crtc *test_crtc;
1439 uint32_t pll_in_use = 0;
1440
1441 if (ASIC_IS_DCE4(rdev)) {
1442 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1443 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1444 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1445 * depending on the asic:
1446 * DCE4: PPLL or ext clock
1447 * DCE5: DCPLL or ext clock
1448 *
1449 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1450 * PPLL/DCPLL programming and only program the DP DTO for the
1451 * crtc virtual pixel clock.
1452 */
1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1455 return ATOM_PPLL_INVALID;
1456 }
1457 }
1458 }
1459
1460 /* otherwise, pick one of the plls */
1461 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1462 struct radeon_crtc *radeon_test_crtc;
1463
1464 if (crtc == test_crtc)
1465 continue;
1466
1467 radeon_test_crtc = to_radeon_crtc(test_crtc);
1468 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1469 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1470 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1471 }
1472 if (!(pll_in_use & 1))
1473 return ATOM_PPLL1;
1474 return ATOM_PPLL2;
1475 } else
1476 return radeon_crtc->crtc_id;
1477
1478}
1479
1480int atombios_crtc_mode_set(struct drm_crtc *crtc,
1481 struct drm_display_mode *mode,
1482 struct drm_display_mode *adjusted_mode,
1483 int x, int y, struct drm_framebuffer *old_fb)
1484{
1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1486 struct drm_device *dev = crtc->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct drm_encoder *encoder;
1489 bool is_tvcv = false;
1490
1491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1492 /* find tv std */
1493 if (encoder->crtc == crtc) {
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 if (radeon_encoder->active_device &
1496 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1497 is_tvcv = true;
1498 }
1499 }
1500
1501 /* always set DCPLL */
1502 if (ASIC_IS_DCE4(rdev)) {
1503 struct radeon_atom_ss ss;
1504 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1505 ASIC_INTERNAL_SS_ON_DCPLL,
1506 rdev->clock.default_dispclk);
1507 if (ss_enabled)
1508 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1509 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1510 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1511 if (ss_enabled)
1512 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1513 }
1514 atombios_crtc_set_pll(crtc, adjusted_mode);
1515
1516 if (ASIC_IS_DCE4(rdev))
1517 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1518 else if (ASIC_IS_AVIVO(rdev)) {
1519 if (is_tvcv)
1520 atombios_crtc_set_timing(crtc, adjusted_mode);
1521 else
1522 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1523 } else {
1524 atombios_crtc_set_timing(crtc, adjusted_mode);
1525 if (radeon_crtc->crtc_id == 0)
1526 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1527 radeon_legacy_atom_fixup(crtc);
1528 }
1529 atombios_crtc_set_base(crtc, x, y, old_fb);
1530 atombios_overscan_setup(crtc, mode, adjusted_mode);
1531 atombios_scaler_setup(crtc);
1532 return 0;
1533}
1534
1535static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1536 struct drm_display_mode *mode,
1537 struct drm_display_mode *adjusted_mode)
1538{
1539 struct drm_device *dev = crtc->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541
1542 /* adjust pm to upcoming mode change */
1543 radeon_pm_compute_clocks(rdev);
1544
1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1546 return false;
1547 return true;
1548}
1549
1550static void atombios_crtc_prepare(struct drm_crtc *crtc)
1551{
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553
1554 /* pick pll */
1555 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1556
1557 atombios_lock_crtc(crtc, ATOM_ENABLE);
1558 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1559}
1560
1561static void atombios_crtc_commit(struct drm_crtc *crtc)
1562{
1563 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1564 atombios_lock_crtc(crtc, ATOM_DISABLE);
1565}
1566
1567static void atombios_crtc_disable(struct drm_crtc *crtc)
1568{
1569 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1570 struct radeon_atom_ss ss;
1571
1572 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1573
1574 switch (radeon_crtc->pll_id) {
1575 case ATOM_PPLL1:
1576 case ATOM_PPLL2:
1577 /* disable the ppll */
1578 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1580 break;
1581 default:
1582 break;
1583 }
1584 radeon_crtc->pll_id = -1;
1585}
1586
1587static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1588 .dpms = atombios_crtc_dpms,
1589 .mode_fixup = atombios_crtc_mode_fixup,
1590 .mode_set = atombios_crtc_mode_set,
1591 .mode_set_base = atombios_crtc_set_base,
1592 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1593 .prepare = atombios_crtc_prepare,
1594 .commit = atombios_crtc_commit,
1595 .load_lut = radeon_crtc_load_lut,
1596 .disable = atombios_crtc_disable,
1597};
1598
1599void radeon_atombios_init_crtc(struct drm_device *dev,
1600 struct radeon_crtc *radeon_crtc)
1601{
1602 struct radeon_device *rdev = dev->dev_private;
1603
1604 if (ASIC_IS_DCE4(rdev)) {
1605 switch (radeon_crtc->crtc_id) {
1606 case 0:
1607 default:
1608 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1609 break;
1610 case 1:
1611 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1612 break;
1613 case 2:
1614 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1615 break;
1616 case 3:
1617 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1618 break;
1619 case 4:
1620 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1621 break;
1622 case 5:
1623 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1624 break;
1625 }
1626 } else {
1627 if (radeon_crtc->crtc_id == 1)
1628 radeon_crtc->crtc_offset =
1629 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1630 else
1631 radeon_crtc->crtc_offset = 0;
1632 }
1633 radeon_crtc->pll_id = -1;
1634 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1635}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_fb_helper.h>
29#include <drm/radeon_drm.h>
30#include <drm/drm_fixed.h>
31#include "radeon.h"
32#include "atom.h"
33#include "atom-bits.h"
34
35static void atombios_overscan_setup(struct drm_crtc *crtc,
36 struct drm_display_mode *mode,
37 struct drm_display_mode *adjusted_mode)
38{
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
44 int a1, a2;
45
46 memset(&args, 0, sizeof(args));
47
48 args.ucCRTC = radeon_crtc->crtc_id;
49
50 switch (radeon_crtc->rmx_type) {
51 case RMX_CENTER:
52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
56 break;
57 case RMX_ASPECT:
58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
60
61 if (a1 > a2) {
62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
64 } else if (a2 > a1) {
65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
67 }
68 break;
69 case RMX_FULL:
70 default:
71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
75 break;
76 }
77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
78}
79
80static void atombios_scaler_setup(struct drm_crtc *crtc)
81{
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
85 ENABLE_SCALER_PS_ALLOCATION args;
86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 struct radeon_encoder *radeon_encoder =
88 to_radeon_encoder(radeon_crtc->encoder);
89 /* fixme - fill in enc_priv for atom dac */
90 enum radeon_tv_std tv_std = TV_STD_NTSC;
91 bool is_tv = false, is_cv = false;
92
93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
94 return;
95
96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
98 tv_std = tv_dac->tv_std;
99 is_tv = true;
100 }
101
102 memset(&args, 0, sizeof(args));
103
104 args.ucScaler = radeon_crtc->crtc_id;
105
106 if (is_tv) {
107 switch (tv_std) {
108 case TV_STD_NTSC:
109 default:
110 args.ucTVStandard = ATOM_TV_NTSC;
111 break;
112 case TV_STD_PAL:
113 args.ucTVStandard = ATOM_TV_PAL;
114 break;
115 case TV_STD_PAL_M:
116 args.ucTVStandard = ATOM_TV_PALM;
117 break;
118 case TV_STD_PAL_60:
119 args.ucTVStandard = ATOM_TV_PAL60;
120 break;
121 case TV_STD_NTSC_J:
122 args.ucTVStandard = ATOM_TV_NTSCJ;
123 break;
124 case TV_STD_SCART_PAL:
125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
126 break;
127 case TV_STD_SECAM:
128 args.ucTVStandard = ATOM_TV_SECAM;
129 break;
130 case TV_STD_PAL_CN:
131 args.ucTVStandard = ATOM_TV_PALCN;
132 break;
133 }
134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
135 } else if (is_cv) {
136 args.ucTVStandard = ATOM_TV_CV;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 } else {
139 switch (radeon_crtc->rmx_type) {
140 case RMX_FULL:
141 args.ucEnable = ATOM_SCALER_EXPANSION;
142 break;
143 case RMX_CENTER:
144 args.ucEnable = ATOM_SCALER_CENTER;
145 break;
146 case RMX_ASPECT:
147 args.ucEnable = ATOM_SCALER_EXPANSION;
148 break;
149 default:
150 if (ASIC_IS_AVIVO(rdev))
151 args.ucEnable = ATOM_SCALER_DISABLE;
152 else
153 args.ucEnable = ATOM_SCALER_CENTER;
154 break;
155 }
156 }
157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
158 if ((is_tv || is_cv)
159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
160 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
161 }
162}
163
164static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 struct drm_device *dev = crtc->dev;
168 struct radeon_device *rdev = dev->dev_private;
169 int index =
170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
171 ENABLE_CRTC_PS_ALLOCATION args;
172
173 memset(&args, 0, sizeof(args));
174
175 args.ucCRTC = radeon_crtc->crtc_id;
176 args.ucEnable = lock;
177
178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
179}
180
181static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
182{
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
184 struct drm_device *dev = crtc->dev;
185 struct radeon_device *rdev = dev->dev_private;
186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
187 ENABLE_CRTC_PS_ALLOCATION args;
188
189 memset(&args, 0, sizeof(args));
190
191 args.ucCRTC = radeon_crtc->crtc_id;
192 args.ucEnable = state;
193
194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
195}
196
197static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
198{
199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
200 struct drm_device *dev = crtc->dev;
201 struct radeon_device *rdev = dev->dev_private;
202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
203 ENABLE_CRTC_PS_ALLOCATION args;
204
205 memset(&args, 0, sizeof(args));
206
207 args.ucCRTC = radeon_crtc->crtc_id;
208 args.ucEnable = state;
209
210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
211}
212
213static const u32 vga_control_regs[6] =
214{
215 AVIVO_D1VGA_CONTROL,
216 AVIVO_D2VGA_CONTROL,
217 EVERGREEN_D3VGA_CONTROL,
218 EVERGREEN_D4VGA_CONTROL,
219 EVERGREEN_D5VGA_CONTROL,
220 EVERGREEN_D6VGA_CONTROL,
221};
222
223static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
224{
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
229 BLANK_CRTC_PS_ALLOCATION args;
230 u32 vga_control = 0;
231
232 memset(&args, 0, sizeof(args));
233
234 if (ASIC_IS_DCE8(rdev)) {
235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
237 }
238
239 args.ucCRTC = radeon_crtc->crtc_id;
240 args.ucBlanking = state;
241
242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
243
244 if (ASIC_IS_DCE8(rdev)) {
245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
246 }
247}
248
249static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
250{
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
256
257 memset(&args, 0, sizeof(args));
258
259 args.ucDispPipeId = radeon_crtc->crtc_id;
260 args.ucEnable = state;
261
262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
263}
264
265void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
266{
267 struct drm_device *dev = crtc->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
270
271 switch (mode) {
272 case DRM_MODE_DPMS_ON:
273 radeon_crtc->enabled = true;
274 atombios_enable_crtc(crtc, ATOM_ENABLE);
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_crtc_vblank_on(crtc);
280 radeon_crtc_load_lut(crtc);
281 break;
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_crtc_vblank_off(crtc);
287 if (radeon_crtc->enabled)
288 atombios_blank_crtc(crtc, ATOM_ENABLE);
289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
291 atombios_enable_crtc(crtc, ATOM_DISABLE);
292 radeon_crtc->enabled = false;
293 break;
294 }
295 /* adjust pm to dpms */
296 radeon_pm_compute_clocks(rdev);
297}
298
299static void
300atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
301 struct drm_display_mode *mode)
302{
303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
304 struct drm_device *dev = crtc->dev;
305 struct radeon_device *rdev = dev->dev_private;
306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
308 u16 misc = 0;
309
310 memset(&args, 0, sizeof(args));
311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
312 args.usH_Blanking_Time =
313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
315 args.usV_Blanking_Time =
316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
317 args.usH_SyncOffset =
318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
319 args.usH_SyncWidth =
320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
321 args.usV_SyncOffset =
322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
323 args.usV_SyncWidth =
324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
325 args.ucH_Border = radeon_crtc->h_border;
326 args.ucV_Border = radeon_crtc->v_border;
327
328 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
329 misc |= ATOM_VSYNC_POLARITY;
330 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
331 misc |= ATOM_HSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_CSYNC)
333 misc |= ATOM_COMPOSITESYNC;
334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
335 misc |= ATOM_INTERLACE;
336 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337 misc |= ATOM_DOUBLE_CLOCK_MODE;
338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
340
341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
342 args.ucCRTC = radeon_crtc->crtc_id;
343
344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
345}
346
347static void atombios_crtc_set_timing(struct drm_crtc *crtc,
348 struct drm_display_mode *mode)
349{
350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
355 u16 misc = 0;
356
357 memset(&args, 0, sizeof(args));
358 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
361 args.usH_SyncWidth =
362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
366 args.usV_SyncWidth =
367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
368
369 args.ucOverscanRight = radeon_crtc->h_border;
370 args.ucOverscanLeft = radeon_crtc->h_border;
371 args.ucOverscanBottom = radeon_crtc->v_border;
372 args.ucOverscanTop = radeon_crtc->v_border;
373
374 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
375 misc |= ATOM_VSYNC_POLARITY;
376 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
377 misc |= ATOM_HSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_CSYNC)
379 misc |= ATOM_COMPOSITESYNC;
380 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
381 misc |= ATOM_INTERLACE;
382 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383 misc |= ATOM_DOUBLE_CLOCK_MODE;
384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
386
387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
388 args.ucCRTC = radeon_crtc->crtc_id;
389
390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
391}
392
393static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
394{
395 u32 ss_cntl;
396
397 if (ASIC_IS_DCE4(rdev)) {
398 switch (pll_id) {
399 case ATOM_PPLL1:
400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
403 break;
404 case ATOM_PPLL2:
405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
408 break;
409 case ATOM_DCPLL:
410 case ATOM_PPLL_INVALID:
411 return;
412 }
413 } else if (ASIC_IS_AVIVO(rdev)) {
414 switch (pll_id) {
415 case ATOM_PPLL1:
416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
417 ss_cntl &= ~1;
418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
419 break;
420 case ATOM_PPLL2:
421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
422 ss_cntl &= ~1;
423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
424 break;
425 case ATOM_DCPLL:
426 case ATOM_PPLL_INVALID:
427 return;
428 }
429 }
430}
431
432
433union atom_enable_ss {
434 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
439};
440
441static void atombios_crtc_program_ss(struct radeon_device *rdev,
442 int enable,
443 int pll_id,
444 int crtc_id,
445 struct radeon_atom_ss *ss)
446{
447 unsigned i;
448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
449 union atom_enable_ss args;
450
451 if (enable) {
452 /* Don't mess with SS if percentage is 0 or external ss.
453 * SS is already disabled previously, and disabling it
454 * again can cause display problems if the pll is already
455 * programmed.
456 */
457 if (ss->percentage == 0)
458 return;
459 if (ss->type & ATOM_EXTERNAL_SS_MASK)
460 return;
461 } else {
462 for (i = 0; i < rdev->num_crtc; i++) {
463 if (rdev->mode_info.crtcs[i] &&
464 rdev->mode_info.crtcs[i]->enabled &&
465 i != crtc_id &&
466 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
467 /* one other crtc is using this pll don't turn
468 * off spread spectrum as it might turn off
469 * display on active crtc
470 */
471 return;
472 }
473 }
474 }
475
476 memset(&args, 0, sizeof(args));
477
478 if (ASIC_IS_DCE5(rdev)) {
479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
481 switch (pll_id) {
482 case ATOM_PPLL1:
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
484 break;
485 case ATOM_PPLL2:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
487 break;
488 case ATOM_DCPLL:
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
490 break;
491 case ATOM_PPLL_INVALID:
492 return;
493 }
494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
496 args.v3.ucEnable = enable;
497 } else if (ASIC_IS_DCE4(rdev)) {
498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
500 switch (pll_id) {
501 case ATOM_PPLL1:
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
503 break;
504 case ATOM_PPLL2:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
506 break;
507 case ATOM_DCPLL:
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
509 break;
510 case ATOM_PPLL_INVALID:
511 return;
512 }
513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
515 args.v2.ucEnable = enable;
516 } else if (ASIC_IS_DCE3(rdev)) {
517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519 args.v1.ucSpreadSpectrumStep = ss->step;
520 args.v1.ucSpreadSpectrumDelay = ss->delay;
521 args.v1.ucSpreadSpectrumRange = ss->range;
522 args.v1.ucPpll = pll_id;
523 args.v1.ucEnable = enable;
524 } else if (ASIC_IS_AVIVO(rdev)) {
525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
527 atombios_disable_ss(rdev, pll_id);
528 return;
529 }
530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
535 args.lvds_ss_2.ucEnable = enable;
536 } else {
537 if (enable == ATOM_DISABLE) {
538 atombios_disable_ss(rdev, pll_id);
539 return;
540 }
541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
545 args.lvds_ss.ucEnable = enable;
546 }
547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
548}
549
550union adjust_pixel_clock {
551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
553};
554
555static u32 atombios_adjust_pll(struct drm_crtc *crtc,
556 struct drm_display_mode *mode)
557{
558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
559 struct drm_device *dev = crtc->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct drm_encoder *encoder = radeon_crtc->encoder;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
564 u32 adjusted_clock = mode->clock;
565 int encoder_mode = atombios_get_encoder_mode(encoder);
566 u32 dp_clock = mode->clock;
567 u32 clock = mode->clock;
568 int bpc = radeon_crtc->bpc;
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
570
571 /* reset the pll flags */
572 radeon_crtc->pll_flags = 0;
573
574 if (ASIC_IS_AVIVO(rdev)) {
575 if ((rdev->family == CHIP_RS600) ||
576 (rdev->family == CHIP_RS690) ||
577 (rdev->family == CHIP_RS740))
578 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
579 RADEON_PLL_PREFER_CLOSEST_LOWER);
580
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
583 else
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
585
586 if (rdev->family < CHIP_RV770)
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
588 /* use frac fb div on APUs */
589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
591 /* use frac fb div on RS780/RS880 */
592 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593 && !radeon_crtc->ss_enabled)
594 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
595 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 } else {
598 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
599
600 if (mode->clock > 200000) /* range limits??? */
601 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
602 else
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
604 }
605
606 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
607 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
608 if (connector) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
610 struct radeon_connector_atom_dig *dig_connector =
611 radeon_connector->con_priv;
612
613 dp_clock = dig_connector->dp_clock;
614 }
615 }
616
617 if (radeon_encoder->is_mst_encoder) {
618 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
619 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
620
621 dp_clock = dig_connector->dp_clock;
622 }
623
624 /* use recommended ref_div for ss */
625 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
626 if (radeon_crtc->ss_enabled) {
627 if (radeon_crtc->ss.refdiv) {
628 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
629 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
630 if (ASIC_IS_AVIVO(rdev) &&
631 rdev->family != CHIP_RS780 &&
632 rdev->family != CHIP_RS880)
633 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
634 }
635 }
636 }
637
638 if (ASIC_IS_AVIVO(rdev)) {
639 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
640 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
641 adjusted_clock = mode->clock * 2;
642 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
643 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
644 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
645 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
646 } else {
647 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
648 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
649 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
650 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
651 }
652
653 /* adjust pll for deep color modes */
654 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
655 switch (bpc) {
656 case 8:
657 default:
658 break;
659 case 10:
660 clock = (clock * 5) / 4;
661 break;
662 case 12:
663 clock = (clock * 3) / 2;
664 break;
665 case 16:
666 clock = clock * 2;
667 break;
668 }
669 }
670
671 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
672 * accordingly based on the encoder/transmitter to work around
673 * special hw requirements.
674 */
675 if (ASIC_IS_DCE3(rdev)) {
676 union adjust_pixel_clock args;
677 u8 frev, crev;
678 int index;
679
680 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
681 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
682 &crev))
683 return adjusted_clock;
684
685 memset(&args, 0, sizeof(args));
686
687 switch (frev) {
688 case 1:
689 switch (crev) {
690 case 1:
691 case 2:
692 args.v1.usPixelClock = cpu_to_le16(clock / 10);
693 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
694 args.v1.ucEncodeMode = encoder_mode;
695 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
696 args.v1.ucConfig |=
697 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
698
699 atom_execute_table(rdev->mode_info.atom_context,
700 index, (uint32_t *)&args);
701 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
702 break;
703 case 3:
704 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
705 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
706 args.v3.sInput.ucEncodeMode = encoder_mode;
707 args.v3.sInput.ucDispPllConfig = 0;
708 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
709 args.v3.sInput.ucDispPllConfig |=
710 DISPPLL_CONFIG_SS_ENABLE;
711 if (ENCODER_MODE_IS_DP(encoder_mode)) {
712 args.v3.sInput.ucDispPllConfig |=
713 DISPPLL_CONFIG_COHERENT_MODE;
714 /* 16200 or 27000 */
715 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
716 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
717 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
718 if (dig->coherent_mode)
719 args.v3.sInput.ucDispPllConfig |=
720 DISPPLL_CONFIG_COHERENT_MODE;
721 if (is_duallink)
722 args.v3.sInput.ucDispPllConfig |=
723 DISPPLL_CONFIG_DUAL_LINK;
724 }
725 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
726 ENCODER_OBJECT_ID_NONE)
727 args.v3.sInput.ucExtTransmitterID =
728 radeon_encoder_get_dp_bridge_encoder_id(encoder);
729 else
730 args.v3.sInput.ucExtTransmitterID = 0;
731
732 atom_execute_table(rdev->mode_info.atom_context,
733 index, (uint32_t *)&args);
734 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
735 if (args.v3.sOutput.ucRefDiv) {
736 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
738 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
739 }
740 if (args.v3.sOutput.ucPostDiv) {
741 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
742 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
743 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
744 }
745 break;
746 default:
747 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
748 return adjusted_clock;
749 }
750 break;
751 default:
752 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
753 return adjusted_clock;
754 }
755 }
756 return adjusted_clock;
757}
758
759union set_pixel_clock {
760 SET_PIXEL_CLOCK_PS_ALLOCATION base;
761 PIXEL_CLOCK_PARAMETERS v1;
762 PIXEL_CLOCK_PARAMETERS_V2 v2;
763 PIXEL_CLOCK_PARAMETERS_V3 v3;
764 PIXEL_CLOCK_PARAMETERS_V5 v5;
765 PIXEL_CLOCK_PARAMETERS_V6 v6;
766};
767
768/* on DCE5, make sure the voltage is high enough to support the
769 * required disp clk.
770 */
771static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
772 u32 dispclk)
773{
774 u8 frev, crev;
775 int index;
776 union set_pixel_clock args;
777
778 memset(&args, 0, sizeof(args));
779
780 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
781 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
782 &crev))
783 return;
784
785 switch (frev) {
786 case 1:
787 switch (crev) {
788 case 5:
789 /* if the default dcpll clock is specified,
790 * SetPixelClock provides the dividers
791 */
792 args.v5.ucCRTC = ATOM_CRTC_INVALID;
793 args.v5.usPixelClock = cpu_to_le16(dispclk);
794 args.v5.ucPpll = ATOM_DCPLL;
795 break;
796 case 6:
797 /* if the default dcpll clock is specified,
798 * SetPixelClock provides the dividers
799 */
800 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
801 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
802 args.v6.ucPpll = ATOM_EXT_PLL1;
803 else if (ASIC_IS_DCE6(rdev))
804 args.v6.ucPpll = ATOM_PPLL0;
805 else
806 args.v6.ucPpll = ATOM_DCPLL;
807 break;
808 default:
809 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
810 return;
811 }
812 break;
813 default:
814 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
815 return;
816 }
817 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
818}
819
820static void atombios_crtc_program_pll(struct drm_crtc *crtc,
821 u32 crtc_id,
822 int pll_id,
823 u32 encoder_mode,
824 u32 encoder_id,
825 u32 clock,
826 u32 ref_div,
827 u32 fb_div,
828 u32 frac_fb_div,
829 u32 post_div,
830 int bpc,
831 bool ss_enabled,
832 struct radeon_atom_ss *ss)
833{
834 struct drm_device *dev = crtc->dev;
835 struct radeon_device *rdev = dev->dev_private;
836 u8 frev, crev;
837 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
838 union set_pixel_clock args;
839
840 memset(&args, 0, sizeof(args));
841
842 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
843 &crev))
844 return;
845
846 switch (frev) {
847 case 1:
848 switch (crev) {
849 case 1:
850 if (clock == ATOM_DISABLE)
851 return;
852 args.v1.usPixelClock = cpu_to_le16(clock / 10);
853 args.v1.usRefDiv = cpu_to_le16(ref_div);
854 args.v1.usFbDiv = cpu_to_le16(fb_div);
855 args.v1.ucFracFbDiv = frac_fb_div;
856 args.v1.ucPostDiv = post_div;
857 args.v1.ucPpll = pll_id;
858 args.v1.ucCRTC = crtc_id;
859 args.v1.ucRefDivSrc = 1;
860 break;
861 case 2:
862 args.v2.usPixelClock = cpu_to_le16(clock / 10);
863 args.v2.usRefDiv = cpu_to_le16(ref_div);
864 args.v2.usFbDiv = cpu_to_le16(fb_div);
865 args.v2.ucFracFbDiv = frac_fb_div;
866 args.v2.ucPostDiv = post_div;
867 args.v2.ucPpll = pll_id;
868 args.v2.ucCRTC = crtc_id;
869 args.v2.ucRefDivSrc = 1;
870 break;
871 case 3:
872 args.v3.usPixelClock = cpu_to_le16(clock / 10);
873 args.v3.usRefDiv = cpu_to_le16(ref_div);
874 args.v3.usFbDiv = cpu_to_le16(fb_div);
875 args.v3.ucFracFbDiv = frac_fb_div;
876 args.v3.ucPostDiv = post_div;
877 args.v3.ucPpll = pll_id;
878 if (crtc_id == ATOM_CRTC2)
879 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
880 else
881 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
882 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
883 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
884 args.v3.ucTransmitterId = encoder_id;
885 args.v3.ucEncoderMode = encoder_mode;
886 break;
887 case 5:
888 args.v5.ucCRTC = crtc_id;
889 args.v5.usPixelClock = cpu_to_le16(clock / 10);
890 args.v5.ucRefDiv = ref_div;
891 args.v5.usFbDiv = cpu_to_le16(fb_div);
892 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
893 args.v5.ucPostDiv = post_div;
894 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
895 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
896 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
897 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
898 switch (bpc) {
899 case 8:
900 default:
901 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
902 break;
903 case 10:
904 /* yes this is correct, the atom define is wrong */
905 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
906 break;
907 case 12:
908 /* yes this is correct, the atom define is wrong */
909 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
910 break;
911 }
912 }
913 args.v5.ucTransmitterID = encoder_id;
914 args.v5.ucEncoderMode = encoder_mode;
915 args.v5.ucPpll = pll_id;
916 break;
917 case 6:
918 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
919 args.v6.ucRefDiv = ref_div;
920 args.v6.usFbDiv = cpu_to_le16(fb_div);
921 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
922 args.v6.ucPostDiv = post_div;
923 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
924 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
925 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
926 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
927 switch (bpc) {
928 case 8:
929 default:
930 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
931 break;
932 case 10:
933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
934 break;
935 case 12:
936 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
937 break;
938 case 16:
939 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
940 break;
941 }
942 }
943 args.v6.ucTransmitterID = encoder_id;
944 args.v6.ucEncoderMode = encoder_mode;
945 args.v6.ucPpll = pll_id;
946 break;
947 default:
948 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
949 return;
950 }
951 break;
952 default:
953 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
954 return;
955 }
956
957 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
958}
959
960static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
961{
962 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
963 struct drm_device *dev = crtc->dev;
964 struct radeon_device *rdev = dev->dev_private;
965 struct radeon_encoder *radeon_encoder =
966 to_radeon_encoder(radeon_crtc->encoder);
967 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
968
969 radeon_crtc->bpc = 8;
970 radeon_crtc->ss_enabled = false;
971
972 if (radeon_encoder->is_mst_encoder) {
973 radeon_dp_mst_prepare_pll(crtc, mode);
974 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
975 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
976 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
977 struct drm_connector *connector =
978 radeon_get_connector_for_encoder(radeon_crtc->encoder);
979 struct radeon_connector *radeon_connector =
980 to_radeon_connector(connector);
981 struct radeon_connector_atom_dig *dig_connector =
982 radeon_connector->con_priv;
983 int dp_clock;
984
985 /* Assign mode clock for hdmi deep color max clock limit check */
986 radeon_connector->pixelclock_for_modeset = mode->clock;
987 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
988
989 switch (encoder_mode) {
990 case ATOM_ENCODER_MODE_DP_MST:
991 case ATOM_ENCODER_MODE_DP:
992 /* DP/eDP */
993 dp_clock = dig_connector->dp_clock / 10;
994 if (ASIC_IS_DCE4(rdev))
995 radeon_crtc->ss_enabled =
996 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
997 ASIC_INTERNAL_SS_ON_DP,
998 dp_clock);
999 else {
1000 if (dp_clock == 16200) {
1001 radeon_crtc->ss_enabled =
1002 radeon_atombios_get_ppll_ss_info(rdev,
1003 &radeon_crtc->ss,
1004 ATOM_DP_SS_ID2);
1005 if (!radeon_crtc->ss_enabled)
1006 radeon_crtc->ss_enabled =
1007 radeon_atombios_get_ppll_ss_info(rdev,
1008 &radeon_crtc->ss,
1009 ATOM_DP_SS_ID1);
1010 } else {
1011 radeon_crtc->ss_enabled =
1012 radeon_atombios_get_ppll_ss_info(rdev,
1013 &radeon_crtc->ss,
1014 ATOM_DP_SS_ID1);
1015 }
1016 /* disable spread spectrum on DCE3 DP */
1017 radeon_crtc->ss_enabled = false;
1018 }
1019 break;
1020 case ATOM_ENCODER_MODE_LVDS:
1021 if (ASIC_IS_DCE4(rdev))
1022 radeon_crtc->ss_enabled =
1023 radeon_atombios_get_asic_ss_info(rdev,
1024 &radeon_crtc->ss,
1025 dig->lcd_ss_id,
1026 mode->clock / 10);
1027 else
1028 radeon_crtc->ss_enabled =
1029 radeon_atombios_get_ppll_ss_info(rdev,
1030 &radeon_crtc->ss,
1031 dig->lcd_ss_id);
1032 break;
1033 case ATOM_ENCODER_MODE_DVI:
1034 if (ASIC_IS_DCE4(rdev))
1035 radeon_crtc->ss_enabled =
1036 radeon_atombios_get_asic_ss_info(rdev,
1037 &radeon_crtc->ss,
1038 ASIC_INTERNAL_SS_ON_TMDS,
1039 mode->clock / 10);
1040 break;
1041 case ATOM_ENCODER_MODE_HDMI:
1042 if (ASIC_IS_DCE4(rdev))
1043 radeon_crtc->ss_enabled =
1044 radeon_atombios_get_asic_ss_info(rdev,
1045 &radeon_crtc->ss,
1046 ASIC_INTERNAL_SS_ON_HDMI,
1047 mode->clock / 10);
1048 break;
1049 default:
1050 break;
1051 }
1052 }
1053
1054 /* adjust pixel clock as needed */
1055 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1056
1057 return true;
1058}
1059
1060static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1061{
1062 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1063 struct drm_device *dev = crtc->dev;
1064 struct radeon_device *rdev = dev->dev_private;
1065 struct radeon_encoder *radeon_encoder =
1066 to_radeon_encoder(radeon_crtc->encoder);
1067 u32 pll_clock = mode->clock;
1068 u32 clock = mode->clock;
1069 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1070 struct radeon_pll *pll;
1071 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1072
1073 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1074 if (ASIC_IS_DCE5(rdev) &&
1075 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1076 (radeon_crtc->bpc > 8))
1077 clock = radeon_crtc->adjusted_clock;
1078
1079 switch (radeon_crtc->pll_id) {
1080 case ATOM_PPLL1:
1081 pll = &rdev->clock.p1pll;
1082 break;
1083 case ATOM_PPLL2:
1084 pll = &rdev->clock.p2pll;
1085 break;
1086 case ATOM_DCPLL:
1087 case ATOM_PPLL_INVALID:
1088 default:
1089 pll = &rdev->clock.dcpll;
1090 break;
1091 }
1092
1093 /* update pll params */
1094 pll->flags = radeon_crtc->pll_flags;
1095 pll->reference_div = radeon_crtc->pll_reference_div;
1096 pll->post_div = radeon_crtc->pll_post_div;
1097
1098 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1099 /* TV seems to prefer the legacy algo on some boards */
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101 &fb_div, &frac_fb_div, &ref_div, &post_div);
1102 else if (ASIC_IS_AVIVO(rdev))
1103 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1104 &fb_div, &frac_fb_div, &ref_div, &post_div);
1105 else
1106 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1107 &fb_div, &frac_fb_div, &ref_div, &post_div);
1108
1109 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1110 radeon_crtc->crtc_id, &radeon_crtc->ss);
1111
1112 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1113 encoder_mode, radeon_encoder->encoder_id, clock,
1114 ref_div, fb_div, frac_fb_div, post_div,
1115 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1116
1117 if (radeon_crtc->ss_enabled) {
1118 /* calculate ss amount and step size */
1119 if (ASIC_IS_DCE4(rdev)) {
1120 u32 step_size;
1121 u32 amount = (((fb_div * 10) + frac_fb_div) *
1122 (u32)radeon_crtc->ss.percentage) /
1123 (100 * (u32)radeon_crtc->ss.percentage_divider);
1124 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1125 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1126 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1127 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1128 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1129 (125 * 25 * pll->reference_freq / 100);
1130 else
1131 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1132 (125 * 25 * pll->reference_freq / 100);
1133 radeon_crtc->ss.step = step_size;
1134 }
1135
1136 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1137 radeon_crtc->crtc_id, &radeon_crtc->ss);
1138 }
1139}
1140
1141static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1142 struct drm_framebuffer *fb,
1143 int x, int y, int atomic)
1144{
1145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1146 struct drm_device *dev = crtc->dev;
1147 struct radeon_device *rdev = dev->dev_private;
1148 struct radeon_framebuffer *radeon_fb;
1149 struct drm_framebuffer *target_fb;
1150 struct drm_gem_object *obj;
1151 struct radeon_bo *rbo;
1152 uint64_t fb_location;
1153 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1154 unsigned bankw, bankh, mtaspect, tile_split;
1155 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1156 u32 tmp, viewport_w, viewport_h;
1157 int r;
1158 bool bypass_lut = false;
1159 struct drm_format_name_buf format_name;
1160
1161 /* no fb bound */
1162 if (!atomic && !crtc->primary->fb) {
1163 DRM_DEBUG_KMS("No FB bound\n");
1164 return 0;
1165 }
1166
1167 if (atomic) {
1168 radeon_fb = to_radeon_framebuffer(fb);
1169 target_fb = fb;
1170 }
1171 else {
1172 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1173 target_fb = crtc->primary->fb;
1174 }
1175
1176 /* If atomic, assume fb object is pinned & idle & fenced and
1177 * just update base pointers
1178 */
1179 obj = radeon_fb->obj;
1180 rbo = gem_to_radeon_bo(obj);
1181 r = radeon_bo_reserve(rbo, false);
1182 if (unlikely(r != 0))
1183 return r;
1184
1185 if (atomic)
1186 fb_location = radeon_bo_gpu_offset(rbo);
1187 else {
1188 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1189 if (unlikely(r != 0)) {
1190 radeon_bo_unreserve(rbo);
1191 return -EINVAL;
1192 }
1193 }
1194
1195 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1196 radeon_bo_unreserve(rbo);
1197
1198 switch (target_fb->pixel_format) {
1199 case DRM_FORMAT_C8:
1200 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1201 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1202 break;
1203 case DRM_FORMAT_XRGB4444:
1204 case DRM_FORMAT_ARGB4444:
1205 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1206 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1207#ifdef __BIG_ENDIAN
1208 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1209#endif
1210 break;
1211 case DRM_FORMAT_XRGB1555:
1212 case DRM_FORMAT_ARGB1555:
1213 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1214 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1215#ifdef __BIG_ENDIAN
1216 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1217#endif
1218 break;
1219 case DRM_FORMAT_BGRX5551:
1220 case DRM_FORMAT_BGRA5551:
1221 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1222 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1223#ifdef __BIG_ENDIAN
1224 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1225#endif
1226 break;
1227 case DRM_FORMAT_RGB565:
1228 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1229 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1230#ifdef __BIG_ENDIAN
1231 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1232#endif
1233 break;
1234 case DRM_FORMAT_XRGB8888:
1235 case DRM_FORMAT_ARGB8888:
1236 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1237 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1238#ifdef __BIG_ENDIAN
1239 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1240#endif
1241 break;
1242 case DRM_FORMAT_XRGB2101010:
1243 case DRM_FORMAT_ARGB2101010:
1244 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1245 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1246#ifdef __BIG_ENDIAN
1247 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1248#endif
1249 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1250 bypass_lut = true;
1251 break;
1252 case DRM_FORMAT_BGRX1010102:
1253 case DRM_FORMAT_BGRA1010102:
1254 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1255 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1256#ifdef __BIG_ENDIAN
1257 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1258#endif
1259 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1260 bypass_lut = true;
1261 break;
1262 default:
1263 DRM_ERROR("Unsupported screen format %s\n",
1264 drm_get_format_name(target_fb->pixel_format, &format_name));
1265 return -EINVAL;
1266 }
1267
1268 if (tiling_flags & RADEON_TILING_MACRO) {
1269 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1270
1271 /* Set NUM_BANKS. */
1272 if (rdev->family >= CHIP_TAHITI) {
1273 unsigned index, num_banks;
1274
1275 if (rdev->family >= CHIP_BONAIRE) {
1276 unsigned tileb, tile_split_bytes;
1277
1278 /* Calculate the macrotile mode index. */
1279 tile_split_bytes = 64 << tile_split;
1280 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1281 tileb = min(tile_split_bytes, tileb);
1282
1283 for (index = 0; tileb > 64; index++)
1284 tileb >>= 1;
1285
1286 if (index >= 16) {
1287 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1288 target_fb->bits_per_pixel, tile_split);
1289 return -EINVAL;
1290 }
1291
1292 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1293 } else {
1294 switch (target_fb->bits_per_pixel) {
1295 case 8:
1296 index = 10;
1297 break;
1298 case 16:
1299 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1300 break;
1301 default:
1302 case 32:
1303 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1304 break;
1305 }
1306
1307 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1308 }
1309
1310 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1311 } else {
1312 /* NI and older. */
1313 if (rdev->family >= CHIP_CAYMAN)
1314 tmp = rdev->config.cayman.tile_config;
1315 else
1316 tmp = rdev->config.evergreen.tile_config;
1317
1318 switch ((tmp & 0xf0) >> 4) {
1319 case 0: /* 4 banks */
1320 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1321 break;
1322 case 1: /* 8 banks */
1323 default:
1324 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1325 break;
1326 case 2: /* 16 banks */
1327 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1328 break;
1329 }
1330 }
1331
1332 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1333 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1334 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1335 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1336 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1337 if (rdev->family >= CHIP_BONAIRE) {
1338 /* XXX need to know more about the surface tiling mode */
1339 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1340 }
1341 } else if (tiling_flags & RADEON_TILING_MICRO)
1342 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1343
1344 if (rdev->family >= CHIP_BONAIRE) {
1345 /* Read the pipe config from the 2D TILED SCANOUT mode.
1346 * It should be the same for the other modes too, but not all
1347 * modes set the pipe config field. */
1348 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1349
1350 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1351 } else if ((rdev->family == CHIP_TAHITI) ||
1352 (rdev->family == CHIP_PITCAIRN))
1353 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1354 else if ((rdev->family == CHIP_VERDE) ||
1355 (rdev->family == CHIP_OLAND) ||
1356 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1357 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1358
1359 switch (radeon_crtc->crtc_id) {
1360 case 0:
1361 WREG32(AVIVO_D1VGA_CONTROL, 0);
1362 break;
1363 case 1:
1364 WREG32(AVIVO_D2VGA_CONTROL, 0);
1365 break;
1366 case 2:
1367 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1368 break;
1369 case 3:
1370 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1371 break;
1372 case 4:
1373 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1374 break;
1375 case 5:
1376 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1377 break;
1378 default:
1379 break;
1380 }
1381
1382 /* Make sure surface address is updated at vertical blank rather than
1383 * horizontal blank
1384 */
1385 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1386
1387 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1388 upper_32_bits(fb_location));
1389 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1390 upper_32_bits(fb_location));
1391 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1392 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1393 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1394 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1395 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1396 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1397
1398 /*
1399 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1400 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1401 * retain the full precision throughout the pipeline.
1402 */
1403 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1404 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1405 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1406
1407 if (bypass_lut)
1408 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1409
1410 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1411 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1412 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1413 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1414 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1415 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1416
1417 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1418 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1419 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1420
1421 if (rdev->family >= CHIP_BONAIRE)
1422 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1423 target_fb->height);
1424 else
1425 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1426 target_fb->height);
1427 x &= ~3;
1428 y &= ~1;
1429 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1430 (x << 16) | y);
1431 viewport_w = crtc->mode.hdisplay;
1432 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1433 if ((rdev->family >= CHIP_BONAIRE) &&
1434 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1435 viewport_h *= 2;
1436 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1437 (viewport_w << 16) | viewport_h);
1438
1439 /* set pageflip to happen anywhere in vblank interval */
1440 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1441
1442 if (!atomic && fb && fb != crtc->primary->fb) {
1443 radeon_fb = to_radeon_framebuffer(fb);
1444 rbo = gem_to_radeon_bo(radeon_fb->obj);
1445 r = radeon_bo_reserve(rbo, false);
1446 if (unlikely(r != 0))
1447 return r;
1448 radeon_bo_unpin(rbo);
1449 radeon_bo_unreserve(rbo);
1450 }
1451
1452 /* Bytes per pixel may have changed */
1453 radeon_bandwidth_update(rdev);
1454
1455 return 0;
1456}
1457
1458static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1459 struct drm_framebuffer *fb,
1460 int x, int y, int atomic)
1461{
1462 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1463 struct drm_device *dev = crtc->dev;
1464 struct radeon_device *rdev = dev->dev_private;
1465 struct radeon_framebuffer *radeon_fb;
1466 struct drm_gem_object *obj;
1467 struct radeon_bo *rbo;
1468 struct drm_framebuffer *target_fb;
1469 uint64_t fb_location;
1470 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1471 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1472 u32 viewport_w, viewport_h;
1473 int r;
1474 bool bypass_lut = false;
1475 struct drm_format_name_buf format_name;
1476
1477 /* no fb bound */
1478 if (!atomic && !crtc->primary->fb) {
1479 DRM_DEBUG_KMS("No FB bound\n");
1480 return 0;
1481 }
1482
1483 if (atomic) {
1484 radeon_fb = to_radeon_framebuffer(fb);
1485 target_fb = fb;
1486 }
1487 else {
1488 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1489 target_fb = crtc->primary->fb;
1490 }
1491
1492 obj = radeon_fb->obj;
1493 rbo = gem_to_radeon_bo(obj);
1494 r = radeon_bo_reserve(rbo, false);
1495 if (unlikely(r != 0))
1496 return r;
1497
1498 /* If atomic, assume fb object is pinned & idle & fenced and
1499 * just update base pointers
1500 */
1501 if (atomic)
1502 fb_location = radeon_bo_gpu_offset(rbo);
1503 else {
1504 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1505 if (unlikely(r != 0)) {
1506 radeon_bo_unreserve(rbo);
1507 return -EINVAL;
1508 }
1509 }
1510 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1511 radeon_bo_unreserve(rbo);
1512
1513 switch (target_fb->pixel_format) {
1514 case DRM_FORMAT_C8:
1515 fb_format =
1516 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1517 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1518 break;
1519 case DRM_FORMAT_XRGB4444:
1520 case DRM_FORMAT_ARGB4444:
1521 fb_format =
1522 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1523 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1524#ifdef __BIG_ENDIAN
1525 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1526#endif
1527 break;
1528 case DRM_FORMAT_XRGB1555:
1529 fb_format =
1530 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1531 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1532#ifdef __BIG_ENDIAN
1533 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1534#endif
1535 break;
1536 case DRM_FORMAT_RGB565:
1537 fb_format =
1538 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1539 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1540#ifdef __BIG_ENDIAN
1541 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1542#endif
1543 break;
1544 case DRM_FORMAT_XRGB8888:
1545 case DRM_FORMAT_ARGB8888:
1546 fb_format =
1547 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1548 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1549#ifdef __BIG_ENDIAN
1550 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1551#endif
1552 break;
1553 case DRM_FORMAT_XRGB2101010:
1554 case DRM_FORMAT_ARGB2101010:
1555 fb_format =
1556 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1557 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1558#ifdef __BIG_ENDIAN
1559 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1560#endif
1561 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1562 bypass_lut = true;
1563 break;
1564 default:
1565 DRM_ERROR("Unsupported screen format %s\n",
1566 drm_get_format_name(target_fb->pixel_format, &format_name));
1567 return -EINVAL;
1568 }
1569
1570 if (rdev->family >= CHIP_R600) {
1571 if (tiling_flags & RADEON_TILING_MACRO)
1572 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1573 else if (tiling_flags & RADEON_TILING_MICRO)
1574 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1575 } else {
1576 if (tiling_flags & RADEON_TILING_MACRO)
1577 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1578
1579 if (tiling_flags & RADEON_TILING_MICRO)
1580 fb_format |= AVIVO_D1GRPH_TILED;
1581 }
1582
1583 if (radeon_crtc->crtc_id == 0)
1584 WREG32(AVIVO_D1VGA_CONTROL, 0);
1585 else
1586 WREG32(AVIVO_D2VGA_CONTROL, 0);
1587
1588 /* Make sure surface address is update at vertical blank rather than
1589 * horizontal blank
1590 */
1591 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1592
1593 if (rdev->family >= CHIP_RV770) {
1594 if (radeon_crtc->crtc_id) {
1595 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1596 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1597 } else {
1598 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1599 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1600 }
1601 }
1602 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1603 (u32) fb_location);
1604 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1605 radeon_crtc->crtc_offset, (u32) fb_location);
1606 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1607 if (rdev->family >= CHIP_R600)
1608 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1609
1610 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1611 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1612 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1613
1614 if (bypass_lut)
1615 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1616
1617 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1618 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1619 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1620 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1621 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1622 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1623
1624 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1625 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1626 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1627
1628 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1629 target_fb->height);
1630 x &= ~3;
1631 y &= ~1;
1632 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1633 (x << 16) | y);
1634 viewport_w = crtc->mode.hdisplay;
1635 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1636 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1637 (viewport_w << 16) | viewport_h);
1638
1639 /* set pageflip to happen only at start of vblank interval (front porch) */
1640 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1641
1642 if (!atomic && fb && fb != crtc->primary->fb) {
1643 radeon_fb = to_radeon_framebuffer(fb);
1644 rbo = gem_to_radeon_bo(radeon_fb->obj);
1645 r = radeon_bo_reserve(rbo, false);
1646 if (unlikely(r != 0))
1647 return r;
1648 radeon_bo_unpin(rbo);
1649 radeon_bo_unreserve(rbo);
1650 }
1651
1652 /* Bytes per pixel may have changed */
1653 radeon_bandwidth_update(rdev);
1654
1655 return 0;
1656}
1657
1658int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1659 struct drm_framebuffer *old_fb)
1660{
1661 struct drm_device *dev = crtc->dev;
1662 struct radeon_device *rdev = dev->dev_private;
1663
1664 if (ASIC_IS_DCE4(rdev))
1665 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1666 else if (ASIC_IS_AVIVO(rdev))
1667 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1668 else
1669 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1670}
1671
1672int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1673 struct drm_framebuffer *fb,
1674 int x, int y, enum mode_set_atomic state)
1675{
1676 struct drm_device *dev = crtc->dev;
1677 struct radeon_device *rdev = dev->dev_private;
1678
1679 if (ASIC_IS_DCE4(rdev))
1680 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1681 else if (ASIC_IS_AVIVO(rdev))
1682 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1683 else
1684 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1685}
1686
1687/* properly set additional regs when using atombios */
1688static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1689{
1690 struct drm_device *dev = crtc->dev;
1691 struct radeon_device *rdev = dev->dev_private;
1692 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1693 u32 disp_merge_cntl;
1694
1695 switch (radeon_crtc->crtc_id) {
1696 case 0:
1697 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1698 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1699 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1700 break;
1701 case 1:
1702 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1703 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1704 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1705 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1706 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1707 break;
1708 }
1709}
1710
1711/**
1712 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1713 *
1714 * @crtc: drm crtc
1715 *
1716 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1717 */
1718static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1719{
1720 struct drm_device *dev = crtc->dev;
1721 struct drm_crtc *test_crtc;
1722 struct radeon_crtc *test_radeon_crtc;
1723 u32 pll_in_use = 0;
1724
1725 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1726 if (crtc == test_crtc)
1727 continue;
1728
1729 test_radeon_crtc = to_radeon_crtc(test_crtc);
1730 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1731 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1732 }
1733 return pll_in_use;
1734}
1735
1736/**
1737 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1738 *
1739 * @crtc: drm crtc
1740 *
1741 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1742 * also in DP mode. For DP, a single PPLL can be used for all DP
1743 * crtcs/encoders.
1744 */
1745static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1746{
1747 struct drm_device *dev = crtc->dev;
1748 struct radeon_device *rdev = dev->dev_private;
1749 struct drm_crtc *test_crtc;
1750 struct radeon_crtc *test_radeon_crtc;
1751
1752 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1753 if (crtc == test_crtc)
1754 continue;
1755 test_radeon_crtc = to_radeon_crtc(test_crtc);
1756 if (test_radeon_crtc->encoder &&
1757 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1758 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1759 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1760 test_radeon_crtc->pll_id == ATOM_PPLL2)
1761 continue;
1762 /* for DP use the same PLL for all */
1763 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1764 return test_radeon_crtc->pll_id;
1765 }
1766 }
1767 return ATOM_PPLL_INVALID;
1768}
1769
1770/**
1771 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1772 *
1773 * @crtc: drm crtc
1774 * @encoder: drm encoder
1775 *
1776 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1777 * be shared (i.e., same clock).
1778 */
1779static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1780{
1781 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1782 struct drm_device *dev = crtc->dev;
1783 struct radeon_device *rdev = dev->dev_private;
1784 struct drm_crtc *test_crtc;
1785 struct radeon_crtc *test_radeon_crtc;
1786 u32 adjusted_clock, test_adjusted_clock;
1787
1788 adjusted_clock = radeon_crtc->adjusted_clock;
1789
1790 if (adjusted_clock == 0)
1791 return ATOM_PPLL_INVALID;
1792
1793 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1794 if (crtc == test_crtc)
1795 continue;
1796 test_radeon_crtc = to_radeon_crtc(test_crtc);
1797 if (test_radeon_crtc->encoder &&
1798 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1799 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1800 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1801 test_radeon_crtc->pll_id == ATOM_PPLL2)
1802 continue;
1803 /* check if we are already driving this connector with another crtc */
1804 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1805 /* if we are, return that pll */
1806 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1807 return test_radeon_crtc->pll_id;
1808 }
1809 /* for non-DP check the clock */
1810 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1811 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1812 (adjusted_clock == test_adjusted_clock) &&
1813 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1814 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1815 return test_radeon_crtc->pll_id;
1816 }
1817 }
1818 return ATOM_PPLL_INVALID;
1819}
1820
1821/**
1822 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1823 *
1824 * @crtc: drm crtc
1825 *
1826 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1827 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1828 * monitors a dedicated PPLL must be used. If a particular board has
1829 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1830 * as there is no need to program the PLL itself. If we are not able to
1831 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1832 * avoid messing up an existing monitor.
1833 *
1834 * Asic specific PLL information
1835 *
1836 * DCE 8.x
1837 * KB/KV
1838 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1839 * CI
1840 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1841 *
1842 * DCE 6.1
1843 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1844 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1845 *
1846 * DCE 6.0
1847 * - PPLL0 is available to all UNIPHY (DP only)
1848 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1849 *
1850 * DCE 5.0
1851 * - DCPLL is available to all UNIPHY (DP only)
1852 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1853 *
1854 * DCE 3.0/4.0/4.1
1855 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1856 *
1857 */
1858static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1859{
1860 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1861 struct drm_device *dev = crtc->dev;
1862 struct radeon_device *rdev = dev->dev_private;
1863 struct radeon_encoder *radeon_encoder =
1864 to_radeon_encoder(radeon_crtc->encoder);
1865 u32 pll_in_use;
1866 int pll;
1867
1868 if (ASIC_IS_DCE8(rdev)) {
1869 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1870 if (rdev->clock.dp_extclk)
1871 /* skip PPLL programming if using ext clock */
1872 return ATOM_PPLL_INVALID;
1873 else {
1874 /* use the same PPLL for all DP monitors */
1875 pll = radeon_get_shared_dp_ppll(crtc);
1876 if (pll != ATOM_PPLL_INVALID)
1877 return pll;
1878 }
1879 } else {
1880 /* use the same PPLL for all monitors with the same clock */
1881 pll = radeon_get_shared_nondp_ppll(crtc);
1882 if (pll != ATOM_PPLL_INVALID)
1883 return pll;
1884 }
1885 /* otherwise, pick one of the plls */
1886 if ((rdev->family == CHIP_KABINI) ||
1887 (rdev->family == CHIP_MULLINS)) {
1888 /* KB/ML has PPLL1 and PPLL2 */
1889 pll_in_use = radeon_get_pll_use_mask(crtc);
1890 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1891 return ATOM_PPLL2;
1892 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1893 return ATOM_PPLL1;
1894 DRM_ERROR("unable to allocate a PPLL\n");
1895 return ATOM_PPLL_INVALID;
1896 } else {
1897 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1898 pll_in_use = radeon_get_pll_use_mask(crtc);
1899 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1900 return ATOM_PPLL2;
1901 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1902 return ATOM_PPLL1;
1903 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1904 return ATOM_PPLL0;
1905 DRM_ERROR("unable to allocate a PPLL\n");
1906 return ATOM_PPLL_INVALID;
1907 }
1908 } else if (ASIC_IS_DCE61(rdev)) {
1909 struct radeon_encoder_atom_dig *dig =
1910 radeon_encoder->enc_priv;
1911
1912 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1913 (dig->linkb == false))
1914 /* UNIPHY A uses PPLL2 */
1915 return ATOM_PPLL2;
1916 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1917 /* UNIPHY B/C/D/E/F */
1918 if (rdev->clock.dp_extclk)
1919 /* skip PPLL programming if using ext clock */
1920 return ATOM_PPLL_INVALID;
1921 else {
1922 /* use the same PPLL for all DP monitors */
1923 pll = radeon_get_shared_dp_ppll(crtc);
1924 if (pll != ATOM_PPLL_INVALID)
1925 return pll;
1926 }
1927 } else {
1928 /* use the same PPLL for all monitors with the same clock */
1929 pll = radeon_get_shared_nondp_ppll(crtc);
1930 if (pll != ATOM_PPLL_INVALID)
1931 return pll;
1932 }
1933 /* UNIPHY B/C/D/E/F */
1934 pll_in_use = radeon_get_pll_use_mask(crtc);
1935 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1936 return ATOM_PPLL0;
1937 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1938 return ATOM_PPLL1;
1939 DRM_ERROR("unable to allocate a PPLL\n");
1940 return ATOM_PPLL_INVALID;
1941 } else if (ASIC_IS_DCE41(rdev)) {
1942 /* Don't share PLLs on DCE4.1 chips */
1943 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1944 if (rdev->clock.dp_extclk)
1945 /* skip PPLL programming if using ext clock */
1946 return ATOM_PPLL_INVALID;
1947 }
1948 pll_in_use = radeon_get_pll_use_mask(crtc);
1949 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1950 return ATOM_PPLL1;
1951 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1952 return ATOM_PPLL2;
1953 DRM_ERROR("unable to allocate a PPLL\n");
1954 return ATOM_PPLL_INVALID;
1955 } else if (ASIC_IS_DCE4(rdev)) {
1956 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1957 * depending on the asic:
1958 * DCE4: PPLL or ext clock
1959 * DCE5: PPLL, DCPLL, or ext clock
1960 * DCE6: PPLL, PPLL0, or ext clock
1961 *
1962 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1963 * PPLL/DCPLL programming and only program the DP DTO for the
1964 * crtc virtual pixel clock.
1965 */
1966 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1967 if (rdev->clock.dp_extclk)
1968 /* skip PPLL programming if using ext clock */
1969 return ATOM_PPLL_INVALID;
1970 else if (ASIC_IS_DCE6(rdev))
1971 /* use PPLL0 for all DP */
1972 return ATOM_PPLL0;
1973 else if (ASIC_IS_DCE5(rdev))
1974 /* use DCPLL for all DP */
1975 return ATOM_DCPLL;
1976 else {
1977 /* use the same PPLL for all DP monitors */
1978 pll = radeon_get_shared_dp_ppll(crtc);
1979 if (pll != ATOM_PPLL_INVALID)
1980 return pll;
1981 }
1982 } else {
1983 /* use the same PPLL for all monitors with the same clock */
1984 pll = radeon_get_shared_nondp_ppll(crtc);
1985 if (pll != ATOM_PPLL_INVALID)
1986 return pll;
1987 }
1988 /* all other cases */
1989 pll_in_use = radeon_get_pll_use_mask(crtc);
1990 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1991 return ATOM_PPLL1;
1992 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1993 return ATOM_PPLL2;
1994 DRM_ERROR("unable to allocate a PPLL\n");
1995 return ATOM_PPLL_INVALID;
1996 } else {
1997 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1998 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1999 * the matching btw pll and crtc is done through
2000 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
2001 * pll (1 or 2) to select which register to write. ie if using
2002 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
2003 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
2004 * choose which value to write. Which is reverse order from
2005 * register logic. So only case that works is when pllid is
2006 * same as crtcid or when both pll and crtc are enabled and
2007 * both use same clock.
2008 *
2009 * So just return crtc id as if crtc and pll were hard linked
2010 * together even if they aren't
2011 */
2012 return radeon_crtc->crtc_id;
2013 }
2014}
2015
2016void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2017{
2018 /* always set DCPLL */
2019 if (ASIC_IS_DCE6(rdev))
2020 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2021 else if (ASIC_IS_DCE4(rdev)) {
2022 struct radeon_atom_ss ss;
2023 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2024 ASIC_INTERNAL_SS_ON_DCPLL,
2025 rdev->clock.default_dispclk);
2026 if (ss_enabled)
2027 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2028 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2029 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2030 if (ss_enabled)
2031 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2032 }
2033
2034}
2035
2036int atombios_crtc_mode_set(struct drm_crtc *crtc,
2037 struct drm_display_mode *mode,
2038 struct drm_display_mode *adjusted_mode,
2039 int x, int y, struct drm_framebuffer *old_fb)
2040{
2041 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2042 struct drm_device *dev = crtc->dev;
2043 struct radeon_device *rdev = dev->dev_private;
2044 struct radeon_encoder *radeon_encoder =
2045 to_radeon_encoder(radeon_crtc->encoder);
2046 bool is_tvcv = false;
2047
2048 if (radeon_encoder->active_device &
2049 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2050 is_tvcv = true;
2051
2052 if (!radeon_crtc->adjusted_clock)
2053 return -EINVAL;
2054
2055 atombios_crtc_set_pll(crtc, adjusted_mode);
2056
2057 if (ASIC_IS_DCE4(rdev))
2058 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2059 else if (ASIC_IS_AVIVO(rdev)) {
2060 if (is_tvcv)
2061 atombios_crtc_set_timing(crtc, adjusted_mode);
2062 else
2063 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2064 } else {
2065 atombios_crtc_set_timing(crtc, adjusted_mode);
2066 if (radeon_crtc->crtc_id == 0)
2067 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2068 radeon_legacy_atom_fixup(crtc);
2069 }
2070 atombios_crtc_set_base(crtc, x, y, old_fb);
2071 atombios_overscan_setup(crtc, mode, adjusted_mode);
2072 atombios_scaler_setup(crtc);
2073 radeon_cursor_reset(crtc);
2074 /* update the hw version fpr dpm */
2075 radeon_crtc->hw_mode = *adjusted_mode;
2076
2077 return 0;
2078}
2079
2080static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2081 const struct drm_display_mode *mode,
2082 struct drm_display_mode *adjusted_mode)
2083{
2084 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2085 struct drm_device *dev = crtc->dev;
2086 struct drm_encoder *encoder;
2087
2088 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2089 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2090 if (encoder->crtc == crtc) {
2091 radeon_crtc->encoder = encoder;
2092 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2093 break;
2094 }
2095 }
2096 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2097 radeon_crtc->encoder = NULL;
2098 radeon_crtc->connector = NULL;
2099 return false;
2100 }
2101 if (radeon_crtc->encoder) {
2102 struct radeon_encoder *radeon_encoder =
2103 to_radeon_encoder(radeon_crtc->encoder);
2104
2105 radeon_crtc->output_csc = radeon_encoder->output_csc;
2106 }
2107 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2108 return false;
2109 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2110 return false;
2111 /* pick pll */
2112 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2113 /* if we can't get a PPLL for a non-DP encoder, fail */
2114 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2115 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2116 return false;
2117
2118 return true;
2119}
2120
2121static void atombios_crtc_prepare(struct drm_crtc *crtc)
2122{
2123 struct drm_device *dev = crtc->dev;
2124 struct radeon_device *rdev = dev->dev_private;
2125
2126 /* disable crtc pair power gating before programming */
2127 if (ASIC_IS_DCE6(rdev))
2128 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2129
2130 atombios_lock_crtc(crtc, ATOM_ENABLE);
2131 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2132}
2133
2134static void atombios_crtc_commit(struct drm_crtc *crtc)
2135{
2136 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2137 atombios_lock_crtc(crtc, ATOM_DISABLE);
2138}
2139
2140static void atombios_crtc_disable(struct drm_crtc *crtc)
2141{
2142 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2143 struct drm_device *dev = crtc->dev;
2144 struct radeon_device *rdev = dev->dev_private;
2145 struct radeon_atom_ss ss;
2146 int i;
2147
2148 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2149 if (crtc->primary->fb) {
2150 int r;
2151 struct radeon_framebuffer *radeon_fb;
2152 struct radeon_bo *rbo;
2153
2154 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2155 rbo = gem_to_radeon_bo(radeon_fb->obj);
2156 r = radeon_bo_reserve(rbo, false);
2157 if (unlikely(r))
2158 DRM_ERROR("failed to reserve rbo before unpin\n");
2159 else {
2160 radeon_bo_unpin(rbo);
2161 radeon_bo_unreserve(rbo);
2162 }
2163 }
2164 /* disable the GRPH */
2165 if (ASIC_IS_DCE4(rdev))
2166 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2167 else if (ASIC_IS_AVIVO(rdev))
2168 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2169
2170 if (ASIC_IS_DCE6(rdev))
2171 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2172
2173 for (i = 0; i < rdev->num_crtc; i++) {
2174 if (rdev->mode_info.crtcs[i] &&
2175 rdev->mode_info.crtcs[i]->enabled &&
2176 i != radeon_crtc->crtc_id &&
2177 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2178 /* one other crtc is using this pll don't turn
2179 * off the pll
2180 */
2181 goto done;
2182 }
2183 }
2184
2185 switch (radeon_crtc->pll_id) {
2186 case ATOM_PPLL1:
2187 case ATOM_PPLL2:
2188 /* disable the ppll */
2189 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2190 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2191 break;
2192 case ATOM_PPLL0:
2193 /* disable the ppll */
2194 if ((rdev->family == CHIP_ARUBA) ||
2195 (rdev->family == CHIP_KAVERI) ||
2196 (rdev->family == CHIP_BONAIRE) ||
2197 (rdev->family == CHIP_HAWAII))
2198 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2199 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2200 break;
2201 default:
2202 break;
2203 }
2204done:
2205 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2206 radeon_crtc->adjusted_clock = 0;
2207 radeon_crtc->encoder = NULL;
2208 radeon_crtc->connector = NULL;
2209}
2210
2211static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2212 .dpms = atombios_crtc_dpms,
2213 .mode_fixup = atombios_crtc_mode_fixup,
2214 .mode_set = atombios_crtc_mode_set,
2215 .mode_set_base = atombios_crtc_set_base,
2216 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2217 .prepare = atombios_crtc_prepare,
2218 .commit = atombios_crtc_commit,
2219 .load_lut = radeon_crtc_load_lut,
2220 .disable = atombios_crtc_disable,
2221};
2222
2223void radeon_atombios_init_crtc(struct drm_device *dev,
2224 struct radeon_crtc *radeon_crtc)
2225{
2226 struct radeon_device *rdev = dev->dev_private;
2227
2228 if (ASIC_IS_DCE4(rdev)) {
2229 switch (radeon_crtc->crtc_id) {
2230 case 0:
2231 default:
2232 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2233 break;
2234 case 1:
2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2236 break;
2237 case 2:
2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2239 break;
2240 case 3:
2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2242 break;
2243 case 4:
2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2245 break;
2246 case 5:
2247 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2248 break;
2249 }
2250 } else {
2251 if (radeon_crtc->crtc_id == 1)
2252 radeon_crtc->crtc_offset =
2253 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2254 else
2255 radeon_crtc->crtc_offset = 0;
2256 }
2257 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2258 radeon_crtc->adjusted_clock = 0;
2259 radeon_crtc->encoder = NULL;
2260 radeon_crtc->connector = NULL;
2261 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2262}