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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167}
168
169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
261 radeon_crtc->enabled = false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
264 break;
265 }
266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
270 struct drm_display_mode *mode)
271{
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
277 u16 misc = 0;
278
279 memset(&args, 0, sizeof(args));
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
281 args.usH_Blanking_Time =
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
284 args.usV_Blanking_Time =
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
286 args.usH_SyncOffset =
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
310
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312}
313
314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
316{
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
322 u16 misc = 0;
323
324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
354
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356}
357
358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
401union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
407};
408
409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
413{
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args;
418
419 memset(&args, 0, sizeof(args));
420
421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v3.ucEnable = enable;
444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
446 } else if (ASIC_IS_DCE4(rdev)) {
447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
449 switch (pll_id) {
450 case ATOM_PPLL1:
451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
454 break;
455 case ATOM_PPLL2:
456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
459 break;
460 case ATOM_DCPLL:
461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
464 break;
465 case ATOM_PPLL_INVALID:
466 return;
467 }
468 args.v2.ucEnable = enable;
469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
470 args.v2.ucEnable = ATOM_DISABLE;
471 } else if (ASIC_IS_DCE3(rdev)) {
472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 args.v1.ucSpreadSpectrumStep = ss->step;
475 args.v1.ucSpreadSpectrumDelay = ss->delay;
476 args.v1.ucSpreadSpectrumRange = ss->range;
477 args.v1.ucPpll = pll_id;
478 args.v1.ucEnable = enable;
479 } else if (ASIC_IS_AVIVO(rdev)) {
480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
482 atombios_disable_ss(crtc);
483 return;
484 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
490 args.lvds_ss_2.ucEnable = enable;
491 } else {
492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
494 atombios_disable_ss(crtc);
495 return;
496 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
501 args.lvds_ss.ucEnable = enable;
502 }
503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
504}
505
506union adjust_pixel_clock {
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
509};
510
511static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct drm_display_mode *mode,
513 struct radeon_pll *pll,
514 bool ss_enabled,
515 struct radeon_atom_ss *ss)
516{
517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct drm_encoder *encoder = NULL;
520 struct radeon_encoder *radeon_encoder = NULL;
521 struct drm_connector *connector = NULL;
522 u32 adjusted_clock = mode->clock;
523 int encoder_mode = 0;
524 u32 dp_clock = mode->clock;
525 int bpc = 8;
526
527 /* reset the pll flags */
528 pll->flags = 0;
529
530 if (ASIC_IS_AVIVO(rdev)) {
531 if ((rdev->family == CHIP_RS600) ||
532 (rdev->family == CHIP_RS690) ||
533 (rdev->family == CHIP_RS740))
534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
535 RADEON_PLL_PREFER_CLOSEST_LOWER);
536
537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 if (rdev->family < CHIP_RV770)
543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
544 } else {
545 pll->flags |= RADEON_PLL_LEGACY;
546
547 if (mode->clock > 200000) /* range limits??? */
548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
549 else
550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
551 }
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
554 if (encoder->crtc == crtc) {
555 radeon_encoder = to_radeon_encoder(encoder);
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (connector)
558 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 radeon_encoder_is_dp_bridge(encoder)) {
562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector =
565 radeon_connector->con_priv;
566
567 dp_clock = dig_connector->dp_clock;
568 }
569 }
570
571 /* use recommended ref_div for ss */
572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573 if (ss_enabled) {
574 if (ss->refdiv) {
575 pll->flags |= RADEON_PLL_USE_REF_DIV;
576 pll->reference_div = ss->refdiv;
577 if (ASIC_IS_AVIVO(rdev))
578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
579 }
580 }
581 }
582
583 if (ASIC_IS_AVIVO(rdev)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
586 adjusted_clock = mode->clock * 2;
587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
590 pll->flags |= RADEON_PLL_IS_LCD;
591 } else {
592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
595 pll->flags |= RADEON_PLL_USE_REF_DIV;
596 }
597 break;
598 }
599 }
600
601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
604 */
605 if (ASIC_IS_DCE3(rdev)) {
606 union adjust_pixel_clock args;
607 u8 frev, crev;
608 int index;
609
610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
612 &crev))
613 return adjusted_clock;
614
615 memset(&args, 0, sizeof(args));
616
617 switch (frev) {
618 case 1:
619 switch (crev) {
620 case 1:
621 case 2:
622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
624 args.v1.ucEncodeMode = encoder_mode;
625 if (ss_enabled && ss->percentage)
626 args.v1.ucConfig |=
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
628
629 atom_execute_table(rdev->mode_info.atom_context,
630 index, (uint32_t *)&args);
631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
632 break;
633 case 3:
634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
636 args.v3.sInput.ucEncodeMode = encoder_mode;
637 args.v3.sInput.ucDispPllConfig = 0;
638 if (ss_enabled && ss->percentage)
639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE;
641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642 radeon_encoder_is_dp_bridge(encoder)) {
643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
645 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE;
647 /* 16200 or 27000 */
648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649 } else {
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 /* deep color support */
652 args.v3.sInput.usPixelClock =
653 cpu_to_le16((mode->clock * bpc / 8) / 10);
654 }
655 if (dig->coherent_mode)
656 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_COHERENT_MODE;
658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE;
666 /* 16200 or 27000 */
667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669 if (mode->clock > 165000)
670 args.v3.sInput.ucDispPllConfig |=
671 DISPPLL_CONFIG_DUAL_LINK;
672 }
673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
681 atom_execute_table(rdev->mode_info.atom_context,
682 index, (uint32_t *)&args);
683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
684 if (args.v3.sOutput.ucRefDiv) {
685 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
686 pll->flags |= RADEON_PLL_USE_REF_DIV;
687 pll->reference_div = args.v3.sOutput.ucRefDiv;
688 }
689 if (args.v3.sOutput.ucPostDiv) {
690 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
691 pll->flags |= RADEON_PLL_USE_POST_DIV;
692 pll->post_div = args.v3.sOutput.ucPostDiv;
693 }
694 break;
695 default:
696 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 return adjusted_clock;
698 }
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
702 return adjusted_clock;
703 }
704 }
705 return adjusted_clock;
706}
707
708union set_pixel_clock {
709 SET_PIXEL_CLOCK_PS_ALLOCATION base;
710 PIXEL_CLOCK_PARAMETERS v1;
711 PIXEL_CLOCK_PARAMETERS_V2 v2;
712 PIXEL_CLOCK_PARAMETERS_V3 v3;
713 PIXEL_CLOCK_PARAMETERS_V5 v5;
714 PIXEL_CLOCK_PARAMETERS_V6 v6;
715};
716
717/* on DCE5, make sure the voltage is high enough to support the
718 * required disp clk.
719 */
720static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
721 u32 dispclk)
722{
723 struct drm_device *dev = crtc->dev;
724 struct radeon_device *rdev = dev->dev_private;
725 u8 frev, crev;
726 int index;
727 union set_pixel_clock args;
728
729 memset(&args, 0, sizeof(args));
730
731 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
733 &crev))
734 return;
735
736 switch (frev) {
737 case 1:
738 switch (crev) {
739 case 5:
740 /* if the default dcpll clock is specified,
741 * SetPixelClock provides the dividers
742 */
743 args.v5.ucCRTC = ATOM_CRTC_INVALID;
744 args.v5.usPixelClock = cpu_to_le16(dispclk);
745 args.v5.ucPpll = ATOM_DCPLL;
746 break;
747 case 6:
748 /* if the default dcpll clock is specified,
749 * SetPixelClock provides the dividers
750 */
751 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
752 args.v6.ucPpll = ATOM_DCPLL;
753 break;
754 default:
755 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
756 return;
757 }
758 break;
759 default:
760 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
761 return;
762 }
763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
764}
765
766static void atombios_crtc_program_pll(struct drm_crtc *crtc,
767 u32 crtc_id,
768 int pll_id,
769 u32 encoder_mode,
770 u32 encoder_id,
771 u32 clock,
772 u32 ref_div,
773 u32 fb_div,
774 u32 frac_fb_div,
775 u32 post_div,
776 int bpc,
777 bool ss_enabled,
778 struct radeon_atom_ss *ss)
779{
780 struct drm_device *dev = crtc->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 u8 frev, crev;
783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
784 union set_pixel_clock args;
785
786 memset(&args, 0, sizeof(args));
787
788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
789 &crev))
790 return;
791
792 switch (frev) {
793 case 1:
794 switch (crev) {
795 case 1:
796 if (clock == ATOM_DISABLE)
797 return;
798 args.v1.usPixelClock = cpu_to_le16(clock / 10);
799 args.v1.usRefDiv = cpu_to_le16(ref_div);
800 args.v1.usFbDiv = cpu_to_le16(fb_div);
801 args.v1.ucFracFbDiv = frac_fb_div;
802 args.v1.ucPostDiv = post_div;
803 args.v1.ucPpll = pll_id;
804 args.v1.ucCRTC = crtc_id;
805 args.v1.ucRefDivSrc = 1;
806 break;
807 case 2:
808 args.v2.usPixelClock = cpu_to_le16(clock / 10);
809 args.v2.usRefDiv = cpu_to_le16(ref_div);
810 args.v2.usFbDiv = cpu_to_le16(fb_div);
811 args.v2.ucFracFbDiv = frac_fb_div;
812 args.v2.ucPostDiv = post_div;
813 args.v2.ucPpll = pll_id;
814 args.v2.ucCRTC = crtc_id;
815 args.v2.ucRefDivSrc = 1;
816 break;
817 case 3:
818 args.v3.usPixelClock = cpu_to_le16(clock / 10);
819 args.v3.usRefDiv = cpu_to_le16(ref_div);
820 args.v3.usFbDiv = cpu_to_le16(fb_div);
821 args.v3.ucFracFbDiv = frac_fb_div;
822 args.v3.ucPostDiv = post_div;
823 args.v3.ucPpll = pll_id;
824 args.v3.ucMiscInfo = (pll_id << 2);
825 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
826 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
827 args.v3.ucTransmitterId = encoder_id;
828 args.v3.ucEncoderMode = encoder_mode;
829 break;
830 case 5:
831 args.v5.ucCRTC = crtc_id;
832 args.v5.usPixelClock = cpu_to_le16(clock / 10);
833 args.v5.ucRefDiv = ref_div;
834 args.v5.usFbDiv = cpu_to_le16(fb_div);
835 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
836 args.v5.ucPostDiv = post_div;
837 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
838 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
840 switch (bpc) {
841 case 8:
842 default:
843 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
844 break;
845 case 10:
846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
847 break;
848 }
849 args.v5.ucTransmitterID = encoder_id;
850 args.v5.ucEncoderMode = encoder_mode;
851 args.v5.ucPpll = pll_id;
852 break;
853 case 6:
854 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
855 args.v6.ucRefDiv = ref_div;
856 args.v6.usFbDiv = cpu_to_le16(fb_div);
857 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
858 args.v6.ucPostDiv = post_div;
859 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
860 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
861 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
862 switch (bpc) {
863 case 8:
864 default:
865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
866 break;
867 case 10:
868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
869 break;
870 case 12:
871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
872 break;
873 case 16:
874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
875 break;
876 }
877 args.v6.ucTransmitterID = encoder_id;
878 args.v6.ucEncoderMode = encoder_mode;
879 args.v6.ucPpll = pll_id;
880 break;
881 default:
882 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
883 return;
884 }
885 break;
886 default:
887 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
888 return;
889 }
890
891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
892}
893
894static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
895{
896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
897 struct drm_device *dev = crtc->dev;
898 struct radeon_device *rdev = dev->dev_private;
899 struct drm_encoder *encoder = NULL;
900 struct radeon_encoder *radeon_encoder = NULL;
901 u32 pll_clock = mode->clock;
902 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
903 struct radeon_pll *pll;
904 u32 adjusted_clock;
905 int encoder_mode = 0;
906 struct radeon_atom_ss ss;
907 bool ss_enabled = false;
908 int bpc = 8;
909
910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
911 if (encoder->crtc == crtc) {
912 radeon_encoder = to_radeon_encoder(encoder);
913 encoder_mode = atombios_get_encoder_mode(encoder);
914 break;
915 }
916 }
917
918 if (!radeon_encoder)
919 return;
920
921 switch (radeon_crtc->pll_id) {
922 case ATOM_PPLL1:
923 pll = &rdev->clock.p1pll;
924 break;
925 case ATOM_PPLL2:
926 pll = &rdev->clock.p2pll;
927 break;
928 case ATOM_DCPLL:
929 case ATOM_PPLL_INVALID:
930 default:
931 pll = &rdev->clock.dcpll;
932 break;
933 }
934
935 if (radeon_encoder->active_device &
936 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector =
939 radeon_get_connector_for_encoder(encoder);
940 struct radeon_connector *radeon_connector =
941 to_radeon_connector(connector);
942 struct radeon_connector_atom_dig *dig_connector =
943 radeon_connector->con_priv;
944 int dp_clock;
945 bpc = connector->display_info.bpc;
946
947 switch (encoder_mode) {
948 case ATOM_ENCODER_MODE_DP:
949 /* DP/eDP */
950 dp_clock = dig_connector->dp_clock / 10;
951 if (ASIC_IS_DCE4(rdev))
952 ss_enabled =
953 radeon_atombios_get_asic_ss_info(rdev, &ss,
954 ASIC_INTERNAL_SS_ON_DP,
955 dp_clock);
956 else {
957 if (dp_clock == 16200) {
958 ss_enabled =
959 radeon_atombios_get_ppll_ss_info(rdev, &ss,
960 ATOM_DP_SS_ID2);
961 if (!ss_enabled)
962 ss_enabled =
963 radeon_atombios_get_ppll_ss_info(rdev, &ss,
964 ATOM_DP_SS_ID1);
965 } else
966 ss_enabled =
967 radeon_atombios_get_ppll_ss_info(rdev, &ss,
968 ATOM_DP_SS_ID1);
969 }
970 break;
971 case ATOM_ENCODER_MODE_LVDS:
972 if (ASIC_IS_DCE4(rdev))
973 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
974 dig->lcd_ss_id,
975 mode->clock / 10);
976 else
977 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
978 dig->lcd_ss_id);
979 break;
980 case ATOM_ENCODER_MODE_DVI:
981 if (ASIC_IS_DCE4(rdev))
982 ss_enabled =
983 radeon_atombios_get_asic_ss_info(rdev, &ss,
984 ASIC_INTERNAL_SS_ON_TMDS,
985 mode->clock / 10);
986 break;
987 case ATOM_ENCODER_MODE_HDMI:
988 if (ASIC_IS_DCE4(rdev))
989 ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev, &ss,
991 ASIC_INTERNAL_SS_ON_HDMI,
992 mode->clock / 10);
993 break;
994 default:
995 break;
996 }
997 }
998
999 /* adjust pixel clock as needed */
1000 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1001
1002 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1003 /* TV seems to prefer the legacy algo on some boards */
1004 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1005 &ref_div, &post_div);
1006 else if (ASIC_IS_AVIVO(rdev))
1007 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1008 &ref_div, &post_div);
1009 else
1010 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1011 &ref_div, &post_div);
1012
1013 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1014
1015 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1016 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1017 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1018
1019 if (ss_enabled) {
1020 /* calculate ss amount and step size */
1021 if (ASIC_IS_DCE4(rdev)) {
1022 u32 step_size;
1023 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1024 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1025 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1026 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1027 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1028 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1029 (125 * 25 * pll->reference_freq / 100);
1030 else
1031 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1032 (125 * 25 * pll->reference_freq / 100);
1033 ss.step = step_size;
1034 }
1035
1036 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1037 }
1038}
1039
1040static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1041 struct drm_framebuffer *fb,
1042 int x, int y, int atomic)
1043{
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 struct drm_device *dev = crtc->dev;
1046 struct radeon_device *rdev = dev->dev_private;
1047 struct radeon_framebuffer *radeon_fb;
1048 struct drm_framebuffer *target_fb;
1049 struct drm_gem_object *obj;
1050 struct radeon_bo *rbo;
1051 uint64_t fb_location;
1052 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1053 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1054 u32 tmp, viewport_w, viewport_h;
1055 int r;
1056
1057 /* no fb bound */
1058 if (!atomic && !crtc->fb) {
1059 DRM_DEBUG_KMS("No FB bound\n");
1060 return 0;
1061 }
1062
1063 if (atomic) {
1064 radeon_fb = to_radeon_framebuffer(fb);
1065 target_fb = fb;
1066 }
1067 else {
1068 radeon_fb = to_radeon_framebuffer(crtc->fb);
1069 target_fb = crtc->fb;
1070 }
1071
1072 /* If atomic, assume fb object is pinned & idle & fenced and
1073 * just update base pointers
1074 */
1075 obj = radeon_fb->obj;
1076 rbo = gem_to_radeon_bo(obj);
1077 r = radeon_bo_reserve(rbo, false);
1078 if (unlikely(r != 0))
1079 return r;
1080
1081 if (atomic)
1082 fb_location = radeon_bo_gpu_offset(rbo);
1083 else {
1084 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1085 if (unlikely(r != 0)) {
1086 radeon_bo_unreserve(rbo);
1087 return -EINVAL;
1088 }
1089 }
1090
1091 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1092 radeon_bo_unreserve(rbo);
1093
1094 switch (target_fb->bits_per_pixel) {
1095 case 8:
1096 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1097 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1098 break;
1099 case 15:
1100 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1101 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1102 break;
1103 case 16:
1104 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1105 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1106#ifdef __BIG_ENDIAN
1107 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1108#endif
1109 break;
1110 case 24:
1111 case 32:
1112 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1113 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1114#ifdef __BIG_ENDIAN
1115 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1116#endif
1117 break;
1118 default:
1119 DRM_ERROR("Unsupported screen depth %d\n",
1120 target_fb->bits_per_pixel);
1121 return -EINVAL;
1122 }
1123
1124 if (tiling_flags & RADEON_TILING_MACRO)
1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 else if (tiling_flags & RADEON_TILING_MICRO)
1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1128
1129 switch (radeon_crtc->crtc_id) {
1130 case 0:
1131 WREG32(AVIVO_D1VGA_CONTROL, 0);
1132 break;
1133 case 1:
1134 WREG32(AVIVO_D2VGA_CONTROL, 0);
1135 break;
1136 case 2:
1137 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1138 break;
1139 case 3:
1140 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1141 break;
1142 case 4:
1143 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1144 break;
1145 case 5:
1146 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1147 break;
1148 default:
1149 break;
1150 }
1151
1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1153 upper_32_bits(fb_location));
1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1155 upper_32_bits(fb_location));
1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1157 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1159 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1160 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1161 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1162
1163 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1164 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1165 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1166 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1167 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1168 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1169
1170 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1171 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1172 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1173
1174 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1175 crtc->mode.vdisplay);
1176 x &= ~3;
1177 y &= ~1;
1178 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1179 (x << 16) | y);
1180 viewport_w = crtc->mode.hdisplay;
1181 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1182 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1183 (viewport_w << 16) | viewport_h);
1184
1185 /* pageflip setup */
1186 /* make sure flip is at vb rather than hb */
1187 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1188 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1189 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1190
1191 /* set pageflip to happen anywhere in vblank interval */
1192 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1193
1194 if (!atomic && fb && fb != crtc->fb) {
1195 radeon_fb = to_radeon_framebuffer(fb);
1196 rbo = gem_to_radeon_bo(radeon_fb->obj);
1197 r = radeon_bo_reserve(rbo, false);
1198 if (unlikely(r != 0))
1199 return r;
1200 radeon_bo_unpin(rbo);
1201 radeon_bo_unreserve(rbo);
1202 }
1203
1204 /* Bytes per pixel may have changed */
1205 radeon_bandwidth_update(rdev);
1206
1207 return 0;
1208}
1209
1210static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1211 struct drm_framebuffer *fb,
1212 int x, int y, int atomic)
1213{
1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1215 struct drm_device *dev = crtc->dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_framebuffer *radeon_fb;
1218 struct drm_gem_object *obj;
1219 struct radeon_bo *rbo;
1220 struct drm_framebuffer *target_fb;
1221 uint64_t fb_location;
1222 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1223 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1224 u32 tmp, viewport_w, viewport_h;
1225 int r;
1226
1227 /* no fb bound */
1228 if (!atomic && !crtc->fb) {
1229 DRM_DEBUG_KMS("No FB bound\n");
1230 return 0;
1231 }
1232
1233 if (atomic) {
1234 radeon_fb = to_radeon_framebuffer(fb);
1235 target_fb = fb;
1236 }
1237 else {
1238 radeon_fb = to_radeon_framebuffer(crtc->fb);
1239 target_fb = crtc->fb;
1240 }
1241
1242 obj = radeon_fb->obj;
1243 rbo = gem_to_radeon_bo(obj);
1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1246 return r;
1247
1248 /* If atomic, assume fb object is pinned & idle & fenced and
1249 * just update base pointers
1250 */
1251 if (atomic)
1252 fb_location = radeon_bo_gpu_offset(rbo);
1253 else {
1254 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1255 if (unlikely(r != 0)) {
1256 radeon_bo_unreserve(rbo);
1257 return -EINVAL;
1258 }
1259 }
1260 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1261 radeon_bo_unreserve(rbo);
1262
1263 switch (target_fb->bits_per_pixel) {
1264 case 8:
1265 fb_format =
1266 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1267 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1268 break;
1269 case 15:
1270 fb_format =
1271 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1272 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1273 break;
1274 case 16:
1275 fb_format =
1276 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1277 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1278#ifdef __BIG_ENDIAN
1279 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1280#endif
1281 break;
1282 case 24:
1283 case 32:
1284 fb_format =
1285 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1286 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1287#ifdef __BIG_ENDIAN
1288 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1289#endif
1290 break;
1291 default:
1292 DRM_ERROR("Unsupported screen depth %d\n",
1293 target_fb->bits_per_pixel);
1294 return -EINVAL;
1295 }
1296
1297 if (rdev->family >= CHIP_R600) {
1298 if (tiling_flags & RADEON_TILING_MACRO)
1299 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1300 else if (tiling_flags & RADEON_TILING_MICRO)
1301 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1302 } else {
1303 if (tiling_flags & RADEON_TILING_MACRO)
1304 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1305
1306 if (tiling_flags & RADEON_TILING_MICRO)
1307 fb_format |= AVIVO_D1GRPH_TILED;
1308 }
1309
1310 if (radeon_crtc->crtc_id == 0)
1311 WREG32(AVIVO_D1VGA_CONTROL, 0);
1312 else
1313 WREG32(AVIVO_D2VGA_CONTROL, 0);
1314
1315 if (rdev->family >= CHIP_RV770) {
1316 if (radeon_crtc->crtc_id) {
1317 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1318 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1319 } else {
1320 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1321 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1322 }
1323 }
1324 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1325 (u32) fb_location);
1326 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1327 radeon_crtc->crtc_offset, (u32) fb_location);
1328 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1329 if (rdev->family >= CHIP_R600)
1330 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331
1332 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1335 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1336 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1337 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1338
1339 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1340 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1341 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1342
1343 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1344 crtc->mode.vdisplay);
1345 x &= ~3;
1346 y &= ~1;
1347 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1348 (x << 16) | y);
1349 viewport_w = crtc->mode.hdisplay;
1350 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1351 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1352 (viewport_w << 16) | viewport_h);
1353
1354 /* pageflip setup */
1355 /* make sure flip is at vb rather than hb */
1356 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1357 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1358 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1359
1360 /* set pageflip to happen anywhere in vblank interval */
1361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1362
1363 if (!atomic && fb && fb != crtc->fb) {
1364 radeon_fb = to_radeon_framebuffer(fb);
1365 rbo = gem_to_radeon_bo(radeon_fb->obj);
1366 r = radeon_bo_reserve(rbo, false);
1367 if (unlikely(r != 0))
1368 return r;
1369 radeon_bo_unpin(rbo);
1370 radeon_bo_unreserve(rbo);
1371 }
1372
1373 /* Bytes per pixel may have changed */
1374 radeon_bandwidth_update(rdev);
1375
1376 return 0;
1377}
1378
1379int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1380 struct drm_framebuffer *old_fb)
1381{
1382 struct drm_device *dev = crtc->dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384
1385 if (ASIC_IS_DCE4(rdev))
1386 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1387 else if (ASIC_IS_AVIVO(rdev))
1388 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1389 else
1390 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1391}
1392
1393int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1394 struct drm_framebuffer *fb,
1395 int x, int y, enum mode_set_atomic state)
1396{
1397 struct drm_device *dev = crtc->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399
1400 if (ASIC_IS_DCE4(rdev))
1401 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1402 else if (ASIC_IS_AVIVO(rdev))
1403 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1404 else
1405 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1406}
1407
1408/* properly set additional regs when using atombios */
1409static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct radeon_device *rdev = dev->dev_private;
1413 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1414 u32 disp_merge_cntl;
1415
1416 switch (radeon_crtc->crtc_id) {
1417 case 0:
1418 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1419 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1420 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1421 break;
1422 case 1:
1423 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1424 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1425 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1426 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1427 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1428 break;
1429 }
1430}
1431
1432static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1433{
1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1435 struct drm_device *dev = crtc->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1437 struct drm_encoder *test_encoder;
1438 struct drm_crtc *test_crtc;
1439 uint32_t pll_in_use = 0;
1440
1441 if (ASIC_IS_DCE4(rdev)) {
1442 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1443 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1444 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1445 * depending on the asic:
1446 * DCE4: PPLL or ext clock
1447 * DCE5: DCPLL or ext clock
1448 *
1449 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1450 * PPLL/DCPLL programming and only program the DP DTO for the
1451 * crtc virtual pixel clock.
1452 */
1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1455 return ATOM_PPLL_INVALID;
1456 }
1457 }
1458 }
1459
1460 /* otherwise, pick one of the plls */
1461 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1462 struct radeon_crtc *radeon_test_crtc;
1463
1464 if (crtc == test_crtc)
1465 continue;
1466
1467 radeon_test_crtc = to_radeon_crtc(test_crtc);
1468 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1469 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1470 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1471 }
1472 if (!(pll_in_use & 1))
1473 return ATOM_PPLL1;
1474 return ATOM_PPLL2;
1475 } else
1476 return radeon_crtc->crtc_id;
1477
1478}
1479
1480int atombios_crtc_mode_set(struct drm_crtc *crtc,
1481 struct drm_display_mode *mode,
1482 struct drm_display_mode *adjusted_mode,
1483 int x, int y, struct drm_framebuffer *old_fb)
1484{
1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1486 struct drm_device *dev = crtc->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct drm_encoder *encoder;
1489 bool is_tvcv = false;
1490
1491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1492 /* find tv std */
1493 if (encoder->crtc == crtc) {
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 if (radeon_encoder->active_device &
1496 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1497 is_tvcv = true;
1498 }
1499 }
1500
1501 /* always set DCPLL */
1502 if (ASIC_IS_DCE4(rdev)) {
1503 struct radeon_atom_ss ss;
1504 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1505 ASIC_INTERNAL_SS_ON_DCPLL,
1506 rdev->clock.default_dispclk);
1507 if (ss_enabled)
1508 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1509 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1510 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1511 if (ss_enabled)
1512 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1513 }
1514 atombios_crtc_set_pll(crtc, adjusted_mode);
1515
1516 if (ASIC_IS_DCE4(rdev))
1517 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1518 else if (ASIC_IS_AVIVO(rdev)) {
1519 if (is_tvcv)
1520 atombios_crtc_set_timing(crtc, adjusted_mode);
1521 else
1522 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1523 } else {
1524 atombios_crtc_set_timing(crtc, adjusted_mode);
1525 if (radeon_crtc->crtc_id == 0)
1526 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1527 radeon_legacy_atom_fixup(crtc);
1528 }
1529 atombios_crtc_set_base(crtc, x, y, old_fb);
1530 atombios_overscan_setup(crtc, mode, adjusted_mode);
1531 atombios_scaler_setup(crtc);
1532 return 0;
1533}
1534
1535static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1536 struct drm_display_mode *mode,
1537 struct drm_display_mode *adjusted_mode)
1538{
1539 struct drm_device *dev = crtc->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541
1542 /* adjust pm to upcoming mode change */
1543 radeon_pm_compute_clocks(rdev);
1544
1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1546 return false;
1547 return true;
1548}
1549
1550static void atombios_crtc_prepare(struct drm_crtc *crtc)
1551{
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553
1554 /* pick pll */
1555 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1556
1557 atombios_lock_crtc(crtc, ATOM_ENABLE);
1558 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1559}
1560
1561static void atombios_crtc_commit(struct drm_crtc *crtc)
1562{
1563 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1564 atombios_lock_crtc(crtc, ATOM_DISABLE);
1565}
1566
1567static void atombios_crtc_disable(struct drm_crtc *crtc)
1568{
1569 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1570 struct radeon_atom_ss ss;
1571
1572 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1573
1574 switch (radeon_crtc->pll_id) {
1575 case ATOM_PPLL1:
1576 case ATOM_PPLL2:
1577 /* disable the ppll */
1578 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1580 break;
1581 default:
1582 break;
1583 }
1584 radeon_crtc->pll_id = -1;
1585}
1586
1587static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1588 .dpms = atombios_crtc_dpms,
1589 .mode_fixup = atombios_crtc_mode_fixup,
1590 .mode_set = atombios_crtc_mode_set,
1591 .mode_set_base = atombios_crtc_set_base,
1592 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1593 .prepare = atombios_crtc_prepare,
1594 .commit = atombios_crtc_commit,
1595 .load_lut = radeon_crtc_load_lut,
1596 .disable = atombios_crtc_disable,
1597};
1598
1599void radeon_atombios_init_crtc(struct drm_device *dev,
1600 struct radeon_crtc *radeon_crtc)
1601{
1602 struct radeon_device *rdev = dev->dev_private;
1603
1604 if (ASIC_IS_DCE4(rdev)) {
1605 switch (radeon_crtc->crtc_id) {
1606 case 0:
1607 default:
1608 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1609 break;
1610 case 1:
1611 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1612 break;
1613 case 2:
1614 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1615 break;
1616 case 3:
1617 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1618 break;
1619 case 4:
1620 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1621 break;
1622 case 5:
1623 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1624 break;
1625 }
1626 } else {
1627 if (radeon_crtc->crtc_id == 1)
1628 radeon_crtc->crtc_offset =
1629 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1630 else
1631 radeon_crtc->crtc_offset = 0;
1632 }
1633 radeon_crtc->pll_id = -1;
1634 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1635}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
90 bool is_tv = false, is_cv = false;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
99 }
100
101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
105 if (is_tv) {
106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
134 } else if (is_cv) {
135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
160 }
161}
162
163static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164{
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178}
179
180static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181{
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194}
195
196static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210}
211
212static const u32 vga_control_regs[6] =
213{
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220};
221
222static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
223{
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct drm_device *dev = crtc->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
228 BLANK_CRTC_PS_ALLOCATION args;
229 u32 vga_control = 0;
230
231 memset(&args, 0, sizeof(args));
232
233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
246}
247
248static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
249{
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 struct drm_device *dev = crtc->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
254 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
255
256 memset(&args, 0, sizeof(args));
257
258 args.ucDispPipeId = radeon_crtc->crtc_id;
259 args.ucEnable = state;
260
261 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
262}
263
264void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
265{
266 struct drm_device *dev = crtc->dev;
267 struct radeon_device *rdev = dev->dev_private;
268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
269
270 switch (mode) {
271 case DRM_MODE_DPMS_ON:
272 radeon_crtc->enabled = true;
273 atombios_enable_crtc(crtc, ATOM_ENABLE);
274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
275 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
276 atombios_blank_crtc(crtc, ATOM_DISABLE);
277 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
278 radeon_crtc_load_lut(crtc);
279 break;
280 case DRM_MODE_DPMS_STANDBY:
281 case DRM_MODE_DPMS_SUSPEND:
282 case DRM_MODE_DPMS_OFF:
283 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
284 if (radeon_crtc->enabled)
285 atombios_blank_crtc(crtc, ATOM_ENABLE);
286 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
287 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
288 atombios_enable_crtc(crtc, ATOM_DISABLE);
289 radeon_crtc->enabled = false;
290 break;
291 }
292 /* adjust pm to dpms */
293 radeon_pm_compute_clocks(rdev);
294}
295
296static void
297atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
298 struct drm_display_mode *mode)
299{
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
304 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
305 u16 misc = 0;
306
307 memset(&args, 0, sizeof(args));
308 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
309 args.usH_Blanking_Time =
310 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
311 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
312 args.usV_Blanking_Time =
313 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
314 args.usH_SyncOffset =
315 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
316 args.usH_SyncWidth =
317 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
318 args.usV_SyncOffset =
319 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
320 args.usV_SyncWidth =
321 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
322 args.ucH_Border = radeon_crtc->h_border;
323 args.ucV_Border = radeon_crtc->v_border;
324
325 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
326 misc |= ATOM_VSYNC_POLARITY;
327 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
328 misc |= ATOM_HSYNC_POLARITY;
329 if (mode->flags & DRM_MODE_FLAG_CSYNC)
330 misc |= ATOM_COMPOSITESYNC;
331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
332 misc |= ATOM_INTERLACE;
333 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
334 misc |= ATOM_DOUBLE_CLOCK_MODE;
335
336 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
337 args.ucCRTC = radeon_crtc->crtc_id;
338
339 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
340}
341
342static void atombios_crtc_set_timing(struct drm_crtc *crtc,
343 struct drm_display_mode *mode)
344{
345 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
346 struct drm_device *dev = crtc->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
349 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
350 u16 misc = 0;
351
352 memset(&args, 0, sizeof(args));
353 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
354 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
355 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
356 args.usH_SyncWidth =
357 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
358 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
359 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
360 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
361 args.usV_SyncWidth =
362 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
363
364 args.ucOverscanRight = radeon_crtc->h_border;
365 args.ucOverscanLeft = radeon_crtc->h_border;
366 args.ucOverscanBottom = radeon_crtc->v_border;
367 args.ucOverscanTop = radeon_crtc->v_border;
368
369 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
370 misc |= ATOM_VSYNC_POLARITY;
371 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
372 misc |= ATOM_HSYNC_POLARITY;
373 if (mode->flags & DRM_MODE_FLAG_CSYNC)
374 misc |= ATOM_COMPOSITESYNC;
375 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
376 misc |= ATOM_INTERLACE;
377 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
378 misc |= ATOM_DOUBLE_CLOCK_MODE;
379
380 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
381 args.ucCRTC = radeon_crtc->crtc_id;
382
383 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
384}
385
386static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
387{
388 u32 ss_cntl;
389
390 if (ASIC_IS_DCE4(rdev)) {
391 switch (pll_id) {
392 case ATOM_PPLL1:
393 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
394 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
395 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
396 break;
397 case ATOM_PPLL2:
398 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
399 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
400 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
401 break;
402 case ATOM_DCPLL:
403 case ATOM_PPLL_INVALID:
404 return;
405 }
406 } else if (ASIC_IS_AVIVO(rdev)) {
407 switch (pll_id) {
408 case ATOM_PPLL1:
409 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
410 ss_cntl &= ~1;
411 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
412 break;
413 case ATOM_PPLL2:
414 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
415 ss_cntl &= ~1;
416 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
417 break;
418 case ATOM_DCPLL:
419 case ATOM_PPLL_INVALID:
420 return;
421 }
422 }
423}
424
425
426union atom_enable_ss {
427 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
428 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
429 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
430 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
431 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
432};
433
434static void atombios_crtc_program_ss(struct radeon_device *rdev,
435 int enable,
436 int pll_id,
437 int crtc_id,
438 struct radeon_atom_ss *ss)
439{
440 unsigned i;
441 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
442 union atom_enable_ss args;
443
444 if (enable) {
445 /* Don't mess with SS if percentage is 0 or external ss.
446 * SS is already disabled previously, and disabling it
447 * again can cause display problems if the pll is already
448 * programmed.
449 */
450 if (ss->percentage == 0)
451 return;
452 if (ss->type & ATOM_EXTERNAL_SS_MASK)
453 return;
454 } else {
455 for (i = 0; i < rdev->num_crtc; i++) {
456 if (rdev->mode_info.crtcs[i] &&
457 rdev->mode_info.crtcs[i]->enabled &&
458 i != crtc_id &&
459 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
460 /* one other crtc is using this pll don't turn
461 * off spread spectrum as it might turn off
462 * display on active crtc
463 */
464 return;
465 }
466 }
467 }
468
469 memset(&args, 0, sizeof(args));
470
471 if (ASIC_IS_DCE5(rdev)) {
472 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
473 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 switch (pll_id) {
475 case ATOM_PPLL1:
476 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
477 break;
478 case ATOM_PPLL2:
479 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
480 break;
481 case ATOM_DCPLL:
482 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
483 break;
484 case ATOM_PPLL_INVALID:
485 return;
486 }
487 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
488 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
489 args.v3.ucEnable = enable;
490 } else if (ASIC_IS_DCE4(rdev)) {
491 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
493 switch (pll_id) {
494 case ATOM_PPLL1:
495 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
496 break;
497 case ATOM_PPLL2:
498 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
499 break;
500 case ATOM_DCPLL:
501 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
502 break;
503 case ATOM_PPLL_INVALID:
504 return;
505 }
506 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
507 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
508 args.v2.ucEnable = enable;
509 } else if (ASIC_IS_DCE3(rdev)) {
510 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
511 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
512 args.v1.ucSpreadSpectrumStep = ss->step;
513 args.v1.ucSpreadSpectrumDelay = ss->delay;
514 args.v1.ucSpreadSpectrumRange = ss->range;
515 args.v1.ucPpll = pll_id;
516 args.v1.ucEnable = enable;
517 } else if (ASIC_IS_AVIVO(rdev)) {
518 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
519 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
520 atombios_disable_ss(rdev, pll_id);
521 return;
522 }
523 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
524 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
525 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
526 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
527 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
528 args.lvds_ss_2.ucEnable = enable;
529 } else {
530 if (enable == ATOM_DISABLE) {
531 atombios_disable_ss(rdev, pll_id);
532 return;
533 }
534 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
535 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
536 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
537 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
538 args.lvds_ss.ucEnable = enable;
539 }
540 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
541}
542
543union adjust_pixel_clock {
544 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
545 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
546};
547
548static u32 atombios_adjust_pll(struct drm_crtc *crtc,
549 struct drm_display_mode *mode)
550{
551 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
552 struct drm_device *dev = crtc->dev;
553 struct radeon_device *rdev = dev->dev_private;
554 struct drm_encoder *encoder = radeon_crtc->encoder;
555 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
556 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
557 u32 adjusted_clock = mode->clock;
558 int encoder_mode = atombios_get_encoder_mode(encoder);
559 u32 dp_clock = mode->clock;
560 int bpc = radeon_crtc->bpc;
561 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
562
563 /* reset the pll flags */
564 radeon_crtc->pll_flags = 0;
565
566 if (ASIC_IS_AVIVO(rdev)) {
567 if ((rdev->family == CHIP_RS600) ||
568 (rdev->family == CHIP_RS690) ||
569 (rdev->family == CHIP_RS740))
570 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
571 RADEON_PLL_PREFER_CLOSEST_LOWER);
572
573 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
574 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
575 else
576 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
577
578 if (rdev->family < CHIP_RV770)
579 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
580 /* use frac fb div on APUs */
581 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
582 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
583 /* use frac fb div on RS780/RS880 */
584 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
585 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
586 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
587 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
588 } else {
589 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
590
591 if (mode->clock > 200000) /* range limits??? */
592 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
593 else
594 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
595 }
596
597 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
598 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
599 if (connector) {
600 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
601 struct radeon_connector_atom_dig *dig_connector =
602 radeon_connector->con_priv;
603
604 dp_clock = dig_connector->dp_clock;
605 }
606 }
607
608 /* use recommended ref_div for ss */
609 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
610 if (radeon_crtc->ss_enabled) {
611 if (radeon_crtc->ss.refdiv) {
612 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
613 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
614 if (ASIC_IS_AVIVO(rdev))
615 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
616 }
617 }
618 }
619
620 if (ASIC_IS_AVIVO(rdev)) {
621 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
622 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
623 adjusted_clock = mode->clock * 2;
624 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
625 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
626 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
627 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
628 } else {
629 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
630 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
631 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
632 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
633 }
634
635 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
636 * accordingly based on the encoder/transmitter to work around
637 * special hw requirements.
638 */
639 if (ASIC_IS_DCE3(rdev)) {
640 union adjust_pixel_clock args;
641 u8 frev, crev;
642 int index;
643
644 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
645 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
646 &crev))
647 return adjusted_clock;
648
649 memset(&args, 0, sizeof(args));
650
651 switch (frev) {
652 case 1:
653 switch (crev) {
654 case 1:
655 case 2:
656 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
657 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
658 args.v1.ucEncodeMode = encoder_mode;
659 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
660 args.v1.ucConfig |=
661 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
662
663 atom_execute_table(rdev->mode_info.atom_context,
664 index, (uint32_t *)&args);
665 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
666 break;
667 case 3:
668 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
669 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
670 args.v3.sInput.ucEncodeMode = encoder_mode;
671 args.v3.sInput.ucDispPllConfig = 0;
672 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
673 args.v3.sInput.ucDispPllConfig |=
674 DISPPLL_CONFIG_SS_ENABLE;
675 if (ENCODER_MODE_IS_DP(encoder_mode)) {
676 args.v3.sInput.ucDispPllConfig |=
677 DISPPLL_CONFIG_COHERENT_MODE;
678 /* 16200 or 27000 */
679 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
680 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
681 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
682 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
683 /* deep color support */
684 args.v3.sInput.usPixelClock =
685 cpu_to_le16((mode->clock * bpc / 8) / 10);
686 if (dig->coherent_mode)
687 args.v3.sInput.ucDispPllConfig |=
688 DISPPLL_CONFIG_COHERENT_MODE;
689 if (is_duallink)
690 args.v3.sInput.ucDispPllConfig |=
691 DISPPLL_CONFIG_DUAL_LINK;
692 }
693 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
694 ENCODER_OBJECT_ID_NONE)
695 args.v3.sInput.ucExtTransmitterID =
696 radeon_encoder_get_dp_bridge_encoder_id(encoder);
697 else
698 args.v3.sInput.ucExtTransmitterID = 0;
699
700 atom_execute_table(rdev->mode_info.atom_context,
701 index, (uint32_t *)&args);
702 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
703 if (args.v3.sOutput.ucRefDiv) {
704 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
705 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
706 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
707 }
708 if (args.v3.sOutput.ucPostDiv) {
709 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
710 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
711 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
712 }
713 break;
714 default:
715 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
716 return adjusted_clock;
717 }
718 break;
719 default:
720 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
721 return adjusted_clock;
722 }
723 }
724 return adjusted_clock;
725}
726
727union set_pixel_clock {
728 SET_PIXEL_CLOCK_PS_ALLOCATION base;
729 PIXEL_CLOCK_PARAMETERS v1;
730 PIXEL_CLOCK_PARAMETERS_V2 v2;
731 PIXEL_CLOCK_PARAMETERS_V3 v3;
732 PIXEL_CLOCK_PARAMETERS_V5 v5;
733 PIXEL_CLOCK_PARAMETERS_V6 v6;
734};
735
736/* on DCE5, make sure the voltage is high enough to support the
737 * required disp clk.
738 */
739static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
740 u32 dispclk)
741{
742 u8 frev, crev;
743 int index;
744 union set_pixel_clock args;
745
746 memset(&args, 0, sizeof(args));
747
748 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
749 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
750 &crev))
751 return;
752
753 switch (frev) {
754 case 1:
755 switch (crev) {
756 case 5:
757 /* if the default dcpll clock is specified,
758 * SetPixelClock provides the dividers
759 */
760 args.v5.ucCRTC = ATOM_CRTC_INVALID;
761 args.v5.usPixelClock = cpu_to_le16(dispclk);
762 args.v5.ucPpll = ATOM_DCPLL;
763 break;
764 case 6:
765 /* if the default dcpll clock is specified,
766 * SetPixelClock provides the dividers
767 */
768 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
769 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
770 args.v6.ucPpll = ATOM_EXT_PLL1;
771 else if (ASIC_IS_DCE6(rdev))
772 args.v6.ucPpll = ATOM_PPLL0;
773 else
774 args.v6.ucPpll = ATOM_DCPLL;
775 break;
776 default:
777 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
778 return;
779 }
780 break;
781 default:
782 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
783 return;
784 }
785 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
786}
787
788static void atombios_crtc_program_pll(struct drm_crtc *crtc,
789 u32 crtc_id,
790 int pll_id,
791 u32 encoder_mode,
792 u32 encoder_id,
793 u32 clock,
794 u32 ref_div,
795 u32 fb_div,
796 u32 frac_fb_div,
797 u32 post_div,
798 int bpc,
799 bool ss_enabled,
800 struct radeon_atom_ss *ss)
801{
802 struct drm_device *dev = crtc->dev;
803 struct radeon_device *rdev = dev->dev_private;
804 u8 frev, crev;
805 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
806 union set_pixel_clock args;
807
808 memset(&args, 0, sizeof(args));
809
810 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
811 &crev))
812 return;
813
814 switch (frev) {
815 case 1:
816 switch (crev) {
817 case 1:
818 if (clock == ATOM_DISABLE)
819 return;
820 args.v1.usPixelClock = cpu_to_le16(clock / 10);
821 args.v1.usRefDiv = cpu_to_le16(ref_div);
822 args.v1.usFbDiv = cpu_to_le16(fb_div);
823 args.v1.ucFracFbDiv = frac_fb_div;
824 args.v1.ucPostDiv = post_div;
825 args.v1.ucPpll = pll_id;
826 args.v1.ucCRTC = crtc_id;
827 args.v1.ucRefDivSrc = 1;
828 break;
829 case 2:
830 args.v2.usPixelClock = cpu_to_le16(clock / 10);
831 args.v2.usRefDiv = cpu_to_le16(ref_div);
832 args.v2.usFbDiv = cpu_to_le16(fb_div);
833 args.v2.ucFracFbDiv = frac_fb_div;
834 args.v2.ucPostDiv = post_div;
835 args.v2.ucPpll = pll_id;
836 args.v2.ucCRTC = crtc_id;
837 args.v2.ucRefDivSrc = 1;
838 break;
839 case 3:
840 args.v3.usPixelClock = cpu_to_le16(clock / 10);
841 args.v3.usRefDiv = cpu_to_le16(ref_div);
842 args.v3.usFbDiv = cpu_to_le16(fb_div);
843 args.v3.ucFracFbDiv = frac_fb_div;
844 args.v3.ucPostDiv = post_div;
845 args.v3.ucPpll = pll_id;
846 if (crtc_id == ATOM_CRTC2)
847 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
848 else
849 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
850 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
851 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
852 args.v3.ucTransmitterId = encoder_id;
853 args.v3.ucEncoderMode = encoder_mode;
854 break;
855 case 5:
856 args.v5.ucCRTC = crtc_id;
857 args.v5.usPixelClock = cpu_to_le16(clock / 10);
858 args.v5.ucRefDiv = ref_div;
859 args.v5.usFbDiv = cpu_to_le16(fb_div);
860 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
861 args.v5.ucPostDiv = post_div;
862 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
863 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
864 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
865 switch (bpc) {
866 case 8:
867 default:
868 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
869 break;
870 case 10:
871 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
872 break;
873 }
874 args.v5.ucTransmitterID = encoder_id;
875 args.v5.ucEncoderMode = encoder_mode;
876 args.v5.ucPpll = pll_id;
877 break;
878 case 6:
879 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
880 args.v6.ucRefDiv = ref_div;
881 args.v6.usFbDiv = cpu_to_le16(fb_div);
882 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
883 args.v6.ucPostDiv = post_div;
884 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
885 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
886 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
887 switch (bpc) {
888 case 8:
889 default:
890 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
891 break;
892 case 10:
893 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
894 break;
895 case 12:
896 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
897 break;
898 case 16:
899 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
900 break;
901 }
902 args.v6.ucTransmitterID = encoder_id;
903 args.v6.ucEncoderMode = encoder_mode;
904 args.v6.ucPpll = pll_id;
905 break;
906 default:
907 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
908 return;
909 }
910 break;
911 default:
912 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
913 return;
914 }
915
916 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
917}
918
919static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
920{
921 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
922 struct drm_device *dev = crtc->dev;
923 struct radeon_device *rdev = dev->dev_private;
924 struct radeon_encoder *radeon_encoder =
925 to_radeon_encoder(radeon_crtc->encoder);
926 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
927
928 radeon_crtc->bpc = 8;
929 radeon_crtc->ss_enabled = false;
930
931 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
932 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
933 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
934 struct drm_connector *connector =
935 radeon_get_connector_for_encoder(radeon_crtc->encoder);
936 struct radeon_connector *radeon_connector =
937 to_radeon_connector(connector);
938 struct radeon_connector_atom_dig *dig_connector =
939 radeon_connector->con_priv;
940 int dp_clock;
941 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
942
943 switch (encoder_mode) {
944 case ATOM_ENCODER_MODE_DP_MST:
945 case ATOM_ENCODER_MODE_DP:
946 /* DP/eDP */
947 dp_clock = dig_connector->dp_clock / 10;
948 if (ASIC_IS_DCE4(rdev))
949 radeon_crtc->ss_enabled =
950 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
951 ASIC_INTERNAL_SS_ON_DP,
952 dp_clock);
953 else {
954 if (dp_clock == 16200) {
955 radeon_crtc->ss_enabled =
956 radeon_atombios_get_ppll_ss_info(rdev,
957 &radeon_crtc->ss,
958 ATOM_DP_SS_ID2);
959 if (!radeon_crtc->ss_enabled)
960 radeon_crtc->ss_enabled =
961 radeon_atombios_get_ppll_ss_info(rdev,
962 &radeon_crtc->ss,
963 ATOM_DP_SS_ID1);
964 } else {
965 radeon_crtc->ss_enabled =
966 radeon_atombios_get_ppll_ss_info(rdev,
967 &radeon_crtc->ss,
968 ATOM_DP_SS_ID1);
969 }
970 /* disable spread spectrum on DCE3 DP */
971 radeon_crtc->ss_enabled = false;
972 }
973 break;
974 case ATOM_ENCODER_MODE_LVDS:
975 if (ASIC_IS_DCE4(rdev))
976 radeon_crtc->ss_enabled =
977 radeon_atombios_get_asic_ss_info(rdev,
978 &radeon_crtc->ss,
979 dig->lcd_ss_id,
980 mode->clock / 10);
981 else
982 radeon_crtc->ss_enabled =
983 radeon_atombios_get_ppll_ss_info(rdev,
984 &radeon_crtc->ss,
985 dig->lcd_ss_id);
986 break;
987 case ATOM_ENCODER_MODE_DVI:
988 if (ASIC_IS_DCE4(rdev))
989 radeon_crtc->ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev,
991 &radeon_crtc->ss,
992 ASIC_INTERNAL_SS_ON_TMDS,
993 mode->clock / 10);
994 break;
995 case ATOM_ENCODER_MODE_HDMI:
996 if (ASIC_IS_DCE4(rdev))
997 radeon_crtc->ss_enabled =
998 radeon_atombios_get_asic_ss_info(rdev,
999 &radeon_crtc->ss,
1000 ASIC_INTERNAL_SS_ON_HDMI,
1001 mode->clock / 10);
1002 break;
1003 default:
1004 break;
1005 }
1006 }
1007
1008 /* adjust pixel clock as needed */
1009 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1010
1011 return true;
1012}
1013
1014static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1015{
1016 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1017 struct drm_device *dev = crtc->dev;
1018 struct radeon_device *rdev = dev->dev_private;
1019 struct radeon_encoder *radeon_encoder =
1020 to_radeon_encoder(radeon_crtc->encoder);
1021 u32 pll_clock = mode->clock;
1022 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1023 struct radeon_pll *pll;
1024 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1025
1026 switch (radeon_crtc->pll_id) {
1027 case ATOM_PPLL1:
1028 pll = &rdev->clock.p1pll;
1029 break;
1030 case ATOM_PPLL2:
1031 pll = &rdev->clock.p2pll;
1032 break;
1033 case ATOM_DCPLL:
1034 case ATOM_PPLL_INVALID:
1035 default:
1036 pll = &rdev->clock.dcpll;
1037 break;
1038 }
1039
1040 /* update pll params */
1041 pll->flags = radeon_crtc->pll_flags;
1042 pll->reference_div = radeon_crtc->pll_reference_div;
1043 pll->post_div = radeon_crtc->pll_post_div;
1044
1045 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1046 /* TV seems to prefer the legacy algo on some boards */
1047 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1048 &fb_div, &frac_fb_div, &ref_div, &post_div);
1049 else if (ASIC_IS_AVIVO(rdev))
1050 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1051 &fb_div, &frac_fb_div, &ref_div, &post_div);
1052 else
1053 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1054 &fb_div, &frac_fb_div, &ref_div, &post_div);
1055
1056 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1057 radeon_crtc->crtc_id, &radeon_crtc->ss);
1058
1059 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1060 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1061 ref_div, fb_div, frac_fb_div, post_div,
1062 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1063
1064 if (radeon_crtc->ss_enabled) {
1065 /* calculate ss amount and step size */
1066 if (ASIC_IS_DCE4(rdev)) {
1067 u32 step_size;
1068 u32 amount = (((fb_div * 10) + frac_fb_div) *
1069 (u32)radeon_crtc->ss.percentage) /
1070 (100 * (u32)radeon_crtc->ss.percentage_divider);
1071 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1072 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1073 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1074 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1075 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1076 (125 * 25 * pll->reference_freq / 100);
1077 else
1078 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1079 (125 * 25 * pll->reference_freq / 100);
1080 radeon_crtc->ss.step = step_size;
1081 }
1082
1083 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1084 radeon_crtc->crtc_id, &radeon_crtc->ss);
1085 }
1086}
1087
1088static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1089 struct drm_framebuffer *fb,
1090 int x, int y, int atomic)
1091{
1092 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1093 struct drm_device *dev = crtc->dev;
1094 struct radeon_device *rdev = dev->dev_private;
1095 struct radeon_framebuffer *radeon_fb;
1096 struct drm_framebuffer *target_fb;
1097 struct drm_gem_object *obj;
1098 struct radeon_bo *rbo;
1099 uint64_t fb_location;
1100 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1101 unsigned bankw, bankh, mtaspect, tile_split;
1102 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1103 u32 tmp, viewport_w, viewport_h;
1104 int r;
1105
1106 /* no fb bound */
1107 if (!atomic && !crtc->primary->fb) {
1108 DRM_DEBUG_KMS("No FB bound\n");
1109 return 0;
1110 }
1111
1112 if (atomic) {
1113 radeon_fb = to_radeon_framebuffer(fb);
1114 target_fb = fb;
1115 }
1116 else {
1117 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1118 target_fb = crtc->primary->fb;
1119 }
1120
1121 /* If atomic, assume fb object is pinned & idle & fenced and
1122 * just update base pointers
1123 */
1124 obj = radeon_fb->obj;
1125 rbo = gem_to_radeon_bo(obj);
1126 r = radeon_bo_reserve(rbo, false);
1127 if (unlikely(r != 0))
1128 return r;
1129
1130 if (atomic)
1131 fb_location = radeon_bo_gpu_offset(rbo);
1132 else {
1133 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1134 if (unlikely(r != 0)) {
1135 radeon_bo_unreserve(rbo);
1136 return -EINVAL;
1137 }
1138 }
1139
1140 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1141 radeon_bo_unreserve(rbo);
1142
1143 switch (target_fb->bits_per_pixel) {
1144 case 8:
1145 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1146 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1147 break;
1148 case 15:
1149 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1150 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1151 break;
1152 case 16:
1153 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1154 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1155#ifdef __BIG_ENDIAN
1156 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1157#endif
1158 break;
1159 case 24:
1160 case 32:
1161 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1162 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1163#ifdef __BIG_ENDIAN
1164 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1165#endif
1166 break;
1167 default:
1168 DRM_ERROR("Unsupported screen depth %d\n",
1169 target_fb->bits_per_pixel);
1170 return -EINVAL;
1171 }
1172
1173 if (tiling_flags & RADEON_TILING_MACRO) {
1174 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1175
1176 /* Set NUM_BANKS. */
1177 if (rdev->family >= CHIP_TAHITI) {
1178 unsigned index, num_banks;
1179
1180 if (rdev->family >= CHIP_BONAIRE) {
1181 unsigned tileb, tile_split_bytes;
1182
1183 /* Calculate the macrotile mode index. */
1184 tile_split_bytes = 64 << tile_split;
1185 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1186 tileb = min(tile_split_bytes, tileb);
1187
1188 for (index = 0; tileb > 64; index++)
1189 tileb >>= 1;
1190
1191 if (index >= 16) {
1192 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1193 target_fb->bits_per_pixel, tile_split);
1194 return -EINVAL;
1195 }
1196
1197 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1198 } else {
1199 switch (target_fb->bits_per_pixel) {
1200 case 8:
1201 index = 10;
1202 break;
1203 case 16:
1204 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1205 break;
1206 default:
1207 case 32:
1208 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1209 break;
1210 }
1211
1212 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1213 }
1214
1215 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1216 } else {
1217 /* NI and older. */
1218 if (rdev->family >= CHIP_CAYMAN)
1219 tmp = rdev->config.cayman.tile_config;
1220 else
1221 tmp = rdev->config.evergreen.tile_config;
1222
1223 switch ((tmp & 0xf0) >> 4) {
1224 case 0: /* 4 banks */
1225 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1226 break;
1227 case 1: /* 8 banks */
1228 default:
1229 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1230 break;
1231 case 2: /* 16 banks */
1232 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1233 break;
1234 }
1235 }
1236
1237 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1238 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1239 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1240 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1241 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1242 if (rdev->family >= CHIP_BONAIRE) {
1243 /* XXX need to know more about the surface tiling mode */
1244 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1245 }
1246 } else if (tiling_flags & RADEON_TILING_MICRO)
1247 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1248
1249 if (rdev->family >= CHIP_BONAIRE) {
1250 /* Read the pipe config from the 2D TILED SCANOUT mode.
1251 * It should be the same for the other modes too, but not all
1252 * modes set the pipe config field. */
1253 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1254
1255 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1256 } else if ((rdev->family == CHIP_TAHITI) ||
1257 (rdev->family == CHIP_PITCAIRN))
1258 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1259 else if ((rdev->family == CHIP_VERDE) ||
1260 (rdev->family == CHIP_OLAND) ||
1261 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1262 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1263
1264 switch (radeon_crtc->crtc_id) {
1265 case 0:
1266 WREG32(AVIVO_D1VGA_CONTROL, 0);
1267 break;
1268 case 1:
1269 WREG32(AVIVO_D2VGA_CONTROL, 0);
1270 break;
1271 case 2:
1272 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1273 break;
1274 case 3:
1275 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1276 break;
1277 case 4:
1278 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1279 break;
1280 case 5:
1281 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1282 break;
1283 default:
1284 break;
1285 }
1286
1287 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1288 upper_32_bits(fb_location));
1289 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1290 upper_32_bits(fb_location));
1291 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1292 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1293 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1294 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1295 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1296 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1297
1298 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1299 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1300 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1301 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1302 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1303 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1304
1305 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1306 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1307 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1308
1309 if (rdev->family >= CHIP_BONAIRE)
1310 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1311 target_fb->height);
1312 else
1313 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1314 target_fb->height);
1315 x &= ~3;
1316 y &= ~1;
1317 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1318 (x << 16) | y);
1319 viewport_w = crtc->mode.hdisplay;
1320 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1321 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1322 (viewport_w << 16) | viewport_h);
1323
1324 /* pageflip setup */
1325 /* make sure flip is at vb rather than hb */
1326 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1327 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1328 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1329
1330 /* set pageflip to happen anywhere in vblank interval */
1331 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1332
1333 if (!atomic && fb && fb != crtc->primary->fb) {
1334 radeon_fb = to_radeon_framebuffer(fb);
1335 rbo = gem_to_radeon_bo(radeon_fb->obj);
1336 r = radeon_bo_reserve(rbo, false);
1337 if (unlikely(r != 0))
1338 return r;
1339 radeon_bo_unpin(rbo);
1340 radeon_bo_unreserve(rbo);
1341 }
1342
1343 /* Bytes per pixel may have changed */
1344 radeon_bandwidth_update(rdev);
1345
1346 return 0;
1347}
1348
1349static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1350 struct drm_framebuffer *fb,
1351 int x, int y, int atomic)
1352{
1353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1354 struct drm_device *dev = crtc->dev;
1355 struct radeon_device *rdev = dev->dev_private;
1356 struct radeon_framebuffer *radeon_fb;
1357 struct drm_gem_object *obj;
1358 struct radeon_bo *rbo;
1359 struct drm_framebuffer *target_fb;
1360 uint64_t fb_location;
1361 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1362 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1363 u32 tmp, viewport_w, viewport_h;
1364 int r;
1365
1366 /* no fb bound */
1367 if (!atomic && !crtc->primary->fb) {
1368 DRM_DEBUG_KMS("No FB bound\n");
1369 return 0;
1370 }
1371
1372 if (atomic) {
1373 radeon_fb = to_radeon_framebuffer(fb);
1374 target_fb = fb;
1375 }
1376 else {
1377 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1378 target_fb = crtc->primary->fb;
1379 }
1380
1381 obj = radeon_fb->obj;
1382 rbo = gem_to_radeon_bo(obj);
1383 r = radeon_bo_reserve(rbo, false);
1384 if (unlikely(r != 0))
1385 return r;
1386
1387 /* If atomic, assume fb object is pinned & idle & fenced and
1388 * just update base pointers
1389 */
1390 if (atomic)
1391 fb_location = radeon_bo_gpu_offset(rbo);
1392 else {
1393 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1394 if (unlikely(r != 0)) {
1395 radeon_bo_unreserve(rbo);
1396 return -EINVAL;
1397 }
1398 }
1399 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1400 radeon_bo_unreserve(rbo);
1401
1402 switch (target_fb->bits_per_pixel) {
1403 case 8:
1404 fb_format =
1405 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1406 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1407 break;
1408 case 15:
1409 fb_format =
1410 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1411 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1412 break;
1413 case 16:
1414 fb_format =
1415 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1416 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1417#ifdef __BIG_ENDIAN
1418 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1419#endif
1420 break;
1421 case 24:
1422 case 32:
1423 fb_format =
1424 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1425 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1426#ifdef __BIG_ENDIAN
1427 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1428#endif
1429 break;
1430 default:
1431 DRM_ERROR("Unsupported screen depth %d\n",
1432 target_fb->bits_per_pixel);
1433 return -EINVAL;
1434 }
1435
1436 if (rdev->family >= CHIP_R600) {
1437 if (tiling_flags & RADEON_TILING_MACRO)
1438 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1439 else if (tiling_flags & RADEON_TILING_MICRO)
1440 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1441 } else {
1442 if (tiling_flags & RADEON_TILING_MACRO)
1443 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1444
1445 if (tiling_flags & RADEON_TILING_MICRO)
1446 fb_format |= AVIVO_D1GRPH_TILED;
1447 }
1448
1449 if (radeon_crtc->crtc_id == 0)
1450 WREG32(AVIVO_D1VGA_CONTROL, 0);
1451 else
1452 WREG32(AVIVO_D2VGA_CONTROL, 0);
1453
1454 if (rdev->family >= CHIP_RV770) {
1455 if (radeon_crtc->crtc_id) {
1456 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1457 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1458 } else {
1459 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1460 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1461 }
1462 }
1463 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1464 (u32) fb_location);
1465 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1466 radeon_crtc->crtc_offset, (u32) fb_location);
1467 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1468 if (rdev->family >= CHIP_R600)
1469 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1470
1471 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1472 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1473 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1474 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1475 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1476 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1477
1478 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1479 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1480 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1481
1482 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1483 target_fb->height);
1484 x &= ~3;
1485 y &= ~1;
1486 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1487 (x << 16) | y);
1488 viewport_w = crtc->mode.hdisplay;
1489 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1490 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1491 (viewport_w << 16) | viewport_h);
1492
1493 /* pageflip setup */
1494 /* make sure flip is at vb rather than hb */
1495 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1496 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1497 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1498
1499 /* set pageflip to happen anywhere in vblank interval */
1500 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1501
1502 if (!atomic && fb && fb != crtc->primary->fb) {
1503 radeon_fb = to_radeon_framebuffer(fb);
1504 rbo = gem_to_radeon_bo(radeon_fb->obj);
1505 r = radeon_bo_reserve(rbo, false);
1506 if (unlikely(r != 0))
1507 return r;
1508 radeon_bo_unpin(rbo);
1509 radeon_bo_unreserve(rbo);
1510 }
1511
1512 /* Bytes per pixel may have changed */
1513 radeon_bandwidth_update(rdev);
1514
1515 return 0;
1516}
1517
1518int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1519 struct drm_framebuffer *old_fb)
1520{
1521 struct drm_device *dev = crtc->dev;
1522 struct radeon_device *rdev = dev->dev_private;
1523
1524 if (ASIC_IS_DCE4(rdev))
1525 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1526 else if (ASIC_IS_AVIVO(rdev))
1527 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1528 else
1529 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1530}
1531
1532int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1533 struct drm_framebuffer *fb,
1534 int x, int y, enum mode_set_atomic state)
1535{
1536 struct drm_device *dev = crtc->dev;
1537 struct radeon_device *rdev = dev->dev_private;
1538
1539 if (ASIC_IS_DCE4(rdev))
1540 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1541 else if (ASIC_IS_AVIVO(rdev))
1542 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1543 else
1544 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1545}
1546
1547/* properly set additional regs when using atombios */
1548static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1549{
1550 struct drm_device *dev = crtc->dev;
1551 struct radeon_device *rdev = dev->dev_private;
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553 u32 disp_merge_cntl;
1554
1555 switch (radeon_crtc->crtc_id) {
1556 case 0:
1557 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1558 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1559 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1560 break;
1561 case 1:
1562 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1563 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1564 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1565 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1566 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1567 break;
1568 }
1569}
1570
1571/**
1572 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1573 *
1574 * @crtc: drm crtc
1575 *
1576 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1577 */
1578static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1579{
1580 struct drm_device *dev = crtc->dev;
1581 struct drm_crtc *test_crtc;
1582 struct radeon_crtc *test_radeon_crtc;
1583 u32 pll_in_use = 0;
1584
1585 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1586 if (crtc == test_crtc)
1587 continue;
1588
1589 test_radeon_crtc = to_radeon_crtc(test_crtc);
1590 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1591 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1592 }
1593 return pll_in_use;
1594}
1595
1596/**
1597 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1598 *
1599 * @crtc: drm crtc
1600 *
1601 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1602 * also in DP mode. For DP, a single PPLL can be used for all DP
1603 * crtcs/encoders.
1604 */
1605static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1606{
1607 struct drm_device *dev = crtc->dev;
1608 struct drm_crtc *test_crtc;
1609 struct radeon_crtc *test_radeon_crtc;
1610
1611 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1612 if (crtc == test_crtc)
1613 continue;
1614 test_radeon_crtc = to_radeon_crtc(test_crtc);
1615 if (test_radeon_crtc->encoder &&
1616 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1617 /* for DP use the same PLL for all */
1618 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1619 return test_radeon_crtc->pll_id;
1620 }
1621 }
1622 return ATOM_PPLL_INVALID;
1623}
1624
1625/**
1626 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1627 *
1628 * @crtc: drm crtc
1629 * @encoder: drm encoder
1630 *
1631 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1632 * be shared (i.e., same clock).
1633 */
1634static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1635{
1636 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1637 struct drm_device *dev = crtc->dev;
1638 struct drm_crtc *test_crtc;
1639 struct radeon_crtc *test_radeon_crtc;
1640 u32 adjusted_clock, test_adjusted_clock;
1641
1642 adjusted_clock = radeon_crtc->adjusted_clock;
1643
1644 if (adjusted_clock == 0)
1645 return ATOM_PPLL_INVALID;
1646
1647 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1648 if (crtc == test_crtc)
1649 continue;
1650 test_radeon_crtc = to_radeon_crtc(test_crtc);
1651 if (test_radeon_crtc->encoder &&
1652 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1653 /* check if we are already driving this connector with another crtc */
1654 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1655 /* if we are, return that pll */
1656 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1657 return test_radeon_crtc->pll_id;
1658 }
1659 /* for non-DP check the clock */
1660 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1661 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1662 (adjusted_clock == test_adjusted_clock) &&
1663 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1664 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1665 return test_radeon_crtc->pll_id;
1666 }
1667 }
1668 return ATOM_PPLL_INVALID;
1669}
1670
1671/**
1672 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1673 *
1674 * @crtc: drm crtc
1675 *
1676 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1677 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1678 * monitors a dedicated PPLL must be used. If a particular board has
1679 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1680 * as there is no need to program the PLL itself. If we are not able to
1681 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1682 * avoid messing up an existing monitor.
1683 *
1684 * Asic specific PLL information
1685 *
1686 * DCE 8.x
1687 * KB/KV
1688 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1689 * CI
1690 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1691 *
1692 * DCE 6.1
1693 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1694 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1695 *
1696 * DCE 6.0
1697 * - PPLL0 is available to all UNIPHY (DP only)
1698 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1699 *
1700 * DCE 5.0
1701 * - DCPLL is available to all UNIPHY (DP only)
1702 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1703 *
1704 * DCE 3.0/4.0/4.1
1705 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1706 *
1707 */
1708static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1709{
1710 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1711 struct drm_device *dev = crtc->dev;
1712 struct radeon_device *rdev = dev->dev_private;
1713 struct radeon_encoder *radeon_encoder =
1714 to_radeon_encoder(radeon_crtc->encoder);
1715 u32 pll_in_use;
1716 int pll;
1717
1718 if (ASIC_IS_DCE8(rdev)) {
1719 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1720 if (rdev->clock.dp_extclk)
1721 /* skip PPLL programming if using ext clock */
1722 return ATOM_PPLL_INVALID;
1723 else {
1724 /* use the same PPLL for all DP monitors */
1725 pll = radeon_get_shared_dp_ppll(crtc);
1726 if (pll != ATOM_PPLL_INVALID)
1727 return pll;
1728 }
1729 } else {
1730 /* use the same PPLL for all monitors with the same clock */
1731 pll = radeon_get_shared_nondp_ppll(crtc);
1732 if (pll != ATOM_PPLL_INVALID)
1733 return pll;
1734 }
1735 /* otherwise, pick one of the plls */
1736 if ((rdev->family == CHIP_KAVERI) ||
1737 (rdev->family == CHIP_KABINI) ||
1738 (rdev->family == CHIP_MULLINS)) {
1739 /* KB/KV/ML has PPLL1 and PPLL2 */
1740 pll_in_use = radeon_get_pll_use_mask(crtc);
1741 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1742 return ATOM_PPLL2;
1743 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1744 return ATOM_PPLL1;
1745 DRM_ERROR("unable to allocate a PPLL\n");
1746 return ATOM_PPLL_INVALID;
1747 } else {
1748 /* CI has PPLL0, PPLL1, and PPLL2 */
1749 pll_in_use = radeon_get_pll_use_mask(crtc);
1750 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1751 return ATOM_PPLL2;
1752 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1753 return ATOM_PPLL1;
1754 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1755 return ATOM_PPLL0;
1756 DRM_ERROR("unable to allocate a PPLL\n");
1757 return ATOM_PPLL_INVALID;
1758 }
1759 } else if (ASIC_IS_DCE61(rdev)) {
1760 struct radeon_encoder_atom_dig *dig =
1761 radeon_encoder->enc_priv;
1762
1763 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1764 (dig->linkb == false))
1765 /* UNIPHY A uses PPLL2 */
1766 return ATOM_PPLL2;
1767 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1768 /* UNIPHY B/C/D/E/F */
1769 if (rdev->clock.dp_extclk)
1770 /* skip PPLL programming if using ext clock */
1771 return ATOM_PPLL_INVALID;
1772 else {
1773 /* use the same PPLL for all DP monitors */
1774 pll = radeon_get_shared_dp_ppll(crtc);
1775 if (pll != ATOM_PPLL_INVALID)
1776 return pll;
1777 }
1778 } else {
1779 /* use the same PPLL for all monitors with the same clock */
1780 pll = radeon_get_shared_nondp_ppll(crtc);
1781 if (pll != ATOM_PPLL_INVALID)
1782 return pll;
1783 }
1784 /* UNIPHY B/C/D/E/F */
1785 pll_in_use = radeon_get_pll_use_mask(crtc);
1786 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1787 return ATOM_PPLL0;
1788 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1789 return ATOM_PPLL1;
1790 DRM_ERROR("unable to allocate a PPLL\n");
1791 return ATOM_PPLL_INVALID;
1792 } else if (ASIC_IS_DCE41(rdev)) {
1793 /* Don't share PLLs on DCE4.1 chips */
1794 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1795 if (rdev->clock.dp_extclk)
1796 /* skip PPLL programming if using ext clock */
1797 return ATOM_PPLL_INVALID;
1798 }
1799 pll_in_use = radeon_get_pll_use_mask(crtc);
1800 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1801 return ATOM_PPLL1;
1802 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1803 return ATOM_PPLL2;
1804 DRM_ERROR("unable to allocate a PPLL\n");
1805 return ATOM_PPLL_INVALID;
1806 } else if (ASIC_IS_DCE4(rdev)) {
1807 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1808 * depending on the asic:
1809 * DCE4: PPLL or ext clock
1810 * DCE5: PPLL, DCPLL, or ext clock
1811 * DCE6: PPLL, PPLL0, or ext clock
1812 *
1813 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1814 * PPLL/DCPLL programming and only program the DP DTO for the
1815 * crtc virtual pixel clock.
1816 */
1817 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1818 if (rdev->clock.dp_extclk)
1819 /* skip PPLL programming if using ext clock */
1820 return ATOM_PPLL_INVALID;
1821 else if (ASIC_IS_DCE6(rdev))
1822 /* use PPLL0 for all DP */
1823 return ATOM_PPLL0;
1824 else if (ASIC_IS_DCE5(rdev))
1825 /* use DCPLL for all DP */
1826 return ATOM_DCPLL;
1827 else {
1828 /* use the same PPLL for all DP monitors */
1829 pll = radeon_get_shared_dp_ppll(crtc);
1830 if (pll != ATOM_PPLL_INVALID)
1831 return pll;
1832 }
1833 } else {
1834 /* use the same PPLL for all monitors with the same clock */
1835 pll = radeon_get_shared_nondp_ppll(crtc);
1836 if (pll != ATOM_PPLL_INVALID)
1837 return pll;
1838 }
1839 /* all other cases */
1840 pll_in_use = radeon_get_pll_use_mask(crtc);
1841 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1842 return ATOM_PPLL1;
1843 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1844 return ATOM_PPLL2;
1845 DRM_ERROR("unable to allocate a PPLL\n");
1846 return ATOM_PPLL_INVALID;
1847 } else {
1848 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1849 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1850 * the matching btw pll and crtc is done through
1851 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1852 * pll (1 or 2) to select which register to write. ie if using
1853 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1854 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1855 * choose which value to write. Which is reverse order from
1856 * register logic. So only case that works is when pllid is
1857 * same as crtcid or when both pll and crtc are enabled and
1858 * both use same clock.
1859 *
1860 * So just return crtc id as if crtc and pll were hard linked
1861 * together even if they aren't
1862 */
1863 return radeon_crtc->crtc_id;
1864 }
1865}
1866
1867void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1868{
1869 /* always set DCPLL */
1870 if (ASIC_IS_DCE6(rdev))
1871 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1872 else if (ASIC_IS_DCE4(rdev)) {
1873 struct radeon_atom_ss ss;
1874 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1875 ASIC_INTERNAL_SS_ON_DCPLL,
1876 rdev->clock.default_dispclk);
1877 if (ss_enabled)
1878 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1879 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1880 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1881 if (ss_enabled)
1882 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1883 }
1884
1885}
1886
1887int atombios_crtc_mode_set(struct drm_crtc *crtc,
1888 struct drm_display_mode *mode,
1889 struct drm_display_mode *adjusted_mode,
1890 int x, int y, struct drm_framebuffer *old_fb)
1891{
1892 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1893 struct drm_device *dev = crtc->dev;
1894 struct radeon_device *rdev = dev->dev_private;
1895 struct radeon_encoder *radeon_encoder =
1896 to_radeon_encoder(radeon_crtc->encoder);
1897 bool is_tvcv = false;
1898
1899 if (radeon_encoder->active_device &
1900 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1901 is_tvcv = true;
1902
1903 if (!radeon_crtc->adjusted_clock)
1904 return -EINVAL;
1905
1906 atombios_crtc_set_pll(crtc, adjusted_mode);
1907
1908 if (ASIC_IS_DCE4(rdev))
1909 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1910 else if (ASIC_IS_AVIVO(rdev)) {
1911 if (is_tvcv)
1912 atombios_crtc_set_timing(crtc, adjusted_mode);
1913 else
1914 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1915 } else {
1916 atombios_crtc_set_timing(crtc, adjusted_mode);
1917 if (radeon_crtc->crtc_id == 0)
1918 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1919 radeon_legacy_atom_fixup(crtc);
1920 }
1921 atombios_crtc_set_base(crtc, x, y, old_fb);
1922 atombios_overscan_setup(crtc, mode, adjusted_mode);
1923 atombios_scaler_setup(crtc);
1924 /* update the hw version fpr dpm */
1925 radeon_crtc->hw_mode = *adjusted_mode;
1926
1927 return 0;
1928}
1929
1930static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1931 const struct drm_display_mode *mode,
1932 struct drm_display_mode *adjusted_mode)
1933{
1934 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1935 struct drm_device *dev = crtc->dev;
1936 struct drm_encoder *encoder;
1937
1938 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1939 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1940 if (encoder->crtc == crtc) {
1941 radeon_crtc->encoder = encoder;
1942 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1943 break;
1944 }
1945 }
1946 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1947 radeon_crtc->encoder = NULL;
1948 radeon_crtc->connector = NULL;
1949 return false;
1950 }
1951 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1952 return false;
1953 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1954 return false;
1955 /* pick pll */
1956 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1957 /* if we can't get a PPLL for a non-DP encoder, fail */
1958 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1959 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1960 return false;
1961
1962 return true;
1963}
1964
1965static void atombios_crtc_prepare(struct drm_crtc *crtc)
1966{
1967 struct drm_device *dev = crtc->dev;
1968 struct radeon_device *rdev = dev->dev_private;
1969
1970 /* disable crtc pair power gating before programming */
1971 if (ASIC_IS_DCE6(rdev))
1972 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1973
1974 atombios_lock_crtc(crtc, ATOM_ENABLE);
1975 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1976}
1977
1978static void atombios_crtc_commit(struct drm_crtc *crtc)
1979{
1980 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1981 atombios_lock_crtc(crtc, ATOM_DISABLE);
1982}
1983
1984static void atombios_crtc_disable(struct drm_crtc *crtc)
1985{
1986 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1987 struct drm_device *dev = crtc->dev;
1988 struct radeon_device *rdev = dev->dev_private;
1989 struct radeon_atom_ss ss;
1990 int i;
1991
1992 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1993 if (crtc->primary->fb) {
1994 int r;
1995 struct radeon_framebuffer *radeon_fb;
1996 struct radeon_bo *rbo;
1997
1998 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1999 rbo = gem_to_radeon_bo(radeon_fb->obj);
2000 r = radeon_bo_reserve(rbo, false);
2001 if (unlikely(r))
2002 DRM_ERROR("failed to reserve rbo before unpin\n");
2003 else {
2004 radeon_bo_unpin(rbo);
2005 radeon_bo_unreserve(rbo);
2006 }
2007 }
2008 /* disable the GRPH */
2009 if (ASIC_IS_DCE4(rdev))
2010 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2011 else if (ASIC_IS_AVIVO(rdev))
2012 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2013
2014 if (ASIC_IS_DCE6(rdev))
2015 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2016
2017 for (i = 0; i < rdev->num_crtc; i++) {
2018 if (rdev->mode_info.crtcs[i] &&
2019 rdev->mode_info.crtcs[i]->enabled &&
2020 i != radeon_crtc->crtc_id &&
2021 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2022 /* one other crtc is using this pll don't turn
2023 * off the pll
2024 */
2025 goto done;
2026 }
2027 }
2028
2029 switch (radeon_crtc->pll_id) {
2030 case ATOM_PPLL1:
2031 case ATOM_PPLL2:
2032 /* disable the ppll */
2033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2034 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2035 break;
2036 case ATOM_PPLL0:
2037 /* disable the ppll */
2038 if ((rdev->family == CHIP_ARUBA) ||
2039 (rdev->family == CHIP_BONAIRE) ||
2040 (rdev->family == CHIP_HAWAII))
2041 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2042 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2043 break;
2044 default:
2045 break;
2046 }
2047done:
2048 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2049 radeon_crtc->adjusted_clock = 0;
2050 radeon_crtc->encoder = NULL;
2051 radeon_crtc->connector = NULL;
2052}
2053
2054static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2055 .dpms = atombios_crtc_dpms,
2056 .mode_fixup = atombios_crtc_mode_fixup,
2057 .mode_set = atombios_crtc_mode_set,
2058 .mode_set_base = atombios_crtc_set_base,
2059 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2060 .prepare = atombios_crtc_prepare,
2061 .commit = atombios_crtc_commit,
2062 .load_lut = radeon_crtc_load_lut,
2063 .disable = atombios_crtc_disable,
2064};
2065
2066void radeon_atombios_init_crtc(struct drm_device *dev,
2067 struct radeon_crtc *radeon_crtc)
2068{
2069 struct radeon_device *rdev = dev->dev_private;
2070
2071 if (ASIC_IS_DCE4(rdev)) {
2072 switch (radeon_crtc->crtc_id) {
2073 case 0:
2074 default:
2075 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2076 break;
2077 case 1:
2078 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2079 break;
2080 case 2:
2081 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2082 break;
2083 case 3:
2084 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2085 break;
2086 case 4:
2087 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2088 break;
2089 case 5:
2090 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2091 break;
2092 }
2093 } else {
2094 if (radeon_crtc->crtc_id == 1)
2095 radeon_crtc->crtc_offset =
2096 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2097 else
2098 radeon_crtc->crtc_offset = 0;
2099 }
2100 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2101 radeon_crtc->adjusted_clock = 0;
2102 radeon_crtc->encoder = NULL;
2103 radeon_crtc->connector = NULL;
2104 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2105}