1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * arch/arm/mm/proc-v7-2level.S
  4 *
  5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
  6 */
  7
  8#define TTB_S		(1 << 1)
  9#define TTB_RGN_NC	(0 << 3)
 10#define TTB_RGN_OC_WBWA	(1 << 3)
 11#define TTB_RGN_OC_WT	(2 << 3)
 12#define TTB_RGN_OC_WB	(3 << 3)
 13#define TTB_NOS		(1 << 5)
 14#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
 15#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
 16#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 17#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 18
 19/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 20#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
 21#define PMD_FLAGS_UP	PMD_SECT_WB
 22
 23/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
 24#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 25#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 26
 27.arch armv7-a
 28
 29/*
 30 *	cpu_v7_switch_mm(pgd_phys, tsk)
 31 *
 32 *	Set the translation table base pointer to be pgd_phys
 33 *
 34 *	- pgd_phys - physical address of new TTB
 35 *
 36 *	It is assumed that:
 37 *	- we are not using split page tables
 38 *
 39 *	Note that we always need to flush BTAC/BTB if IBE is set
 40 *	even on Cortex-A8 revisions not affected by 430973.
 41 *	If IBE is not set, the flush BTAC/BTB won't do anything.
 42 */
 43ENTRY(cpu_v7_switch_mm)
 44#ifdef CONFIG_MMU
 45	mmid	r1, r1				@ get mm->context.id
 46	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
 47	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
 48#ifdef CONFIG_PID_IN_CONTEXTIDR
 49	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID
 50	lsr	r2, r2, #8			@ extract the PID
 51	bfi	r1, r2, #8, #24			@ insert into new context ID
 52#endif
 53#ifdef CONFIG_ARM_ERRATA_754322
 54	dsb
 55#endif
 56	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
 57	isb
 58	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
 59	isb
 60#endif
 61	bx	lr
 62ENDPROC(cpu_v7_switch_mm)
 63
 64/*
 65 *	cpu_v7_set_pte_ext(ptep, pte)
 66 *
 67 *	Set a level 2 translation table entry.
 68 *
 69 *	- ptep  - pointer to level 2 translation table entry
 70 *		  (hardware version is stored at +2048 bytes)
 71 *	- pte   - PTE value to store
 72 *	- ext	- value for extended PTE bits
 73 */
 74ENTRY(cpu_v7_set_pte_ext)
 75#ifdef CONFIG_MMU
 76	str	r1, [r0]			@ linux version
 77
 78	bic	r3, r1, #0x000003f0
 79	bic	r3, r3, #PTE_TYPE_MASK
 80	orr	r3, r3, r2
 81	orr	r3, r3, #PTE_EXT_AP0 | 2
 82
 83	tst	r1, #1 << 4
 84	orrne	r3, r3, #PTE_EXT_TEX(1)
 85
 86	eor	r1, r1, #L_PTE_DIRTY
 87	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
 88	orrne	r3, r3, #PTE_EXT_APX
 89
 90	tst	r1, #L_PTE_USER
 91	orrne	r3, r3, #PTE_EXT_AP1
 92
 93	tst	r1, #L_PTE_XN
 94	orrne	r3, r3, #PTE_EXT_XN
 95
 96	tst	r1, #L_PTE_YOUNG
 97	tstne	r1, #L_PTE_VALID
 98	eorne	r1, r1, #L_PTE_NONE
 99	tstne	r1, #L_PTE_NONE
100	moveq	r3, #0
101
102 ARM(	str	r3, [r0, #2048]! )
103 THUMB(	add	r0, r0, #2048 )
104 THUMB(	str	r3, [r0] )
105	ALT_SMP(W(nop))
106	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
107#endif
108	bx	lr
109ENDPROC(cpu_v7_set_pte_ext)
110
111	/*
112	 * Memory region attributes with SCTLR.TRE=1
113	 *
114	 *   n = TEX[0],C,B
115	 *   TR = PRRR[2n+1:2n]		- memory type
116	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
117	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
118	 *
119	 *			n	TR	IR	OR
120	 *   UNCACHED		000	00
121	 *   BUFFERABLE		001	10	00	00
122	 *   WRITETHROUGH	010	10	10	10
123	 *   WRITEBACK		011	10	11	11
124	 *   reserved		110
125	 *   WRITEALLOC		111	10	01	01
126	 *   DEV_SHARED		100	01
127	 *   DEV_NONSHARED	100	01
128	 *   DEV_WC		001	10
129	 *   DEV_CACHED		011	10
130	 *
131	 * Other attributes:
132	 *
133	 *   DS0 = PRRR[16] = 0		- device shareable property
134	 *   DS1 = PRRR[17] = 1		- device shareable property
135	 *   NS0 = PRRR[18] = 0		- normal shareable property
136	 *   NS1 = PRRR[19] = 1		- normal shareable property
137	 *   NOS = PRRR[24+n] = 1	- not outer shareable
138	 */
139.equ	PRRR,	0xff0a81a8
140.equ	NMRR,	0x40e040e0
141
142	/*
143	 * Macro for setting up the TTBRx and TTBCR registers.
144	 * - \ttb0 and \ttb1 updated with the corresponding flags.
145	 */
146	.macro	v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
147	mcr	p15, 0, \zero, c2, c0, 2	@ TTB control register
148	ALT_SMP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
149	ALT_UP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
150	ALT_SMP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_SMP)
151	ALT_UP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_UP)
152	mcr	p15, 0, \ttbr1, c2, c0, 1	@ load TTB1
153	.endm
154
155	/*   AT
156	 *  TFR   EV X F   I D LR    S
157	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
158	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
159	 *   01    0 110       0011 1100 .111 1101 < we want
160	 */
161	.align	2
162	.type	v7_crval, #object
163v7_crval:
164	crval	clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c