1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * arch/arm/mm/proc-v7-2level.S
  4 *
  5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
  6 */
  7
  8#define TTB_S		(1 << 1)
  9#define TTB_RGN_NC	(0 << 3)
 10#define TTB_RGN_OC_WBWA	(1 << 3)
 11#define TTB_RGN_OC_WT	(2 << 3)
 12#define TTB_RGN_OC_WB	(3 << 3)
 13#define TTB_NOS		(1 << 5)
 14#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
 15#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
 16#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 17#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 18
 19/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 20#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
 21#define PMD_FLAGS_UP	PMD_SECT_WB
 22
 23/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
 24#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 25#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 26
 27/*
 28 *	cpu_v7_switch_mm(pgd_phys, tsk)
 29 *
 30 *	Set the translation table base pointer to be pgd_phys
 31 *
 32 *	- pgd_phys - physical address of new TTB
 33 *
 34 *	It is assumed that:
 35 *	- we are not using split page tables
 36 *
 37 *	Note that we always need to flush BTAC/BTB if IBE is set
 38 *	even on Cortex-A8 revisions not affected by 430973.
 39 *	If IBE is not set, the flush BTAC/BTB won't do anything.
 40 */
 41ENTRY(cpu_v7_switch_mm)
 42#ifdef CONFIG_MMU
 43	mmid	r1, r1				@ get mm->context.id
 44	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
 45	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
 46#ifdef CONFIG_PID_IN_CONTEXTIDR
 47	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID
 48	lsr	r2, r2, #8			@ extract the PID
 49	bfi	r1, r2, #8, #24			@ insert into new context ID
 50#endif
 51#ifdef CONFIG_ARM_ERRATA_754322
 52	dsb
 53#endif
 54	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
 55	isb
 56	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
 57	isb
 58#endif
 59	bx	lr
 60ENDPROC(cpu_v7_switch_mm)
 61
 62/*
 63 *	cpu_v7_set_pte_ext(ptep, pte)
 64 *
 65 *	Set a level 2 translation table entry.
 66 *
 67 *	- ptep  - pointer to level 2 translation table entry
 68 *		  (hardware version is stored at +2048 bytes)
 69 *	- pte   - PTE value to store
 70 *	- ext	- value for extended PTE bits
 71 */
 72ENTRY(cpu_v7_set_pte_ext)
 73#ifdef CONFIG_MMU
 74	str	r1, [r0]			@ linux version
 75
 76	bic	r3, r1, #0x000003f0
 77	bic	r3, r3, #PTE_TYPE_MASK
 78	orr	r3, r3, r2
 79	orr	r3, r3, #PTE_EXT_AP0 | 2
 80
 81	tst	r1, #1 << 4
 82	orrne	r3, r3, #PTE_EXT_TEX(1)
 83
 84	eor	r1, r1, #L_PTE_DIRTY
 85	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
 86	orrne	r3, r3, #PTE_EXT_APX
 87
 88	tst	r1, #L_PTE_USER
 89	orrne	r3, r3, #PTE_EXT_AP1
 90
 91	tst	r1, #L_PTE_XN
 92	orrne	r3, r3, #PTE_EXT_XN
 93
 94	tst	r1, #L_PTE_YOUNG
 95	tstne	r1, #L_PTE_VALID
 96	eorne	r1, r1, #L_PTE_NONE
 97	tstne	r1, #L_PTE_NONE
 98	moveq	r3, #0
 99
100 ARM(	str	r3, [r0, #2048]! )
101 THUMB(	add	r0, r0, #2048 )
102 THUMB(	str	r3, [r0] )
103	ALT_SMP(W(nop))
104	ALT_UP (mcr	p15, 0, r0, c7, c10, 1)		@ flush_pte
105#endif
106	bx	lr
107ENDPROC(cpu_v7_set_pte_ext)
108
109	/*
110	 * Memory region attributes with SCTLR.TRE=1
111	 *
112	 *   n = TEX[0],C,B
113	 *   TR = PRRR[2n+1:2n]		- memory type
114	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
115	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
116	 *
117	 *			n	TR	IR	OR
118	 *   UNCACHED		000	00
119	 *   BUFFERABLE		001	10	00	00
120	 *   WRITETHROUGH	010	10	10	10
121	 *   WRITEBACK		011	10	11	11
122	 *   reserved		110
123	 *   WRITEALLOC		111	10	01	01
124	 *   DEV_SHARED		100	01
125	 *   DEV_NONSHARED	100	01
126	 *   DEV_WC		001	10
127	 *   DEV_CACHED		011	10
128	 *
129	 * Other attributes:
130	 *
131	 *   DS0 = PRRR[16] = 0		- device shareable property
132	 *   DS1 = PRRR[17] = 1		- device shareable property
133	 *   NS0 = PRRR[18] = 0		- normal shareable property
134	 *   NS1 = PRRR[19] = 1		- normal shareable property
135	 *   NOS = PRRR[24+n] = 1	- not outer shareable
136	 */
137.equ	PRRR,	0xff0a81a8
138.equ	NMRR,	0x40e040e0
139
140	/*
141	 * Macro for setting up the TTBRx and TTBCR registers.
142	 * - \ttb0 and \ttb1 updated with the corresponding flags.
143	 */
144	.macro	v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp
145	mcr	p15, 0, \zero, c2, c0, 2	@ TTB control register
146	ALT_SMP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
147	ALT_UP(orr	\ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
148	ALT_SMP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_SMP)
149	ALT_UP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_UP)
150	mcr	p15, 0, \ttbr1, c2, c0, 1	@ load TTB1
151	.endm
152
153	/*   AT
154	 *  TFR   EV X F   I D LR    S
155	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
156	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
157	 *   01    0 110       0011 1100 .111 1101 < we want
158	 */
159	.align	2
160	.type	v7_crval, #object
161v7_crval:
162	crval	clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c