1/*
  2 * arch/arm/mm/proc-v7-2level.S
  3 *
  4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10
 11#define TTB_S		(1 << 1)
 12#define TTB_RGN_NC	(0 << 3)
 13#define TTB_RGN_OC_WBWA	(1 << 3)
 14#define TTB_RGN_OC_WT	(2 << 3)
 15#define TTB_RGN_OC_WB	(3 << 3)
 16#define TTB_NOS		(1 << 5)
 17#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
 18#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
 19#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 20#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 21
 22/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
 23#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
 24#define PMD_FLAGS_UP	PMD_SECT_WB
 25
 26/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
 27#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
 28#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 29
 30/*
 31 *	cpu_v7_switch_mm(pgd_phys, tsk)
 32 *
 33 *	Set the translation table base pointer to be pgd_phys
 34 *
 35 *	- pgd_phys - physical address of new TTB
 36 *
 37 *	It is assumed that:
 38 *	- we are not using split page tables
 39 */
 40ENTRY(cpu_v7_switch_mm)
 41#ifdef CONFIG_MMU
 42	mov	r2, #0
 43	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
 44	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
 45	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
 46#ifdef CONFIG_ARM_ERRATA_430973
 47	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 48#endif
 49#ifdef CONFIG_ARM_ERRATA_754322
 50	dsb
 51#endif
 52	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
 53	isb
 54	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
 55	isb
 56#endif
 57	mov	pc, lr
 58ENDPROC(cpu_v7_switch_mm)
 59
 60/*
 61 *	cpu_v7_set_pte_ext(ptep, pte)
 62 *
 63 *	Set a level 2 translation table entry.
 64 *
 65 *	- ptep  - pointer to level 2 translation table entry
 66 *		  (hardware version is stored at +2048 bytes)
 67 *	- pte   - PTE value to store
 68 *	- ext	- value for extended PTE bits
 69 */
 70ENTRY(cpu_v7_set_pte_ext)
 71#ifdef CONFIG_MMU
 72	str	r1, [r0]			@ linux version
 73
 74	bic	r3, r1, #0x000003f0
 75	bic	r3, r3, #PTE_TYPE_MASK
 76	orr	r3, r3, r2
 77	orr	r3, r3, #PTE_EXT_AP0 | 2
 78
 79	tst	r1, #1 << 4
 80	orrne	r3, r3, #PTE_EXT_TEX(1)
 81
 82	eor	r1, r1, #L_PTE_DIRTY
 83	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
 84	orrne	r3, r3, #PTE_EXT_APX
 85
 86	tst	r1, #L_PTE_USER
 87	orrne	r3, r3, #PTE_EXT_AP1
 88#ifdef CONFIG_CPU_USE_DOMAINS
 89	@ allow kernel read/write access to read-only user pages
 90	tstne	r3, #PTE_EXT_APX
 91	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
 92#endif
 93
 94	tst	r1, #L_PTE_XN
 95	orrne	r3, r3, #PTE_EXT_XN
 96
 97	tst	r1, #L_PTE_YOUNG
 98	tstne	r1, #L_PTE_PRESENT
 99	moveq	r3, #0
100
101 ARM(	str	r3, [r0, #2048]! )
102 THUMB(	add	r0, r0, #2048 )
103 THUMB(	str	r3, [r0] )
104	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
105#endif
106	mov	pc, lr
107ENDPROC(cpu_v7_set_pte_ext)
108
109	/*
110	 * Memory region attributes with SCTLR.TRE=1
111	 *
112	 *   n = TEX[0],C,B
113	 *   TR = PRRR[2n+1:2n]		- memory type
114	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
115	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
116	 *
117	 *			n	TR	IR	OR
118	 *   UNCACHED		000	00
119	 *   BUFFERABLE		001	10	00	00
120	 *   WRITETHROUGH	010	10	10	10
121	 *   WRITEBACK		011	10	11	11
122	 *   reserved		110
123	 *   WRITEALLOC		111	10	01	01
124	 *   DEV_SHARED		100	01
125	 *   DEV_NONSHARED	100	01
126	 *   DEV_WC		001	10
127	 *   DEV_CACHED		011	10
128	 *
129	 * Other attributes:
130	 *
131	 *   DS0 = PRRR[16] = 0		- device shareable property
132	 *   DS1 = PRRR[17] = 1		- device shareable property
133	 *   NS0 = PRRR[18] = 0		- normal shareable property
134	 *   NS1 = PRRR[19] = 1		- normal shareable property
135	 *   NOS = PRRR[24+n] = 1	- not outer shareable
136	 */
137.equ	PRRR,	0xff0a81a8
138.equ	NMRR,	0x40e040e0
139
140	/*
141	 * Macro for setting up the TTBRx and TTBCR registers.
142	 * - \ttb0 and \ttb1 updated with the corresponding flags.
143	 */
144	.macro	v7_ttb_setup, zero, ttbr0, ttbr1, tmp
145	mcr	p15, 0, \zero, c2, c0, 2	@ TTB control register
146	ALT_SMP(orr	\ttbr0, \ttbr0, #TTB_FLAGS_SMP)
147	ALT_UP(orr	\ttbr0, \ttbr0, #TTB_FLAGS_UP)
148	ALT_SMP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_SMP)
149	ALT_UP(orr	\ttbr1, \ttbr1, #TTB_FLAGS_UP)
150	mcr	p15, 0, \ttbr1, c2, c0, 1	@ load TTB1
151	.endm
152
153	__CPUINIT
154
155	/*   AT
156	 *  TFR   EV X F   I D LR    S
157	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
158	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
159	 *    1    0 110       0011 1100 .111 1101 < we want
160	 */
161	.align	2
162	.type	v7_crval, #object
163v7_crval:
164	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
165
166	.previous