Loading...
1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include "pci.h"
29
30struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39};
40
41#define free_list(type, head) do { \
42 struct type *list, *tmp; \
43 for (list = (head)->next; list;) { \
44 tmp = list; \
45 list = list->next; \
46 kfree(tmp); \
47 } \
48 (head)->next = NULL; \
49} while (0)
50
51int pci_realloc_enable = 0;
52#define pci_realloc_enabled() pci_realloc_enable
53void pci_realloc(void)
54{
55 pci_realloc_enable = 1;
56}
57
58/**
59 * add_to_list() - add a new resource tracker to the list
60 * @head: Head of the list
61 * @dev: device corresponding to which the resource
62 * belongs
63 * @res: The resource to be tracked
64 * @add_size: additional size to be optionally added
65 * to the resource
66 */
67static void add_to_list(struct resource_list_x *head,
68 struct pci_dev *dev, struct resource *res,
69 resource_size_t add_size, resource_size_t min_align)
70{
71 struct resource_list_x *list = head;
72 struct resource_list_x *ln = list->next;
73 struct resource_list_x *tmp;
74
75 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
76 if (!tmp) {
77 pr_warning("add_to_list: kmalloc() failed!\n");
78 return;
79 }
80
81 tmp->next = ln;
82 tmp->res = res;
83 tmp->dev = dev;
84 tmp->start = res->start;
85 tmp->end = res->end;
86 tmp->flags = res->flags;
87 tmp->add_size = add_size;
88 tmp->min_align = min_align;
89 list->next = tmp;
90}
91
92static void add_to_failed_list(struct resource_list_x *head,
93 struct pci_dev *dev, struct resource *res)
94{
95 add_to_list(head, dev, res,
96 0 /* dont care */,
97 0 /* dont care */);
98}
99
100static void __dev_sort_resources(struct pci_dev *dev,
101 struct resource_list *head)
102{
103 u16 class = dev->class >> 8;
104
105 /* Don't touch classless devices or host bridges or ioapics. */
106 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
107 return;
108
109 /* Don't touch ioapic devices already enabled by firmware */
110 if (class == PCI_CLASS_SYSTEM_PIC) {
111 u16 command;
112 pci_read_config_word(dev, PCI_COMMAND, &command);
113 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
114 return;
115 }
116
117 pdev_sort_resources(dev, head);
118}
119
120static inline void reset_resource(struct resource *res)
121{
122 res->start = 0;
123 res->end = 0;
124 res->flags = 0;
125}
126
127/**
128 * reassign_resources_sorted() - satisfy any additional resource requests
129 *
130 * @realloc_head : head of the list tracking requests requiring additional
131 * resources
132 * @head : head of the list tracking requests with allocated
133 * resources
134 *
135 * Walk through each element of the realloc_head and try to procure
136 * additional resources for the element, provided the element
137 * is in the head list.
138 */
139static void reassign_resources_sorted(struct resource_list_x *realloc_head,
140 struct resource_list *head)
141{
142 struct resource *res;
143 struct resource_list_x *list, *tmp, *prev;
144 struct resource_list *hlist;
145 resource_size_t add_size;
146 int idx;
147
148 prev = realloc_head;
149 for (list = realloc_head->next; list;) {
150 res = list->res;
151 /* skip resource that has been reset */
152 if (!res->flags)
153 goto out;
154
155 /* skip this resource if not found in head list */
156 for (hlist = head->next; hlist && hlist->res != res;
157 hlist = hlist->next);
158 if (!hlist) { /* just skip */
159 prev = list;
160 list = list->next;
161 continue;
162 }
163
164 idx = res - &list->dev->resource[0];
165 add_size=list->add_size;
166 if (!resource_size(res)) {
167 res->start = list->start;
168 res->end = res->start + add_size - 1;
169 if(pci_assign_resource(list->dev, idx))
170 reset_resource(res);
171 } else {
172 resource_size_t align = list->min_align;
173 res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
174 if (pci_reassign_resource(list->dev, idx, add_size, align))
175 dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n",
176 res);
177 }
178out:
179 tmp = list;
180 prev->next = list = list->next;
181 kfree(tmp);
182 }
183}
184
185/**
186 * assign_requested_resources_sorted() - satisfy resource requests
187 *
188 * @head : head of the list tracking requests for resources
189 * @failed_list : head of the list tracking requests that could
190 * not be allocated
191 *
192 * Satisfy resource requests of each element in the list. Add
193 * requests that could not satisfied to the failed_list.
194 */
195static void assign_requested_resources_sorted(struct resource_list *head,
196 struct resource_list_x *fail_head)
197{
198 struct resource *res;
199 struct resource_list *list;
200 int idx;
201
202 for (list = head->next; list; list = list->next) {
203 res = list->res;
204 idx = res - &list->dev->resource[0];
205 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
206 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
207 /*
208 * if the failed res is for ROM BAR, and it will
209 * be enabled later, don't add it to the list
210 */
211 if (!((idx == PCI_ROM_RESOURCE) &&
212 (!(res->flags & IORESOURCE_ROM_ENABLE))))
213 add_to_failed_list(fail_head, list->dev, res);
214 }
215 reset_resource(res);
216 }
217 }
218}
219
220static void __assign_resources_sorted(struct resource_list *head,
221 struct resource_list_x *realloc_head,
222 struct resource_list_x *fail_head)
223{
224 /* Satisfy the must-have resource requests */
225 assign_requested_resources_sorted(head, fail_head);
226
227 /* Try to satisfy any additional optional resource
228 requests */
229 if (realloc_head)
230 reassign_resources_sorted(realloc_head, head);
231 free_list(resource_list, head);
232}
233
234static void pdev_assign_resources_sorted(struct pci_dev *dev,
235 struct resource_list_x *fail_head)
236{
237 struct resource_list head;
238
239 head.next = NULL;
240 __dev_sort_resources(dev, &head);
241 __assign_resources_sorted(&head, NULL, fail_head);
242
243}
244
245static void pbus_assign_resources_sorted(const struct pci_bus *bus,
246 struct resource_list_x *realloc_head,
247 struct resource_list_x *fail_head)
248{
249 struct pci_dev *dev;
250 struct resource_list head;
251
252 head.next = NULL;
253 list_for_each_entry(dev, &bus->devices, bus_list)
254 __dev_sort_resources(dev, &head);
255
256 __assign_resources_sorted(&head, realloc_head, fail_head);
257}
258
259void pci_setup_cardbus(struct pci_bus *bus)
260{
261 struct pci_dev *bridge = bus->self;
262 struct resource *res;
263 struct pci_bus_region region;
264
265 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
266 bus->secondary, bus->subordinate);
267
268 res = bus->resource[0];
269 pcibios_resource_to_bus(bridge, ®ion, res);
270 if (res->flags & IORESOURCE_IO) {
271 /*
272 * The IO resource is allocated a range twice as large as it
273 * would normally need. This allows us to set both IO regs.
274 */
275 dev_info(&bridge->dev, " bridge window %pR\n", res);
276 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
277 region.start);
278 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
279 region.end);
280 }
281
282 res = bus->resource[1];
283 pcibios_resource_to_bus(bridge, ®ion, res);
284 if (res->flags & IORESOURCE_IO) {
285 dev_info(&bridge->dev, " bridge window %pR\n", res);
286 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
287 region.start);
288 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
289 region.end);
290 }
291
292 res = bus->resource[2];
293 pcibios_resource_to_bus(bridge, ®ion, res);
294 if (res->flags & IORESOURCE_MEM) {
295 dev_info(&bridge->dev, " bridge window %pR\n", res);
296 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
297 region.start);
298 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
299 region.end);
300 }
301
302 res = bus->resource[3];
303 pcibios_resource_to_bus(bridge, ®ion, res);
304 if (res->flags & IORESOURCE_MEM) {
305 dev_info(&bridge->dev, " bridge window %pR\n", res);
306 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
307 region.start);
308 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
309 region.end);
310 }
311}
312EXPORT_SYMBOL(pci_setup_cardbus);
313
314/* Initialize bridges with base/limit values we have collected.
315 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
316 requires that if there is no I/O ports or memory behind the
317 bridge, corresponding range must be turned off by writing base
318 value greater than limit to the bridge's base/limit registers.
319
320 Note: care must be taken when updating I/O base/limit registers
321 of bridges which support 32-bit I/O. This update requires two
322 config space writes, so it's quite possible that an I/O window of
323 the bridge will have some undesirable address (e.g. 0) after the
324 first write. Ditto 64-bit prefetchable MMIO. */
325static void pci_setup_bridge_io(struct pci_bus *bus)
326{
327 struct pci_dev *bridge = bus->self;
328 struct resource *res;
329 struct pci_bus_region region;
330 u32 l, io_upper16;
331
332 /* Set up the top and bottom of the PCI I/O segment for this bus. */
333 res = bus->resource[0];
334 pcibios_resource_to_bus(bridge, ®ion, res);
335 if (res->flags & IORESOURCE_IO) {
336 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
337 l &= 0xffff0000;
338 l |= (region.start >> 8) & 0x00f0;
339 l |= region.end & 0xf000;
340 /* Set up upper 16 bits of I/O base/limit. */
341 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
342 dev_info(&bridge->dev, " bridge window %pR\n", res);
343 } else {
344 /* Clear upper 16 bits of I/O base/limit. */
345 io_upper16 = 0;
346 l = 0x00f0;
347 }
348 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
349 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
350 /* Update lower 16 bits of I/O base/limit. */
351 pci_write_config_dword(bridge, PCI_IO_BASE, l);
352 /* Update upper 16 bits of I/O base/limit. */
353 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
354}
355
356static void pci_setup_bridge_mmio(struct pci_bus *bus)
357{
358 struct pci_dev *bridge = bus->self;
359 struct resource *res;
360 struct pci_bus_region region;
361 u32 l;
362
363 /* Set up the top and bottom of the PCI Memory segment for this bus. */
364 res = bus->resource[1];
365 pcibios_resource_to_bus(bridge, ®ion, res);
366 if (res->flags & IORESOURCE_MEM) {
367 l = (region.start >> 16) & 0xfff0;
368 l |= region.end & 0xfff00000;
369 dev_info(&bridge->dev, " bridge window %pR\n", res);
370 } else {
371 l = 0x0000fff0;
372 }
373 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
374}
375
376static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
377{
378 struct pci_dev *bridge = bus->self;
379 struct resource *res;
380 struct pci_bus_region region;
381 u32 l, bu, lu;
382
383 /* Clear out the upper 32 bits of PREF limit.
384 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
385 disables PREF range, which is ok. */
386 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
387
388 /* Set up PREF base/limit. */
389 bu = lu = 0;
390 res = bus->resource[2];
391 pcibios_resource_to_bus(bridge, ®ion, res);
392 if (res->flags & IORESOURCE_PREFETCH) {
393 l = (region.start >> 16) & 0xfff0;
394 l |= region.end & 0xfff00000;
395 if (res->flags & IORESOURCE_MEM_64) {
396 bu = upper_32_bits(region.start);
397 lu = upper_32_bits(region.end);
398 }
399 dev_info(&bridge->dev, " bridge window %pR\n", res);
400 } else {
401 l = 0x0000fff0;
402 }
403 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
404
405 /* Set the upper 32 bits of PREF base & limit. */
406 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
407 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
408}
409
410static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
411{
412 struct pci_dev *bridge = bus->self;
413
414 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
415 bus->secondary, bus->subordinate);
416
417 if (type & IORESOURCE_IO)
418 pci_setup_bridge_io(bus);
419
420 if (type & IORESOURCE_MEM)
421 pci_setup_bridge_mmio(bus);
422
423 if (type & IORESOURCE_PREFETCH)
424 pci_setup_bridge_mmio_pref(bus);
425
426 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
427}
428
429static void pci_setup_bridge(struct pci_bus *bus)
430{
431 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
432 IORESOURCE_PREFETCH;
433
434 __pci_setup_bridge(bus, type);
435}
436
437/* Check whether the bridge supports optional I/O and
438 prefetchable memory ranges. If not, the respective
439 base/limit registers must be read-only and read as 0. */
440static void pci_bridge_check_ranges(struct pci_bus *bus)
441{
442 u16 io;
443 u32 pmem;
444 struct pci_dev *bridge = bus->self;
445 struct resource *b_res;
446
447 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
448 b_res[1].flags |= IORESOURCE_MEM;
449
450 pci_read_config_word(bridge, PCI_IO_BASE, &io);
451 if (!io) {
452 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
453 pci_read_config_word(bridge, PCI_IO_BASE, &io);
454 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
455 }
456 if (io)
457 b_res[0].flags |= IORESOURCE_IO;
458 /* DECchip 21050 pass 2 errata: the bridge may miss an address
459 disconnect boundary by one PCI data phase.
460 Workaround: do not use prefetching on this device. */
461 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
462 return;
463 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
464 if (!pmem) {
465 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
466 0xfff0fff0);
467 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
468 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
469 }
470 if (pmem) {
471 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
472 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
473 PCI_PREF_RANGE_TYPE_64) {
474 b_res[2].flags |= IORESOURCE_MEM_64;
475 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
476 }
477 }
478
479 /* double check if bridge does support 64 bit pref */
480 if (b_res[2].flags & IORESOURCE_MEM_64) {
481 u32 mem_base_hi, tmp;
482 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
483 &mem_base_hi);
484 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
485 0xffffffff);
486 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
487 if (!tmp)
488 b_res[2].flags &= ~IORESOURCE_MEM_64;
489 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
490 mem_base_hi);
491 }
492}
493
494/* Helper function for sizing routines: find first available
495 bus resource of a given type. Note: we intentionally skip
496 the bus resources which have already been assigned (that is,
497 have non-NULL parent resource). */
498static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
499{
500 int i;
501 struct resource *r;
502 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
503 IORESOURCE_PREFETCH;
504
505 pci_bus_for_each_resource(bus, r, i) {
506 if (r == &ioport_resource || r == &iomem_resource)
507 continue;
508 if (r && (r->flags & type_mask) == type && !r->parent)
509 return r;
510 }
511 return NULL;
512}
513
514static resource_size_t calculate_iosize(resource_size_t size,
515 resource_size_t min_size,
516 resource_size_t size1,
517 resource_size_t old_size,
518 resource_size_t align)
519{
520 if (size < min_size)
521 size = min_size;
522 if (old_size == 1 )
523 old_size = 0;
524 /* To be fixed in 2.5: we should have sort of HAVE_ISA
525 flag in the struct pci_bus. */
526#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
527 size = (size & 0xff) + ((size & ~0xffUL) << 2);
528#endif
529 size = ALIGN(size + size1, align);
530 if (size < old_size)
531 size = old_size;
532 return size;
533}
534
535static resource_size_t calculate_memsize(resource_size_t size,
536 resource_size_t min_size,
537 resource_size_t size1,
538 resource_size_t old_size,
539 resource_size_t align)
540{
541 if (size < min_size)
542 size = min_size;
543 if (old_size == 1 )
544 old_size = 0;
545 if (size < old_size)
546 size = old_size;
547 size = ALIGN(size + size1, align);
548 return size;
549}
550
551static resource_size_t get_res_add_size(struct resource_list_x *realloc_head,
552 struct resource *res)
553{
554 struct resource_list_x *list;
555
556 /* check if it is in realloc_head list */
557 for (list = realloc_head->next; list && list->res != res;
558 list = list->next);
559 if (list)
560 return list->add_size;
561
562 return 0;
563}
564
565/**
566 * pbus_size_io() - size the io window of a given bus
567 *
568 * @bus : the bus
569 * @min_size : the minimum io window that must to be allocated
570 * @add_size : additional optional io window
571 * @realloc_head : track the additional io window on this list
572 *
573 * Sizing the IO windows of the PCI-PCI bridge is trivial,
574 * since these windows have 4K granularity and the IO ranges
575 * of non-bridge PCI devices are limited to 256 bytes.
576 * We must be careful with the ISA aliasing though.
577 */
578static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
579 resource_size_t add_size, struct resource_list_x *realloc_head)
580{
581 struct pci_dev *dev;
582 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
583 unsigned long size = 0, size0 = 0, size1 = 0;
584 resource_size_t children_add_size = 0;
585
586 if (!b_res)
587 return;
588
589 list_for_each_entry(dev, &bus->devices, bus_list) {
590 int i;
591
592 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
593 struct resource *r = &dev->resource[i];
594 unsigned long r_size;
595
596 if (r->parent || !(r->flags & IORESOURCE_IO))
597 continue;
598 r_size = resource_size(r);
599
600 if (r_size < 0x400)
601 /* Might be re-aligned for ISA */
602 size += r_size;
603 else
604 size1 += r_size;
605
606 if (realloc_head)
607 children_add_size += get_res_add_size(realloc_head, r);
608 }
609 }
610 size0 = calculate_iosize(size, min_size, size1,
611 resource_size(b_res), 4096);
612 if (children_add_size > add_size)
613 add_size = children_add_size;
614 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
615 calculate_iosize(size, min_size+add_size, size1,
616 resource_size(b_res), 4096);
617 if (!size0 && !size1) {
618 if (b_res->start || b_res->end)
619 dev_info(&bus->self->dev, "disabling bridge window "
620 "%pR to [bus %02x-%02x] (unused)\n", b_res,
621 bus->secondary, bus->subordinate);
622 b_res->flags = 0;
623 return;
624 }
625 /* Alignment of the IO window is always 4K */
626 b_res->start = 4096;
627 b_res->end = b_res->start + size0 - 1;
628 b_res->flags |= IORESOURCE_STARTALIGN;
629 if (size1 > size0 && realloc_head)
630 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
631}
632
633/**
634 * pbus_size_mem() - size the memory window of a given bus
635 *
636 * @bus : the bus
637 * @min_size : the minimum memory window that must to be allocated
638 * @add_size : additional optional memory window
639 * @realloc_head : track the additional memory window on this list
640 *
641 * Calculate the size of the bus and minimal alignment which
642 * guarantees that all child resources fit in this size.
643 */
644static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
645 unsigned long type, resource_size_t min_size,
646 resource_size_t add_size,
647 struct resource_list_x *realloc_head)
648{
649 struct pci_dev *dev;
650 resource_size_t min_align, align, size, size0, size1;
651 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
652 int order, max_order;
653 struct resource *b_res = find_free_bus_resource(bus, type);
654 unsigned int mem64_mask = 0;
655 resource_size_t children_add_size = 0;
656
657 if (!b_res)
658 return 0;
659
660 memset(aligns, 0, sizeof(aligns));
661 max_order = 0;
662 size = 0;
663
664 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
665 b_res->flags &= ~IORESOURCE_MEM_64;
666
667 list_for_each_entry(dev, &bus->devices, bus_list) {
668 int i;
669
670 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
671 struct resource *r = &dev->resource[i];
672 resource_size_t r_size;
673
674 if (r->parent || (r->flags & mask) != type)
675 continue;
676 r_size = resource_size(r);
677#ifdef CONFIG_PCI_IOV
678 /* put SRIOV requested res to the optional list */
679 if (realloc_head && i >= PCI_IOV_RESOURCES &&
680 i <= PCI_IOV_RESOURCE_END) {
681 r->end = r->start - 1;
682 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
683 children_add_size += r_size;
684 continue;
685 }
686#endif
687 /* For bridges size != alignment */
688 align = pci_resource_alignment(dev, r);
689 order = __ffs(align) - 20;
690 if (order > 11) {
691 dev_warn(&dev->dev, "disabling BAR %d: %pR "
692 "(bad alignment %#llx)\n", i, r,
693 (unsigned long long) align);
694 r->flags = 0;
695 continue;
696 }
697 size += r_size;
698 if (order < 0)
699 order = 0;
700 /* Exclude ranges with size > align from
701 calculation of the alignment. */
702 if (r_size == align)
703 aligns[order] += align;
704 if (order > max_order)
705 max_order = order;
706 mem64_mask &= r->flags & IORESOURCE_MEM_64;
707
708 if (realloc_head)
709 children_add_size += get_res_add_size(realloc_head, r);
710 }
711 }
712 align = 0;
713 min_align = 0;
714 for (order = 0; order <= max_order; order++) {
715 resource_size_t align1 = 1;
716
717 align1 <<= (order + 20);
718
719 if (!align)
720 min_align = align1;
721 else if (ALIGN(align + min_align, min_align) < align1)
722 min_align = align1 >> 1;
723 align += aligns[order];
724 }
725 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
726 if (children_add_size > add_size)
727 add_size = children_add_size;
728 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
729 calculate_memsize(size, min_size+add_size, 0,
730 resource_size(b_res), min_align);
731 if (!size0 && !size1) {
732 if (b_res->start || b_res->end)
733 dev_info(&bus->self->dev, "disabling bridge window "
734 "%pR to [bus %02x-%02x] (unused)\n", b_res,
735 bus->secondary, bus->subordinate);
736 b_res->flags = 0;
737 return 1;
738 }
739 b_res->start = min_align;
740 b_res->end = size0 + min_align - 1;
741 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
742 if (size1 > size0 && realloc_head)
743 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
744 return 1;
745}
746
747unsigned long pci_cardbus_resource_alignment(struct resource *res)
748{
749 if (res->flags & IORESOURCE_IO)
750 return pci_cardbus_io_size;
751 if (res->flags & IORESOURCE_MEM)
752 return pci_cardbus_mem_size;
753 return 0;
754}
755
756static void pci_bus_size_cardbus(struct pci_bus *bus,
757 struct resource_list_x *realloc_head)
758{
759 struct pci_dev *bridge = bus->self;
760 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
761 u16 ctrl;
762
763 /*
764 * Reserve some resources for CardBus. We reserve
765 * a fixed amount of bus space for CardBus bridges.
766 */
767 b_res[0].start = 0;
768 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
769 if (realloc_head)
770 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */);
771
772 b_res[1].start = 0;
773 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
774 if (realloc_head)
775 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
776
777 /*
778 * Check whether prefetchable memory is supported
779 * by this bridge.
780 */
781 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
782 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
783 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
784 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
785 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
786 }
787
788 /*
789 * If we have prefetchable memory support, allocate
790 * two regions. Otherwise, allocate one region of
791 * twice the size.
792 */
793 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
794 b_res[2].start = 0;
795 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
796 if (realloc_head)
797 add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */);
798
799 b_res[3].start = 0;
800 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
801 if (realloc_head)
802 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */);
803 } else {
804 b_res[3].start = 0;
805 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
806 if (realloc_head)
807 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */);
808 }
809
810 /* set the size of the resource to zero, so that the resource does not
811 * get assigned during required-resource allocation cycle but gets assigned
812 * during the optional-resource allocation cycle.
813 */
814 b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1;
815 b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0;
816}
817
818void __ref __pci_bus_size_bridges(struct pci_bus *bus,
819 struct resource_list_x *realloc_head)
820{
821 struct pci_dev *dev;
822 unsigned long mask, prefmask;
823 resource_size_t additional_mem_size = 0, additional_io_size = 0;
824
825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 struct pci_bus *b = dev->subordinate;
827 if (!b)
828 continue;
829
830 switch (dev->class >> 8) {
831 case PCI_CLASS_BRIDGE_CARDBUS:
832 pci_bus_size_cardbus(b, realloc_head);
833 break;
834
835 case PCI_CLASS_BRIDGE_PCI:
836 default:
837 __pci_bus_size_bridges(b, realloc_head);
838 break;
839 }
840 }
841
842 /* The root bus? */
843 if (!bus->self)
844 return;
845
846 switch (bus->self->class >> 8) {
847 case PCI_CLASS_BRIDGE_CARDBUS:
848 /* don't size cardbuses yet. */
849 break;
850
851 case PCI_CLASS_BRIDGE_PCI:
852 pci_bridge_check_ranges(bus);
853 if (bus->self->is_hotplug_bridge) {
854 additional_io_size = pci_hotplug_io_size;
855 additional_mem_size = pci_hotplug_mem_size;
856 }
857 /*
858 * Follow thru
859 */
860 default:
861 pbus_size_io(bus, 0, additional_io_size, realloc_head);
862 /* If the bridge supports prefetchable range, size it
863 separately. If it doesn't, or its prefetchable window
864 has already been allocated by arch code, try
865 non-prefetchable range for both types of PCI memory
866 resources. */
867 mask = IORESOURCE_MEM;
868 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
869 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head))
870 mask = prefmask; /* Success, size non-prefetch only. */
871 else
872 additional_mem_size += additional_mem_size;
873 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head);
874 break;
875 }
876}
877
878void __ref pci_bus_size_bridges(struct pci_bus *bus)
879{
880 __pci_bus_size_bridges(bus, NULL);
881}
882EXPORT_SYMBOL(pci_bus_size_bridges);
883
884static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
885 struct resource_list_x *realloc_head,
886 struct resource_list_x *fail_head)
887{
888 struct pci_bus *b;
889 struct pci_dev *dev;
890
891 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
892
893 list_for_each_entry(dev, &bus->devices, bus_list) {
894 b = dev->subordinate;
895 if (!b)
896 continue;
897
898 __pci_bus_assign_resources(b, realloc_head, fail_head);
899
900 switch (dev->class >> 8) {
901 case PCI_CLASS_BRIDGE_PCI:
902 if (!pci_is_enabled(dev))
903 pci_setup_bridge(b);
904 break;
905
906 case PCI_CLASS_BRIDGE_CARDBUS:
907 pci_setup_cardbus(b);
908 break;
909
910 default:
911 dev_info(&dev->dev, "not setting up bridge for bus "
912 "%04x:%02x\n", pci_domain_nr(b), b->number);
913 break;
914 }
915 }
916}
917
918void __ref pci_bus_assign_resources(const struct pci_bus *bus)
919{
920 __pci_bus_assign_resources(bus, NULL, NULL);
921}
922EXPORT_SYMBOL(pci_bus_assign_resources);
923
924static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
925 struct resource_list_x *fail_head)
926{
927 struct pci_bus *b;
928
929 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
930
931 b = bridge->subordinate;
932 if (!b)
933 return;
934
935 __pci_bus_assign_resources(b, NULL, fail_head);
936
937 switch (bridge->class >> 8) {
938 case PCI_CLASS_BRIDGE_PCI:
939 pci_setup_bridge(b);
940 break;
941
942 case PCI_CLASS_BRIDGE_CARDBUS:
943 pci_setup_cardbus(b);
944 break;
945
946 default:
947 dev_info(&bridge->dev, "not setting up bridge for bus "
948 "%04x:%02x\n", pci_domain_nr(b), b->number);
949 break;
950 }
951}
952static void pci_bridge_release_resources(struct pci_bus *bus,
953 unsigned long type)
954{
955 int idx;
956 bool changed = false;
957 struct pci_dev *dev;
958 struct resource *r;
959 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
960 IORESOURCE_PREFETCH;
961
962 dev = bus->self;
963 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
964 idx++) {
965 r = &dev->resource[idx];
966 if ((r->flags & type_mask) != type)
967 continue;
968 if (!r->parent)
969 continue;
970 /*
971 * if there are children under that, we should release them
972 * all
973 */
974 release_child_resources(r);
975 if (!release_resource(r)) {
976 dev_printk(KERN_DEBUG, &dev->dev,
977 "resource %d %pR released\n", idx, r);
978 /* keep the old size */
979 r->end = resource_size(r) - 1;
980 r->start = 0;
981 r->flags = 0;
982 changed = true;
983 }
984 }
985
986 if (changed) {
987 /* avoiding touch the one without PREF */
988 if (type & IORESOURCE_PREFETCH)
989 type = IORESOURCE_PREFETCH;
990 __pci_setup_bridge(bus, type);
991 }
992}
993
994enum release_type {
995 leaf_only,
996 whole_subtree,
997};
998/*
999 * try to release pci bridge resources that is from leaf bridge,
1000 * so we can allocate big new one later
1001 */
1002static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1003 unsigned long type,
1004 enum release_type rel_type)
1005{
1006 struct pci_dev *dev;
1007 bool is_leaf_bridge = true;
1008
1009 list_for_each_entry(dev, &bus->devices, bus_list) {
1010 struct pci_bus *b = dev->subordinate;
1011 if (!b)
1012 continue;
1013
1014 is_leaf_bridge = false;
1015
1016 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1017 continue;
1018
1019 if (rel_type == whole_subtree)
1020 pci_bus_release_bridge_resources(b, type,
1021 whole_subtree);
1022 }
1023
1024 if (pci_is_root_bus(bus))
1025 return;
1026
1027 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1028 return;
1029
1030 if ((rel_type == whole_subtree) || is_leaf_bridge)
1031 pci_bridge_release_resources(bus, type);
1032}
1033
1034static void pci_bus_dump_res(struct pci_bus *bus)
1035{
1036 struct resource *res;
1037 int i;
1038
1039 pci_bus_for_each_resource(bus, res, i) {
1040 if (!res || !res->end || !res->flags)
1041 continue;
1042
1043 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1044 }
1045}
1046
1047static void pci_bus_dump_resources(struct pci_bus *bus)
1048{
1049 struct pci_bus *b;
1050 struct pci_dev *dev;
1051
1052
1053 pci_bus_dump_res(bus);
1054
1055 list_for_each_entry(dev, &bus->devices, bus_list) {
1056 b = dev->subordinate;
1057 if (!b)
1058 continue;
1059
1060 pci_bus_dump_resources(b);
1061 }
1062}
1063
1064static int __init pci_bus_get_depth(struct pci_bus *bus)
1065{
1066 int depth = 0;
1067 struct pci_dev *dev;
1068
1069 list_for_each_entry(dev, &bus->devices, bus_list) {
1070 int ret;
1071 struct pci_bus *b = dev->subordinate;
1072 if (!b)
1073 continue;
1074
1075 ret = pci_bus_get_depth(b);
1076 if (ret + 1 > depth)
1077 depth = ret + 1;
1078 }
1079
1080 return depth;
1081}
1082static int __init pci_get_max_depth(void)
1083{
1084 int depth = 0;
1085 struct pci_bus *bus;
1086
1087 list_for_each_entry(bus, &pci_root_buses, node) {
1088 int ret;
1089
1090 ret = pci_bus_get_depth(bus);
1091 if (ret > depth)
1092 depth = ret;
1093 }
1094
1095 return depth;
1096}
1097
1098
1099/*
1100 * first try will not touch pci bridge res
1101 * second and later try will clear small leaf bridge res
1102 * will stop till to the max deepth if can not find good one
1103 */
1104void __init
1105pci_assign_unassigned_resources(void)
1106{
1107 struct pci_bus *bus;
1108 struct resource_list_x realloc_list; /* list of resources that
1109 want additional resources */
1110 int tried_times = 0;
1111 enum release_type rel_type = leaf_only;
1112 struct resource_list_x head, *list;
1113 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1114 IORESOURCE_PREFETCH;
1115 unsigned long failed_type;
1116 int max_depth = pci_get_max_depth();
1117 int pci_try_num;
1118
1119
1120 head.next = NULL;
1121 realloc_list.next = NULL;
1122
1123 pci_try_num = max_depth + 1;
1124 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1125 max_depth, pci_try_num);
1126
1127again:
1128 /* Depth first, calculate sizes and alignments of all
1129 subordinate buses. */
1130 list_for_each_entry(bus, &pci_root_buses, node)
1131 __pci_bus_size_bridges(bus, &realloc_list);
1132
1133 /* Depth last, allocate resources and update the hardware. */
1134 list_for_each_entry(bus, &pci_root_buses, node)
1135 __pci_bus_assign_resources(bus, &realloc_list, &head);
1136 BUG_ON(realloc_list.next);
1137 tried_times++;
1138
1139 /* any device complain? */
1140 if (!head.next)
1141 goto enable_and_dump;
1142
1143 /* don't realloc if asked to do so */
1144 if (!pci_realloc_enabled()) {
1145 free_list(resource_list_x, &head);
1146 goto enable_and_dump;
1147 }
1148
1149 failed_type = 0;
1150 for (list = head.next; list;) {
1151 failed_type |= list->flags;
1152 list = list->next;
1153 }
1154 /*
1155 * io port are tight, don't try extra
1156 * or if reach the limit, don't want to try more
1157 */
1158 failed_type &= type_mask;
1159 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1160 free_list(resource_list_x, &head);
1161 goto enable_and_dump;
1162 }
1163
1164 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1165 tried_times + 1);
1166
1167 /* third times and later will not check if it is leaf */
1168 if ((tried_times + 1) > 2)
1169 rel_type = whole_subtree;
1170
1171 /*
1172 * Try to release leaf bridge's resources that doesn't fit resource of
1173 * child device under that bridge
1174 */
1175 for (list = head.next; list;) {
1176 bus = list->dev->bus;
1177 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1178 rel_type);
1179 list = list->next;
1180 }
1181 /* restore size and flags */
1182 for (list = head.next; list;) {
1183 struct resource *res = list->res;
1184
1185 res->start = list->start;
1186 res->end = list->end;
1187 res->flags = list->flags;
1188 if (list->dev->subordinate)
1189 res->flags = 0;
1190
1191 list = list->next;
1192 }
1193 free_list(resource_list_x, &head);
1194
1195 goto again;
1196
1197enable_and_dump:
1198 /* Depth last, update the hardware. */
1199 list_for_each_entry(bus, &pci_root_buses, node)
1200 pci_enable_bridges(bus);
1201
1202 /* dump the resource on buses */
1203 list_for_each_entry(bus, &pci_root_buses, node)
1204 pci_bus_dump_resources(bus);
1205}
1206
1207void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1208{
1209 struct pci_bus *parent = bridge->subordinate;
1210 int tried_times = 0;
1211 struct resource_list_x head, *list;
1212 int retval;
1213 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1214 IORESOURCE_PREFETCH;
1215
1216 head.next = NULL;
1217
1218again:
1219 pci_bus_size_bridges(parent);
1220 __pci_bridge_assign_resources(bridge, &head);
1221
1222 tried_times++;
1223
1224 if (!head.next)
1225 goto enable_all;
1226
1227 if (tried_times >= 2) {
1228 /* still fail, don't need to try more */
1229 free_list(resource_list_x, &head);
1230 goto enable_all;
1231 }
1232
1233 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1234 tried_times + 1);
1235
1236 /*
1237 * Try to release leaf bridge's resources that doesn't fit resource of
1238 * child device under that bridge
1239 */
1240 for (list = head.next; list;) {
1241 struct pci_bus *bus = list->dev->bus;
1242 unsigned long flags = list->flags;
1243
1244 pci_bus_release_bridge_resources(bus, flags & type_mask,
1245 whole_subtree);
1246 list = list->next;
1247 }
1248 /* restore size and flags */
1249 for (list = head.next; list;) {
1250 struct resource *res = list->res;
1251
1252 res->start = list->start;
1253 res->end = list->end;
1254 res->flags = list->flags;
1255 if (list->dev->subordinate)
1256 res->flags = 0;
1257
1258 list = list->next;
1259 }
1260 free_list(resource_list_x, &head);
1261
1262 goto again;
1263
1264enable_all:
1265 retval = pci_reenable_device(bridge);
1266 pci_set_master(bridge);
1267 pci_enable_bridges(parent);
1268}
1269EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/errno.h>
22#include <linux/ioport.h>
23#include <linux/cache.h>
24#include <linux/slab.h>
25#include <linux/acpi.h>
26#include "pci.h"
27
28unsigned int pci_flags;
29EXPORT_SYMBOL_GPL(pci_flags);
30
31struct pci_dev_resource {
32 struct list_head list;
33 struct resource *res;
34 struct pci_dev *dev;
35 resource_size_t start;
36 resource_size_t end;
37 resource_size_t add_size;
38 resource_size_t min_align;
39 unsigned long flags;
40};
41
42static void free_list(struct list_head *head)
43{
44 struct pci_dev_resource *dev_res, *tmp;
45
46 list_for_each_entry_safe(dev_res, tmp, head, list) {
47 list_del(&dev_res->list);
48 kfree(dev_res);
49 }
50}
51
52/**
53 * add_to_list() - Add a new resource tracker to the list
54 * @head: Head of the list
55 * @dev: Device to which the resource belongs
56 * @res: Resource to be tracked
57 * @add_size: Additional size to be optionally added to the resource
58 * @min_align: Minimum memory window alignment
59 */
60static int add_to_list(struct list_head *head, struct pci_dev *dev,
61 struct resource *res, resource_size_t add_size,
62 resource_size_t min_align)
63{
64 struct pci_dev_resource *tmp;
65
66 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
67 if (!tmp)
68 return -ENOMEM;
69
70 tmp->res = res;
71 tmp->dev = dev;
72 tmp->start = res->start;
73 tmp->end = res->end;
74 tmp->flags = res->flags;
75 tmp->add_size = add_size;
76 tmp->min_align = min_align;
77
78 list_add(&tmp->list, head);
79
80 return 0;
81}
82
83static void remove_from_list(struct list_head *head, struct resource *res)
84{
85 struct pci_dev_resource *dev_res, *tmp;
86
87 list_for_each_entry_safe(dev_res, tmp, head, list) {
88 if (dev_res->res == res) {
89 list_del(&dev_res->list);
90 kfree(dev_res);
91 break;
92 }
93 }
94}
95
96static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
97 struct resource *res)
98{
99 struct pci_dev_resource *dev_res;
100
101 list_for_each_entry(dev_res, head, list) {
102 if (dev_res->res == res)
103 return dev_res;
104 }
105
106 return NULL;
107}
108
109static resource_size_t get_res_add_size(struct list_head *head,
110 struct resource *res)
111{
112 struct pci_dev_resource *dev_res;
113
114 dev_res = res_to_dev_res(head, res);
115 return dev_res ? dev_res->add_size : 0;
116}
117
118static resource_size_t get_res_add_align(struct list_head *head,
119 struct resource *res)
120{
121 struct pci_dev_resource *dev_res;
122
123 dev_res = res_to_dev_res(head, res);
124 return dev_res ? dev_res->min_align : 0;
125}
126
127
128/* Sort resources by alignment */
129static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
130{
131 int i;
132
133 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
134 struct resource *r;
135 struct pci_dev_resource *dev_res, *tmp;
136 resource_size_t r_align;
137 struct list_head *n;
138
139 r = &dev->resource[i];
140
141 if (r->flags & IORESOURCE_PCI_FIXED)
142 continue;
143
144 if (!(r->flags) || r->parent)
145 continue;
146
147 r_align = pci_resource_alignment(dev, r);
148 if (!r_align) {
149 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
150 i, r);
151 continue;
152 }
153
154 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
155 if (!tmp)
156 panic("%s: kzalloc() failed!\n", __func__);
157 tmp->res = r;
158 tmp->dev = dev;
159
160 /* Fallback is smallest one or list is empty */
161 n = head;
162 list_for_each_entry(dev_res, head, list) {
163 resource_size_t align;
164
165 align = pci_resource_alignment(dev_res->dev,
166 dev_res->res);
167
168 if (r_align > align) {
169 n = &dev_res->list;
170 break;
171 }
172 }
173 /* Insert it just before n */
174 list_add_tail(&tmp->list, n);
175 }
176}
177
178static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
179{
180 u16 class = dev->class >> 8;
181
182 /* Don't touch classless devices or host bridges or IOAPICs */
183 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
184 return;
185
186 /* Don't touch IOAPIC devices already enabled by firmware */
187 if (class == PCI_CLASS_SYSTEM_PIC) {
188 u16 command;
189 pci_read_config_word(dev, PCI_COMMAND, &command);
190 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
191 return;
192 }
193
194 pdev_sort_resources(dev, head);
195}
196
197static inline void reset_resource(struct resource *res)
198{
199 res->start = 0;
200 res->end = 0;
201 res->flags = 0;
202}
203
204/**
205 * reassign_resources_sorted() - Satisfy any additional resource requests
206 *
207 * @realloc_head: Head of the list tracking requests requiring
208 * additional resources
209 * @head: Head of the list tracking requests with allocated
210 * resources
211 *
212 * Walk through each element of the realloc_head and try to procure additional
213 * resources for the element, provided the element is in the head list.
214 */
215static void reassign_resources_sorted(struct list_head *realloc_head,
216 struct list_head *head)
217{
218 struct resource *res;
219 struct pci_dev_resource *add_res, *tmp;
220 struct pci_dev_resource *dev_res;
221 resource_size_t add_size, align;
222 int idx;
223
224 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
225 bool found_match = false;
226
227 res = add_res->res;
228 /* Skip resource that has been reset */
229 if (!res->flags)
230 goto out;
231
232 /* Skip this resource if not found in head list */
233 list_for_each_entry(dev_res, head, list) {
234 if (dev_res->res == res) {
235 found_match = true;
236 break;
237 }
238 }
239 if (!found_match) /* Just skip */
240 continue;
241
242 idx = res - &add_res->dev->resource[0];
243 add_size = add_res->add_size;
244 align = add_res->min_align;
245 if (!resource_size(res)) {
246 res->start = align;
247 res->end = res->start + add_size - 1;
248 if (pci_assign_resource(add_res->dev, idx))
249 reset_resource(res);
250 } else {
251 res->flags |= add_res->flags &
252 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
253 if (pci_reassign_resource(add_res->dev, idx,
254 add_size, align))
255 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
256 (unsigned long long) add_size, idx,
257 res);
258 }
259out:
260 list_del(&add_res->list);
261 kfree(add_res);
262 }
263}
264
265/**
266 * assign_requested_resources_sorted() - Satisfy resource requests
267 *
268 * @head: Head of the list tracking requests for resources
269 * @fail_head: Head of the list tracking requests that could not be
270 * allocated
271 *
272 * Satisfy resource requests of each element in the list. Add requests that
273 * could not be satisfied to the failed_list.
274 */
275static void assign_requested_resources_sorted(struct list_head *head,
276 struct list_head *fail_head)
277{
278 struct resource *res;
279 struct pci_dev_resource *dev_res;
280 int idx;
281
282 list_for_each_entry(dev_res, head, list) {
283 res = dev_res->res;
284 idx = res - &dev_res->dev->resource[0];
285 if (resource_size(res) &&
286 pci_assign_resource(dev_res->dev, idx)) {
287 if (fail_head) {
288 /*
289 * If the failed resource is a ROM BAR and
290 * it will be enabled later, don't add it
291 * to the list.
292 */
293 if (!((idx == PCI_ROM_RESOURCE) &&
294 (!(res->flags & IORESOURCE_ROM_ENABLE))))
295 add_to_list(fail_head,
296 dev_res->dev, res,
297 0 /* don't care */,
298 0 /* don't care */);
299 }
300 reset_resource(res);
301 }
302 }
303}
304
305static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
306{
307 struct pci_dev_resource *fail_res;
308 unsigned long mask = 0;
309
310 /* Check failed type */
311 list_for_each_entry(fail_res, fail_head, list)
312 mask |= fail_res->flags;
313
314 /*
315 * One pref failed resource will set IORESOURCE_MEM, as we can
316 * allocate pref in non-pref range. Will release all assigned
317 * non-pref sibling resources according to that bit.
318 */
319 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
320}
321
322static bool pci_need_to_release(unsigned long mask, struct resource *res)
323{
324 if (res->flags & IORESOURCE_IO)
325 return !!(mask & IORESOURCE_IO);
326
327 /* Check pref at first */
328 if (res->flags & IORESOURCE_PREFETCH) {
329 if (mask & IORESOURCE_PREFETCH)
330 return true;
331 /* Count pref if its parent is non-pref */
332 else if ((mask & IORESOURCE_MEM) &&
333 !(res->parent->flags & IORESOURCE_PREFETCH))
334 return true;
335 else
336 return false;
337 }
338
339 if (res->flags & IORESOURCE_MEM)
340 return !!(mask & IORESOURCE_MEM);
341
342 return false; /* Should not get here */
343}
344
345static void __assign_resources_sorted(struct list_head *head,
346 struct list_head *realloc_head,
347 struct list_head *fail_head)
348{
349 /*
350 * Should not assign requested resources at first. They could be
351 * adjacent, so later reassign can not reallocate them one by one in
352 * parent resource window.
353 *
354 * Try to assign requested + add_size at beginning. If could do that,
355 * could get out early. If could not do that, we still try to assign
356 * requested at first, then try to reassign add_size for some resources.
357 *
358 * Separate three resource type checking if we need to release
359 * assigned resource after requested + add_size try.
360 *
361 * 1. If IO port assignment fails, will release assigned IO
362 * port.
363 * 2. If pref MMIO assignment fails, release assigned pref
364 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
365 * and non-pref MMIO assignment fails, will release that
366 * assigned pref MMIO.
367 * 3. If non-pref MMIO assignment fails or pref MMIO
368 * assignment fails, will release assigned non-pref MMIO.
369 */
370 LIST_HEAD(save_head);
371 LIST_HEAD(local_fail_head);
372 struct pci_dev_resource *save_res;
373 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
374 unsigned long fail_type;
375 resource_size_t add_align, align;
376
377 /* Check if optional add_size is there */
378 if (!realloc_head || list_empty(realloc_head))
379 goto requested_and_reassign;
380
381 /* Save original start, end, flags etc at first */
382 list_for_each_entry(dev_res, head, list) {
383 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
384 free_list(&save_head);
385 goto requested_and_reassign;
386 }
387 }
388
389 /* Update res in head list with add_size in realloc_head list */
390 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
391 dev_res->res->end += get_res_add_size(realloc_head,
392 dev_res->res);
393
394 /*
395 * There are two kinds of additional resources in the list:
396 * 1. bridge resource -- IORESOURCE_STARTALIGN
397 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
398 * Here just fix the additional alignment for bridge
399 */
400 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
401 continue;
402
403 add_align = get_res_add_align(realloc_head, dev_res->res);
404
405 /*
406 * The "head" list is sorted by alignment so resources with
407 * bigger alignment will be assigned first. After we
408 * change the alignment of a dev_res in "head" list, we
409 * need to reorder the list by alignment to make it
410 * consistent.
411 */
412 if (add_align > dev_res->res->start) {
413 resource_size_t r_size = resource_size(dev_res->res);
414
415 dev_res->res->start = add_align;
416 dev_res->res->end = add_align + r_size - 1;
417
418 list_for_each_entry(dev_res2, head, list) {
419 align = pci_resource_alignment(dev_res2->dev,
420 dev_res2->res);
421 if (add_align > align) {
422 list_move_tail(&dev_res->list,
423 &dev_res2->list);
424 break;
425 }
426 }
427 }
428
429 }
430
431 /* Try updated head list with add_size added */
432 assign_requested_resources_sorted(head, &local_fail_head);
433
434 /* All assigned with add_size? */
435 if (list_empty(&local_fail_head)) {
436 /* Remove head list from realloc_head list */
437 list_for_each_entry(dev_res, head, list)
438 remove_from_list(realloc_head, dev_res->res);
439 free_list(&save_head);
440 free_list(head);
441 return;
442 }
443
444 /* Check failed type */
445 fail_type = pci_fail_res_type_mask(&local_fail_head);
446 /* Remove not need to be released assigned res from head list etc */
447 list_for_each_entry_safe(dev_res, tmp_res, head, list)
448 if (dev_res->res->parent &&
449 !pci_need_to_release(fail_type, dev_res->res)) {
450 /* Remove it from realloc_head list */
451 remove_from_list(realloc_head, dev_res->res);
452 remove_from_list(&save_head, dev_res->res);
453 list_del(&dev_res->list);
454 kfree(dev_res);
455 }
456
457 free_list(&local_fail_head);
458 /* Release assigned resource */
459 list_for_each_entry(dev_res, head, list)
460 if (dev_res->res->parent)
461 release_resource(dev_res->res);
462 /* Restore start/end/flags from saved list */
463 list_for_each_entry(save_res, &save_head, list) {
464 struct resource *res = save_res->res;
465
466 res->start = save_res->start;
467 res->end = save_res->end;
468 res->flags = save_res->flags;
469 }
470 free_list(&save_head);
471
472requested_and_reassign:
473 /* Satisfy the must-have resource requests */
474 assign_requested_resources_sorted(head, fail_head);
475
476 /* Try to satisfy any additional optional resource requests */
477 if (realloc_head)
478 reassign_resources_sorted(realloc_head, head);
479 free_list(head);
480}
481
482static void pdev_assign_resources_sorted(struct pci_dev *dev,
483 struct list_head *add_head,
484 struct list_head *fail_head)
485{
486 LIST_HEAD(head);
487
488 __dev_sort_resources(dev, &head);
489 __assign_resources_sorted(&head, add_head, fail_head);
490
491}
492
493static void pbus_assign_resources_sorted(const struct pci_bus *bus,
494 struct list_head *realloc_head,
495 struct list_head *fail_head)
496{
497 struct pci_dev *dev;
498 LIST_HEAD(head);
499
500 list_for_each_entry(dev, &bus->devices, bus_list)
501 __dev_sort_resources(dev, &head);
502
503 __assign_resources_sorted(&head, realloc_head, fail_head);
504}
505
506void pci_setup_cardbus(struct pci_bus *bus)
507{
508 struct pci_dev *bridge = bus->self;
509 struct resource *res;
510 struct pci_bus_region region;
511
512 pci_info(bridge, "CardBus bridge to %pR\n",
513 &bus->busn_res);
514
515 res = bus->resource[0];
516 pcibios_resource_to_bus(bridge->bus, ®ion, res);
517 if (res->flags & IORESOURCE_IO) {
518 /*
519 * The IO resource is allocated a range twice as large as it
520 * would normally need. This allows us to set both IO regs.
521 */
522 pci_info(bridge, " bridge window %pR\n", res);
523 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
524 region.start);
525 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
526 region.end);
527 }
528
529 res = bus->resource[1];
530 pcibios_resource_to_bus(bridge->bus, ®ion, res);
531 if (res->flags & IORESOURCE_IO) {
532 pci_info(bridge, " bridge window %pR\n", res);
533 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
534 region.start);
535 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
536 region.end);
537 }
538
539 res = bus->resource[2];
540 pcibios_resource_to_bus(bridge->bus, ®ion, res);
541 if (res->flags & IORESOURCE_MEM) {
542 pci_info(bridge, " bridge window %pR\n", res);
543 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
544 region.start);
545 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
546 region.end);
547 }
548
549 res = bus->resource[3];
550 pcibios_resource_to_bus(bridge->bus, ®ion, res);
551 if (res->flags & IORESOURCE_MEM) {
552 pci_info(bridge, " bridge window %pR\n", res);
553 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
554 region.start);
555 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
556 region.end);
557 }
558}
559EXPORT_SYMBOL(pci_setup_cardbus);
560
561/*
562 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
563 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
564 * are no I/O ports or memory behind the bridge, the corresponding range
565 * must be turned off by writing base value greater than limit to the
566 * bridge's base/limit registers.
567 *
568 * Note: care must be taken when updating I/O base/limit registers of
569 * bridges which support 32-bit I/O. This update requires two config space
570 * writes, so it's quite possible that an I/O window of the bridge will
571 * have some undesirable address (e.g. 0) after the first write. Ditto
572 * 64-bit prefetchable MMIO.
573 */
574static void pci_setup_bridge_io(struct pci_dev *bridge)
575{
576 struct resource *res;
577 struct pci_bus_region region;
578 unsigned long io_mask;
579 u8 io_base_lo, io_limit_lo;
580 u16 l;
581 u32 io_upper16;
582
583 io_mask = PCI_IO_RANGE_MASK;
584 if (bridge->io_window_1k)
585 io_mask = PCI_IO_1K_RANGE_MASK;
586
587 /* Set up the top and bottom of the PCI I/O segment for this bus */
588 res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
589 pcibios_resource_to_bus(bridge->bus, ®ion, res);
590 if (res->flags & IORESOURCE_IO) {
591 pci_read_config_word(bridge, PCI_IO_BASE, &l);
592 io_base_lo = (region.start >> 8) & io_mask;
593 io_limit_lo = (region.end >> 8) & io_mask;
594 l = ((u16) io_limit_lo << 8) | io_base_lo;
595 /* Set up upper 16 bits of I/O base/limit */
596 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
597 pci_info(bridge, " bridge window %pR\n", res);
598 } else {
599 /* Clear upper 16 bits of I/O base/limit */
600 io_upper16 = 0;
601 l = 0x00f0;
602 }
603 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
604 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
605 /* Update lower 16 bits of I/O base/limit */
606 pci_write_config_word(bridge, PCI_IO_BASE, l);
607 /* Update upper 16 bits of I/O base/limit */
608 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
609}
610
611static void pci_setup_bridge_mmio(struct pci_dev *bridge)
612{
613 struct resource *res;
614 struct pci_bus_region region;
615 u32 l;
616
617 /* Set up the top and bottom of the PCI Memory segment for this bus */
618 res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
619 pcibios_resource_to_bus(bridge->bus, ®ion, res);
620 if (res->flags & IORESOURCE_MEM) {
621 l = (region.start >> 16) & 0xfff0;
622 l |= region.end & 0xfff00000;
623 pci_info(bridge, " bridge window %pR\n", res);
624 } else {
625 l = 0x0000fff0;
626 }
627 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
628}
629
630static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
631{
632 struct resource *res;
633 struct pci_bus_region region;
634 u32 l, bu, lu;
635
636 /*
637 * Clear out the upper 32 bits of PREF limit. If
638 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
639 * PREF range, which is ok.
640 */
641 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
642
643 /* Set up PREF base/limit */
644 bu = lu = 0;
645 res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
646 pcibios_resource_to_bus(bridge->bus, ®ion, res);
647 if (res->flags & IORESOURCE_PREFETCH) {
648 l = (region.start >> 16) & 0xfff0;
649 l |= region.end & 0xfff00000;
650 if (res->flags & IORESOURCE_MEM_64) {
651 bu = upper_32_bits(region.start);
652 lu = upper_32_bits(region.end);
653 }
654 pci_info(bridge, " bridge window %pR\n", res);
655 } else {
656 l = 0x0000fff0;
657 }
658 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
659
660 /* Set the upper 32 bits of PREF base & limit */
661 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
662 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
663}
664
665static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
666{
667 struct pci_dev *bridge = bus->self;
668
669 pci_info(bridge, "PCI bridge to %pR\n",
670 &bus->busn_res);
671
672 if (type & IORESOURCE_IO)
673 pci_setup_bridge_io(bridge);
674
675 if (type & IORESOURCE_MEM)
676 pci_setup_bridge_mmio(bridge);
677
678 if (type & IORESOURCE_PREFETCH)
679 pci_setup_bridge_mmio_pref(bridge);
680
681 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
682}
683
684void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
685{
686}
687
688void pci_setup_bridge(struct pci_bus *bus)
689{
690 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
691 IORESOURCE_PREFETCH;
692
693 pcibios_setup_bridge(bus, type);
694 __pci_setup_bridge(bus, type);
695}
696
697
698int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
699{
700 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
701 return 0;
702
703 if (pci_claim_resource(bridge, i) == 0)
704 return 0; /* Claimed the window */
705
706 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
707 return 0;
708
709 if (!pci_bus_clip_resource(bridge, i))
710 return -EINVAL; /* Clipping didn't change anything */
711
712 switch (i) {
713 case PCI_BRIDGE_IO_WINDOW:
714 pci_setup_bridge_io(bridge);
715 break;
716 case PCI_BRIDGE_MEM_WINDOW:
717 pci_setup_bridge_mmio(bridge);
718 break;
719 case PCI_BRIDGE_PREF_MEM_WINDOW:
720 pci_setup_bridge_mmio_pref(bridge);
721 break;
722 default:
723 return -EINVAL;
724 }
725
726 if (pci_claim_resource(bridge, i) == 0)
727 return 0; /* Claimed a smaller window */
728
729 return -EINVAL;
730}
731
732/*
733 * Check whether the bridge supports optional I/O and prefetchable memory
734 * ranges. If not, the respective base/limit registers must be read-only
735 * and read as 0.
736 */
737static void pci_bridge_check_ranges(struct pci_bus *bus)
738{
739 struct pci_dev *bridge = bus->self;
740 struct resource *b_res;
741
742 b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
743 b_res->flags |= IORESOURCE_MEM;
744
745 if (bridge->io_window) {
746 b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
747 b_res->flags |= IORESOURCE_IO;
748 }
749
750 if (bridge->pref_window) {
751 b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
752 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
753 if (bridge->pref_64_window) {
754 b_res->flags |= IORESOURCE_MEM_64 |
755 PCI_PREF_RANGE_TYPE_64;
756 }
757 }
758}
759
760/*
761 * Helper function for sizing routines. Assigned resources have non-NULL
762 * parent resource.
763 *
764 * Return first unassigned resource of the correct type. If there is none,
765 * return first assigned resource of the correct type. If none of the
766 * above, return NULL.
767 *
768 * Returning an assigned resource of the correct type allows the caller to
769 * distinguish between already assigned and no resource of the correct type.
770 */
771static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
772 unsigned long type_mask,
773 unsigned long type)
774{
775 struct resource *r, *r_assigned = NULL;
776 int i;
777
778 pci_bus_for_each_resource(bus, r, i) {
779 if (r == &ioport_resource || r == &iomem_resource)
780 continue;
781 if (r && (r->flags & type_mask) == type && !r->parent)
782 return r;
783 if (r && (r->flags & type_mask) == type && !r_assigned)
784 r_assigned = r;
785 }
786 return r_assigned;
787}
788
789static resource_size_t calculate_iosize(resource_size_t size,
790 resource_size_t min_size,
791 resource_size_t size1,
792 resource_size_t add_size,
793 resource_size_t children_add_size,
794 resource_size_t old_size,
795 resource_size_t align)
796{
797 if (size < min_size)
798 size = min_size;
799 if (old_size == 1)
800 old_size = 0;
801 /*
802 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
803 * struct pci_bus.
804 */
805#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
806 size = (size & 0xff) + ((size & ~0xffUL) << 2);
807#endif
808 size = size + size1;
809 if (size < old_size)
810 size = old_size;
811
812 size = ALIGN(max(size, add_size) + children_add_size, align);
813 return size;
814}
815
816static resource_size_t calculate_memsize(resource_size_t size,
817 resource_size_t min_size,
818 resource_size_t add_size,
819 resource_size_t children_add_size,
820 resource_size_t old_size,
821 resource_size_t align)
822{
823 if (size < min_size)
824 size = min_size;
825 if (old_size == 1)
826 old_size = 0;
827 if (size < old_size)
828 size = old_size;
829
830 size = ALIGN(max(size, add_size) + children_add_size, align);
831 return size;
832}
833
834resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
835 unsigned long type)
836{
837 return 1;
838}
839
840#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
841#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
842#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
843
844static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
845{
846 resource_size_t align = 1, arch_align;
847
848 if (type & IORESOURCE_MEM)
849 align = PCI_P2P_DEFAULT_MEM_ALIGN;
850 else if (type & IORESOURCE_IO) {
851 /*
852 * Per spec, I/O windows are 4K-aligned, but some bridges have
853 * an extension to support 1K alignment.
854 */
855 if (bus->self && bus->self->io_window_1k)
856 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
857 else
858 align = PCI_P2P_DEFAULT_IO_ALIGN;
859 }
860
861 arch_align = pcibios_window_alignment(bus, type);
862 return max(align, arch_align);
863}
864
865/**
866 * pbus_size_io() - Size the I/O window of a given bus
867 *
868 * @bus: The bus
869 * @min_size: The minimum I/O window that must be allocated
870 * @add_size: Additional optional I/O window
871 * @realloc_head: Track the additional I/O window on this list
872 *
873 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
874 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
875 * devices are limited to 256 bytes. We must be careful with the ISA
876 * aliasing though.
877 */
878static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
879 resource_size_t add_size,
880 struct list_head *realloc_head)
881{
882 struct pci_dev *dev;
883 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
884 IORESOURCE_IO);
885 resource_size_t size = 0, size0 = 0, size1 = 0;
886 resource_size_t children_add_size = 0;
887 resource_size_t min_align, align;
888
889 if (!b_res)
890 return;
891
892 /* If resource is already assigned, nothing more to do */
893 if (b_res->parent)
894 return;
895
896 min_align = window_alignment(bus, IORESOURCE_IO);
897 list_for_each_entry(dev, &bus->devices, bus_list) {
898 int i;
899
900 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
901 struct resource *r = &dev->resource[i];
902 unsigned long r_size;
903
904 if (r->parent || !(r->flags & IORESOURCE_IO))
905 continue;
906 r_size = resource_size(r);
907
908 if (r_size < 0x400)
909 /* Might be re-aligned for ISA */
910 size += r_size;
911 else
912 size1 += r_size;
913
914 align = pci_resource_alignment(dev, r);
915 if (align > min_align)
916 min_align = align;
917
918 if (realloc_head)
919 children_add_size += get_res_add_size(realloc_head, r);
920 }
921 }
922
923 size0 = calculate_iosize(size, min_size, size1, 0, 0,
924 resource_size(b_res), min_align);
925 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
926 calculate_iosize(size, min_size, size1, add_size, children_add_size,
927 resource_size(b_res), min_align);
928 if (!size0 && !size1) {
929 if (bus->self && (b_res->start || b_res->end))
930 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
931 b_res, &bus->busn_res);
932 b_res->flags = 0;
933 return;
934 }
935
936 b_res->start = min_align;
937 b_res->end = b_res->start + size0 - 1;
938 b_res->flags |= IORESOURCE_STARTALIGN;
939 if (bus->self && size1 > size0 && realloc_head) {
940 add_to_list(realloc_head, bus->self, b_res, size1-size0,
941 min_align);
942 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
943 b_res, &bus->busn_res,
944 (unsigned long long) size1 - size0);
945 }
946}
947
948static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
949 int max_order)
950{
951 resource_size_t align = 0;
952 resource_size_t min_align = 0;
953 int order;
954
955 for (order = 0; order <= max_order; order++) {
956 resource_size_t align1 = 1;
957
958 align1 <<= (order + 20);
959
960 if (!align)
961 min_align = align1;
962 else if (ALIGN(align + min_align, min_align) < align1)
963 min_align = align1 >> 1;
964 align += aligns[order];
965 }
966
967 return min_align;
968}
969
970/**
971 * pbus_size_mem() - Size the memory window of a given bus
972 *
973 * @bus: The bus
974 * @mask: Mask the resource flag, then compare it with type
975 * @type: The type of free resource from bridge
976 * @type2: Second match type
977 * @type3: Third match type
978 * @min_size: The minimum memory window that must be allocated
979 * @add_size: Additional optional memory window
980 * @realloc_head: Track the additional memory window on this list
981 *
982 * Calculate the size of the bus and minimal alignment which guarantees
983 * that all child resources fit in this size.
984 *
985 * Return -ENOSPC if there's no available bus resource of the desired
986 * type. Otherwise, set the bus resource start/end to indicate the
987 * required size, add things to realloc_head (if supplied), and return 0.
988 */
989static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
990 unsigned long type, unsigned long type2,
991 unsigned long type3, resource_size_t min_size,
992 resource_size_t add_size,
993 struct list_head *realloc_head)
994{
995 struct pci_dev *dev;
996 resource_size_t min_align, align, size, size0, size1;
997 resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
998 int order, max_order;
999 struct resource *b_res = find_bus_resource_of_type(bus,
1000 mask | IORESOURCE_PREFETCH, type);
1001 resource_size_t children_add_size = 0;
1002 resource_size_t children_add_align = 0;
1003 resource_size_t add_align = 0;
1004
1005 if (!b_res)
1006 return -ENOSPC;
1007
1008 /* If resource is already assigned, nothing more to do */
1009 if (b_res->parent)
1010 return 0;
1011
1012 memset(aligns, 0, sizeof(aligns));
1013 max_order = 0;
1014 size = 0;
1015
1016 list_for_each_entry(dev, &bus->devices, bus_list) {
1017 int i;
1018
1019 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1020 struct resource *r = &dev->resource[i];
1021 resource_size_t r_size;
1022
1023 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1024 ((r->flags & mask) != type &&
1025 (r->flags & mask) != type2 &&
1026 (r->flags & mask) != type3))
1027 continue;
1028 r_size = resource_size(r);
1029#ifdef CONFIG_PCI_IOV
1030 /* Put SRIOV requested res to the optional list */
1031 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1032 i <= PCI_IOV_RESOURCE_END) {
1033 add_align = max(pci_resource_alignment(dev, r), add_align);
1034 r->end = r->start - 1;
1035 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1036 children_add_size += r_size;
1037 continue;
1038 }
1039#endif
1040 /*
1041 * aligns[0] is for 1MB (since bridge memory
1042 * windows are always at least 1MB aligned), so
1043 * keep "order" from being negative for smaller
1044 * resources.
1045 */
1046 align = pci_resource_alignment(dev, r);
1047 order = __ffs(align) - 20;
1048 if (order < 0)
1049 order = 0;
1050 if (order >= ARRAY_SIZE(aligns)) {
1051 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1052 i, r, (unsigned long long) align);
1053 r->flags = 0;
1054 continue;
1055 }
1056 size += max(r_size, align);
1057 /*
1058 * Exclude ranges with size > align from calculation of
1059 * the alignment.
1060 */
1061 if (r_size <= align)
1062 aligns[order] += align;
1063 if (order > max_order)
1064 max_order = order;
1065
1066 if (realloc_head) {
1067 children_add_size += get_res_add_size(realloc_head, r);
1068 children_add_align = get_res_add_align(realloc_head, r);
1069 add_align = max(add_align, children_add_align);
1070 }
1071 }
1072 }
1073
1074 min_align = calculate_mem_align(aligns, max_order);
1075 min_align = max(min_align, window_alignment(bus, b_res->flags));
1076 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1077 add_align = max(min_align, add_align);
1078 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1079 calculate_memsize(size, min_size, add_size, children_add_size,
1080 resource_size(b_res), add_align);
1081 if (!size0 && !size1) {
1082 if (bus->self && (b_res->start || b_res->end))
1083 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1084 b_res, &bus->busn_res);
1085 b_res->flags = 0;
1086 return 0;
1087 }
1088 b_res->start = min_align;
1089 b_res->end = size0 + min_align - 1;
1090 b_res->flags |= IORESOURCE_STARTALIGN;
1091 if (bus->self && size1 > size0 && realloc_head) {
1092 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1093 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1094 b_res, &bus->busn_res,
1095 (unsigned long long) (size1 - size0),
1096 (unsigned long long) add_align);
1097 }
1098 return 0;
1099}
1100
1101unsigned long pci_cardbus_resource_alignment(struct resource *res)
1102{
1103 if (res->flags & IORESOURCE_IO)
1104 return pci_cardbus_io_size;
1105 if (res->flags & IORESOURCE_MEM)
1106 return pci_cardbus_mem_size;
1107 return 0;
1108}
1109
1110static void pci_bus_size_cardbus(struct pci_bus *bus,
1111 struct list_head *realloc_head)
1112{
1113 struct pci_dev *bridge = bus->self;
1114 struct resource *b_res;
1115 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1116 u16 ctrl;
1117
1118 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
1119 if (b_res->parent)
1120 goto handle_b_res_1;
1121 /*
1122 * Reserve some resources for CardBus. We reserve a fixed amount
1123 * of bus space for CardBus bridges.
1124 */
1125 b_res->start = pci_cardbus_io_size;
1126 b_res->end = b_res->start + pci_cardbus_io_size - 1;
1127 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1128 if (realloc_head) {
1129 b_res->end -= pci_cardbus_io_size;
1130 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1131 pci_cardbus_io_size);
1132 }
1133
1134handle_b_res_1:
1135 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
1136 if (b_res->parent)
1137 goto handle_b_res_2;
1138 b_res->start = pci_cardbus_io_size;
1139 b_res->end = b_res->start + pci_cardbus_io_size - 1;
1140 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1141 if (realloc_head) {
1142 b_res->end -= pci_cardbus_io_size;
1143 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1144 pci_cardbus_io_size);
1145 }
1146
1147handle_b_res_2:
1148 /* MEM1 must not be pref MMIO */
1149 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1150 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1151 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1152 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1153 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1154 }
1155
1156 /* Check whether prefetchable memory is supported by this bridge. */
1157 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1158 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1159 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1160 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1161 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1162 }
1163
1164 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
1165 if (b_res->parent)
1166 goto handle_b_res_3;
1167 /*
1168 * If we have prefetchable memory support, allocate two regions.
1169 * Otherwise, allocate one region of twice the size.
1170 */
1171 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1172 b_res->start = pci_cardbus_mem_size;
1173 b_res->end = b_res->start + pci_cardbus_mem_size - 1;
1174 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1175 IORESOURCE_STARTALIGN;
1176 if (realloc_head) {
1177 b_res->end -= pci_cardbus_mem_size;
1178 add_to_list(realloc_head, bridge, b_res,
1179 pci_cardbus_mem_size, pci_cardbus_mem_size);
1180 }
1181
1182 /* Reduce that to half */
1183 b_res_3_size = pci_cardbus_mem_size;
1184 }
1185
1186handle_b_res_3:
1187 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
1188 if (b_res->parent)
1189 goto handle_done;
1190 b_res->start = pci_cardbus_mem_size;
1191 b_res->end = b_res->start + b_res_3_size - 1;
1192 b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1193 if (realloc_head) {
1194 b_res->end -= b_res_3_size;
1195 add_to_list(realloc_head, bridge, b_res, b_res_3_size,
1196 pci_cardbus_mem_size);
1197 }
1198
1199handle_done:
1200 ;
1201}
1202
1203void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1204{
1205 struct pci_dev *dev;
1206 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1207 resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1208 additional_mmio_pref_size = 0;
1209 struct resource *pref;
1210 struct pci_host_bridge *host;
1211 int hdr_type, i, ret;
1212
1213 list_for_each_entry(dev, &bus->devices, bus_list) {
1214 struct pci_bus *b = dev->subordinate;
1215 if (!b)
1216 continue;
1217
1218 switch (dev->hdr_type) {
1219 case PCI_HEADER_TYPE_CARDBUS:
1220 pci_bus_size_cardbus(b, realloc_head);
1221 break;
1222
1223 case PCI_HEADER_TYPE_BRIDGE:
1224 default:
1225 __pci_bus_size_bridges(b, realloc_head);
1226 break;
1227 }
1228 }
1229
1230 /* The root bus? */
1231 if (pci_is_root_bus(bus)) {
1232 host = to_pci_host_bridge(bus->bridge);
1233 if (!host->size_windows)
1234 return;
1235 pci_bus_for_each_resource(bus, pref, i)
1236 if (pref && (pref->flags & IORESOURCE_PREFETCH))
1237 break;
1238 hdr_type = -1; /* Intentionally invalid - not a PCI device. */
1239 } else {
1240 pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1241 hdr_type = bus->self->hdr_type;
1242 }
1243
1244 switch (hdr_type) {
1245 case PCI_HEADER_TYPE_CARDBUS:
1246 /* Don't size CardBuses yet */
1247 break;
1248
1249 case PCI_HEADER_TYPE_BRIDGE:
1250 pci_bridge_check_ranges(bus);
1251 if (bus->self->is_hotplug_bridge) {
1252 additional_io_size = pci_hotplug_io_size;
1253 additional_mmio_size = pci_hotplug_mmio_size;
1254 additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1255 }
1256 fallthrough;
1257 default:
1258 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1259 additional_io_size, realloc_head);
1260
1261 /*
1262 * If there's a 64-bit prefetchable MMIO window, compute
1263 * the size required to put all 64-bit prefetchable
1264 * resources in it.
1265 */
1266 mask = IORESOURCE_MEM;
1267 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1268 if (pref && (pref->flags & IORESOURCE_MEM_64)) {
1269 prefmask |= IORESOURCE_MEM_64;
1270 ret = pbus_size_mem(bus, prefmask, prefmask,
1271 prefmask, prefmask,
1272 realloc_head ? 0 : additional_mmio_pref_size,
1273 additional_mmio_pref_size, realloc_head);
1274
1275 /*
1276 * If successful, all non-prefetchable resources
1277 * and any 32-bit prefetchable resources will go in
1278 * the non-prefetchable window.
1279 */
1280 if (ret == 0) {
1281 mask = prefmask;
1282 type2 = prefmask & ~IORESOURCE_MEM_64;
1283 type3 = prefmask & ~IORESOURCE_PREFETCH;
1284 }
1285 }
1286
1287 /*
1288 * If there is no 64-bit prefetchable window, compute the
1289 * size required to put all prefetchable resources in the
1290 * 32-bit prefetchable window (if there is one).
1291 */
1292 if (!type2) {
1293 prefmask &= ~IORESOURCE_MEM_64;
1294 ret = pbus_size_mem(bus, prefmask, prefmask,
1295 prefmask, prefmask,
1296 realloc_head ? 0 : additional_mmio_pref_size,
1297 additional_mmio_pref_size, realloc_head);
1298
1299 /*
1300 * If successful, only non-prefetchable resources
1301 * will go in the non-prefetchable window.
1302 */
1303 if (ret == 0)
1304 mask = prefmask;
1305 else
1306 additional_mmio_size += additional_mmio_pref_size;
1307
1308 type2 = type3 = IORESOURCE_MEM;
1309 }
1310
1311 /*
1312 * Compute the size required to put everything else in the
1313 * non-prefetchable window. This includes:
1314 *
1315 * - all non-prefetchable resources
1316 * - 32-bit prefetchable resources if there's a 64-bit
1317 * prefetchable window or no prefetchable window at all
1318 * - 64-bit prefetchable resources if there's no prefetchable
1319 * window at all
1320 *
1321 * Note that the strategy in __pci_assign_resource() must match
1322 * that used here. Specifically, we cannot put a 32-bit
1323 * prefetchable resource in a 64-bit prefetchable window.
1324 */
1325 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1326 realloc_head ? 0 : additional_mmio_size,
1327 additional_mmio_size, realloc_head);
1328 break;
1329 }
1330}
1331
1332void pci_bus_size_bridges(struct pci_bus *bus)
1333{
1334 __pci_bus_size_bridges(bus, NULL);
1335}
1336EXPORT_SYMBOL(pci_bus_size_bridges);
1337
1338static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1339{
1340 int i;
1341 struct resource *parent_r;
1342 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1343 IORESOURCE_PREFETCH;
1344
1345 pci_bus_for_each_resource(b, parent_r, i) {
1346 if (!parent_r)
1347 continue;
1348
1349 if ((r->flags & mask) == (parent_r->flags & mask) &&
1350 resource_contains(parent_r, r))
1351 request_resource(parent_r, r);
1352 }
1353}
1354
1355/*
1356 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1357 * skipped by pbus_assign_resources_sorted().
1358 */
1359static void pdev_assign_fixed_resources(struct pci_dev *dev)
1360{
1361 int i;
1362
1363 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1364 struct pci_bus *b;
1365 struct resource *r = &dev->resource[i];
1366
1367 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1368 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1369 continue;
1370
1371 b = dev->bus;
1372 while (b && !r->parent) {
1373 assign_fixed_resource_on_bus(b, r);
1374 b = b->parent;
1375 }
1376 }
1377}
1378
1379void __pci_bus_assign_resources(const struct pci_bus *bus,
1380 struct list_head *realloc_head,
1381 struct list_head *fail_head)
1382{
1383 struct pci_bus *b;
1384 struct pci_dev *dev;
1385
1386 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1387
1388 list_for_each_entry(dev, &bus->devices, bus_list) {
1389 pdev_assign_fixed_resources(dev);
1390
1391 b = dev->subordinate;
1392 if (!b)
1393 continue;
1394
1395 __pci_bus_assign_resources(b, realloc_head, fail_head);
1396
1397 switch (dev->hdr_type) {
1398 case PCI_HEADER_TYPE_BRIDGE:
1399 if (!pci_is_enabled(dev))
1400 pci_setup_bridge(b);
1401 break;
1402
1403 case PCI_HEADER_TYPE_CARDBUS:
1404 pci_setup_cardbus(b);
1405 break;
1406
1407 default:
1408 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1409 pci_domain_nr(b), b->number);
1410 break;
1411 }
1412 }
1413}
1414
1415void pci_bus_assign_resources(const struct pci_bus *bus)
1416{
1417 __pci_bus_assign_resources(bus, NULL, NULL);
1418}
1419EXPORT_SYMBOL(pci_bus_assign_resources);
1420
1421static void pci_claim_device_resources(struct pci_dev *dev)
1422{
1423 int i;
1424
1425 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1426 struct resource *r = &dev->resource[i];
1427
1428 if (!r->flags || r->parent)
1429 continue;
1430
1431 pci_claim_resource(dev, i);
1432 }
1433}
1434
1435static void pci_claim_bridge_resources(struct pci_dev *dev)
1436{
1437 int i;
1438
1439 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1440 struct resource *r = &dev->resource[i];
1441
1442 if (!r->flags || r->parent)
1443 continue;
1444
1445 pci_claim_bridge_resource(dev, i);
1446 }
1447}
1448
1449static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1450{
1451 struct pci_dev *dev;
1452 struct pci_bus *child;
1453
1454 list_for_each_entry(dev, &b->devices, bus_list) {
1455 pci_claim_device_resources(dev);
1456
1457 child = dev->subordinate;
1458 if (child)
1459 pci_bus_allocate_dev_resources(child);
1460 }
1461}
1462
1463static void pci_bus_allocate_resources(struct pci_bus *b)
1464{
1465 struct pci_bus *child;
1466
1467 /*
1468 * Carry out a depth-first search on the PCI bus tree to allocate
1469 * bridge apertures. Read the programmed bridge bases and
1470 * recursively claim the respective bridge resources.
1471 */
1472 if (b->self) {
1473 pci_read_bridge_bases(b);
1474 pci_claim_bridge_resources(b->self);
1475 }
1476
1477 list_for_each_entry(child, &b->children, node)
1478 pci_bus_allocate_resources(child);
1479}
1480
1481void pci_bus_claim_resources(struct pci_bus *b)
1482{
1483 pci_bus_allocate_resources(b);
1484 pci_bus_allocate_dev_resources(b);
1485}
1486EXPORT_SYMBOL(pci_bus_claim_resources);
1487
1488static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1489 struct list_head *add_head,
1490 struct list_head *fail_head)
1491{
1492 struct pci_bus *b;
1493
1494 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1495 add_head, fail_head);
1496
1497 b = bridge->subordinate;
1498 if (!b)
1499 return;
1500
1501 __pci_bus_assign_resources(b, add_head, fail_head);
1502
1503 switch (bridge->class >> 8) {
1504 case PCI_CLASS_BRIDGE_PCI:
1505 pci_setup_bridge(b);
1506 break;
1507
1508 case PCI_CLASS_BRIDGE_CARDBUS:
1509 pci_setup_cardbus(b);
1510 break;
1511
1512 default:
1513 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1514 pci_domain_nr(b), b->number);
1515 break;
1516 }
1517}
1518
1519#define PCI_RES_TYPE_MASK \
1520 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1521 IORESOURCE_MEM_64)
1522
1523static void pci_bridge_release_resources(struct pci_bus *bus,
1524 unsigned long type)
1525{
1526 struct pci_dev *dev = bus->self;
1527 struct resource *r;
1528 unsigned int old_flags;
1529 struct resource *b_res;
1530 int idx = 1;
1531
1532 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1533
1534 /*
1535 * 1. If IO port assignment fails, release bridge IO port.
1536 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1537 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1538 * release bridge pref MMIO.
1539 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1540 * release bridge pref MMIO.
1541 * 5. If pref MMIO assignment fails, and bridge pref is not
1542 * assigned, release bridge nonpref MMIO.
1543 */
1544 if (type & IORESOURCE_IO)
1545 idx = 0;
1546 else if (!(type & IORESOURCE_PREFETCH))
1547 idx = 1;
1548 else if ((type & IORESOURCE_MEM_64) &&
1549 (b_res[2].flags & IORESOURCE_MEM_64))
1550 idx = 2;
1551 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1552 (b_res[2].flags & IORESOURCE_PREFETCH))
1553 idx = 2;
1554 else
1555 idx = 1;
1556
1557 r = &b_res[idx];
1558
1559 if (!r->parent)
1560 return;
1561
1562 /* If there are children, release them all */
1563 release_child_resources(r);
1564 if (!release_resource(r)) {
1565 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1566 pci_info(dev, "resource %d %pR released\n",
1567 PCI_BRIDGE_RESOURCES + idx, r);
1568 /* Keep the old size */
1569 r->end = resource_size(r) - 1;
1570 r->start = 0;
1571 r->flags = 0;
1572
1573 /* Avoiding touch the one without PREF */
1574 if (type & IORESOURCE_PREFETCH)
1575 type = IORESOURCE_PREFETCH;
1576 __pci_setup_bridge(bus, type);
1577 /* For next child res under same bridge */
1578 r->flags = old_flags;
1579 }
1580}
1581
1582enum release_type {
1583 leaf_only,
1584 whole_subtree,
1585};
1586
1587/*
1588 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1589 * a larger window later.
1590 */
1591static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1592 unsigned long type,
1593 enum release_type rel_type)
1594{
1595 struct pci_dev *dev;
1596 bool is_leaf_bridge = true;
1597
1598 list_for_each_entry(dev, &bus->devices, bus_list) {
1599 struct pci_bus *b = dev->subordinate;
1600 if (!b)
1601 continue;
1602
1603 is_leaf_bridge = false;
1604
1605 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1606 continue;
1607
1608 if (rel_type == whole_subtree)
1609 pci_bus_release_bridge_resources(b, type,
1610 whole_subtree);
1611 }
1612
1613 if (pci_is_root_bus(bus))
1614 return;
1615
1616 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1617 return;
1618
1619 if ((rel_type == whole_subtree) || is_leaf_bridge)
1620 pci_bridge_release_resources(bus, type);
1621}
1622
1623static void pci_bus_dump_res(struct pci_bus *bus)
1624{
1625 struct resource *res;
1626 int i;
1627
1628 pci_bus_for_each_resource(bus, res, i) {
1629 if (!res || !res->end || !res->flags)
1630 continue;
1631
1632 dev_info(&bus->dev, "resource %d %pR\n", i, res);
1633 }
1634}
1635
1636static void pci_bus_dump_resources(struct pci_bus *bus)
1637{
1638 struct pci_bus *b;
1639 struct pci_dev *dev;
1640
1641
1642 pci_bus_dump_res(bus);
1643
1644 list_for_each_entry(dev, &bus->devices, bus_list) {
1645 b = dev->subordinate;
1646 if (!b)
1647 continue;
1648
1649 pci_bus_dump_resources(b);
1650 }
1651}
1652
1653static int pci_bus_get_depth(struct pci_bus *bus)
1654{
1655 int depth = 0;
1656 struct pci_bus *child_bus;
1657
1658 list_for_each_entry(child_bus, &bus->children, node) {
1659 int ret;
1660
1661 ret = pci_bus_get_depth(child_bus);
1662 if (ret + 1 > depth)
1663 depth = ret + 1;
1664 }
1665
1666 return depth;
1667}
1668
1669/*
1670 * -1: undefined, will auto detect later
1671 * 0: disabled by user
1672 * 1: disabled by auto detect
1673 * 2: enabled by user
1674 * 3: enabled by auto detect
1675 */
1676enum enable_type {
1677 undefined = -1,
1678 user_disabled,
1679 auto_disabled,
1680 user_enabled,
1681 auto_enabled,
1682};
1683
1684static enum enable_type pci_realloc_enable = undefined;
1685void __init pci_realloc_get_opt(char *str)
1686{
1687 if (!strncmp(str, "off", 3))
1688 pci_realloc_enable = user_disabled;
1689 else if (!strncmp(str, "on", 2))
1690 pci_realloc_enable = user_enabled;
1691}
1692static bool pci_realloc_enabled(enum enable_type enable)
1693{
1694 return enable >= user_enabled;
1695}
1696
1697#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1698static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1699{
1700 int i;
1701 bool *unassigned = data;
1702
1703 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1704 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1705 struct pci_bus_region region;
1706
1707 /* Not assigned or rejected by kernel? */
1708 if (!r->flags)
1709 continue;
1710
1711 pcibios_resource_to_bus(dev->bus, ®ion, r);
1712 if (!region.start) {
1713 *unassigned = true;
1714 return 1; /* Return early from pci_walk_bus() */
1715 }
1716 }
1717
1718 return 0;
1719}
1720
1721static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1722 enum enable_type enable_local)
1723{
1724 bool unassigned = false;
1725 struct pci_host_bridge *host;
1726
1727 if (enable_local != undefined)
1728 return enable_local;
1729
1730 host = pci_find_host_bridge(bus);
1731 if (host->preserve_config)
1732 return auto_disabled;
1733
1734 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1735 if (unassigned)
1736 return auto_enabled;
1737
1738 return enable_local;
1739}
1740#else
1741static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1742 enum enable_type enable_local)
1743{
1744 return enable_local;
1745}
1746#endif
1747
1748static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1749 struct list_head *add_list,
1750 resource_size_t new_size)
1751{
1752 resource_size_t add_size, size = resource_size(res);
1753
1754 if (res->parent)
1755 return;
1756
1757 if (!new_size)
1758 return;
1759
1760 if (new_size > size) {
1761 add_size = new_size - size;
1762 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1763 &add_size);
1764 } else if (new_size < size) {
1765 add_size = size - new_size;
1766 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1767 &add_size);
1768 }
1769
1770 res->end = res->start + new_size - 1;
1771 remove_from_list(add_list, res);
1772}
1773
1774static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1775 struct list_head *add_list,
1776 struct resource io,
1777 struct resource mmio,
1778 struct resource mmio_pref)
1779{
1780 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1781 struct resource *io_res, *mmio_res, *mmio_pref_res;
1782 struct pci_dev *dev, *bridge = bus->self;
1783 resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
1784
1785 io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
1786 mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
1787 mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1788
1789 /*
1790 * The alignment of this bridge is yet to be considered, hence it must
1791 * be done now before extending its bridge window.
1792 */
1793 align = pci_resource_alignment(bridge, io_res);
1794 if (!io_res->parent && align)
1795 io.start = min(ALIGN(io.start, align), io.end + 1);
1796
1797 align = pci_resource_alignment(bridge, mmio_res);
1798 if (!mmio_res->parent && align)
1799 mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
1800
1801 align = pci_resource_alignment(bridge, mmio_pref_res);
1802 if (!mmio_pref_res->parent && align)
1803 mmio_pref.start = min(ALIGN(mmio_pref.start, align),
1804 mmio_pref.end + 1);
1805
1806 /*
1807 * Now that we have adjusted for alignment, update the bridge window
1808 * resources to fill as much remaining resource space as possible.
1809 */
1810 adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
1811 adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
1812 adjust_bridge_window(bridge, mmio_pref_res, add_list,
1813 resource_size(&mmio_pref));
1814
1815 /*
1816 * Calculate how many hotplug bridges and normal bridges there
1817 * are on this bus. We will distribute the additional available
1818 * resources between hotplug bridges.
1819 */
1820 for_each_pci_bridge(dev, bus) {
1821 if (dev->is_hotplug_bridge)
1822 hotplug_bridges++;
1823 else
1824 normal_bridges++;
1825 }
1826
1827 /*
1828 * There is only one bridge on the bus so it gets all available
1829 * resources which it can then distribute to the possible hotplug
1830 * bridges below.
1831 */
1832 if (hotplug_bridges + normal_bridges == 1) {
1833 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1834 if (dev->subordinate)
1835 pci_bus_distribute_available_resources(dev->subordinate,
1836 add_list, io, mmio, mmio_pref);
1837 return;
1838 }
1839
1840 if (hotplug_bridges == 0)
1841 return;
1842
1843 /*
1844 * Calculate the total amount of extra resource space we can
1845 * pass to bridges below this one. This is basically the
1846 * extra space reduced by the minimal required space for the
1847 * non-hotplug bridges.
1848 */
1849 for_each_pci_bridge(dev, bus) {
1850 resource_size_t used_size;
1851 struct resource *res;
1852
1853 if (dev->is_hotplug_bridge)
1854 continue;
1855
1856 /*
1857 * Reduce the available resource space by what the
1858 * bridge and devices below it occupy.
1859 */
1860 res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
1861 align = pci_resource_alignment(dev, res);
1862 align = align ? ALIGN(io.start, align) - io.start : 0;
1863 used_size = align + resource_size(res);
1864 if (!res->parent)
1865 io.start = min(io.start + used_size, io.end + 1);
1866
1867 res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
1868 align = pci_resource_alignment(dev, res);
1869 align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
1870 used_size = align + resource_size(res);
1871 if (!res->parent)
1872 mmio.start = min(mmio.start + used_size, mmio.end + 1);
1873
1874 res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1875 align = pci_resource_alignment(dev, res);
1876 align = align ? ALIGN(mmio_pref.start, align) -
1877 mmio_pref.start : 0;
1878 used_size = align + resource_size(res);
1879 if (!res->parent)
1880 mmio_pref.start = min(mmio_pref.start + used_size,
1881 mmio_pref.end + 1);
1882 }
1883
1884 io_per_hp = div64_ul(resource_size(&io), hotplug_bridges);
1885 mmio_per_hp = div64_ul(resource_size(&mmio), hotplug_bridges);
1886 mmio_pref_per_hp = div64_ul(resource_size(&mmio_pref),
1887 hotplug_bridges);
1888
1889 /*
1890 * Go over devices on this bus and distribute the remaining
1891 * resource space between hotplug bridges.
1892 */
1893 for_each_pci_bridge(dev, bus) {
1894 struct pci_bus *b;
1895
1896 b = dev->subordinate;
1897 if (!b || !dev->is_hotplug_bridge)
1898 continue;
1899
1900 /*
1901 * Distribute available extra resources equally between
1902 * hotplug-capable downstream ports taking alignment into
1903 * account.
1904 */
1905 io.end = io.start + io_per_hp - 1;
1906 mmio.end = mmio.start + mmio_per_hp - 1;
1907 mmio_pref.end = mmio_pref.start + mmio_pref_per_hp - 1;
1908
1909 pci_bus_distribute_available_resources(b, add_list, io, mmio,
1910 mmio_pref);
1911
1912 io.start += io_per_hp;
1913 mmio.start += mmio_per_hp;
1914 mmio_pref.start += mmio_pref_per_hp;
1915 }
1916}
1917
1918static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
1919 struct list_head *add_list)
1920{
1921 struct resource available_io, available_mmio, available_mmio_pref;
1922
1923 if (!bridge->is_hotplug_bridge)
1924 return;
1925
1926 /* Take the initial extra resources from the hotplug port */
1927 available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
1928 available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
1929 available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1930
1931 pci_bus_distribute_available_resources(bridge->subordinate,
1932 add_list, available_io,
1933 available_mmio,
1934 available_mmio_pref);
1935}
1936
1937/*
1938 * First try will not touch PCI bridge res.
1939 * Second and later try will clear small leaf bridge res.
1940 * Will stop till to the max depth if can not find good one.
1941 */
1942void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1943{
1944 LIST_HEAD(realloc_head);
1945 /* List of resources that want additional resources */
1946 struct list_head *add_list = NULL;
1947 int tried_times = 0;
1948 enum release_type rel_type = leaf_only;
1949 LIST_HEAD(fail_head);
1950 struct pci_dev_resource *fail_res;
1951 int pci_try_num = 1;
1952 enum enable_type enable_local;
1953
1954 /* Don't realloc if asked to do so */
1955 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1956 if (pci_realloc_enabled(enable_local)) {
1957 int max_depth = pci_bus_get_depth(bus);
1958
1959 pci_try_num = max_depth + 1;
1960 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
1961 max_depth, pci_try_num);
1962 }
1963
1964again:
1965 /*
1966 * Last try will use add_list, otherwise will try good to have as must
1967 * have, so can realloc parent bridge resource
1968 */
1969 if (tried_times + 1 == pci_try_num)
1970 add_list = &realloc_head;
1971 /*
1972 * Depth first, calculate sizes and alignments of all subordinate buses.
1973 */
1974 __pci_bus_size_bridges(bus, add_list);
1975
1976 /* Depth last, allocate resources and update the hardware. */
1977 __pci_bus_assign_resources(bus, add_list, &fail_head);
1978 if (add_list)
1979 BUG_ON(!list_empty(add_list));
1980 tried_times++;
1981
1982 /* Any device complain? */
1983 if (list_empty(&fail_head))
1984 goto dump;
1985
1986 if (tried_times >= pci_try_num) {
1987 if (enable_local == undefined)
1988 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1989 else if (enable_local == auto_enabled)
1990 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1991
1992 free_list(&fail_head);
1993 goto dump;
1994 }
1995
1996 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1997 tried_times + 1);
1998
1999 /* Third times and later will not check if it is leaf */
2000 if ((tried_times + 1) > 2)
2001 rel_type = whole_subtree;
2002
2003 /*
2004 * Try to release leaf bridge's resources that doesn't fit resource of
2005 * child device under that bridge.
2006 */
2007 list_for_each_entry(fail_res, &fail_head, list)
2008 pci_bus_release_bridge_resources(fail_res->dev->bus,
2009 fail_res->flags & PCI_RES_TYPE_MASK,
2010 rel_type);
2011
2012 /* Restore size and flags */
2013 list_for_each_entry(fail_res, &fail_head, list) {
2014 struct resource *res = fail_res->res;
2015 int idx;
2016
2017 res->start = fail_res->start;
2018 res->end = fail_res->end;
2019 res->flags = fail_res->flags;
2020
2021 if (pci_is_bridge(fail_res->dev)) {
2022 idx = res - &fail_res->dev->resource[0];
2023 if (idx >= PCI_BRIDGE_RESOURCES &&
2024 idx <= PCI_BRIDGE_RESOURCE_END)
2025 res->flags = 0;
2026 }
2027 }
2028 free_list(&fail_head);
2029
2030 goto again;
2031
2032dump:
2033 /* Dump the resource on buses */
2034 pci_bus_dump_resources(bus);
2035}
2036
2037void __init pci_assign_unassigned_resources(void)
2038{
2039 struct pci_bus *root_bus;
2040
2041 list_for_each_entry(root_bus, &pci_root_buses, node) {
2042 pci_assign_unassigned_root_bus_resources(root_bus);
2043
2044 /* Make sure the root bridge has a companion ACPI device */
2045 if (ACPI_HANDLE(root_bus->bridge))
2046 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
2047 }
2048}
2049
2050void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2051{
2052 struct pci_bus *parent = bridge->subordinate;
2053 /* List of resources that want additional resources */
2054 LIST_HEAD(add_list);
2055
2056 int tried_times = 0;
2057 LIST_HEAD(fail_head);
2058 struct pci_dev_resource *fail_res;
2059 int retval;
2060
2061again:
2062 __pci_bus_size_bridges(parent, &add_list);
2063
2064 /*
2065 * Distribute remaining resources (if any) equally between hotplug
2066 * bridges below. This makes it possible to extend the hierarchy
2067 * later without running out of resources.
2068 */
2069 pci_bridge_distribute_available_resources(bridge, &add_list);
2070
2071 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2072 BUG_ON(!list_empty(&add_list));
2073 tried_times++;
2074
2075 if (list_empty(&fail_head))
2076 goto enable_all;
2077
2078 if (tried_times >= 2) {
2079 /* Still fail, don't need to try more */
2080 free_list(&fail_head);
2081 goto enable_all;
2082 }
2083
2084 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2085 tried_times + 1);
2086
2087 /*
2088 * Try to release leaf bridge's resources that aren't big enough
2089 * to contain child device resources.
2090 */
2091 list_for_each_entry(fail_res, &fail_head, list)
2092 pci_bus_release_bridge_resources(fail_res->dev->bus,
2093 fail_res->flags & PCI_RES_TYPE_MASK,
2094 whole_subtree);
2095
2096 /* Restore size and flags */
2097 list_for_each_entry(fail_res, &fail_head, list) {
2098 struct resource *res = fail_res->res;
2099 int idx;
2100
2101 res->start = fail_res->start;
2102 res->end = fail_res->end;
2103 res->flags = fail_res->flags;
2104
2105 if (pci_is_bridge(fail_res->dev)) {
2106 idx = res - &fail_res->dev->resource[0];
2107 if (idx >= PCI_BRIDGE_RESOURCES &&
2108 idx <= PCI_BRIDGE_RESOURCE_END)
2109 res->flags = 0;
2110 }
2111 }
2112 free_list(&fail_head);
2113
2114 goto again;
2115
2116enable_all:
2117 retval = pci_reenable_device(bridge);
2118 if (retval)
2119 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2120 pci_set_master(bridge);
2121}
2122EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2123
2124int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2125{
2126 struct pci_dev_resource *dev_res;
2127 struct pci_dev *next;
2128 LIST_HEAD(saved);
2129 LIST_HEAD(added);
2130 LIST_HEAD(failed);
2131 unsigned int i;
2132 int ret;
2133
2134 down_read(&pci_bus_sem);
2135
2136 /* Walk to the root hub, releasing bridge BARs when possible */
2137 next = bridge;
2138 do {
2139 bridge = next;
2140 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2141 i++) {
2142 struct resource *res = &bridge->resource[i];
2143
2144 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2145 continue;
2146
2147 /* Ignore BARs which are still in use */
2148 if (res->child)
2149 continue;
2150
2151 ret = add_to_list(&saved, bridge, res, 0, 0);
2152 if (ret)
2153 goto cleanup;
2154
2155 pci_info(bridge, "BAR %d: releasing %pR\n",
2156 i, res);
2157
2158 if (res->parent)
2159 release_resource(res);
2160 res->start = 0;
2161 res->end = 0;
2162 break;
2163 }
2164 if (i == PCI_BRIDGE_RESOURCE_END)
2165 break;
2166
2167 next = bridge->bus ? bridge->bus->self : NULL;
2168 } while (next);
2169
2170 if (list_empty(&saved)) {
2171 up_read(&pci_bus_sem);
2172 return -ENOENT;
2173 }
2174
2175 __pci_bus_size_bridges(bridge->subordinate, &added);
2176 __pci_bridge_assign_resources(bridge, &added, &failed);
2177 BUG_ON(!list_empty(&added));
2178
2179 if (!list_empty(&failed)) {
2180 ret = -ENOSPC;
2181 goto cleanup;
2182 }
2183
2184 list_for_each_entry(dev_res, &saved, list) {
2185 /* Skip the bridge we just assigned resources for */
2186 if (bridge == dev_res->dev)
2187 continue;
2188
2189 bridge = dev_res->dev;
2190 pci_setup_bridge(bridge->subordinate);
2191 }
2192
2193 free_list(&saved);
2194 up_read(&pci_bus_sem);
2195 return 0;
2196
2197cleanup:
2198 /* Restore size and flags */
2199 list_for_each_entry(dev_res, &failed, list) {
2200 struct resource *res = dev_res->res;
2201
2202 res->start = dev_res->start;
2203 res->end = dev_res->end;
2204 res->flags = dev_res->flags;
2205 }
2206 free_list(&failed);
2207
2208 /* Revert to the old configuration */
2209 list_for_each_entry(dev_res, &saved, list) {
2210 struct resource *res = dev_res->res;
2211
2212 bridge = dev_res->dev;
2213 i = res - bridge->resource;
2214
2215 res->start = dev_res->start;
2216 res->end = dev_res->end;
2217 res->flags = dev_res->flags;
2218
2219 pci_claim_resource(bridge, i);
2220 pci_setup_bridge(bridge->subordinate);
2221 }
2222 free_list(&saved);
2223 up_read(&pci_bus_sem);
2224
2225 return ret;
2226}
2227
2228void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2229{
2230 struct pci_dev *dev;
2231 /* List of resources that want additional resources */
2232 LIST_HEAD(add_list);
2233
2234 down_read(&pci_bus_sem);
2235 for_each_pci_bridge(dev, bus)
2236 if (pci_has_subordinate(dev))
2237 __pci_bus_size_bridges(dev->subordinate, &add_list);
2238 up_read(&pci_bus_sem);
2239 __pci_bus_assign_resources(bus, &add_list, NULL);
2240 BUG_ON(!list_empty(&add_list));
2241}
2242EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);