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1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28#include "pci.h"
29
30struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39};
40
41#define free_list(type, head) do { \
42 struct type *list, *tmp; \
43 for (list = (head)->next; list;) { \
44 tmp = list; \
45 list = list->next; \
46 kfree(tmp); \
47 } \
48 (head)->next = NULL; \
49} while (0)
50
51int pci_realloc_enable = 0;
52#define pci_realloc_enabled() pci_realloc_enable
53void pci_realloc(void)
54{
55 pci_realloc_enable = 1;
56}
57
58/**
59 * add_to_list() - add a new resource tracker to the list
60 * @head: Head of the list
61 * @dev: device corresponding to which the resource
62 * belongs
63 * @res: The resource to be tracked
64 * @add_size: additional size to be optionally added
65 * to the resource
66 */
67static void add_to_list(struct resource_list_x *head,
68 struct pci_dev *dev, struct resource *res,
69 resource_size_t add_size, resource_size_t min_align)
70{
71 struct resource_list_x *list = head;
72 struct resource_list_x *ln = list->next;
73 struct resource_list_x *tmp;
74
75 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
76 if (!tmp) {
77 pr_warning("add_to_list: kmalloc() failed!\n");
78 return;
79 }
80
81 tmp->next = ln;
82 tmp->res = res;
83 tmp->dev = dev;
84 tmp->start = res->start;
85 tmp->end = res->end;
86 tmp->flags = res->flags;
87 tmp->add_size = add_size;
88 tmp->min_align = min_align;
89 list->next = tmp;
90}
91
92static void add_to_failed_list(struct resource_list_x *head,
93 struct pci_dev *dev, struct resource *res)
94{
95 add_to_list(head, dev, res,
96 0 /* dont care */,
97 0 /* dont care */);
98}
99
100static void __dev_sort_resources(struct pci_dev *dev,
101 struct resource_list *head)
102{
103 u16 class = dev->class >> 8;
104
105 /* Don't touch classless devices or host bridges or ioapics. */
106 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
107 return;
108
109 /* Don't touch ioapic devices already enabled by firmware */
110 if (class == PCI_CLASS_SYSTEM_PIC) {
111 u16 command;
112 pci_read_config_word(dev, PCI_COMMAND, &command);
113 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
114 return;
115 }
116
117 pdev_sort_resources(dev, head);
118}
119
120static inline void reset_resource(struct resource *res)
121{
122 res->start = 0;
123 res->end = 0;
124 res->flags = 0;
125}
126
127/**
128 * reassign_resources_sorted() - satisfy any additional resource requests
129 *
130 * @realloc_head : head of the list tracking requests requiring additional
131 * resources
132 * @head : head of the list tracking requests with allocated
133 * resources
134 *
135 * Walk through each element of the realloc_head and try to procure
136 * additional resources for the element, provided the element
137 * is in the head list.
138 */
139static void reassign_resources_sorted(struct resource_list_x *realloc_head,
140 struct resource_list *head)
141{
142 struct resource *res;
143 struct resource_list_x *list, *tmp, *prev;
144 struct resource_list *hlist;
145 resource_size_t add_size;
146 int idx;
147
148 prev = realloc_head;
149 for (list = realloc_head->next; list;) {
150 res = list->res;
151 /* skip resource that has been reset */
152 if (!res->flags)
153 goto out;
154
155 /* skip this resource if not found in head list */
156 for (hlist = head->next; hlist && hlist->res != res;
157 hlist = hlist->next);
158 if (!hlist) { /* just skip */
159 prev = list;
160 list = list->next;
161 continue;
162 }
163
164 idx = res - &list->dev->resource[0];
165 add_size=list->add_size;
166 if (!resource_size(res)) {
167 res->start = list->start;
168 res->end = res->start + add_size - 1;
169 if(pci_assign_resource(list->dev, idx))
170 reset_resource(res);
171 } else {
172 resource_size_t align = list->min_align;
173 res->flags |= list->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
174 if (pci_reassign_resource(list->dev, idx, add_size, align))
175 dev_printk(KERN_DEBUG, &list->dev->dev, "failed to add optional resources res=%pR\n",
176 res);
177 }
178out:
179 tmp = list;
180 prev->next = list = list->next;
181 kfree(tmp);
182 }
183}
184
185/**
186 * assign_requested_resources_sorted() - satisfy resource requests
187 *
188 * @head : head of the list tracking requests for resources
189 * @failed_list : head of the list tracking requests that could
190 * not be allocated
191 *
192 * Satisfy resource requests of each element in the list. Add
193 * requests that could not satisfied to the failed_list.
194 */
195static void assign_requested_resources_sorted(struct resource_list *head,
196 struct resource_list_x *fail_head)
197{
198 struct resource *res;
199 struct resource_list *list;
200 int idx;
201
202 for (list = head->next; list; list = list->next) {
203 res = list->res;
204 idx = res - &list->dev->resource[0];
205 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
206 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
207 /*
208 * if the failed res is for ROM BAR, and it will
209 * be enabled later, don't add it to the list
210 */
211 if (!((idx == PCI_ROM_RESOURCE) &&
212 (!(res->flags & IORESOURCE_ROM_ENABLE))))
213 add_to_failed_list(fail_head, list->dev, res);
214 }
215 reset_resource(res);
216 }
217 }
218}
219
220static void __assign_resources_sorted(struct resource_list *head,
221 struct resource_list_x *realloc_head,
222 struct resource_list_x *fail_head)
223{
224 /* Satisfy the must-have resource requests */
225 assign_requested_resources_sorted(head, fail_head);
226
227 /* Try to satisfy any additional optional resource
228 requests */
229 if (realloc_head)
230 reassign_resources_sorted(realloc_head, head);
231 free_list(resource_list, head);
232}
233
234static void pdev_assign_resources_sorted(struct pci_dev *dev,
235 struct resource_list_x *fail_head)
236{
237 struct resource_list head;
238
239 head.next = NULL;
240 __dev_sort_resources(dev, &head);
241 __assign_resources_sorted(&head, NULL, fail_head);
242
243}
244
245static void pbus_assign_resources_sorted(const struct pci_bus *bus,
246 struct resource_list_x *realloc_head,
247 struct resource_list_x *fail_head)
248{
249 struct pci_dev *dev;
250 struct resource_list head;
251
252 head.next = NULL;
253 list_for_each_entry(dev, &bus->devices, bus_list)
254 __dev_sort_resources(dev, &head);
255
256 __assign_resources_sorted(&head, realloc_head, fail_head);
257}
258
259void pci_setup_cardbus(struct pci_bus *bus)
260{
261 struct pci_dev *bridge = bus->self;
262 struct resource *res;
263 struct pci_bus_region region;
264
265 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
266 bus->secondary, bus->subordinate);
267
268 res = bus->resource[0];
269 pcibios_resource_to_bus(bridge, ®ion, res);
270 if (res->flags & IORESOURCE_IO) {
271 /*
272 * The IO resource is allocated a range twice as large as it
273 * would normally need. This allows us to set both IO regs.
274 */
275 dev_info(&bridge->dev, " bridge window %pR\n", res);
276 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
277 region.start);
278 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
279 region.end);
280 }
281
282 res = bus->resource[1];
283 pcibios_resource_to_bus(bridge, ®ion, res);
284 if (res->flags & IORESOURCE_IO) {
285 dev_info(&bridge->dev, " bridge window %pR\n", res);
286 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
287 region.start);
288 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
289 region.end);
290 }
291
292 res = bus->resource[2];
293 pcibios_resource_to_bus(bridge, ®ion, res);
294 if (res->flags & IORESOURCE_MEM) {
295 dev_info(&bridge->dev, " bridge window %pR\n", res);
296 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
297 region.start);
298 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
299 region.end);
300 }
301
302 res = bus->resource[3];
303 pcibios_resource_to_bus(bridge, ®ion, res);
304 if (res->flags & IORESOURCE_MEM) {
305 dev_info(&bridge->dev, " bridge window %pR\n", res);
306 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
307 region.start);
308 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
309 region.end);
310 }
311}
312EXPORT_SYMBOL(pci_setup_cardbus);
313
314/* Initialize bridges with base/limit values we have collected.
315 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
316 requires that if there is no I/O ports or memory behind the
317 bridge, corresponding range must be turned off by writing base
318 value greater than limit to the bridge's base/limit registers.
319
320 Note: care must be taken when updating I/O base/limit registers
321 of bridges which support 32-bit I/O. This update requires two
322 config space writes, so it's quite possible that an I/O window of
323 the bridge will have some undesirable address (e.g. 0) after the
324 first write. Ditto 64-bit prefetchable MMIO. */
325static void pci_setup_bridge_io(struct pci_bus *bus)
326{
327 struct pci_dev *bridge = bus->self;
328 struct resource *res;
329 struct pci_bus_region region;
330 u32 l, io_upper16;
331
332 /* Set up the top and bottom of the PCI I/O segment for this bus. */
333 res = bus->resource[0];
334 pcibios_resource_to_bus(bridge, ®ion, res);
335 if (res->flags & IORESOURCE_IO) {
336 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
337 l &= 0xffff0000;
338 l |= (region.start >> 8) & 0x00f0;
339 l |= region.end & 0xf000;
340 /* Set up upper 16 bits of I/O base/limit. */
341 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
342 dev_info(&bridge->dev, " bridge window %pR\n", res);
343 } else {
344 /* Clear upper 16 bits of I/O base/limit. */
345 io_upper16 = 0;
346 l = 0x00f0;
347 }
348 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
349 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
350 /* Update lower 16 bits of I/O base/limit. */
351 pci_write_config_dword(bridge, PCI_IO_BASE, l);
352 /* Update upper 16 bits of I/O base/limit. */
353 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
354}
355
356static void pci_setup_bridge_mmio(struct pci_bus *bus)
357{
358 struct pci_dev *bridge = bus->self;
359 struct resource *res;
360 struct pci_bus_region region;
361 u32 l;
362
363 /* Set up the top and bottom of the PCI Memory segment for this bus. */
364 res = bus->resource[1];
365 pcibios_resource_to_bus(bridge, ®ion, res);
366 if (res->flags & IORESOURCE_MEM) {
367 l = (region.start >> 16) & 0xfff0;
368 l |= region.end & 0xfff00000;
369 dev_info(&bridge->dev, " bridge window %pR\n", res);
370 } else {
371 l = 0x0000fff0;
372 }
373 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
374}
375
376static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
377{
378 struct pci_dev *bridge = bus->self;
379 struct resource *res;
380 struct pci_bus_region region;
381 u32 l, bu, lu;
382
383 /* Clear out the upper 32 bits of PREF limit.
384 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
385 disables PREF range, which is ok. */
386 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
387
388 /* Set up PREF base/limit. */
389 bu = lu = 0;
390 res = bus->resource[2];
391 pcibios_resource_to_bus(bridge, ®ion, res);
392 if (res->flags & IORESOURCE_PREFETCH) {
393 l = (region.start >> 16) & 0xfff0;
394 l |= region.end & 0xfff00000;
395 if (res->flags & IORESOURCE_MEM_64) {
396 bu = upper_32_bits(region.start);
397 lu = upper_32_bits(region.end);
398 }
399 dev_info(&bridge->dev, " bridge window %pR\n", res);
400 } else {
401 l = 0x0000fff0;
402 }
403 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
404
405 /* Set the upper 32 bits of PREF base & limit. */
406 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
407 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
408}
409
410static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
411{
412 struct pci_dev *bridge = bus->self;
413
414 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
415 bus->secondary, bus->subordinate);
416
417 if (type & IORESOURCE_IO)
418 pci_setup_bridge_io(bus);
419
420 if (type & IORESOURCE_MEM)
421 pci_setup_bridge_mmio(bus);
422
423 if (type & IORESOURCE_PREFETCH)
424 pci_setup_bridge_mmio_pref(bus);
425
426 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
427}
428
429static void pci_setup_bridge(struct pci_bus *bus)
430{
431 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
432 IORESOURCE_PREFETCH;
433
434 __pci_setup_bridge(bus, type);
435}
436
437/* Check whether the bridge supports optional I/O and
438 prefetchable memory ranges. If not, the respective
439 base/limit registers must be read-only and read as 0. */
440static void pci_bridge_check_ranges(struct pci_bus *bus)
441{
442 u16 io;
443 u32 pmem;
444 struct pci_dev *bridge = bus->self;
445 struct resource *b_res;
446
447 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
448 b_res[1].flags |= IORESOURCE_MEM;
449
450 pci_read_config_word(bridge, PCI_IO_BASE, &io);
451 if (!io) {
452 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
453 pci_read_config_word(bridge, PCI_IO_BASE, &io);
454 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
455 }
456 if (io)
457 b_res[0].flags |= IORESOURCE_IO;
458 /* DECchip 21050 pass 2 errata: the bridge may miss an address
459 disconnect boundary by one PCI data phase.
460 Workaround: do not use prefetching on this device. */
461 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
462 return;
463 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
464 if (!pmem) {
465 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
466 0xfff0fff0);
467 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
468 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
469 }
470 if (pmem) {
471 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
472 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
473 PCI_PREF_RANGE_TYPE_64) {
474 b_res[2].flags |= IORESOURCE_MEM_64;
475 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
476 }
477 }
478
479 /* double check if bridge does support 64 bit pref */
480 if (b_res[2].flags & IORESOURCE_MEM_64) {
481 u32 mem_base_hi, tmp;
482 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
483 &mem_base_hi);
484 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
485 0xffffffff);
486 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
487 if (!tmp)
488 b_res[2].flags &= ~IORESOURCE_MEM_64;
489 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
490 mem_base_hi);
491 }
492}
493
494/* Helper function for sizing routines: find first available
495 bus resource of a given type. Note: we intentionally skip
496 the bus resources which have already been assigned (that is,
497 have non-NULL parent resource). */
498static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
499{
500 int i;
501 struct resource *r;
502 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
503 IORESOURCE_PREFETCH;
504
505 pci_bus_for_each_resource(bus, r, i) {
506 if (r == &ioport_resource || r == &iomem_resource)
507 continue;
508 if (r && (r->flags & type_mask) == type && !r->parent)
509 return r;
510 }
511 return NULL;
512}
513
514static resource_size_t calculate_iosize(resource_size_t size,
515 resource_size_t min_size,
516 resource_size_t size1,
517 resource_size_t old_size,
518 resource_size_t align)
519{
520 if (size < min_size)
521 size = min_size;
522 if (old_size == 1 )
523 old_size = 0;
524 /* To be fixed in 2.5: we should have sort of HAVE_ISA
525 flag in the struct pci_bus. */
526#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
527 size = (size & 0xff) + ((size & ~0xffUL) << 2);
528#endif
529 size = ALIGN(size + size1, align);
530 if (size < old_size)
531 size = old_size;
532 return size;
533}
534
535static resource_size_t calculate_memsize(resource_size_t size,
536 resource_size_t min_size,
537 resource_size_t size1,
538 resource_size_t old_size,
539 resource_size_t align)
540{
541 if (size < min_size)
542 size = min_size;
543 if (old_size == 1 )
544 old_size = 0;
545 if (size < old_size)
546 size = old_size;
547 size = ALIGN(size + size1, align);
548 return size;
549}
550
551static resource_size_t get_res_add_size(struct resource_list_x *realloc_head,
552 struct resource *res)
553{
554 struct resource_list_x *list;
555
556 /* check if it is in realloc_head list */
557 for (list = realloc_head->next; list && list->res != res;
558 list = list->next);
559 if (list)
560 return list->add_size;
561
562 return 0;
563}
564
565/**
566 * pbus_size_io() - size the io window of a given bus
567 *
568 * @bus : the bus
569 * @min_size : the minimum io window that must to be allocated
570 * @add_size : additional optional io window
571 * @realloc_head : track the additional io window on this list
572 *
573 * Sizing the IO windows of the PCI-PCI bridge is trivial,
574 * since these windows have 4K granularity and the IO ranges
575 * of non-bridge PCI devices are limited to 256 bytes.
576 * We must be careful with the ISA aliasing though.
577 */
578static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
579 resource_size_t add_size, struct resource_list_x *realloc_head)
580{
581 struct pci_dev *dev;
582 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
583 unsigned long size = 0, size0 = 0, size1 = 0;
584 resource_size_t children_add_size = 0;
585
586 if (!b_res)
587 return;
588
589 list_for_each_entry(dev, &bus->devices, bus_list) {
590 int i;
591
592 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
593 struct resource *r = &dev->resource[i];
594 unsigned long r_size;
595
596 if (r->parent || !(r->flags & IORESOURCE_IO))
597 continue;
598 r_size = resource_size(r);
599
600 if (r_size < 0x400)
601 /* Might be re-aligned for ISA */
602 size += r_size;
603 else
604 size1 += r_size;
605
606 if (realloc_head)
607 children_add_size += get_res_add_size(realloc_head, r);
608 }
609 }
610 size0 = calculate_iosize(size, min_size, size1,
611 resource_size(b_res), 4096);
612 if (children_add_size > add_size)
613 add_size = children_add_size;
614 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
615 calculate_iosize(size, min_size+add_size, size1,
616 resource_size(b_res), 4096);
617 if (!size0 && !size1) {
618 if (b_res->start || b_res->end)
619 dev_info(&bus->self->dev, "disabling bridge window "
620 "%pR to [bus %02x-%02x] (unused)\n", b_res,
621 bus->secondary, bus->subordinate);
622 b_res->flags = 0;
623 return;
624 }
625 /* Alignment of the IO window is always 4K */
626 b_res->start = 4096;
627 b_res->end = b_res->start + size0 - 1;
628 b_res->flags |= IORESOURCE_STARTALIGN;
629 if (size1 > size0 && realloc_head)
630 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
631}
632
633/**
634 * pbus_size_mem() - size the memory window of a given bus
635 *
636 * @bus : the bus
637 * @min_size : the minimum memory window that must to be allocated
638 * @add_size : additional optional memory window
639 * @realloc_head : track the additional memory window on this list
640 *
641 * Calculate the size of the bus and minimal alignment which
642 * guarantees that all child resources fit in this size.
643 */
644static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
645 unsigned long type, resource_size_t min_size,
646 resource_size_t add_size,
647 struct resource_list_x *realloc_head)
648{
649 struct pci_dev *dev;
650 resource_size_t min_align, align, size, size0, size1;
651 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
652 int order, max_order;
653 struct resource *b_res = find_free_bus_resource(bus, type);
654 unsigned int mem64_mask = 0;
655 resource_size_t children_add_size = 0;
656
657 if (!b_res)
658 return 0;
659
660 memset(aligns, 0, sizeof(aligns));
661 max_order = 0;
662 size = 0;
663
664 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
665 b_res->flags &= ~IORESOURCE_MEM_64;
666
667 list_for_each_entry(dev, &bus->devices, bus_list) {
668 int i;
669
670 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
671 struct resource *r = &dev->resource[i];
672 resource_size_t r_size;
673
674 if (r->parent || (r->flags & mask) != type)
675 continue;
676 r_size = resource_size(r);
677#ifdef CONFIG_PCI_IOV
678 /* put SRIOV requested res to the optional list */
679 if (realloc_head && i >= PCI_IOV_RESOURCES &&
680 i <= PCI_IOV_RESOURCE_END) {
681 r->end = r->start - 1;
682 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
683 children_add_size += r_size;
684 continue;
685 }
686#endif
687 /* For bridges size != alignment */
688 align = pci_resource_alignment(dev, r);
689 order = __ffs(align) - 20;
690 if (order > 11) {
691 dev_warn(&dev->dev, "disabling BAR %d: %pR "
692 "(bad alignment %#llx)\n", i, r,
693 (unsigned long long) align);
694 r->flags = 0;
695 continue;
696 }
697 size += r_size;
698 if (order < 0)
699 order = 0;
700 /* Exclude ranges with size > align from
701 calculation of the alignment. */
702 if (r_size == align)
703 aligns[order] += align;
704 if (order > max_order)
705 max_order = order;
706 mem64_mask &= r->flags & IORESOURCE_MEM_64;
707
708 if (realloc_head)
709 children_add_size += get_res_add_size(realloc_head, r);
710 }
711 }
712 align = 0;
713 min_align = 0;
714 for (order = 0; order <= max_order; order++) {
715 resource_size_t align1 = 1;
716
717 align1 <<= (order + 20);
718
719 if (!align)
720 min_align = align1;
721 else if (ALIGN(align + min_align, min_align) < align1)
722 min_align = align1 >> 1;
723 align += aligns[order];
724 }
725 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
726 if (children_add_size > add_size)
727 add_size = children_add_size;
728 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
729 calculate_memsize(size, min_size+add_size, 0,
730 resource_size(b_res), min_align);
731 if (!size0 && !size1) {
732 if (b_res->start || b_res->end)
733 dev_info(&bus->self->dev, "disabling bridge window "
734 "%pR to [bus %02x-%02x] (unused)\n", b_res,
735 bus->secondary, bus->subordinate);
736 b_res->flags = 0;
737 return 1;
738 }
739 b_res->start = min_align;
740 b_res->end = size0 + min_align - 1;
741 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
742 if (size1 > size0 && realloc_head)
743 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
744 return 1;
745}
746
747unsigned long pci_cardbus_resource_alignment(struct resource *res)
748{
749 if (res->flags & IORESOURCE_IO)
750 return pci_cardbus_io_size;
751 if (res->flags & IORESOURCE_MEM)
752 return pci_cardbus_mem_size;
753 return 0;
754}
755
756static void pci_bus_size_cardbus(struct pci_bus *bus,
757 struct resource_list_x *realloc_head)
758{
759 struct pci_dev *bridge = bus->self;
760 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
761 u16 ctrl;
762
763 /*
764 * Reserve some resources for CardBus. We reserve
765 * a fixed amount of bus space for CardBus bridges.
766 */
767 b_res[0].start = 0;
768 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
769 if (realloc_head)
770 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */);
771
772 b_res[1].start = 0;
773 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
774 if (realloc_head)
775 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
776
777 /*
778 * Check whether prefetchable memory is supported
779 * by this bridge.
780 */
781 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
782 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
783 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
784 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
785 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
786 }
787
788 /*
789 * If we have prefetchable memory support, allocate
790 * two regions. Otherwise, allocate one region of
791 * twice the size.
792 */
793 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
794 b_res[2].start = 0;
795 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
796 if (realloc_head)
797 add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */);
798
799 b_res[3].start = 0;
800 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
801 if (realloc_head)
802 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */);
803 } else {
804 b_res[3].start = 0;
805 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
806 if (realloc_head)
807 add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */);
808 }
809
810 /* set the size of the resource to zero, so that the resource does not
811 * get assigned during required-resource allocation cycle but gets assigned
812 * during the optional-resource allocation cycle.
813 */
814 b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1;
815 b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0;
816}
817
818void __ref __pci_bus_size_bridges(struct pci_bus *bus,
819 struct resource_list_x *realloc_head)
820{
821 struct pci_dev *dev;
822 unsigned long mask, prefmask;
823 resource_size_t additional_mem_size = 0, additional_io_size = 0;
824
825 list_for_each_entry(dev, &bus->devices, bus_list) {
826 struct pci_bus *b = dev->subordinate;
827 if (!b)
828 continue;
829
830 switch (dev->class >> 8) {
831 case PCI_CLASS_BRIDGE_CARDBUS:
832 pci_bus_size_cardbus(b, realloc_head);
833 break;
834
835 case PCI_CLASS_BRIDGE_PCI:
836 default:
837 __pci_bus_size_bridges(b, realloc_head);
838 break;
839 }
840 }
841
842 /* The root bus? */
843 if (!bus->self)
844 return;
845
846 switch (bus->self->class >> 8) {
847 case PCI_CLASS_BRIDGE_CARDBUS:
848 /* don't size cardbuses yet. */
849 break;
850
851 case PCI_CLASS_BRIDGE_PCI:
852 pci_bridge_check_ranges(bus);
853 if (bus->self->is_hotplug_bridge) {
854 additional_io_size = pci_hotplug_io_size;
855 additional_mem_size = pci_hotplug_mem_size;
856 }
857 /*
858 * Follow thru
859 */
860 default:
861 pbus_size_io(bus, 0, additional_io_size, realloc_head);
862 /* If the bridge supports prefetchable range, size it
863 separately. If it doesn't, or its prefetchable window
864 has already been allocated by arch code, try
865 non-prefetchable range for both types of PCI memory
866 resources. */
867 mask = IORESOURCE_MEM;
868 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
869 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, realloc_head))
870 mask = prefmask; /* Success, size non-prefetch only. */
871 else
872 additional_mem_size += additional_mem_size;
873 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, realloc_head);
874 break;
875 }
876}
877
878void __ref pci_bus_size_bridges(struct pci_bus *bus)
879{
880 __pci_bus_size_bridges(bus, NULL);
881}
882EXPORT_SYMBOL(pci_bus_size_bridges);
883
884static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
885 struct resource_list_x *realloc_head,
886 struct resource_list_x *fail_head)
887{
888 struct pci_bus *b;
889 struct pci_dev *dev;
890
891 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
892
893 list_for_each_entry(dev, &bus->devices, bus_list) {
894 b = dev->subordinate;
895 if (!b)
896 continue;
897
898 __pci_bus_assign_resources(b, realloc_head, fail_head);
899
900 switch (dev->class >> 8) {
901 case PCI_CLASS_BRIDGE_PCI:
902 if (!pci_is_enabled(dev))
903 pci_setup_bridge(b);
904 break;
905
906 case PCI_CLASS_BRIDGE_CARDBUS:
907 pci_setup_cardbus(b);
908 break;
909
910 default:
911 dev_info(&dev->dev, "not setting up bridge for bus "
912 "%04x:%02x\n", pci_domain_nr(b), b->number);
913 break;
914 }
915 }
916}
917
918void __ref pci_bus_assign_resources(const struct pci_bus *bus)
919{
920 __pci_bus_assign_resources(bus, NULL, NULL);
921}
922EXPORT_SYMBOL(pci_bus_assign_resources);
923
924static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
925 struct resource_list_x *fail_head)
926{
927 struct pci_bus *b;
928
929 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
930
931 b = bridge->subordinate;
932 if (!b)
933 return;
934
935 __pci_bus_assign_resources(b, NULL, fail_head);
936
937 switch (bridge->class >> 8) {
938 case PCI_CLASS_BRIDGE_PCI:
939 pci_setup_bridge(b);
940 break;
941
942 case PCI_CLASS_BRIDGE_CARDBUS:
943 pci_setup_cardbus(b);
944 break;
945
946 default:
947 dev_info(&bridge->dev, "not setting up bridge for bus "
948 "%04x:%02x\n", pci_domain_nr(b), b->number);
949 break;
950 }
951}
952static void pci_bridge_release_resources(struct pci_bus *bus,
953 unsigned long type)
954{
955 int idx;
956 bool changed = false;
957 struct pci_dev *dev;
958 struct resource *r;
959 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
960 IORESOURCE_PREFETCH;
961
962 dev = bus->self;
963 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
964 idx++) {
965 r = &dev->resource[idx];
966 if ((r->flags & type_mask) != type)
967 continue;
968 if (!r->parent)
969 continue;
970 /*
971 * if there are children under that, we should release them
972 * all
973 */
974 release_child_resources(r);
975 if (!release_resource(r)) {
976 dev_printk(KERN_DEBUG, &dev->dev,
977 "resource %d %pR released\n", idx, r);
978 /* keep the old size */
979 r->end = resource_size(r) - 1;
980 r->start = 0;
981 r->flags = 0;
982 changed = true;
983 }
984 }
985
986 if (changed) {
987 /* avoiding touch the one without PREF */
988 if (type & IORESOURCE_PREFETCH)
989 type = IORESOURCE_PREFETCH;
990 __pci_setup_bridge(bus, type);
991 }
992}
993
994enum release_type {
995 leaf_only,
996 whole_subtree,
997};
998/*
999 * try to release pci bridge resources that is from leaf bridge,
1000 * so we can allocate big new one later
1001 */
1002static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1003 unsigned long type,
1004 enum release_type rel_type)
1005{
1006 struct pci_dev *dev;
1007 bool is_leaf_bridge = true;
1008
1009 list_for_each_entry(dev, &bus->devices, bus_list) {
1010 struct pci_bus *b = dev->subordinate;
1011 if (!b)
1012 continue;
1013
1014 is_leaf_bridge = false;
1015
1016 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1017 continue;
1018
1019 if (rel_type == whole_subtree)
1020 pci_bus_release_bridge_resources(b, type,
1021 whole_subtree);
1022 }
1023
1024 if (pci_is_root_bus(bus))
1025 return;
1026
1027 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1028 return;
1029
1030 if ((rel_type == whole_subtree) || is_leaf_bridge)
1031 pci_bridge_release_resources(bus, type);
1032}
1033
1034static void pci_bus_dump_res(struct pci_bus *bus)
1035{
1036 struct resource *res;
1037 int i;
1038
1039 pci_bus_for_each_resource(bus, res, i) {
1040 if (!res || !res->end || !res->flags)
1041 continue;
1042
1043 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1044 }
1045}
1046
1047static void pci_bus_dump_resources(struct pci_bus *bus)
1048{
1049 struct pci_bus *b;
1050 struct pci_dev *dev;
1051
1052
1053 pci_bus_dump_res(bus);
1054
1055 list_for_each_entry(dev, &bus->devices, bus_list) {
1056 b = dev->subordinate;
1057 if (!b)
1058 continue;
1059
1060 pci_bus_dump_resources(b);
1061 }
1062}
1063
1064static int __init pci_bus_get_depth(struct pci_bus *bus)
1065{
1066 int depth = 0;
1067 struct pci_dev *dev;
1068
1069 list_for_each_entry(dev, &bus->devices, bus_list) {
1070 int ret;
1071 struct pci_bus *b = dev->subordinate;
1072 if (!b)
1073 continue;
1074
1075 ret = pci_bus_get_depth(b);
1076 if (ret + 1 > depth)
1077 depth = ret + 1;
1078 }
1079
1080 return depth;
1081}
1082static int __init pci_get_max_depth(void)
1083{
1084 int depth = 0;
1085 struct pci_bus *bus;
1086
1087 list_for_each_entry(bus, &pci_root_buses, node) {
1088 int ret;
1089
1090 ret = pci_bus_get_depth(bus);
1091 if (ret > depth)
1092 depth = ret;
1093 }
1094
1095 return depth;
1096}
1097
1098
1099/*
1100 * first try will not touch pci bridge res
1101 * second and later try will clear small leaf bridge res
1102 * will stop till to the max deepth if can not find good one
1103 */
1104void __init
1105pci_assign_unassigned_resources(void)
1106{
1107 struct pci_bus *bus;
1108 struct resource_list_x realloc_list; /* list of resources that
1109 want additional resources */
1110 int tried_times = 0;
1111 enum release_type rel_type = leaf_only;
1112 struct resource_list_x head, *list;
1113 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1114 IORESOURCE_PREFETCH;
1115 unsigned long failed_type;
1116 int max_depth = pci_get_max_depth();
1117 int pci_try_num;
1118
1119
1120 head.next = NULL;
1121 realloc_list.next = NULL;
1122
1123 pci_try_num = max_depth + 1;
1124 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1125 max_depth, pci_try_num);
1126
1127again:
1128 /* Depth first, calculate sizes and alignments of all
1129 subordinate buses. */
1130 list_for_each_entry(bus, &pci_root_buses, node)
1131 __pci_bus_size_bridges(bus, &realloc_list);
1132
1133 /* Depth last, allocate resources and update the hardware. */
1134 list_for_each_entry(bus, &pci_root_buses, node)
1135 __pci_bus_assign_resources(bus, &realloc_list, &head);
1136 BUG_ON(realloc_list.next);
1137 tried_times++;
1138
1139 /* any device complain? */
1140 if (!head.next)
1141 goto enable_and_dump;
1142
1143 /* don't realloc if asked to do so */
1144 if (!pci_realloc_enabled()) {
1145 free_list(resource_list_x, &head);
1146 goto enable_and_dump;
1147 }
1148
1149 failed_type = 0;
1150 for (list = head.next; list;) {
1151 failed_type |= list->flags;
1152 list = list->next;
1153 }
1154 /*
1155 * io port are tight, don't try extra
1156 * or if reach the limit, don't want to try more
1157 */
1158 failed_type &= type_mask;
1159 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1160 free_list(resource_list_x, &head);
1161 goto enable_and_dump;
1162 }
1163
1164 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1165 tried_times + 1);
1166
1167 /* third times and later will not check if it is leaf */
1168 if ((tried_times + 1) > 2)
1169 rel_type = whole_subtree;
1170
1171 /*
1172 * Try to release leaf bridge's resources that doesn't fit resource of
1173 * child device under that bridge
1174 */
1175 for (list = head.next; list;) {
1176 bus = list->dev->bus;
1177 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1178 rel_type);
1179 list = list->next;
1180 }
1181 /* restore size and flags */
1182 for (list = head.next; list;) {
1183 struct resource *res = list->res;
1184
1185 res->start = list->start;
1186 res->end = list->end;
1187 res->flags = list->flags;
1188 if (list->dev->subordinate)
1189 res->flags = 0;
1190
1191 list = list->next;
1192 }
1193 free_list(resource_list_x, &head);
1194
1195 goto again;
1196
1197enable_and_dump:
1198 /* Depth last, update the hardware. */
1199 list_for_each_entry(bus, &pci_root_buses, node)
1200 pci_enable_bridges(bus);
1201
1202 /* dump the resource on buses */
1203 list_for_each_entry(bus, &pci_root_buses, node)
1204 pci_bus_dump_resources(bus);
1205}
1206
1207void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1208{
1209 struct pci_bus *parent = bridge->subordinate;
1210 int tried_times = 0;
1211 struct resource_list_x head, *list;
1212 int retval;
1213 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1214 IORESOURCE_PREFETCH;
1215
1216 head.next = NULL;
1217
1218again:
1219 pci_bus_size_bridges(parent);
1220 __pci_bridge_assign_resources(bridge, &head);
1221
1222 tried_times++;
1223
1224 if (!head.next)
1225 goto enable_all;
1226
1227 if (tried_times >= 2) {
1228 /* still fail, don't need to try more */
1229 free_list(resource_list_x, &head);
1230 goto enable_all;
1231 }
1232
1233 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1234 tried_times + 1);
1235
1236 /*
1237 * Try to release leaf bridge's resources that doesn't fit resource of
1238 * child device under that bridge
1239 */
1240 for (list = head.next; list;) {
1241 struct pci_bus *bus = list->dev->bus;
1242 unsigned long flags = list->flags;
1243
1244 pci_bus_release_bridge_resources(bus, flags & type_mask,
1245 whole_subtree);
1246 list = list->next;
1247 }
1248 /* restore size and flags */
1249 for (list = head.next; list;) {
1250 struct resource *res = list->res;
1251
1252 res->start = list->start;
1253 res->end = list->end;
1254 res->flags = list->flags;
1255 if (list->dev->subordinate)
1256 res->flags = 0;
1257
1258 list = list->next;
1259 }
1260 free_list(resource_list_x, &head);
1261
1262 goto again;
1263
1264enable_all:
1265 retval = pci_reenable_device(bridge);
1266 pci_set_master(bridge);
1267 pci_enable_bridges(parent);
1268}
1269EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
15 */
16
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/errno.h>
22#include <linux/ioport.h>
23#include <linux/cache.h>
24#include <linux/slab.h>
25#include <linux/acpi.h>
26#include "pci.h"
27
28unsigned int pci_flags;
29
30struct pci_dev_resource {
31 struct list_head list;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39};
40
41static void free_list(struct list_head *head)
42{
43 struct pci_dev_resource *dev_res, *tmp;
44
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
47 kfree(dev_res);
48 }
49}
50
51/**
52 * add_to_list() - add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: device corresponding to which the resource
55 * belongs
56 * @res: The resource to be tracked
57 * @add_size: additional size to be optionally added
58 * to the resource
59 */
60static int add_to_list(struct list_head *head,
61 struct pci_dev *dev, struct resource *res,
62 resource_size_t add_size, resource_size_t min_align)
63{
64 struct pci_dev_resource *tmp;
65
66 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
67 if (!tmp)
68 return -ENOMEM;
69
70 tmp->res = res;
71 tmp->dev = dev;
72 tmp->start = res->start;
73 tmp->end = res->end;
74 tmp->flags = res->flags;
75 tmp->add_size = add_size;
76 tmp->min_align = min_align;
77
78 list_add(&tmp->list, head);
79
80 return 0;
81}
82
83static void remove_from_list(struct list_head *head,
84 struct resource *res)
85{
86 struct pci_dev_resource *dev_res, *tmp;
87
88 list_for_each_entry_safe(dev_res, tmp, head, list) {
89 if (dev_res->res == res) {
90 list_del(&dev_res->list);
91 kfree(dev_res);
92 break;
93 }
94 }
95}
96
97static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
98 struct resource *res)
99{
100 struct pci_dev_resource *dev_res;
101
102 list_for_each_entry(dev_res, head, list) {
103 if (dev_res->res == res)
104 return dev_res;
105 }
106
107 return NULL;
108}
109
110static resource_size_t get_res_add_size(struct list_head *head,
111 struct resource *res)
112{
113 struct pci_dev_resource *dev_res;
114
115 dev_res = res_to_dev_res(head, res);
116 return dev_res ? dev_res->add_size : 0;
117}
118
119static resource_size_t get_res_add_align(struct list_head *head,
120 struct resource *res)
121{
122 struct pci_dev_resource *dev_res;
123
124 dev_res = res_to_dev_res(head, res);
125 return dev_res ? dev_res->min_align : 0;
126}
127
128
129/* Sort resources by alignment */
130static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
131{
132 int i;
133
134 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
135 struct resource *r;
136 struct pci_dev_resource *dev_res, *tmp;
137 resource_size_t r_align;
138 struct list_head *n;
139
140 r = &dev->resource[i];
141
142 if (r->flags & IORESOURCE_PCI_FIXED)
143 continue;
144
145 if (!(r->flags) || r->parent)
146 continue;
147
148 r_align = pci_resource_alignment(dev, r);
149 if (!r_align) {
150 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
151 i, r);
152 continue;
153 }
154
155 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
156 if (!tmp)
157 panic("pdev_sort_resources(): kmalloc() failed!\n");
158 tmp->res = r;
159 tmp->dev = dev;
160
161 /* fallback is smallest one or list is empty*/
162 n = head;
163 list_for_each_entry(dev_res, head, list) {
164 resource_size_t align;
165
166 align = pci_resource_alignment(dev_res->dev,
167 dev_res->res);
168
169 if (r_align > align) {
170 n = &dev_res->list;
171 break;
172 }
173 }
174 /* Insert it just before n*/
175 list_add_tail(&tmp->list, n);
176 }
177}
178
179static void __dev_sort_resources(struct pci_dev *dev,
180 struct list_head *head)
181{
182 u16 class = dev->class >> 8;
183
184 /* Don't touch classless devices or host bridges or ioapics. */
185 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
186 return;
187
188 /* Don't touch ioapic devices already enabled by firmware */
189 if (class == PCI_CLASS_SYSTEM_PIC) {
190 u16 command;
191 pci_read_config_word(dev, PCI_COMMAND, &command);
192 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
193 return;
194 }
195
196 pdev_sort_resources(dev, head);
197}
198
199static inline void reset_resource(struct resource *res)
200{
201 res->start = 0;
202 res->end = 0;
203 res->flags = 0;
204}
205
206/**
207 * reassign_resources_sorted() - satisfy any additional resource requests
208 *
209 * @realloc_head : head of the list tracking requests requiring additional
210 * resources
211 * @head : head of the list tracking requests with allocated
212 * resources
213 *
214 * Walk through each element of the realloc_head and try to procure
215 * additional resources for the element, provided the element
216 * is in the head list.
217 */
218static void reassign_resources_sorted(struct list_head *realloc_head,
219 struct list_head *head)
220{
221 struct resource *res;
222 struct pci_dev_resource *add_res, *tmp;
223 struct pci_dev_resource *dev_res;
224 resource_size_t add_size, align;
225 int idx;
226
227 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
228 bool found_match = false;
229
230 res = add_res->res;
231 /* skip resource that has been reset */
232 if (!res->flags)
233 goto out;
234
235 /* skip this resource if not found in head list */
236 list_for_each_entry(dev_res, head, list) {
237 if (dev_res->res == res) {
238 found_match = true;
239 break;
240 }
241 }
242 if (!found_match)/* just skip */
243 continue;
244
245 idx = res - &add_res->dev->resource[0];
246 add_size = add_res->add_size;
247 align = add_res->min_align;
248 if (!resource_size(res)) {
249 res->start = align;
250 res->end = res->start + add_size - 1;
251 if (pci_assign_resource(add_res->dev, idx))
252 reset_resource(res);
253 } else {
254 res->flags |= add_res->flags &
255 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
256 if (pci_reassign_resource(add_res->dev, idx,
257 add_size, align))
258 pci_printk(KERN_DEBUG, add_res->dev,
259 "failed to add %llx res[%d]=%pR\n",
260 (unsigned long long)add_size,
261 idx, res);
262 }
263out:
264 list_del(&add_res->list);
265 kfree(add_res);
266 }
267}
268
269/**
270 * assign_requested_resources_sorted() - satisfy resource requests
271 *
272 * @head : head of the list tracking requests for resources
273 * @fail_head : head of the list tracking requests that could
274 * not be allocated
275 *
276 * Satisfy resource requests of each element in the list. Add
277 * requests that could not satisfied to the failed_list.
278 */
279static void assign_requested_resources_sorted(struct list_head *head,
280 struct list_head *fail_head)
281{
282 struct resource *res;
283 struct pci_dev_resource *dev_res;
284 int idx;
285
286 list_for_each_entry(dev_res, head, list) {
287 res = dev_res->res;
288 idx = res - &dev_res->dev->resource[0];
289 if (resource_size(res) &&
290 pci_assign_resource(dev_res->dev, idx)) {
291 if (fail_head) {
292 /*
293 * if the failed res is for ROM BAR, and it will
294 * be enabled later, don't add it to the list
295 */
296 if (!((idx == PCI_ROM_RESOURCE) &&
297 (!(res->flags & IORESOURCE_ROM_ENABLE))))
298 add_to_list(fail_head,
299 dev_res->dev, res,
300 0 /* don't care */,
301 0 /* don't care */);
302 }
303 reset_resource(res);
304 }
305 }
306}
307
308static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
309{
310 struct pci_dev_resource *fail_res;
311 unsigned long mask = 0;
312
313 /* check failed type */
314 list_for_each_entry(fail_res, fail_head, list)
315 mask |= fail_res->flags;
316
317 /*
318 * one pref failed resource will set IORESOURCE_MEM,
319 * as we can allocate pref in non-pref range.
320 * Will release all assigned non-pref sibling resources
321 * according to that bit.
322 */
323 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
324}
325
326static bool pci_need_to_release(unsigned long mask, struct resource *res)
327{
328 if (res->flags & IORESOURCE_IO)
329 return !!(mask & IORESOURCE_IO);
330
331 /* check pref at first */
332 if (res->flags & IORESOURCE_PREFETCH) {
333 if (mask & IORESOURCE_PREFETCH)
334 return true;
335 /* count pref if its parent is non-pref */
336 else if ((mask & IORESOURCE_MEM) &&
337 !(res->parent->flags & IORESOURCE_PREFETCH))
338 return true;
339 else
340 return false;
341 }
342
343 if (res->flags & IORESOURCE_MEM)
344 return !!(mask & IORESOURCE_MEM);
345
346 return false; /* should not get here */
347}
348
349static void __assign_resources_sorted(struct list_head *head,
350 struct list_head *realloc_head,
351 struct list_head *fail_head)
352{
353 /*
354 * Should not assign requested resources at first.
355 * they could be adjacent, so later reassign can not reallocate
356 * them one by one in parent resource window.
357 * Try to assign requested + add_size at beginning
358 * if could do that, could get out early.
359 * if could not do that, we still try to assign requested at first,
360 * then try to reassign add_size for some resources.
361 *
362 * Separate three resource type checking if we need to release
363 * assigned resource after requested + add_size try.
364 * 1. if there is io port assign fail, will release assigned
365 * io port.
366 * 2. if there is pref mmio assign fail, release assigned
367 * pref mmio.
368 * if assigned pref mmio's parent is non-pref mmio and there
369 * is non-pref mmio assign fail, will release that assigned
370 * pref mmio.
371 * 3. if there is non-pref mmio assign fail or pref mmio
372 * assigned fail, will release assigned non-pref mmio.
373 */
374 LIST_HEAD(save_head);
375 LIST_HEAD(local_fail_head);
376 struct pci_dev_resource *save_res;
377 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
378 unsigned long fail_type;
379 resource_size_t add_align, align;
380
381 /* Check if optional add_size is there */
382 if (!realloc_head || list_empty(realloc_head))
383 goto requested_and_reassign;
384
385 /* Save original start, end, flags etc at first */
386 list_for_each_entry(dev_res, head, list) {
387 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
388 free_list(&save_head);
389 goto requested_and_reassign;
390 }
391 }
392
393 /* Update res in head list with add_size in realloc_head list */
394 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
395 dev_res->res->end += get_res_add_size(realloc_head,
396 dev_res->res);
397
398 /*
399 * There are two kinds of additional resources in the list:
400 * 1. bridge resource -- IORESOURCE_STARTALIGN
401 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
402 * Here just fix the additional alignment for bridge
403 */
404 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
405 continue;
406
407 add_align = get_res_add_align(realloc_head, dev_res->res);
408
409 /*
410 * The "head" list is sorted by the alignment to make sure
411 * resources with bigger alignment will be assigned first.
412 * After we change the alignment of a dev_res in "head" list,
413 * we need to reorder the list by alignment to make it
414 * consistent.
415 */
416 if (add_align > dev_res->res->start) {
417 resource_size_t r_size = resource_size(dev_res->res);
418
419 dev_res->res->start = add_align;
420 dev_res->res->end = add_align + r_size - 1;
421
422 list_for_each_entry(dev_res2, head, list) {
423 align = pci_resource_alignment(dev_res2->dev,
424 dev_res2->res);
425 if (add_align > align) {
426 list_move_tail(&dev_res->list,
427 &dev_res2->list);
428 break;
429 }
430 }
431 }
432
433 }
434
435 /* Try updated head list with add_size added */
436 assign_requested_resources_sorted(head, &local_fail_head);
437
438 /* all assigned with add_size ? */
439 if (list_empty(&local_fail_head)) {
440 /* Remove head list from realloc_head list */
441 list_for_each_entry(dev_res, head, list)
442 remove_from_list(realloc_head, dev_res->res);
443 free_list(&save_head);
444 free_list(head);
445 return;
446 }
447
448 /* check failed type */
449 fail_type = pci_fail_res_type_mask(&local_fail_head);
450 /* remove not need to be released assigned res from head list etc */
451 list_for_each_entry_safe(dev_res, tmp_res, head, list)
452 if (dev_res->res->parent &&
453 !pci_need_to_release(fail_type, dev_res->res)) {
454 /* remove it from realloc_head list */
455 remove_from_list(realloc_head, dev_res->res);
456 remove_from_list(&save_head, dev_res->res);
457 list_del(&dev_res->list);
458 kfree(dev_res);
459 }
460
461 free_list(&local_fail_head);
462 /* Release assigned resource */
463 list_for_each_entry(dev_res, head, list)
464 if (dev_res->res->parent)
465 release_resource(dev_res->res);
466 /* Restore start/end/flags from saved list */
467 list_for_each_entry(save_res, &save_head, list) {
468 struct resource *res = save_res->res;
469
470 res->start = save_res->start;
471 res->end = save_res->end;
472 res->flags = save_res->flags;
473 }
474 free_list(&save_head);
475
476requested_and_reassign:
477 /* Satisfy the must-have resource requests */
478 assign_requested_resources_sorted(head, fail_head);
479
480 /* Try to satisfy any additional optional resource
481 requests */
482 if (realloc_head)
483 reassign_resources_sorted(realloc_head, head);
484 free_list(head);
485}
486
487static void pdev_assign_resources_sorted(struct pci_dev *dev,
488 struct list_head *add_head,
489 struct list_head *fail_head)
490{
491 LIST_HEAD(head);
492
493 __dev_sort_resources(dev, &head);
494 __assign_resources_sorted(&head, add_head, fail_head);
495
496}
497
498static void pbus_assign_resources_sorted(const struct pci_bus *bus,
499 struct list_head *realloc_head,
500 struct list_head *fail_head)
501{
502 struct pci_dev *dev;
503 LIST_HEAD(head);
504
505 list_for_each_entry(dev, &bus->devices, bus_list)
506 __dev_sort_resources(dev, &head);
507
508 __assign_resources_sorted(&head, realloc_head, fail_head);
509}
510
511void pci_setup_cardbus(struct pci_bus *bus)
512{
513 struct pci_dev *bridge = bus->self;
514 struct resource *res;
515 struct pci_bus_region region;
516
517 pci_info(bridge, "CardBus bridge to %pR\n",
518 &bus->busn_res);
519
520 res = bus->resource[0];
521 pcibios_resource_to_bus(bridge->bus, ®ion, res);
522 if (res->flags & IORESOURCE_IO) {
523 /*
524 * The IO resource is allocated a range twice as large as it
525 * would normally need. This allows us to set both IO regs.
526 */
527 pci_info(bridge, " bridge window %pR\n", res);
528 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
529 region.start);
530 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
531 region.end);
532 }
533
534 res = bus->resource[1];
535 pcibios_resource_to_bus(bridge->bus, ®ion, res);
536 if (res->flags & IORESOURCE_IO) {
537 pci_info(bridge, " bridge window %pR\n", res);
538 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
539 region.start);
540 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
541 region.end);
542 }
543
544 res = bus->resource[2];
545 pcibios_resource_to_bus(bridge->bus, ®ion, res);
546 if (res->flags & IORESOURCE_MEM) {
547 pci_info(bridge, " bridge window %pR\n", res);
548 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
549 region.start);
550 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
551 region.end);
552 }
553
554 res = bus->resource[3];
555 pcibios_resource_to_bus(bridge->bus, ®ion, res);
556 if (res->flags & IORESOURCE_MEM) {
557 pci_info(bridge, " bridge window %pR\n", res);
558 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
559 region.start);
560 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
561 region.end);
562 }
563}
564EXPORT_SYMBOL(pci_setup_cardbus);
565
566/* Initialize bridges with base/limit values we have collected.
567 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
568 requires that if there is no I/O ports or memory behind the
569 bridge, corresponding range must be turned off by writing base
570 value greater than limit to the bridge's base/limit registers.
571
572 Note: care must be taken when updating I/O base/limit registers
573 of bridges which support 32-bit I/O. This update requires two
574 config space writes, so it's quite possible that an I/O window of
575 the bridge will have some undesirable address (e.g. 0) after the
576 first write. Ditto 64-bit prefetchable MMIO. */
577static void pci_setup_bridge_io(struct pci_dev *bridge)
578{
579 struct resource *res;
580 struct pci_bus_region region;
581 unsigned long io_mask;
582 u8 io_base_lo, io_limit_lo;
583 u16 l;
584 u32 io_upper16;
585
586 io_mask = PCI_IO_RANGE_MASK;
587 if (bridge->io_window_1k)
588 io_mask = PCI_IO_1K_RANGE_MASK;
589
590 /* Set up the top and bottom of the PCI I/O segment for this bus. */
591 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
592 pcibios_resource_to_bus(bridge->bus, ®ion, res);
593 if (res->flags & IORESOURCE_IO) {
594 pci_read_config_word(bridge, PCI_IO_BASE, &l);
595 io_base_lo = (region.start >> 8) & io_mask;
596 io_limit_lo = (region.end >> 8) & io_mask;
597 l = ((u16) io_limit_lo << 8) | io_base_lo;
598 /* Set up upper 16 bits of I/O base/limit. */
599 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
600 pci_info(bridge, " bridge window %pR\n", res);
601 } else {
602 /* Clear upper 16 bits of I/O base/limit. */
603 io_upper16 = 0;
604 l = 0x00f0;
605 }
606 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
607 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
608 /* Update lower 16 bits of I/O base/limit. */
609 pci_write_config_word(bridge, PCI_IO_BASE, l);
610 /* Update upper 16 bits of I/O base/limit. */
611 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
612}
613
614static void pci_setup_bridge_mmio(struct pci_dev *bridge)
615{
616 struct resource *res;
617 struct pci_bus_region region;
618 u32 l;
619
620 /* Set up the top and bottom of the PCI Memory segment for this bus. */
621 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
622 pcibios_resource_to_bus(bridge->bus, ®ion, res);
623 if (res->flags & IORESOURCE_MEM) {
624 l = (region.start >> 16) & 0xfff0;
625 l |= region.end & 0xfff00000;
626 pci_info(bridge, " bridge window %pR\n", res);
627 } else {
628 l = 0x0000fff0;
629 }
630 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
631}
632
633static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
634{
635 struct resource *res;
636 struct pci_bus_region region;
637 u32 l, bu, lu;
638
639 /* Clear out the upper 32 bits of PREF limit.
640 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
641 disables PREF range, which is ok. */
642 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
643
644 /* Set up PREF base/limit. */
645 bu = lu = 0;
646 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
647 pcibios_resource_to_bus(bridge->bus, ®ion, res);
648 if (res->flags & IORESOURCE_PREFETCH) {
649 l = (region.start >> 16) & 0xfff0;
650 l |= region.end & 0xfff00000;
651 if (res->flags & IORESOURCE_MEM_64) {
652 bu = upper_32_bits(region.start);
653 lu = upper_32_bits(region.end);
654 }
655 pci_info(bridge, " bridge window %pR\n", res);
656 } else {
657 l = 0x0000fff0;
658 }
659 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
660
661 /* Set the upper 32 bits of PREF base & limit. */
662 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
663 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
664}
665
666static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
667{
668 struct pci_dev *bridge = bus->self;
669
670 pci_info(bridge, "PCI bridge to %pR\n",
671 &bus->busn_res);
672
673 if (type & IORESOURCE_IO)
674 pci_setup_bridge_io(bridge);
675
676 if (type & IORESOURCE_MEM)
677 pci_setup_bridge_mmio(bridge);
678
679 if (type & IORESOURCE_PREFETCH)
680 pci_setup_bridge_mmio_pref(bridge);
681
682 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
683}
684
685void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
686{
687}
688
689void pci_setup_bridge(struct pci_bus *bus)
690{
691 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
692 IORESOURCE_PREFETCH;
693
694 pcibios_setup_bridge(bus, type);
695 __pci_setup_bridge(bus, type);
696}
697
698
699int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
700{
701 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
702 return 0;
703
704 if (pci_claim_resource(bridge, i) == 0)
705 return 0; /* claimed the window */
706
707 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
708 return 0;
709
710 if (!pci_bus_clip_resource(bridge, i))
711 return -EINVAL; /* clipping didn't change anything */
712
713 switch (i - PCI_BRIDGE_RESOURCES) {
714 case 0:
715 pci_setup_bridge_io(bridge);
716 break;
717 case 1:
718 pci_setup_bridge_mmio(bridge);
719 break;
720 case 2:
721 pci_setup_bridge_mmio_pref(bridge);
722 break;
723 default:
724 return -EINVAL;
725 }
726
727 if (pci_claim_resource(bridge, i) == 0)
728 return 0; /* claimed a smaller window */
729
730 return -EINVAL;
731}
732
733/* Check whether the bridge supports optional I/O and
734 prefetchable memory ranges. If not, the respective
735 base/limit registers must be read-only and read as 0. */
736static void pci_bridge_check_ranges(struct pci_bus *bus)
737{
738 u16 io;
739 u32 pmem;
740 struct pci_dev *bridge = bus->self;
741 struct resource *b_res;
742
743 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
744 b_res[1].flags |= IORESOURCE_MEM;
745
746 pci_read_config_word(bridge, PCI_IO_BASE, &io);
747 if (!io) {
748 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
749 pci_read_config_word(bridge, PCI_IO_BASE, &io);
750 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
751 }
752 if (io)
753 b_res[0].flags |= IORESOURCE_IO;
754
755 /* DECchip 21050 pass 2 errata: the bridge may miss an address
756 disconnect boundary by one PCI data phase.
757 Workaround: do not use prefetching on this device. */
758 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
759 return;
760
761 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
762 if (!pmem) {
763 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
764 0xffe0fff0);
765 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
766 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
767 }
768 if (pmem) {
769 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
770 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
771 PCI_PREF_RANGE_TYPE_64) {
772 b_res[2].flags |= IORESOURCE_MEM_64;
773 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
774 }
775 }
776
777 /* double check if bridge does support 64 bit pref */
778 if (b_res[2].flags & IORESOURCE_MEM_64) {
779 u32 mem_base_hi, tmp;
780 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
781 &mem_base_hi);
782 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
783 0xffffffff);
784 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
785 if (!tmp)
786 b_res[2].flags &= ~IORESOURCE_MEM_64;
787 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
788 mem_base_hi);
789 }
790}
791
792/* Helper function for sizing routines: find first available
793 bus resource of a given type. Note: we intentionally skip
794 the bus resources which have already been assigned (that is,
795 have non-NULL parent resource). */
796static struct resource *find_free_bus_resource(struct pci_bus *bus,
797 unsigned long type_mask, unsigned long type)
798{
799 int i;
800 struct resource *r;
801
802 pci_bus_for_each_resource(bus, r, i) {
803 if (r == &ioport_resource || r == &iomem_resource)
804 continue;
805 if (r && (r->flags & type_mask) == type && !r->parent)
806 return r;
807 }
808 return NULL;
809}
810
811static resource_size_t calculate_iosize(resource_size_t size,
812 resource_size_t min_size,
813 resource_size_t size1,
814 resource_size_t old_size,
815 resource_size_t align)
816{
817 if (size < min_size)
818 size = min_size;
819 if (old_size == 1)
820 old_size = 0;
821 /* To be fixed in 2.5: we should have sort of HAVE_ISA
822 flag in the struct pci_bus. */
823#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
824 size = (size & 0xff) + ((size & ~0xffUL) << 2);
825#endif
826 size = ALIGN(size + size1, align);
827 if (size < old_size)
828 size = old_size;
829 return size;
830}
831
832static resource_size_t calculate_memsize(resource_size_t size,
833 resource_size_t min_size,
834 resource_size_t size1,
835 resource_size_t old_size,
836 resource_size_t align)
837{
838 if (size < min_size)
839 size = min_size;
840 if (old_size == 1)
841 old_size = 0;
842 if (size < old_size)
843 size = old_size;
844 size = ALIGN(size + size1, align);
845 return size;
846}
847
848resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
849 unsigned long type)
850{
851 return 1;
852}
853
854#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
855#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
856#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
857
858static resource_size_t window_alignment(struct pci_bus *bus,
859 unsigned long type)
860{
861 resource_size_t align = 1, arch_align;
862
863 if (type & IORESOURCE_MEM)
864 align = PCI_P2P_DEFAULT_MEM_ALIGN;
865 else if (type & IORESOURCE_IO) {
866 /*
867 * Per spec, I/O windows are 4K-aligned, but some
868 * bridges have an extension to support 1K alignment.
869 */
870 if (bus->self->io_window_1k)
871 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
872 else
873 align = PCI_P2P_DEFAULT_IO_ALIGN;
874 }
875
876 arch_align = pcibios_window_alignment(bus, type);
877 return max(align, arch_align);
878}
879
880/**
881 * pbus_size_io() - size the io window of a given bus
882 *
883 * @bus : the bus
884 * @min_size : the minimum io window that must to be allocated
885 * @add_size : additional optional io window
886 * @realloc_head : track the additional io window on this list
887 *
888 * Sizing the IO windows of the PCI-PCI bridge is trivial,
889 * since these windows have 1K or 4K granularity and the IO ranges
890 * of non-bridge PCI devices are limited to 256 bytes.
891 * We must be careful with the ISA aliasing though.
892 */
893static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
894 resource_size_t add_size, struct list_head *realloc_head)
895{
896 struct pci_dev *dev;
897 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
898 IORESOURCE_IO);
899 resource_size_t size = 0, size0 = 0, size1 = 0;
900 resource_size_t children_add_size = 0;
901 resource_size_t min_align, align;
902
903 if (!b_res)
904 return;
905
906 min_align = window_alignment(bus, IORESOURCE_IO);
907 list_for_each_entry(dev, &bus->devices, bus_list) {
908 int i;
909
910 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
911 struct resource *r = &dev->resource[i];
912 unsigned long r_size;
913
914 if (r->parent || !(r->flags & IORESOURCE_IO))
915 continue;
916 r_size = resource_size(r);
917
918 if (r_size < 0x400)
919 /* Might be re-aligned for ISA */
920 size += r_size;
921 else
922 size1 += r_size;
923
924 align = pci_resource_alignment(dev, r);
925 if (align > min_align)
926 min_align = align;
927
928 if (realloc_head)
929 children_add_size += get_res_add_size(realloc_head, r);
930 }
931 }
932
933 size0 = calculate_iosize(size, min_size, size1,
934 resource_size(b_res), min_align);
935 if (children_add_size > add_size)
936 add_size = children_add_size;
937 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
938 calculate_iosize(size, min_size, add_size + size1,
939 resource_size(b_res), min_align);
940 if (!size0 && !size1) {
941 if (b_res->start || b_res->end)
942 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
943 b_res, &bus->busn_res);
944 b_res->flags = 0;
945 return;
946 }
947
948 b_res->start = min_align;
949 b_res->end = b_res->start + size0 - 1;
950 b_res->flags |= IORESOURCE_STARTALIGN;
951 if (size1 > size0 && realloc_head) {
952 add_to_list(realloc_head, bus->self, b_res, size1-size0,
953 min_align);
954 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
955 b_res, &bus->busn_res,
956 (unsigned long long)size1-size0);
957 }
958}
959
960static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
961 int max_order)
962{
963 resource_size_t align = 0;
964 resource_size_t min_align = 0;
965 int order;
966
967 for (order = 0; order <= max_order; order++) {
968 resource_size_t align1 = 1;
969
970 align1 <<= (order + 20);
971
972 if (!align)
973 min_align = align1;
974 else if (ALIGN(align + min_align, min_align) < align1)
975 min_align = align1 >> 1;
976 align += aligns[order];
977 }
978
979 return min_align;
980}
981
982/**
983 * pbus_size_mem() - size the memory window of a given bus
984 *
985 * @bus : the bus
986 * @mask: mask the resource flag, then compare it with type
987 * @type: the type of free resource from bridge
988 * @type2: second match type
989 * @type3: third match type
990 * @min_size : the minimum memory window that must to be allocated
991 * @add_size : additional optional memory window
992 * @realloc_head : track the additional memory window on this list
993 *
994 * Calculate the size of the bus and minimal alignment which
995 * guarantees that all child resources fit in this size.
996 *
997 * Returns -ENOSPC if there's no available bus resource of the desired type.
998 * Otherwise, sets the bus resource start/end to indicate the required
999 * size, adds things to realloc_head (if supplied), and returns 0.
1000 */
1001static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1002 unsigned long type, unsigned long type2,
1003 unsigned long type3,
1004 resource_size_t min_size, resource_size_t add_size,
1005 struct list_head *realloc_head)
1006{
1007 struct pci_dev *dev;
1008 resource_size_t min_align, align, size, size0, size1;
1009 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
1010 int order, max_order;
1011 struct resource *b_res = find_free_bus_resource(bus,
1012 mask | IORESOURCE_PREFETCH, type);
1013 resource_size_t children_add_size = 0;
1014 resource_size_t children_add_align = 0;
1015 resource_size_t add_align = 0;
1016
1017 if (!b_res)
1018 return -ENOSPC;
1019
1020 memset(aligns, 0, sizeof(aligns));
1021 max_order = 0;
1022 size = 0;
1023
1024 list_for_each_entry(dev, &bus->devices, bus_list) {
1025 int i;
1026
1027 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1028 struct resource *r = &dev->resource[i];
1029 resource_size_t r_size;
1030
1031 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1032 ((r->flags & mask) != type &&
1033 (r->flags & mask) != type2 &&
1034 (r->flags & mask) != type3))
1035 continue;
1036 r_size = resource_size(r);
1037#ifdef CONFIG_PCI_IOV
1038 /* put SRIOV requested res to the optional list */
1039 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1040 i <= PCI_IOV_RESOURCE_END) {
1041 add_align = max(pci_resource_alignment(dev, r), add_align);
1042 r->end = r->start - 1;
1043 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1044 children_add_size += r_size;
1045 continue;
1046 }
1047#endif
1048 /*
1049 * aligns[0] is for 1MB (since bridge memory
1050 * windows are always at least 1MB aligned), so
1051 * keep "order" from being negative for smaller
1052 * resources.
1053 */
1054 align = pci_resource_alignment(dev, r);
1055 order = __ffs(align) - 20;
1056 if (order < 0)
1057 order = 0;
1058 if (order >= ARRAY_SIZE(aligns)) {
1059 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1060 i, r, (unsigned long long) align);
1061 r->flags = 0;
1062 continue;
1063 }
1064 size += max(r_size, align);
1065 /* Exclude ranges with size > align from
1066 calculation of the alignment. */
1067 if (r_size <= align)
1068 aligns[order] += align;
1069 if (order > max_order)
1070 max_order = order;
1071
1072 if (realloc_head) {
1073 children_add_size += get_res_add_size(realloc_head, r);
1074 children_add_align = get_res_add_align(realloc_head, r);
1075 add_align = max(add_align, children_add_align);
1076 }
1077 }
1078 }
1079
1080 min_align = calculate_mem_align(aligns, max_order);
1081 min_align = max(min_align, window_alignment(bus, b_res->flags));
1082 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1083 add_align = max(min_align, add_align);
1084 if (children_add_size > add_size)
1085 add_size = children_add_size;
1086 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1087 calculate_memsize(size, min_size, add_size,
1088 resource_size(b_res), add_align);
1089 if (!size0 && !size1) {
1090 if (b_res->start || b_res->end)
1091 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1092 b_res, &bus->busn_res);
1093 b_res->flags = 0;
1094 return 0;
1095 }
1096 b_res->start = min_align;
1097 b_res->end = size0 + min_align - 1;
1098 b_res->flags |= IORESOURCE_STARTALIGN;
1099 if (size1 > size0 && realloc_head) {
1100 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1101 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1102 b_res, &bus->busn_res,
1103 (unsigned long long) (size1 - size0),
1104 (unsigned long long) add_align);
1105 }
1106 return 0;
1107}
1108
1109unsigned long pci_cardbus_resource_alignment(struct resource *res)
1110{
1111 if (res->flags & IORESOURCE_IO)
1112 return pci_cardbus_io_size;
1113 if (res->flags & IORESOURCE_MEM)
1114 return pci_cardbus_mem_size;
1115 return 0;
1116}
1117
1118static void pci_bus_size_cardbus(struct pci_bus *bus,
1119 struct list_head *realloc_head)
1120{
1121 struct pci_dev *bridge = bus->self;
1122 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1123 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1124 u16 ctrl;
1125
1126 if (b_res[0].parent)
1127 goto handle_b_res_1;
1128 /*
1129 * Reserve some resources for CardBus. We reserve
1130 * a fixed amount of bus space for CardBus bridges.
1131 */
1132 b_res[0].start = pci_cardbus_io_size;
1133 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1134 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1135 if (realloc_head) {
1136 b_res[0].end -= pci_cardbus_io_size;
1137 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1138 pci_cardbus_io_size);
1139 }
1140
1141handle_b_res_1:
1142 if (b_res[1].parent)
1143 goto handle_b_res_2;
1144 b_res[1].start = pci_cardbus_io_size;
1145 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1146 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1147 if (realloc_head) {
1148 b_res[1].end -= pci_cardbus_io_size;
1149 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1150 pci_cardbus_io_size);
1151 }
1152
1153handle_b_res_2:
1154 /* MEM1 must not be pref mmio */
1155 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1156 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1157 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1158 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1159 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1160 }
1161
1162 /*
1163 * Check whether prefetchable memory is supported
1164 * by this bridge.
1165 */
1166 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1167 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1168 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1169 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1170 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1171 }
1172
1173 if (b_res[2].parent)
1174 goto handle_b_res_3;
1175 /*
1176 * If we have prefetchable memory support, allocate
1177 * two regions. Otherwise, allocate one region of
1178 * twice the size.
1179 */
1180 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1181 b_res[2].start = pci_cardbus_mem_size;
1182 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1183 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1184 IORESOURCE_STARTALIGN;
1185 if (realloc_head) {
1186 b_res[2].end -= pci_cardbus_mem_size;
1187 add_to_list(realloc_head, bridge, b_res+2,
1188 pci_cardbus_mem_size, pci_cardbus_mem_size);
1189 }
1190
1191 /* reduce that to half */
1192 b_res_3_size = pci_cardbus_mem_size;
1193 }
1194
1195handle_b_res_3:
1196 if (b_res[3].parent)
1197 goto handle_done;
1198 b_res[3].start = pci_cardbus_mem_size;
1199 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1200 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1201 if (realloc_head) {
1202 b_res[3].end -= b_res_3_size;
1203 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1204 pci_cardbus_mem_size);
1205 }
1206
1207handle_done:
1208 ;
1209}
1210
1211void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1212{
1213 struct pci_dev *dev;
1214 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1215 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1216 struct resource *b_res;
1217 int ret;
1218
1219 list_for_each_entry(dev, &bus->devices, bus_list) {
1220 struct pci_bus *b = dev->subordinate;
1221 if (!b)
1222 continue;
1223
1224 switch (dev->class >> 8) {
1225 case PCI_CLASS_BRIDGE_CARDBUS:
1226 pci_bus_size_cardbus(b, realloc_head);
1227 break;
1228
1229 case PCI_CLASS_BRIDGE_PCI:
1230 default:
1231 __pci_bus_size_bridges(b, realloc_head);
1232 break;
1233 }
1234 }
1235
1236 /* The root bus? */
1237 if (pci_is_root_bus(bus))
1238 return;
1239
1240 switch (bus->self->class >> 8) {
1241 case PCI_CLASS_BRIDGE_CARDBUS:
1242 /* don't size cardbuses yet. */
1243 break;
1244
1245 case PCI_CLASS_BRIDGE_PCI:
1246 pci_bridge_check_ranges(bus);
1247 if (bus->self->is_hotplug_bridge) {
1248 additional_io_size = pci_hotplug_io_size;
1249 additional_mem_size = pci_hotplug_mem_size;
1250 }
1251 /* Fall through */
1252 default:
1253 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1254 additional_io_size, realloc_head);
1255
1256 /*
1257 * If there's a 64-bit prefetchable MMIO window, compute
1258 * the size required to put all 64-bit prefetchable
1259 * resources in it.
1260 */
1261 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1262 mask = IORESOURCE_MEM;
1263 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1264 if (b_res[2].flags & IORESOURCE_MEM_64) {
1265 prefmask |= IORESOURCE_MEM_64;
1266 ret = pbus_size_mem(bus, prefmask, prefmask,
1267 prefmask, prefmask,
1268 realloc_head ? 0 : additional_mem_size,
1269 additional_mem_size, realloc_head);
1270
1271 /*
1272 * If successful, all non-prefetchable resources
1273 * and any 32-bit prefetchable resources will go in
1274 * the non-prefetchable window.
1275 */
1276 if (ret == 0) {
1277 mask = prefmask;
1278 type2 = prefmask & ~IORESOURCE_MEM_64;
1279 type3 = prefmask & ~IORESOURCE_PREFETCH;
1280 }
1281 }
1282
1283 /*
1284 * If there is no 64-bit prefetchable window, compute the
1285 * size required to put all prefetchable resources in the
1286 * 32-bit prefetchable window (if there is one).
1287 */
1288 if (!type2) {
1289 prefmask &= ~IORESOURCE_MEM_64;
1290 ret = pbus_size_mem(bus, prefmask, prefmask,
1291 prefmask, prefmask,
1292 realloc_head ? 0 : additional_mem_size,
1293 additional_mem_size, realloc_head);
1294
1295 /*
1296 * If successful, only non-prefetchable resources
1297 * will go in the non-prefetchable window.
1298 */
1299 if (ret == 0)
1300 mask = prefmask;
1301 else
1302 additional_mem_size += additional_mem_size;
1303
1304 type2 = type3 = IORESOURCE_MEM;
1305 }
1306
1307 /*
1308 * Compute the size required to put everything else in the
1309 * non-prefetchable window. This includes:
1310 *
1311 * - all non-prefetchable resources
1312 * - 32-bit prefetchable resources if there's a 64-bit
1313 * prefetchable window or no prefetchable window at all
1314 * - 64-bit prefetchable resources if there's no
1315 * prefetchable window at all
1316 *
1317 * Note that the strategy in __pci_assign_resource() must
1318 * match that used here. Specifically, we cannot put a
1319 * 32-bit prefetchable resource in a 64-bit prefetchable
1320 * window.
1321 */
1322 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1323 realloc_head ? 0 : additional_mem_size,
1324 additional_mem_size, realloc_head);
1325 break;
1326 }
1327}
1328
1329void pci_bus_size_bridges(struct pci_bus *bus)
1330{
1331 __pci_bus_size_bridges(bus, NULL);
1332}
1333EXPORT_SYMBOL(pci_bus_size_bridges);
1334
1335static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1336{
1337 int i;
1338 struct resource *parent_r;
1339 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1340 IORESOURCE_PREFETCH;
1341
1342 pci_bus_for_each_resource(b, parent_r, i) {
1343 if (!parent_r)
1344 continue;
1345
1346 if ((r->flags & mask) == (parent_r->flags & mask) &&
1347 resource_contains(parent_r, r))
1348 request_resource(parent_r, r);
1349 }
1350}
1351
1352/*
1353 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1354 * are skipped by pbus_assign_resources_sorted().
1355 */
1356static void pdev_assign_fixed_resources(struct pci_dev *dev)
1357{
1358 int i;
1359
1360 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1361 struct pci_bus *b;
1362 struct resource *r = &dev->resource[i];
1363
1364 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1365 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1366 continue;
1367
1368 b = dev->bus;
1369 while (b && !r->parent) {
1370 assign_fixed_resource_on_bus(b, r);
1371 b = b->parent;
1372 }
1373 }
1374}
1375
1376void __pci_bus_assign_resources(const struct pci_bus *bus,
1377 struct list_head *realloc_head,
1378 struct list_head *fail_head)
1379{
1380 struct pci_bus *b;
1381 struct pci_dev *dev;
1382
1383 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1384
1385 list_for_each_entry(dev, &bus->devices, bus_list) {
1386 pdev_assign_fixed_resources(dev);
1387
1388 b = dev->subordinate;
1389 if (!b)
1390 continue;
1391
1392 __pci_bus_assign_resources(b, realloc_head, fail_head);
1393
1394 switch (dev->class >> 8) {
1395 case PCI_CLASS_BRIDGE_PCI:
1396 if (!pci_is_enabled(dev))
1397 pci_setup_bridge(b);
1398 break;
1399
1400 case PCI_CLASS_BRIDGE_CARDBUS:
1401 pci_setup_cardbus(b);
1402 break;
1403
1404 default:
1405 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1406 pci_domain_nr(b), b->number);
1407 break;
1408 }
1409 }
1410}
1411
1412void pci_bus_assign_resources(const struct pci_bus *bus)
1413{
1414 __pci_bus_assign_resources(bus, NULL, NULL);
1415}
1416EXPORT_SYMBOL(pci_bus_assign_resources);
1417
1418static void pci_claim_device_resources(struct pci_dev *dev)
1419{
1420 int i;
1421
1422 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1423 struct resource *r = &dev->resource[i];
1424
1425 if (!r->flags || r->parent)
1426 continue;
1427
1428 pci_claim_resource(dev, i);
1429 }
1430}
1431
1432static void pci_claim_bridge_resources(struct pci_dev *dev)
1433{
1434 int i;
1435
1436 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1437 struct resource *r = &dev->resource[i];
1438
1439 if (!r->flags || r->parent)
1440 continue;
1441
1442 pci_claim_bridge_resource(dev, i);
1443 }
1444}
1445
1446static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1447{
1448 struct pci_dev *dev;
1449 struct pci_bus *child;
1450
1451 list_for_each_entry(dev, &b->devices, bus_list) {
1452 pci_claim_device_resources(dev);
1453
1454 child = dev->subordinate;
1455 if (child)
1456 pci_bus_allocate_dev_resources(child);
1457 }
1458}
1459
1460static void pci_bus_allocate_resources(struct pci_bus *b)
1461{
1462 struct pci_bus *child;
1463
1464 /*
1465 * Carry out a depth-first search on the PCI bus
1466 * tree to allocate bridge apertures. Read the
1467 * programmed bridge bases and recursively claim
1468 * the respective bridge resources.
1469 */
1470 if (b->self) {
1471 pci_read_bridge_bases(b);
1472 pci_claim_bridge_resources(b->self);
1473 }
1474
1475 list_for_each_entry(child, &b->children, node)
1476 pci_bus_allocate_resources(child);
1477}
1478
1479void pci_bus_claim_resources(struct pci_bus *b)
1480{
1481 pci_bus_allocate_resources(b);
1482 pci_bus_allocate_dev_resources(b);
1483}
1484EXPORT_SYMBOL(pci_bus_claim_resources);
1485
1486static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1487 struct list_head *add_head,
1488 struct list_head *fail_head)
1489{
1490 struct pci_bus *b;
1491
1492 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1493 add_head, fail_head);
1494
1495 b = bridge->subordinate;
1496 if (!b)
1497 return;
1498
1499 __pci_bus_assign_resources(b, add_head, fail_head);
1500
1501 switch (bridge->class >> 8) {
1502 case PCI_CLASS_BRIDGE_PCI:
1503 pci_setup_bridge(b);
1504 break;
1505
1506 case PCI_CLASS_BRIDGE_CARDBUS:
1507 pci_setup_cardbus(b);
1508 break;
1509
1510 default:
1511 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1512 pci_domain_nr(b), b->number);
1513 break;
1514 }
1515}
1516
1517#define PCI_RES_TYPE_MASK \
1518 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1519 IORESOURCE_MEM_64)
1520
1521static void pci_bridge_release_resources(struct pci_bus *bus,
1522 unsigned long type)
1523{
1524 struct pci_dev *dev = bus->self;
1525 struct resource *r;
1526 unsigned old_flags = 0;
1527 struct resource *b_res;
1528 int idx = 1;
1529
1530 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1531
1532 /*
1533 * 1. if there is io port assign fail, will release bridge
1534 * io port.
1535 * 2. if there is non pref mmio assign fail, release bridge
1536 * nonpref mmio.
1537 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1538 * is 64bit, release bridge pref mmio.
1539 * 4. if there is pref mmio assign fail, and bridge pref is
1540 * 32bit mmio, release bridge pref mmio
1541 * 5. if there is pref mmio assign fail, and bridge pref is not
1542 * assigned, release bridge nonpref mmio.
1543 */
1544 if (type & IORESOURCE_IO)
1545 idx = 0;
1546 else if (!(type & IORESOURCE_PREFETCH))
1547 idx = 1;
1548 else if ((type & IORESOURCE_MEM_64) &&
1549 (b_res[2].flags & IORESOURCE_MEM_64))
1550 idx = 2;
1551 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1552 (b_res[2].flags & IORESOURCE_PREFETCH))
1553 idx = 2;
1554 else
1555 idx = 1;
1556
1557 r = &b_res[idx];
1558
1559 if (!r->parent)
1560 return;
1561
1562 /*
1563 * if there are children under that, we should release them
1564 * all
1565 */
1566 release_child_resources(r);
1567 if (!release_resource(r)) {
1568 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1569 pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
1570 PCI_BRIDGE_RESOURCES + idx, r);
1571 /* keep the old size */
1572 r->end = resource_size(r) - 1;
1573 r->start = 0;
1574 r->flags = 0;
1575
1576 /* avoiding touch the one without PREF */
1577 if (type & IORESOURCE_PREFETCH)
1578 type = IORESOURCE_PREFETCH;
1579 __pci_setup_bridge(bus, type);
1580 /* for next child res under same bridge */
1581 r->flags = old_flags;
1582 }
1583}
1584
1585enum release_type {
1586 leaf_only,
1587 whole_subtree,
1588};
1589/*
1590 * try to release pci bridge resources that is from leaf bridge,
1591 * so we can allocate big new one later
1592 */
1593static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1594 unsigned long type,
1595 enum release_type rel_type)
1596{
1597 struct pci_dev *dev;
1598 bool is_leaf_bridge = true;
1599
1600 list_for_each_entry(dev, &bus->devices, bus_list) {
1601 struct pci_bus *b = dev->subordinate;
1602 if (!b)
1603 continue;
1604
1605 is_leaf_bridge = false;
1606
1607 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1608 continue;
1609
1610 if (rel_type == whole_subtree)
1611 pci_bus_release_bridge_resources(b, type,
1612 whole_subtree);
1613 }
1614
1615 if (pci_is_root_bus(bus))
1616 return;
1617
1618 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1619 return;
1620
1621 if ((rel_type == whole_subtree) || is_leaf_bridge)
1622 pci_bridge_release_resources(bus, type);
1623}
1624
1625static void pci_bus_dump_res(struct pci_bus *bus)
1626{
1627 struct resource *res;
1628 int i;
1629
1630 pci_bus_for_each_resource(bus, res, i) {
1631 if (!res || !res->end || !res->flags)
1632 continue;
1633
1634 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1635 }
1636}
1637
1638static void pci_bus_dump_resources(struct pci_bus *bus)
1639{
1640 struct pci_bus *b;
1641 struct pci_dev *dev;
1642
1643
1644 pci_bus_dump_res(bus);
1645
1646 list_for_each_entry(dev, &bus->devices, bus_list) {
1647 b = dev->subordinate;
1648 if (!b)
1649 continue;
1650
1651 pci_bus_dump_resources(b);
1652 }
1653}
1654
1655static int pci_bus_get_depth(struct pci_bus *bus)
1656{
1657 int depth = 0;
1658 struct pci_bus *child_bus;
1659
1660 list_for_each_entry(child_bus, &bus->children, node) {
1661 int ret;
1662
1663 ret = pci_bus_get_depth(child_bus);
1664 if (ret + 1 > depth)
1665 depth = ret + 1;
1666 }
1667
1668 return depth;
1669}
1670
1671/*
1672 * -1: undefined, will auto detect later
1673 * 0: disabled by user
1674 * 1: disabled by auto detect
1675 * 2: enabled by user
1676 * 3: enabled by auto detect
1677 */
1678enum enable_type {
1679 undefined = -1,
1680 user_disabled,
1681 auto_disabled,
1682 user_enabled,
1683 auto_enabled,
1684};
1685
1686static enum enable_type pci_realloc_enable = undefined;
1687void __init pci_realloc_get_opt(char *str)
1688{
1689 if (!strncmp(str, "off", 3))
1690 pci_realloc_enable = user_disabled;
1691 else if (!strncmp(str, "on", 2))
1692 pci_realloc_enable = user_enabled;
1693}
1694static bool pci_realloc_enabled(enum enable_type enable)
1695{
1696 return enable >= user_enabled;
1697}
1698
1699#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1700static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1701{
1702 int i;
1703 bool *unassigned = data;
1704
1705 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1706 struct resource *r = &dev->resource[i];
1707 struct pci_bus_region region;
1708
1709 /* Not assigned or rejected by kernel? */
1710 if (!r->flags)
1711 continue;
1712
1713 pcibios_resource_to_bus(dev->bus, ®ion, r);
1714 if (!region.start) {
1715 *unassigned = true;
1716 return 1; /* return early from pci_walk_bus() */
1717 }
1718 }
1719
1720 return 0;
1721}
1722
1723static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1724 enum enable_type enable_local)
1725{
1726 bool unassigned = false;
1727
1728 if (enable_local != undefined)
1729 return enable_local;
1730
1731 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1732 if (unassigned)
1733 return auto_enabled;
1734
1735 return enable_local;
1736}
1737#else
1738static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1739 enum enable_type enable_local)
1740{
1741 return enable_local;
1742}
1743#endif
1744
1745/*
1746 * first try will not touch pci bridge res
1747 * second and later try will clear small leaf bridge res
1748 * will stop till to the max depth if can not find good one
1749 */
1750void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1751{
1752 LIST_HEAD(realloc_head); /* list of resources that
1753 want additional resources */
1754 struct list_head *add_list = NULL;
1755 int tried_times = 0;
1756 enum release_type rel_type = leaf_only;
1757 LIST_HEAD(fail_head);
1758 struct pci_dev_resource *fail_res;
1759 int pci_try_num = 1;
1760 enum enable_type enable_local;
1761
1762 /* don't realloc if asked to do so */
1763 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1764 if (pci_realloc_enabled(enable_local)) {
1765 int max_depth = pci_bus_get_depth(bus);
1766
1767 pci_try_num = max_depth + 1;
1768 dev_printk(KERN_DEBUG, &bus->dev,
1769 "max bus depth: %d pci_try_num: %d\n",
1770 max_depth, pci_try_num);
1771 }
1772
1773again:
1774 /*
1775 * last try will use add_list, otherwise will try good to have as
1776 * must have, so can realloc parent bridge resource
1777 */
1778 if (tried_times + 1 == pci_try_num)
1779 add_list = &realloc_head;
1780 /* Depth first, calculate sizes and alignments of all
1781 subordinate buses. */
1782 __pci_bus_size_bridges(bus, add_list);
1783
1784 /* Depth last, allocate resources and update the hardware. */
1785 __pci_bus_assign_resources(bus, add_list, &fail_head);
1786 if (add_list)
1787 BUG_ON(!list_empty(add_list));
1788 tried_times++;
1789
1790 /* any device complain? */
1791 if (list_empty(&fail_head))
1792 goto dump;
1793
1794 if (tried_times >= pci_try_num) {
1795 if (enable_local == undefined)
1796 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1797 else if (enable_local == auto_enabled)
1798 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1799
1800 free_list(&fail_head);
1801 goto dump;
1802 }
1803
1804 dev_printk(KERN_DEBUG, &bus->dev,
1805 "No. %d try to assign unassigned res\n", tried_times + 1);
1806
1807 /* third times and later will not check if it is leaf */
1808 if ((tried_times + 1) > 2)
1809 rel_type = whole_subtree;
1810
1811 /*
1812 * Try to release leaf bridge's resources that doesn't fit resource of
1813 * child device under that bridge
1814 */
1815 list_for_each_entry(fail_res, &fail_head, list)
1816 pci_bus_release_bridge_resources(fail_res->dev->bus,
1817 fail_res->flags & PCI_RES_TYPE_MASK,
1818 rel_type);
1819
1820 /* restore size and flags */
1821 list_for_each_entry(fail_res, &fail_head, list) {
1822 struct resource *res = fail_res->res;
1823
1824 res->start = fail_res->start;
1825 res->end = fail_res->end;
1826 res->flags = fail_res->flags;
1827 if (fail_res->dev->subordinate)
1828 res->flags = 0;
1829 }
1830 free_list(&fail_head);
1831
1832 goto again;
1833
1834dump:
1835 /* dump the resource on buses */
1836 pci_bus_dump_resources(bus);
1837}
1838
1839void __init pci_assign_unassigned_resources(void)
1840{
1841 struct pci_bus *root_bus;
1842
1843 list_for_each_entry(root_bus, &pci_root_buses, node) {
1844 pci_assign_unassigned_root_bus_resources(root_bus);
1845
1846 /* Make sure the root bridge has a companion ACPI device: */
1847 if (ACPI_HANDLE(root_bus->bridge))
1848 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1849 }
1850}
1851
1852static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1853 struct list_head *add_list, resource_size_t available)
1854{
1855 struct pci_dev_resource *dev_res;
1856
1857 if (res->parent)
1858 return;
1859
1860 if (resource_size(res) >= available)
1861 return;
1862
1863 dev_res = res_to_dev_res(add_list, res);
1864 if (!dev_res)
1865 return;
1866
1867 /* Is there room to extend the window? */
1868 if (available - resource_size(res) <= dev_res->add_size)
1869 return;
1870
1871 dev_res->add_size = available - resource_size(res);
1872 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1873 &dev_res->add_size);
1874}
1875
1876static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1877 struct list_head *add_list, resource_size_t available_io,
1878 resource_size_t available_mmio, resource_size_t available_mmio_pref)
1879{
1880 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1881 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1882 struct resource *io_res, *mmio_res, *mmio_pref_res;
1883 struct pci_dev *dev, *bridge = bus->self;
1884
1885 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1886 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1887 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1888
1889 /*
1890 * Update additional resource list (add_list) to fill all the
1891 * extra resource space available for this port except the space
1892 * calculated in __pci_bus_size_bridges() which covers all the
1893 * devices currently connected to the port and below.
1894 */
1895 extend_bridge_window(bridge, io_res, add_list, available_io);
1896 extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1897 extend_bridge_window(bridge, mmio_pref_res, add_list,
1898 available_mmio_pref);
1899
1900 /*
1901 * Calculate the total amount of extra resource space we can
1902 * pass to bridges below this one. This is basically the
1903 * extra space reduced by the minimal required space for the
1904 * non-hotplug bridges.
1905 */
1906 remaining_io = available_io;
1907 remaining_mmio = available_mmio;
1908 remaining_mmio_pref = available_mmio_pref;
1909
1910 /*
1911 * Calculate how many hotplug bridges and normal bridges there
1912 * are on this bus. We will distribute the additional available
1913 * resources between hotplug bridges.
1914 */
1915 for_each_pci_bridge(dev, bus) {
1916 if (dev->is_hotplug_bridge)
1917 hotplug_bridges++;
1918 else
1919 normal_bridges++;
1920 }
1921
1922 for_each_pci_bridge(dev, bus) {
1923 const struct resource *res;
1924
1925 if (dev->is_hotplug_bridge)
1926 continue;
1927
1928 /*
1929 * Reduce the available resource space by what the
1930 * bridge and devices below it occupy.
1931 */
1932 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1933 if (!res->parent && available_io > resource_size(res))
1934 remaining_io -= resource_size(res);
1935
1936 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1937 if (!res->parent && available_mmio > resource_size(res))
1938 remaining_mmio -= resource_size(res);
1939
1940 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1941 if (!res->parent && available_mmio_pref > resource_size(res))
1942 remaining_mmio_pref -= resource_size(res);
1943 }
1944
1945 /*
1946 * Go over devices on this bus and distribute the remaining
1947 * resource space between hotplug bridges.
1948 */
1949 for_each_pci_bridge(dev, bus) {
1950 struct pci_bus *b;
1951
1952 b = dev->subordinate;
1953 if (!b)
1954 continue;
1955
1956 if (!hotplug_bridges && normal_bridges == 1) {
1957 /*
1958 * There is only one bridge on the bus (upstream
1959 * port) so it gets all available resources
1960 * which it can then distribute to the possible
1961 * hotplug bridges below.
1962 */
1963 pci_bus_distribute_available_resources(b, add_list,
1964 available_io, available_mmio,
1965 available_mmio_pref);
1966 } else if (dev->is_hotplug_bridge) {
1967 resource_size_t align, io, mmio, mmio_pref;
1968
1969 /*
1970 * Distribute available extra resources equally
1971 * between hotplug-capable downstream ports
1972 * taking alignment into account.
1973 *
1974 * Here hotplug_bridges is always != 0.
1975 */
1976 align = pci_resource_alignment(bridge, io_res);
1977 io = div64_ul(available_io, hotplug_bridges);
1978 io = min(ALIGN(io, align), remaining_io);
1979 remaining_io -= io;
1980
1981 align = pci_resource_alignment(bridge, mmio_res);
1982 mmio = div64_ul(available_mmio, hotplug_bridges);
1983 mmio = min(ALIGN(mmio, align), remaining_mmio);
1984 remaining_mmio -= mmio;
1985
1986 align = pci_resource_alignment(bridge, mmio_pref_res);
1987 mmio_pref = div64_ul(available_mmio_pref,
1988 hotplug_bridges);
1989 mmio_pref = min(ALIGN(mmio_pref, align),
1990 remaining_mmio_pref);
1991 remaining_mmio_pref -= mmio_pref;
1992
1993 pci_bus_distribute_available_resources(b, add_list, io,
1994 mmio, mmio_pref);
1995 }
1996 }
1997}
1998
1999static void
2000pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2001 struct list_head *add_list)
2002{
2003 resource_size_t available_io, available_mmio, available_mmio_pref;
2004 const struct resource *res;
2005
2006 if (!bridge->is_hotplug_bridge)
2007 return;
2008
2009 /* Take the initial extra resources from the hotplug port */
2010 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
2011 available_io = resource_size(res);
2012 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
2013 available_mmio = resource_size(res);
2014 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2015 available_mmio_pref = resource_size(res);
2016
2017 pci_bus_distribute_available_resources(bridge->subordinate,
2018 add_list, available_io, available_mmio, available_mmio_pref);
2019}
2020
2021void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2022{
2023 struct pci_bus *parent = bridge->subordinate;
2024 LIST_HEAD(add_list); /* list of resources that
2025 want additional resources */
2026 int tried_times = 0;
2027 LIST_HEAD(fail_head);
2028 struct pci_dev_resource *fail_res;
2029 int retval;
2030
2031again:
2032 __pci_bus_size_bridges(parent, &add_list);
2033
2034 /*
2035 * Distribute remaining resources (if any) equally between
2036 * hotplug bridges below. This makes it possible to extend the
2037 * hierarchy later without running out of resources.
2038 */
2039 pci_bridge_distribute_available_resources(bridge, &add_list);
2040
2041 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2042 BUG_ON(!list_empty(&add_list));
2043 tried_times++;
2044
2045 if (list_empty(&fail_head))
2046 goto enable_all;
2047
2048 if (tried_times >= 2) {
2049 /* still fail, don't need to try more */
2050 free_list(&fail_head);
2051 goto enable_all;
2052 }
2053
2054 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2055 tried_times + 1);
2056
2057 /*
2058 * Try to release leaf bridge's resources that doesn't fit resource of
2059 * child device under that bridge
2060 */
2061 list_for_each_entry(fail_res, &fail_head, list)
2062 pci_bus_release_bridge_resources(fail_res->dev->bus,
2063 fail_res->flags & PCI_RES_TYPE_MASK,
2064 whole_subtree);
2065
2066 /* restore size and flags */
2067 list_for_each_entry(fail_res, &fail_head, list) {
2068 struct resource *res = fail_res->res;
2069
2070 res->start = fail_res->start;
2071 res->end = fail_res->end;
2072 res->flags = fail_res->flags;
2073 if (fail_res->dev->subordinate)
2074 res->flags = 0;
2075 }
2076 free_list(&fail_head);
2077
2078 goto again;
2079
2080enable_all:
2081 retval = pci_reenable_device(bridge);
2082 if (retval)
2083 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2084 pci_set_master(bridge);
2085}
2086EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2087
2088int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2089{
2090 struct pci_dev_resource *dev_res;
2091 struct pci_dev *next;
2092 LIST_HEAD(saved);
2093 LIST_HEAD(added);
2094 LIST_HEAD(failed);
2095 unsigned int i;
2096 int ret;
2097
2098 /* Walk to the root hub, releasing bridge BARs when possible */
2099 next = bridge;
2100 do {
2101 bridge = next;
2102 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2103 i++) {
2104 struct resource *res = &bridge->resource[i];
2105
2106 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2107 continue;
2108
2109 /* Ignore BARs which are still in use */
2110 if (res->child)
2111 continue;
2112
2113 ret = add_to_list(&saved, bridge, res, 0, 0);
2114 if (ret)
2115 goto cleanup;
2116
2117 pci_info(bridge, "BAR %d: releasing %pR\n",
2118 i, res);
2119
2120 if (res->parent)
2121 release_resource(res);
2122 res->start = 0;
2123 res->end = 0;
2124 break;
2125 }
2126 if (i == PCI_BRIDGE_RESOURCE_END)
2127 break;
2128
2129 next = bridge->bus ? bridge->bus->self : NULL;
2130 } while (next);
2131
2132 if (list_empty(&saved))
2133 return -ENOENT;
2134
2135 __pci_bus_size_bridges(bridge->subordinate, &added);
2136 __pci_bridge_assign_resources(bridge, &added, &failed);
2137 BUG_ON(!list_empty(&added));
2138
2139 if (!list_empty(&failed)) {
2140 ret = -ENOSPC;
2141 goto cleanup;
2142 }
2143
2144 list_for_each_entry(dev_res, &saved, list) {
2145 /* Skip the bridge we just assigned resources for. */
2146 if (bridge == dev_res->dev)
2147 continue;
2148
2149 bridge = dev_res->dev;
2150 pci_setup_bridge(bridge->subordinate);
2151 }
2152
2153 free_list(&saved);
2154 return 0;
2155
2156cleanup:
2157 /* restore size and flags */
2158 list_for_each_entry(dev_res, &failed, list) {
2159 struct resource *res = dev_res->res;
2160
2161 res->start = dev_res->start;
2162 res->end = dev_res->end;
2163 res->flags = dev_res->flags;
2164 }
2165 free_list(&failed);
2166
2167 /* Revert to the old configuration */
2168 list_for_each_entry(dev_res, &saved, list) {
2169 struct resource *res = dev_res->res;
2170
2171 bridge = dev_res->dev;
2172 i = res - bridge->resource;
2173
2174 res->start = dev_res->start;
2175 res->end = dev_res->end;
2176 res->flags = dev_res->flags;
2177
2178 pci_claim_resource(bridge, i);
2179 pci_setup_bridge(bridge->subordinate);
2180 }
2181 free_list(&saved);
2182
2183 return ret;
2184}
2185
2186void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2187{
2188 struct pci_dev *dev;
2189 LIST_HEAD(add_list); /* list of resources that
2190 want additional resources */
2191
2192 down_read(&pci_bus_sem);
2193 for_each_pci_bridge(dev, bus)
2194 if (pci_has_subordinate(dev))
2195 __pci_bus_size_bridges(dev->subordinate, &add_list);
2196 up_read(&pci_bus_sem);
2197 __pci_bus_assign_resources(bus, &add_list, NULL);
2198 BUG_ON(!list_empty(&add_list));
2199}
2200EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);