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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/bitops.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/netdevice.h>
13#include <linux/ipv6.h>
14#include <linux/slab.h>
15#include <net/checksum.h>
16#include <net/ip6_checksum.h>
17#include <net/pkt_sched.h>
18#include <net/pkt_cls.h>
19#include <linux/net_tstamp.h>
20#include <linux/mii.h>
21#include <linux/ethtool.h>
22#include <linux/if.h>
23#include <linux/if_vlan.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/ip.h>
28#include <linux/tcp.h>
29#include <linux/sctp.h>
30#include <linux/if_ether.h>
31#include <linux/aer.h>
32#include <linux/prefetch.h>
33#include <linux/bpf.h>
34#include <linux/bpf_trace.h>
35#include <linux/pm_runtime.h>
36#include <linux/etherdevice.h>
37#ifdef CONFIG_IGB_DCA
38#include <linux/dca.h>
39#endif
40#include <linux/i2c.h>
41#include "igb.h"
42
43enum queue_mode {
44 QUEUE_MODE_STRICT_PRIORITY,
45 QUEUE_MODE_STREAM_RESERVATION,
46};
47
48enum tx_queue_prio {
49 TX_QUEUE_PRIO_HIGH,
50 TX_QUEUE_PRIO_LOW,
51};
52
53char igb_driver_name[] = "igb";
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
56static const char igb_copyright[] =
57 "Copyright (c) 2007-2014 Intel Corporation.";
58
59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static const struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
99 /* required last entry */
100 {0, }
101};
102
103MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
104
105static int igb_setup_all_tx_resources(struct igb_adapter *);
106static int igb_setup_all_rx_resources(struct igb_adapter *);
107static void igb_free_all_tx_resources(struct igb_adapter *);
108static void igb_free_all_rx_resources(struct igb_adapter *);
109static void igb_setup_mrqc(struct igb_adapter *);
110static int igb_probe(struct pci_dev *, const struct pci_device_id *);
111static void igb_remove(struct pci_dev *pdev);
112static int igb_sw_init(struct igb_adapter *);
113int igb_open(struct net_device *);
114int igb_close(struct net_device *);
115static void igb_configure(struct igb_adapter *);
116static void igb_configure_tx(struct igb_adapter *);
117static void igb_configure_rx(struct igb_adapter *);
118static void igb_clean_all_tx_rings(struct igb_adapter *);
119static void igb_clean_all_rx_rings(struct igb_adapter *);
120static void igb_clean_tx_ring(struct igb_ring *);
121static void igb_clean_rx_ring(struct igb_ring *);
122static void igb_set_rx_mode(struct net_device *);
123static void igb_update_phy_info(struct timer_list *);
124static void igb_watchdog(struct timer_list *);
125static void igb_watchdog_task(struct work_struct *);
126static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127static void igb_get_stats64(struct net_device *dev,
128 struct rtnl_link_stats64 *stats);
129static int igb_change_mtu(struct net_device *, int);
130static int igb_set_mac(struct net_device *, void *);
131static void igb_set_uta(struct igb_adapter *adapter, bool set);
132static irqreturn_t igb_intr(int irq, void *);
133static irqreturn_t igb_intr_msi(int irq, void *);
134static irqreturn_t igb_msix_other(int irq, void *);
135static irqreturn_t igb_msix_ring(int irq, void *);
136#ifdef CONFIG_IGB_DCA
137static void igb_update_dca(struct igb_q_vector *);
138static void igb_setup_dca(struct igb_adapter *);
139#endif /* CONFIG_IGB_DCA */
140static int igb_poll(struct napi_struct *, int);
141static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142static int igb_clean_rx_irq(struct igb_q_vector *, int);
143static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145static void igb_reset_task(struct work_struct *);
146static void igb_vlan_mode(struct net_device *netdev,
147 netdev_features_t features);
148static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150static void igb_restore_vlan(struct igb_adapter *);
151static void igb_rar_set_index(struct igb_adapter *, u32);
152static void igb_ping_all_vfs(struct igb_adapter *);
153static void igb_msg_task(struct igb_adapter *);
154static void igb_vmm_control(struct igb_adapter *);
155static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156static void igb_flush_mac_table(struct igb_adapter *);
157static int igb_available_rars(struct igb_adapter *, u8);
158static void igb_set_default_mac_filter(struct igb_adapter *);
159static int igb_uc_sync(struct net_device *, const unsigned char *);
160static int igb_uc_unsync(struct net_device *, const unsigned char *);
161static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 bool setting);
168static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 bool setting);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
172static void igb_check_vf_rate_limit(struct igb_adapter *);
173static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175
176#ifdef CONFIG_PCI_IOV
177static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
179static int igb_disable_sriov(struct pci_dev *dev);
180static int igb_pci_disable_sriov(struct pci_dev *dev);
181#endif
182
183static int igb_suspend(struct device *);
184static int igb_resume(struct device *);
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192};
193static void igb_shutdown(struct pci_dev *);
194static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195#ifdef CONFIG_IGB_DCA
196static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201};
202#endif
203#ifdef CONFIG_PCI_IOV
204static unsigned int max_vfs;
205module_param(max_vfs, uint, 0);
206MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207#endif /* CONFIG_PCI_IOV */
208
209static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 pci_channel_state_t);
211static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212static void igb_io_resume(struct pci_dev *);
213
214static const struct pci_error_handlers igb_err_handler = {
215 .error_detected = igb_io_error_detected,
216 .slot_reset = igb_io_slot_reset,
217 .resume = igb_io_resume,
218};
219
220static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221
222static struct pci_driver igb_driver = {
223 .name = igb_driver_name,
224 .id_table = igb_pci_tbl,
225 .probe = igb_probe,
226 .remove = igb_remove,
227#ifdef CONFIG_PM
228 .driver.pm = &igb_pm_ops,
229#endif
230 .shutdown = igb_shutdown,
231 .sriov_configure = igb_pci_sriov_configure,
232 .err_handler = &igb_err_handler
233};
234
235MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237MODULE_LICENSE("GPL v2");
238
239#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240static int debug = -1;
241module_param(debug, int, 0);
242MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243
244struct igb_reg_info {
245 u32 ofs;
246 char *name;
247};
248
249static const struct igb_reg_info igb_reg_info_tbl[] = {
250
251 /* General Registers */
252 {E1000_CTRL, "CTRL"},
253 {E1000_STATUS, "STATUS"},
254 {E1000_CTRL_EXT, "CTRL_EXT"},
255
256 /* Interrupt Registers */
257 {E1000_ICR, "ICR"},
258
259 /* RX Registers */
260 {E1000_RCTL, "RCTL"},
261 {E1000_RDLEN(0), "RDLEN"},
262 {E1000_RDH(0), "RDH"},
263 {E1000_RDT(0), "RDT"},
264 {E1000_RXDCTL(0), "RXDCTL"},
265 {E1000_RDBAL(0), "RDBAL"},
266 {E1000_RDBAH(0), "RDBAH"},
267
268 /* TX Registers */
269 {E1000_TCTL, "TCTL"},
270 {E1000_TDBAL(0), "TDBAL"},
271 {E1000_TDBAH(0), "TDBAH"},
272 {E1000_TDLEN(0), "TDLEN"},
273 {E1000_TDH(0), "TDH"},
274 {E1000_TDT(0), "TDT"},
275 {E1000_TXDCTL(0), "TXDCTL"},
276 {E1000_TDFH, "TDFH"},
277 {E1000_TDFT, "TDFT"},
278 {E1000_TDFHS, "TDFHS"},
279 {E1000_TDFPC, "TDFPC"},
280
281 /* List Terminator */
282 {}
283};
284
285/* igb_regdump - register printout routine */
286static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287{
288 int n = 0;
289 char rname[16];
290 u32 regs[8];
291
292 switch (reginfo->ofs) {
293 case E1000_RDLEN(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDLEN(n));
296 break;
297 case E1000_RDH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDH(n));
300 break;
301 case E1000_RDT(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDT(n));
304 break;
305 case E1000_RXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RXDCTL(n));
308 break;
309 case E1000_RDBAL(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDBAL(n));
312 break;
313 case E1000_RDBAH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDBAH(n));
316 break;
317 case E1000_TDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDBAL(n));
320 break;
321 case E1000_TDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDBAH(n));
324 break;
325 case E1000_TDLEN(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TDLEN(n));
328 break;
329 case E1000_TDH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDH(n));
332 break;
333 case E1000_TDT(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDT(n));
336 break;
337 case E1000_TXDCTL(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TXDCTL(n));
340 break;
341 default:
342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 return;
344 }
345
346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 regs[2], regs[3]);
349}
350
351/* igb_dump - Print registers, Tx-rings and Rx-rings */
352static void igb_dump(struct igb_adapter *adapter)
353{
354 struct net_device *netdev = adapter->netdev;
355 struct e1000_hw *hw = &adapter->hw;
356 struct igb_reg_info *reginfo;
357 struct igb_ring *tx_ring;
358 union e1000_adv_tx_desc *tx_desc;
359 struct my_u0 { __le64 a; __le64 b; } *u0;
360 struct igb_ring *rx_ring;
361 union e1000_adv_rx_desc *rx_desc;
362 u32 staterr;
363 u16 i, n;
364
365 if (!netif_msg_hw(adapter))
366 return;
367
368 /* Print netdevice Info */
369 if (netdev) {
370 dev_info(&adapter->pdev->dev, "Net device Info\n");
371 pr_info("Device Name state trans_start\n");
372 pr_info("%-15s %016lX %016lX\n", netdev->name,
373 netdev->state, dev_trans_start(netdev));
374 }
375
376 /* Print Registers */
377 dev_info(&adapter->pdev->dev, "Register Dump\n");
378 pr_info(" Register Name Value\n");
379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 reginfo->name; reginfo++) {
381 igb_regdump(hw, reginfo);
382 }
383
384 /* Print TX Ring Summary */
385 if (!netdev || !netif_running(netdev))
386 goto exit;
387
388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 struct igb_tx_buffer *buffer_info;
392 tx_ring = adapter->tx_ring[n];
393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 (u64)dma_unmap_addr(buffer_info, dma),
397 dma_unmap_len(buffer_info, len),
398 buffer_info->next_to_watch,
399 (u64)buffer_info->time_stamp);
400 }
401
402 /* Print TX Rings */
403 if (!netif_msg_tx_done(adapter))
404 goto rx_ring_summary;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407
408 /* Transmit Descriptor Formats
409 *
410 * Advanced Transmit Descriptor
411 * +--------------------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +--------------------------------------------------------------+
414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
415 * +--------------------------------------------------------------+
416 * 63 46 45 40 39 38 36 35 32 31 24 15 0
417 */
418
419 for (n = 0; n < adapter->num_tx_queues; n++) {
420 tx_ring = adapter->tx_ring[n];
421 pr_info("------------------------------------\n");
422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 pr_info("------------------------------------\n");
424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
425
426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 const char *next_desc;
428 struct igb_tx_buffer *buffer_info;
429 tx_desc = IGB_TX_DESC(tx_ring, i);
430 buffer_info = &tx_ring->tx_buffer_info[i];
431 u0 = (struct my_u0 *)tx_desc;
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 next_desc = " NTC/U";
435 else if (i == tx_ring->next_to_use)
436 next_desc = " NTU";
437 else if (i == tx_ring->next_to_clean)
438 next_desc = " NTC";
439 else
440 next_desc = "";
441
442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
443 i, le64_to_cpu(u0->a),
444 le64_to_cpu(u0->b),
445 (u64)dma_unmap_addr(buffer_info, dma),
446 dma_unmap_len(buffer_info, len),
447 buffer_info->next_to_watch,
448 (u64)buffer_info->time_stamp,
449 buffer_info->skb, next_desc);
450
451 if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 print_hex_dump(KERN_INFO, "",
453 DUMP_PREFIX_ADDRESS,
454 16, 1, buffer_info->skb->data,
455 dma_unmap_len(buffer_info, len),
456 true);
457 }
458 }
459
460 /* Print RX Rings Summary */
461rx_ring_summary:
462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 pr_info("Queue [NTU] [NTC]\n");
464 for (n = 0; n < adapter->num_rx_queues; n++) {
465 rx_ring = adapter->rx_ring[n];
466 pr_info(" %5d %5X %5X\n",
467 n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 }
469
470 /* Print RX Rings */
471 if (!netif_msg_rx_status(adapter))
472 goto exit;
473
474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475
476 /* Advanced Receive Descriptor (Read) Format
477 * 63 1 0
478 * +-----------------------------------------------------+
479 * 0 | Packet Buffer Address [63:1] |A0/NSE|
480 * +----------------------------------------------+------+
481 * 8 | Header Buffer Address [63:1] | DD |
482 * +-----------------------------------------------------+
483 *
484 *
485 * Advanced Receive Descriptor (Write-Back) Format
486 *
487 * 63 48 47 32 31 30 21 20 17 16 4 3 0
488 * +------------------------------------------------------+
489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
490 * | Checksum Ident | | | | Type | Type |
491 * +------------------------------------------------------+
492 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 * +------------------------------------------------------+
494 * 63 48 47 32 31 20 19 0
495 */
496
497 for (n = 0; n < adapter->num_rx_queues; n++) {
498 rx_ring = adapter->rx_ring[n];
499 pr_info("------------------------------------\n");
500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 pr_info("------------------------------------\n");
502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504
505 for (i = 0; i < rx_ring->count; i++) {
506 const char *next_desc;
507 struct igb_rx_buffer *buffer_info;
508 buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IGB_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512
513 if (i == rx_ring->next_to_use)
514 next_desc = " NTU";
515 else if (i == rx_ring->next_to_clean)
516 next_desc = " NTC";
517 else
518 next_desc = "";
519
520 if (staterr & E1000_RXD_STAT_DD) {
521 /* Descriptor Done */
522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
523 "RWB", i,
524 le64_to_cpu(u0->a),
525 le64_to_cpu(u0->b),
526 next_desc);
527 } else {
528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
529 "R ", i,
530 le64_to_cpu(u0->a),
531 le64_to_cpu(u0->b),
532 (u64)buffer_info->dma,
533 next_desc);
534
535 if (netif_msg_pktdata(adapter) &&
536 buffer_info->dma && buffer_info->page) {
537 print_hex_dump(KERN_INFO, "",
538 DUMP_PREFIX_ADDRESS,
539 16, 1,
540 page_address(buffer_info->page) +
541 buffer_info->page_offset,
542 igb_rx_bufsz(rx_ring), true);
543 }
544 }
545 }
546 }
547
548exit:
549 return;
550}
551
552/**
553 * igb_get_i2c_data - Reads the I2C SDA data bit
554 * @data: opaque pointer to adapter struct
555 *
556 * Returns the I2C data bit value
557 **/
558static int igb_get_i2c_data(void *data)
559{
560 struct igb_adapter *adapter = (struct igb_adapter *)data;
561 struct e1000_hw *hw = &adapter->hw;
562 s32 i2cctl = rd32(E1000_I2CPARAMS);
563
564 return !!(i2cctl & E1000_I2C_DATA_IN);
565}
566
567/**
568 * igb_set_i2c_data - Sets the I2C data bit
569 * @data: pointer to hardware structure
570 * @state: I2C data value (0 or 1) to set
571 *
572 * Sets the I2C data bit
573 **/
574static void igb_set_i2c_data(void *data, int state)
575{
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
579
580 if (state) {
581 i2cctl |= E1000_I2C_DATA_OUT | E1000_I2C_DATA_OE_N;
582 } else {
583 i2cctl &= ~E1000_I2C_DATA_OE_N;
584 i2cctl &= ~E1000_I2C_DATA_OUT;
585 }
586
587 wr32(E1000_I2CPARAMS, i2cctl);
588 wrfl();
589}
590
591/**
592 * igb_set_i2c_clk - Sets the I2C SCL clock
593 * @data: pointer to hardware structure
594 * @state: state to set clock
595 *
596 * Sets the I2C clock line to state
597 **/
598static void igb_set_i2c_clk(void *data, int state)
599{
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state) {
605 i2cctl |= E1000_I2C_CLK_OUT | E1000_I2C_CLK_OE_N;
606 } else {
607 i2cctl &= ~E1000_I2C_CLK_OUT;
608 i2cctl &= ~E1000_I2C_CLK_OE_N;
609 }
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612}
613
614/**
615 * igb_get_i2c_clk - Gets the I2C SCL clock state
616 * @data: pointer to hardware structure
617 *
618 * Gets the I2C clock state
619 **/
620static int igb_get_i2c_clk(void *data)
621{
622 struct igb_adapter *adapter = (struct igb_adapter *)data;
623 struct e1000_hw *hw = &adapter->hw;
624 s32 i2cctl = rd32(E1000_I2CPARAMS);
625
626 return !!(i2cctl & E1000_I2C_CLK_IN);
627}
628
629static const struct i2c_algo_bit_data igb_i2c_algo = {
630 .setsda = igb_set_i2c_data,
631 .setscl = igb_set_i2c_clk,
632 .getsda = igb_get_i2c_data,
633 .getscl = igb_get_i2c_clk,
634 .udelay = 5,
635 .timeout = 20,
636};
637
638/**
639 * igb_get_hw_dev - return device
640 * @hw: pointer to hardware structure
641 *
642 * used by hardware layer to print debugging information
643 **/
644struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
645{
646 struct igb_adapter *adapter = hw->back;
647 return adapter->netdev;
648}
649
650/**
651 * igb_init_module - Driver Registration Routine
652 *
653 * igb_init_module is the first routine called when the driver is
654 * loaded. All it does is register with the PCI subsystem.
655 **/
656static int __init igb_init_module(void)
657{
658 int ret;
659
660 pr_info("%s\n", igb_driver_string);
661 pr_info("%s\n", igb_copyright);
662
663#ifdef CONFIG_IGB_DCA
664 dca_register_notify(&dca_notifier);
665#endif
666 ret = pci_register_driver(&igb_driver);
667 return ret;
668}
669
670module_init(igb_init_module);
671
672/**
673 * igb_exit_module - Driver Exit Cleanup Routine
674 *
675 * igb_exit_module is called just before the driver is removed
676 * from memory.
677 **/
678static void __exit igb_exit_module(void)
679{
680#ifdef CONFIG_IGB_DCA
681 dca_unregister_notify(&dca_notifier);
682#endif
683 pci_unregister_driver(&igb_driver);
684}
685
686module_exit(igb_exit_module);
687
688#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
689/**
690 * igb_cache_ring_register - Descriptor ring to register mapping
691 * @adapter: board private structure to initialize
692 *
693 * Once we know the feature-set enabled for the device, we'll cache
694 * the register offset the descriptor ring is assigned to.
695 **/
696static void igb_cache_ring_register(struct igb_adapter *adapter)
697{
698 int i = 0, j = 0;
699 u32 rbase_offset = adapter->vfs_allocated_count;
700
701 switch (adapter->hw.mac.type) {
702 case e1000_82576:
703 /* The queues are allocated for virtualization such that VF 0
704 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
705 * In order to avoid collision we start at the first free queue
706 * and continue consuming queues in the same sequence
707 */
708 if (adapter->vfs_allocated_count) {
709 for (; i < adapter->rss_queues; i++)
710 adapter->rx_ring[i]->reg_idx = rbase_offset +
711 Q_IDX_82576(i);
712 }
713 fallthrough;
714 case e1000_82575:
715 case e1000_82580:
716 case e1000_i350:
717 case e1000_i354:
718 case e1000_i210:
719 case e1000_i211:
720 default:
721 for (; i < adapter->num_rx_queues; i++)
722 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
723 for (; j < adapter->num_tx_queues; j++)
724 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
725 break;
726 }
727}
728
729u32 igb_rd32(struct e1000_hw *hw, u32 reg)
730{
731 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
732 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
733 u32 value = 0;
734
735 if (E1000_REMOVED(hw_addr))
736 return ~value;
737
738 value = readl(&hw_addr[reg]);
739
740 /* reads should not return all F's */
741 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
742 struct net_device *netdev = igb->netdev;
743 hw->hw_addr = NULL;
744 netdev_err(netdev, "PCIe link lost\n");
745 WARN(pci_device_is_present(igb->pdev),
746 "igb: Failed to read reg 0x%x!\n", reg);
747 }
748
749 return value;
750}
751
752/**
753 * igb_write_ivar - configure ivar for given MSI-X vector
754 * @hw: pointer to the HW structure
755 * @msix_vector: vector number we are allocating to a given ring
756 * @index: row index of IVAR register to write within IVAR table
757 * @offset: column offset of in IVAR, should be multiple of 8
758 *
759 * This function is intended to handle the writing of the IVAR register
760 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
761 * each containing an cause allocation for an Rx and Tx ring, and a
762 * variable number of rows depending on the number of queues supported.
763 **/
764static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 int index, int offset)
766{
767 u32 ivar = array_rd32(E1000_IVAR0, index);
768
769 /* clear any bits that are currently set */
770 ivar &= ~((u32)0xFF << offset);
771
772 /* write vector and valid bit */
773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774
775 array_wr32(E1000_IVAR0, index, ivar);
776}
777
778#define IGB_N0_QUEUE -1
779static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
780{
781 struct igb_adapter *adapter = q_vector->adapter;
782 struct e1000_hw *hw = &adapter->hw;
783 int rx_queue = IGB_N0_QUEUE;
784 int tx_queue = IGB_N0_QUEUE;
785 u32 msixbm = 0;
786
787 if (q_vector->rx.ring)
788 rx_queue = q_vector->rx.ring->reg_idx;
789 if (q_vector->tx.ring)
790 tx_queue = q_vector->tx.ring->reg_idx;
791
792 switch (hw->mac.type) {
793 case e1000_82575:
794 /* The 82575 assigns vectors using a bitmask, which matches the
795 * bitmask for the EICR/EIMS/EIMC registers. To assign one
796 * or more queues to a vector, we write the appropriate bits
797 * into the MSIXBM register for that vector.
798 */
799 if (rx_queue > IGB_N0_QUEUE)
800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
801 if (tx_queue > IGB_N0_QUEUE)
802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
803 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
804 msixbm |= E1000_EIMS_OTHER;
805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
806 q_vector->eims_value = msixbm;
807 break;
808 case e1000_82576:
809 /* 82576 uses a table that essentially consists of 2 columns
810 * with 8 rows. The ordering is column-major so we use the
811 * lower 3 bits as the row index, and the 4th bit as the
812 * column offset.
813 */
814 if (rx_queue > IGB_N0_QUEUE)
815 igb_write_ivar(hw, msix_vector,
816 rx_queue & 0x7,
817 (rx_queue & 0x8) << 1);
818 if (tx_queue > IGB_N0_QUEUE)
819 igb_write_ivar(hw, msix_vector,
820 tx_queue & 0x7,
821 ((tx_queue & 0x8) << 1) + 8);
822 q_vector->eims_value = BIT(msix_vector);
823 break;
824 case e1000_82580:
825 case e1000_i350:
826 case e1000_i354:
827 case e1000_i210:
828 case e1000_i211:
829 /* On 82580 and newer adapters the scheme is similar to 82576
830 * however instead of ordering column-major we have things
831 * ordered row-major. So we traverse the table by using
832 * bit 0 as the column offset, and the remaining bits as the
833 * row index.
834 */
835 if (rx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 rx_queue >> 1,
838 (rx_queue & 0x1) << 4);
839 if (tx_queue > IGB_N0_QUEUE)
840 igb_write_ivar(hw, msix_vector,
841 tx_queue >> 1,
842 ((tx_queue & 0x1) << 4) + 8);
843 q_vector->eims_value = BIT(msix_vector);
844 break;
845 default:
846 BUG();
847 break;
848 }
849
850 /* add q_vector eims value to global eims_enable_mask */
851 adapter->eims_enable_mask |= q_vector->eims_value;
852
853 /* configure q_vector to set itr on first interrupt */
854 q_vector->set_itr = 1;
855}
856
857/**
858 * igb_configure_msix - Configure MSI-X hardware
859 * @adapter: board private structure to initialize
860 *
861 * igb_configure_msix sets up the hardware to properly
862 * generate MSI-X interrupts.
863 **/
864static void igb_configure_msix(struct igb_adapter *adapter)
865{
866 u32 tmp;
867 int i, vector = 0;
868 struct e1000_hw *hw = &adapter->hw;
869
870 adapter->eims_enable_mask = 0;
871
872 /* set vector for other causes, i.e. link changes */
873 switch (hw->mac.type) {
874 case e1000_82575:
875 tmp = rd32(E1000_CTRL_EXT);
876 /* enable MSI-X PBA support*/
877 tmp |= E1000_CTRL_EXT_PBA_CLR;
878
879 /* Auto-Mask interrupts upon ICR read. */
880 tmp |= E1000_CTRL_EXT_EIAME;
881 tmp |= E1000_CTRL_EXT_IRCA;
882
883 wr32(E1000_CTRL_EXT, tmp);
884
885 /* enable msix_other interrupt */
886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
887 adapter->eims_other = E1000_EIMS_OTHER;
888
889 break;
890
891 case e1000_82576:
892 case e1000_82580:
893 case e1000_i350:
894 case e1000_i354:
895 case e1000_i210:
896 case e1000_i211:
897 /* Turn on MSI-X capability first, or our settings
898 * won't stick. And it will take days to debug.
899 */
900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
901 E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 E1000_GPIE_NSICR);
903
904 /* enable msix_other interrupt */
905 adapter->eims_other = BIT(vector);
906 tmp = (vector++ | E1000_IVAR_VALID) << 8;
907
908 wr32(E1000_IVAR_MISC, tmp);
909 break;
910 default:
911 /* do nothing, since nothing else supports MSI-X */
912 break;
913 } /* switch (hw->mac.type) */
914
915 adapter->eims_enable_mask |= adapter->eims_other;
916
917 for (i = 0; i < adapter->num_q_vectors; i++)
918 igb_assign_vector(adapter->q_vector[i], vector++);
919
920 wrfl();
921}
922
923/**
924 * igb_request_msix - Initialize MSI-X interrupts
925 * @adapter: board private structure to initialize
926 *
927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
928 * kernel.
929 **/
930static int igb_request_msix(struct igb_adapter *adapter)
931{
932 unsigned int num_q_vectors = adapter->num_q_vectors;
933 struct net_device *netdev = adapter->netdev;
934 int i, err = 0, vector = 0, free_vector = 0;
935
936 err = request_irq(adapter->msix_entries[vector].vector,
937 igb_msix_other, 0, netdev->name, adapter);
938 if (err)
939 goto err_out;
940
941 if (num_q_vectors > MAX_Q_VECTORS) {
942 num_q_vectors = MAX_Q_VECTORS;
943 dev_warn(&adapter->pdev->dev,
944 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
945 adapter->num_q_vectors, MAX_Q_VECTORS);
946 }
947 for (i = 0; i < num_q_vectors; i++) {
948 struct igb_q_vector *q_vector = adapter->q_vector[i];
949
950 vector++;
951
952 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
953
954 if (q_vector->rx.ring && q_vector->tx.ring)
955 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
956 q_vector->rx.ring->queue_index);
957 else if (q_vector->tx.ring)
958 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
959 q_vector->tx.ring->queue_index);
960 else if (q_vector->rx.ring)
961 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
962 q_vector->rx.ring->queue_index);
963 else
964 sprintf(q_vector->name, "%s-unused", netdev->name);
965
966 err = request_irq(adapter->msix_entries[vector].vector,
967 igb_msix_ring, 0, q_vector->name,
968 q_vector);
969 if (err)
970 goto err_free;
971 }
972
973 igb_configure_msix(adapter);
974 return 0;
975
976err_free:
977 /* free already assigned IRQs */
978 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
979
980 vector--;
981 for (i = 0; i < vector; i++) {
982 free_irq(adapter->msix_entries[free_vector++].vector,
983 adapter->q_vector[i]);
984 }
985err_out:
986 return err;
987}
988
989/**
990 * igb_free_q_vector - Free memory allocated for specific interrupt vector
991 * @adapter: board private structure to initialize
992 * @v_idx: Index of vector to be freed
993 *
994 * This function frees the memory allocated to the q_vector.
995 **/
996static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
997{
998 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
999
1000 adapter->q_vector[v_idx] = NULL;
1001
1002 /* igb_get_stats64() might access the rings on this vector,
1003 * we must wait a grace period before freeing it.
1004 */
1005 if (q_vector)
1006 kfree_rcu(q_vector, rcu);
1007}
1008
1009/**
1010 * igb_reset_q_vector - Reset config for interrupt vector
1011 * @adapter: board private structure to initialize
1012 * @v_idx: Index of vector to be reset
1013 *
1014 * If NAPI is enabled it will delete any references to the
1015 * NAPI struct. This is preparation for igb_free_q_vector.
1016 **/
1017static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1018{
1019 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1020
1021 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1022 * allocated. So, q_vector is NULL so we should stop here.
1023 */
1024 if (!q_vector)
1025 return;
1026
1027 if (q_vector->tx.ring)
1028 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1029
1030 if (q_vector->rx.ring)
1031 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1032
1033 netif_napi_del(&q_vector->napi);
1034
1035}
1036
1037static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1038{
1039 int v_idx = adapter->num_q_vectors;
1040
1041 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1042 pci_disable_msix(adapter->pdev);
1043 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1044 pci_disable_msi(adapter->pdev);
1045
1046 while (v_idx--)
1047 igb_reset_q_vector(adapter, v_idx);
1048}
1049
1050/**
1051 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1052 * @adapter: board private structure to initialize
1053 *
1054 * This function frees the memory allocated to the q_vectors. In addition if
1055 * NAPI is enabled it will delete any references to the NAPI struct prior
1056 * to freeing the q_vector.
1057 **/
1058static void igb_free_q_vectors(struct igb_adapter *adapter)
1059{
1060 int v_idx = adapter->num_q_vectors;
1061
1062 adapter->num_tx_queues = 0;
1063 adapter->num_rx_queues = 0;
1064 adapter->num_q_vectors = 0;
1065
1066 while (v_idx--) {
1067 igb_reset_q_vector(adapter, v_idx);
1068 igb_free_q_vector(adapter, v_idx);
1069 }
1070}
1071
1072/**
1073 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1074 * @adapter: board private structure to initialize
1075 *
1076 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1077 * MSI-X interrupts allocated.
1078 */
1079static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1080{
1081 igb_free_q_vectors(adapter);
1082 igb_reset_interrupt_capability(adapter);
1083}
1084
1085/**
1086 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1087 * @adapter: board private structure to initialize
1088 * @msix: boolean value of MSIX capability
1089 *
1090 * Attempt to configure interrupts using the best available
1091 * capabilities of the hardware and kernel.
1092 **/
1093static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1094{
1095 int err;
1096 int numvecs, i;
1097
1098 if (!msix)
1099 goto msi_only;
1100 adapter->flags |= IGB_FLAG_HAS_MSIX;
1101
1102 /* Number of supported queues. */
1103 adapter->num_rx_queues = adapter->rss_queues;
1104 if (adapter->vfs_allocated_count)
1105 adapter->num_tx_queues = 1;
1106 else
1107 adapter->num_tx_queues = adapter->rss_queues;
1108
1109 /* start with one vector for every Rx queue */
1110 numvecs = adapter->num_rx_queues;
1111
1112 /* if Tx handler is separate add 1 for every Tx queue */
1113 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1114 numvecs += adapter->num_tx_queues;
1115
1116 /* store the number of vectors reserved for queues */
1117 adapter->num_q_vectors = numvecs;
1118
1119 /* add 1 vector for link status interrupts */
1120 numvecs++;
1121 for (i = 0; i < numvecs; i++)
1122 adapter->msix_entries[i].entry = i;
1123
1124 err = pci_enable_msix_range(adapter->pdev,
1125 adapter->msix_entries,
1126 numvecs,
1127 numvecs);
1128 if (err > 0)
1129 return;
1130
1131 igb_reset_interrupt_capability(adapter);
1132
1133 /* If we can't do MSI-X, try MSI */
1134msi_only:
1135 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1136#ifdef CONFIG_PCI_IOV
1137 /* disable SR-IOV for non MSI-X configurations */
1138 if (adapter->vf_data) {
1139 struct e1000_hw *hw = &adapter->hw;
1140 /* disable iov and allow time for transactions to clear */
1141 pci_disable_sriov(adapter->pdev);
1142 msleep(500);
1143
1144 kfree(adapter->vf_mac_list);
1145 adapter->vf_mac_list = NULL;
1146 kfree(adapter->vf_data);
1147 adapter->vf_data = NULL;
1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1149 wrfl();
1150 msleep(100);
1151 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1152 }
1153#endif
1154 adapter->vfs_allocated_count = 0;
1155 adapter->rss_queues = 1;
1156 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1157 adapter->num_rx_queues = 1;
1158 adapter->num_tx_queues = 1;
1159 adapter->num_q_vectors = 1;
1160 if (!pci_enable_msi(adapter->pdev))
1161 adapter->flags |= IGB_FLAG_HAS_MSI;
1162}
1163
1164static void igb_add_ring(struct igb_ring *ring,
1165 struct igb_ring_container *head)
1166{
1167 head->ring = ring;
1168 head->count++;
1169}
1170
1171/**
1172 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1173 * @adapter: board private structure to initialize
1174 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1175 * @v_idx: index of vector in adapter struct
1176 * @txr_count: total number of Tx rings to allocate
1177 * @txr_idx: index of first Tx ring to allocate
1178 * @rxr_count: total number of Rx rings to allocate
1179 * @rxr_idx: index of first Rx ring to allocate
1180 *
1181 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1182 **/
1183static int igb_alloc_q_vector(struct igb_adapter *adapter,
1184 int v_count, int v_idx,
1185 int txr_count, int txr_idx,
1186 int rxr_count, int rxr_idx)
1187{
1188 struct igb_q_vector *q_vector;
1189 struct igb_ring *ring;
1190 int ring_count;
1191 size_t size;
1192
1193 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1194 if (txr_count > 1 || rxr_count > 1)
1195 return -ENOMEM;
1196
1197 ring_count = txr_count + rxr_count;
1198 size = kmalloc_size_roundup(struct_size(q_vector, ring, ring_count));
1199
1200 /* allocate q_vector and rings */
1201 q_vector = adapter->q_vector[v_idx];
1202 if (!q_vector) {
1203 q_vector = kzalloc(size, GFP_KERNEL);
1204 } else if (size > ksize(q_vector)) {
1205 struct igb_q_vector *new_q_vector;
1206
1207 new_q_vector = kzalloc(size, GFP_KERNEL);
1208 if (new_q_vector)
1209 kfree_rcu(q_vector, rcu);
1210 q_vector = new_q_vector;
1211 } else {
1212 memset(q_vector, 0, size);
1213 }
1214 if (!q_vector)
1215 return -ENOMEM;
1216
1217 /* initialize NAPI */
1218 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll);
1219
1220 /* tie q_vector and adapter together */
1221 adapter->q_vector[v_idx] = q_vector;
1222 q_vector->adapter = adapter;
1223
1224 /* initialize work limits */
1225 q_vector->tx.work_limit = adapter->tx_work_limit;
1226
1227 /* initialize ITR configuration */
1228 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1229 q_vector->itr_val = IGB_START_ITR;
1230
1231 /* initialize pointer to rings */
1232 ring = q_vector->ring;
1233
1234 /* intialize ITR */
1235 if (rxr_count) {
1236 /* rx or rx/tx vector */
1237 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1238 q_vector->itr_val = adapter->rx_itr_setting;
1239 } else {
1240 /* tx only vector */
1241 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1242 q_vector->itr_val = adapter->tx_itr_setting;
1243 }
1244
1245 if (txr_count) {
1246 /* assign generic ring traits */
1247 ring->dev = &adapter->pdev->dev;
1248 ring->netdev = adapter->netdev;
1249
1250 /* configure backlink on ring */
1251 ring->q_vector = q_vector;
1252
1253 /* update q_vector Tx values */
1254 igb_add_ring(ring, &q_vector->tx);
1255
1256 /* For 82575, context index must be unique per ring. */
1257 if (adapter->hw.mac.type == e1000_82575)
1258 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1259
1260 /* apply Tx specific ring traits */
1261 ring->count = adapter->tx_ring_count;
1262 ring->queue_index = txr_idx;
1263
1264 ring->cbs_enable = false;
1265 ring->idleslope = 0;
1266 ring->sendslope = 0;
1267 ring->hicredit = 0;
1268 ring->locredit = 0;
1269
1270 u64_stats_init(&ring->tx_syncp);
1271 u64_stats_init(&ring->tx_syncp2);
1272
1273 /* assign ring to adapter */
1274 adapter->tx_ring[txr_idx] = ring;
1275
1276 /* push pointer to next ring */
1277 ring++;
1278 }
1279
1280 if (rxr_count) {
1281 /* assign generic ring traits */
1282 ring->dev = &adapter->pdev->dev;
1283 ring->netdev = adapter->netdev;
1284
1285 /* configure backlink on ring */
1286 ring->q_vector = q_vector;
1287
1288 /* update q_vector Rx values */
1289 igb_add_ring(ring, &q_vector->rx);
1290
1291 /* set flag indicating ring supports SCTP checksum offload */
1292 if (adapter->hw.mac.type >= e1000_82576)
1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1294
1295 /* On i350, i354, i210, and i211, loopback VLAN packets
1296 * have the tag byte-swapped.
1297 */
1298 if (adapter->hw.mac.type >= e1000_i350)
1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1300
1301 /* apply Rx specific ring traits */
1302 ring->count = adapter->rx_ring_count;
1303 ring->queue_index = rxr_idx;
1304
1305 u64_stats_init(&ring->rx_syncp);
1306
1307 /* assign ring to adapter */
1308 adapter->rx_ring[rxr_idx] = ring;
1309 }
1310
1311 return 0;
1312}
1313
1314
1315/**
1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1317 * @adapter: board private structure to initialize
1318 *
1319 * We allocate one q_vector per queue interrupt. If allocation fails we
1320 * return -ENOMEM.
1321 **/
1322static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1323{
1324 int q_vectors = adapter->num_q_vectors;
1325 int rxr_remaining = adapter->num_rx_queues;
1326 int txr_remaining = adapter->num_tx_queues;
1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1328 int err;
1329
1330 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1331 for (; rxr_remaining; v_idx++) {
1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1333 0, 0, 1, rxr_idx);
1334
1335 if (err)
1336 goto err_out;
1337
1338 /* update counts and index */
1339 rxr_remaining--;
1340 rxr_idx++;
1341 }
1342 }
1343
1344 for (; v_idx < q_vectors; v_idx++) {
1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347
1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1349 tqpv, txr_idx, rqpv, rxr_idx);
1350
1351 if (err)
1352 goto err_out;
1353
1354 /* update counts and index */
1355 rxr_remaining -= rqpv;
1356 txr_remaining -= tqpv;
1357 rxr_idx++;
1358 txr_idx++;
1359 }
1360
1361 return 0;
1362
1363err_out:
1364 adapter->num_tx_queues = 0;
1365 adapter->num_rx_queues = 0;
1366 adapter->num_q_vectors = 0;
1367
1368 while (v_idx--)
1369 igb_free_q_vector(adapter, v_idx);
1370
1371 return -ENOMEM;
1372}
1373
1374/**
1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1376 * @adapter: board private structure to initialize
1377 * @msix: boolean value of MSIX capability
1378 *
1379 * This function initializes the interrupts and allocates all of the queues.
1380 **/
1381static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1382{
1383 struct pci_dev *pdev = adapter->pdev;
1384 int err;
1385
1386 igb_set_interrupt_capability(adapter, msix);
1387
1388 err = igb_alloc_q_vectors(adapter);
1389 if (err) {
1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1391 goto err_alloc_q_vectors;
1392 }
1393
1394 igb_cache_ring_register(adapter);
1395
1396 return 0;
1397
1398err_alloc_q_vectors:
1399 igb_reset_interrupt_capability(adapter);
1400 return err;
1401}
1402
1403/**
1404 * igb_request_irq - initialize interrupts
1405 * @adapter: board private structure to initialize
1406 *
1407 * Attempts to configure interrupts using the best available
1408 * capabilities of the hardware and kernel.
1409 **/
1410static int igb_request_irq(struct igb_adapter *adapter)
1411{
1412 struct net_device *netdev = adapter->netdev;
1413 struct pci_dev *pdev = adapter->pdev;
1414 int err = 0;
1415
1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1417 err = igb_request_msix(adapter);
1418 if (!err)
1419 goto request_done;
1420 /* fall back to MSI */
1421 igb_free_all_tx_resources(adapter);
1422 igb_free_all_rx_resources(adapter);
1423
1424 igb_clear_interrupt_scheme(adapter);
1425 err = igb_init_interrupt_scheme(adapter, false);
1426 if (err)
1427 goto request_done;
1428
1429 igb_setup_all_tx_resources(adapter);
1430 igb_setup_all_rx_resources(adapter);
1431 igb_configure(adapter);
1432 }
1433
1434 igb_assign_vector(adapter->q_vector[0], 0);
1435
1436 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1437 err = request_irq(pdev->irq, igb_intr_msi, 0,
1438 netdev->name, adapter);
1439 if (!err)
1440 goto request_done;
1441
1442 /* fall back to legacy interrupts */
1443 igb_reset_interrupt_capability(adapter);
1444 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1445 }
1446
1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1448 netdev->name, adapter);
1449
1450 if (err)
1451 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1452 err);
1453
1454request_done:
1455 return err;
1456}
1457
1458static void igb_free_irq(struct igb_adapter *adapter)
1459{
1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1461 int vector = 0, i;
1462
1463 free_irq(adapter->msix_entries[vector++].vector, adapter);
1464
1465 for (i = 0; i < adapter->num_q_vectors; i++)
1466 free_irq(adapter->msix_entries[vector++].vector,
1467 adapter->q_vector[i]);
1468 } else {
1469 free_irq(adapter->pdev->irq, adapter);
1470 }
1471}
1472
1473/**
1474 * igb_irq_disable - Mask off interrupt generation on the NIC
1475 * @adapter: board private structure
1476 **/
1477static void igb_irq_disable(struct igb_adapter *adapter)
1478{
1479 struct e1000_hw *hw = &adapter->hw;
1480
1481 /* we need to be careful when disabling interrupts. The VFs are also
1482 * mapped into these registers and so clearing the bits can cause
1483 * issues on the VF drivers so we only need to clear what we set
1484 */
1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1486 u32 regval = rd32(E1000_EIAM);
1487
1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1489 wr32(E1000_EIMC, adapter->eims_enable_mask);
1490 regval = rd32(E1000_EIAC);
1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1492 }
1493
1494 wr32(E1000_IAM, 0);
1495 wr32(E1000_IMC, ~0);
1496 wrfl();
1497 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1498 int i;
1499
1500 for (i = 0; i < adapter->num_q_vectors; i++)
1501 synchronize_irq(adapter->msix_entries[i].vector);
1502 } else {
1503 synchronize_irq(adapter->pdev->irq);
1504 }
1505}
1506
1507/**
1508 * igb_irq_enable - Enable default interrupt generation settings
1509 * @adapter: board private structure
1510 **/
1511static void igb_irq_enable(struct igb_adapter *adapter)
1512{
1513 struct e1000_hw *hw = &adapter->hw;
1514
1515 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1516 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1517 u32 regval = rd32(E1000_EIAC);
1518
1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1520 regval = rd32(E1000_EIAM);
1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1522 wr32(E1000_EIMS, adapter->eims_enable_mask);
1523 if (adapter->vfs_allocated_count) {
1524 wr32(E1000_MBVFIMR, 0xFF);
1525 ims |= E1000_IMS_VMMB;
1526 }
1527 wr32(E1000_IMS, ims);
1528 } else {
1529 wr32(E1000_IMS, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
1531 wr32(E1000_IAM, IMS_ENABLE_MASK |
1532 E1000_IMS_DRSTA);
1533 }
1534}
1535
1536static void igb_update_mng_vlan(struct igb_adapter *adapter)
1537{
1538 struct e1000_hw *hw = &adapter->hw;
1539 u16 pf_id = adapter->vfs_allocated_count;
1540 u16 vid = adapter->hw.mng_cookie.vlan_id;
1541 u16 old_vid = adapter->mng_vlan_id;
1542
1543 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1544 /* add VID to filter table */
1545 igb_vfta_set(hw, vid, pf_id, true, true);
1546 adapter->mng_vlan_id = vid;
1547 } else {
1548 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1549 }
1550
1551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1552 (vid != old_vid) &&
1553 !test_bit(old_vid, adapter->active_vlans)) {
1554 /* remove VID from filter table */
1555 igb_vfta_set(hw, vid, pf_id, false, true);
1556 }
1557}
1558
1559/**
1560 * igb_release_hw_control - release control of the h/w to f/w
1561 * @adapter: address of board private structure
1562 *
1563 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1564 * For ASF and Pass Through versions of f/w this means that the
1565 * driver is no longer loaded.
1566 **/
1567static void igb_release_hw_control(struct igb_adapter *adapter)
1568{
1569 struct e1000_hw *hw = &adapter->hw;
1570 u32 ctrl_ext;
1571
1572 /* Let firmware take over control of h/w */
1573 ctrl_ext = rd32(E1000_CTRL_EXT);
1574 wr32(E1000_CTRL_EXT,
1575 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1576}
1577
1578/**
1579 * igb_get_hw_control - get control of the h/w from f/w
1580 * @adapter: address of board private structure
1581 *
1582 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1583 * For ASF and Pass Through versions of f/w this means that
1584 * the driver is loaded.
1585 **/
1586static void igb_get_hw_control(struct igb_adapter *adapter)
1587{
1588 struct e1000_hw *hw = &adapter->hw;
1589 u32 ctrl_ext;
1590
1591 /* Let firmware know the driver has taken over */
1592 ctrl_ext = rd32(E1000_CTRL_EXT);
1593 wr32(E1000_CTRL_EXT,
1594 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1595}
1596
1597static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1598{
1599 struct net_device *netdev = adapter->netdev;
1600 struct e1000_hw *hw = &adapter->hw;
1601
1602 WARN_ON(hw->mac.type != e1000_i210);
1603
1604 if (enable)
1605 adapter->flags |= IGB_FLAG_FQTSS;
1606 else
1607 adapter->flags &= ~IGB_FLAG_FQTSS;
1608
1609 if (netif_running(netdev))
1610 schedule_work(&adapter->reset_task);
1611}
1612
1613static bool is_fqtss_enabled(struct igb_adapter *adapter)
1614{
1615 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1616}
1617
1618static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1619 enum tx_queue_prio prio)
1620{
1621 u32 val;
1622
1623 WARN_ON(hw->mac.type != e1000_i210);
1624 WARN_ON(queue < 0 || queue > 4);
1625
1626 val = rd32(E1000_I210_TXDCTL(queue));
1627
1628 if (prio == TX_QUEUE_PRIO_HIGH)
1629 val |= E1000_TXDCTL_PRIORITY;
1630 else
1631 val &= ~E1000_TXDCTL_PRIORITY;
1632
1633 wr32(E1000_I210_TXDCTL(queue), val);
1634}
1635
1636static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1637{
1638 u32 val;
1639
1640 WARN_ON(hw->mac.type != e1000_i210);
1641 WARN_ON(queue < 0 || queue > 1);
1642
1643 val = rd32(E1000_I210_TQAVCC(queue));
1644
1645 if (mode == QUEUE_MODE_STREAM_RESERVATION)
1646 val |= E1000_TQAVCC_QUEUEMODE;
1647 else
1648 val &= ~E1000_TQAVCC_QUEUEMODE;
1649
1650 wr32(E1000_I210_TQAVCC(queue), val);
1651}
1652
1653static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1654{
1655 int i;
1656
1657 for (i = 0; i < adapter->num_tx_queues; i++) {
1658 if (adapter->tx_ring[i]->cbs_enable)
1659 return true;
1660 }
1661
1662 return false;
1663}
1664
1665static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1666{
1667 int i;
1668
1669 for (i = 0; i < adapter->num_tx_queues; i++) {
1670 if (adapter->tx_ring[i]->launchtime_enable)
1671 return true;
1672 }
1673
1674 return false;
1675}
1676
1677/**
1678 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1679 * @adapter: pointer to adapter struct
1680 * @queue: queue number
1681 *
1682 * Configure CBS and Launchtime for a given hardware queue.
1683 * Parameters are retrieved from the correct Tx ring, so
1684 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1685 * for setting those correctly prior to this function being called.
1686 **/
1687static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1688{
1689 struct net_device *netdev = adapter->netdev;
1690 struct e1000_hw *hw = &adapter->hw;
1691 struct igb_ring *ring;
1692 u32 tqavcc, tqavctrl;
1693 u16 value;
1694
1695 WARN_ON(hw->mac.type != e1000_i210);
1696 WARN_ON(queue < 0 || queue > 1);
1697 ring = adapter->tx_ring[queue];
1698
1699 /* If any of the Qav features is enabled, configure queues as SR and
1700 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1701 * as SP.
1702 */
1703 if (ring->cbs_enable || ring->launchtime_enable) {
1704 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1705 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1706 } else {
1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1708 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1709 }
1710
1711 /* If CBS is enabled, set DataTranARB and config its parameters. */
1712 if (ring->cbs_enable || queue == 0) {
1713 /* i210 does not allow the queue 0 to be in the Strict
1714 * Priority mode while the Qav mode is enabled, so,
1715 * instead of disabling strict priority mode, we give
1716 * queue 0 the maximum of credits possible.
1717 *
1718 * See section 8.12.19 of the i210 datasheet, "Note:
1719 * Queue0 QueueMode must be set to 1b when
1720 * TransmitMode is set to Qav."
1721 */
1722 if (queue == 0 && !ring->cbs_enable) {
1723 /* max "linkspeed" idleslope in kbps */
1724 ring->idleslope = 1000000;
1725 ring->hicredit = ETH_FRAME_LEN;
1726 }
1727
1728 /* Always set data transfer arbitration to credit-based
1729 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1730 * the queues.
1731 */
1732 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1733 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1734 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1735
1736 /* According to i210 datasheet section 7.2.7.7, we should set
1737 * the 'idleSlope' field from TQAVCC register following the
1738 * equation:
1739 *
1740 * For 100 Mbps link speed:
1741 *
1742 * value = BW * 0x7735 * 0.2 (E1)
1743 *
1744 * For 1000Mbps link speed:
1745 *
1746 * value = BW * 0x7735 * 2 (E2)
1747 *
1748 * E1 and E2 can be merged into one equation as shown below.
1749 * Note that 'link-speed' is in Mbps.
1750 *
1751 * value = BW * 0x7735 * 2 * link-speed
1752 * -------------- (E3)
1753 * 1000
1754 *
1755 * 'BW' is the percentage bandwidth out of full link speed
1756 * which can be found with the following equation. Note that
1757 * idleSlope here is the parameter from this function which
1758 * is in kbps.
1759 *
1760 * BW = idleSlope
1761 * ----------------- (E4)
1762 * link-speed * 1000
1763 *
1764 * That said, we can come up with a generic equation to
1765 * calculate the value we should set it TQAVCC register by
1766 * replacing 'BW' in E3 by E4. The resulting equation is:
1767 *
1768 * value = idleSlope * 0x7735 * 2 * link-speed
1769 * ----------------- -------------- (E5)
1770 * link-speed * 1000 1000
1771 *
1772 * 'link-speed' is present in both sides of the fraction so
1773 * it is canceled out. The final equation is the following:
1774 *
1775 * value = idleSlope * 61034
1776 * ----------------- (E6)
1777 * 1000000
1778 *
1779 * NOTE: For i210, given the above, we can see that idleslope
1780 * is represented in 16.38431 kbps units by the value at
1781 * the TQAVCC register (1Gbps / 61034), which reduces
1782 * the granularity for idleslope increments.
1783 * For instance, if you want to configure a 2576kbps
1784 * idleslope, the value to be written on the register
1785 * would have to be 157.23. If rounded down, you end
1786 * up with less bandwidth available than originally
1787 * required (~2572 kbps). If rounded up, you end up
1788 * with a higher bandwidth (~2589 kbps). Below the
1789 * approach we take is to always round up the
1790 * calculated value, so the resulting bandwidth might
1791 * be slightly higher for some configurations.
1792 */
1793 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1794
1795 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1796 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1797 tqavcc |= value;
1798 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1799
1800 wr32(E1000_I210_TQAVHC(queue),
1801 0x80000000 + ring->hicredit * 0x7735);
1802 } else {
1803
1804 /* Set idleSlope to zero. */
1805 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1806 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1807 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1808
1809 /* Set hiCredit to zero. */
1810 wr32(E1000_I210_TQAVHC(queue), 0);
1811
1812 /* If CBS is not enabled for any queues anymore, then return to
1813 * the default state of Data Transmission Arbitration on
1814 * TQAVCTRL.
1815 */
1816 if (!is_any_cbs_enabled(adapter)) {
1817 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1818 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1819 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1820 }
1821 }
1822
1823 /* If LaunchTime is enabled, set DataTranTIM. */
1824 if (ring->launchtime_enable) {
1825 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1826 * for any of the SR queues, and configure fetchtime delta.
1827 * XXX NOTE:
1828 * - LaunchTime will be enabled for all SR queues.
1829 * - A fixed offset can be added relative to the launch
1830 * time of all packets if configured at reg LAUNCH_OS0.
1831 * We are keeping it as 0 for now (default value).
1832 */
1833 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1834 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1835 E1000_TQAVCTRL_FETCHTIME_DELTA;
1836 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1837 } else {
1838 /* If Launchtime is not enabled for any SR queues anymore,
1839 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1840 * effectively disabling Launchtime.
1841 */
1842 if (!is_any_txtime_enabled(adapter)) {
1843 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1844 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1845 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1846 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1847 }
1848 }
1849
1850 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1851 * CBS are not configurable by software so we don't do any 'controller
1852 * configuration' in respect to these parameters.
1853 */
1854
1855 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1856 ring->cbs_enable ? "enabled" : "disabled",
1857 ring->launchtime_enable ? "enabled" : "disabled",
1858 queue,
1859 ring->idleslope, ring->sendslope,
1860 ring->hicredit, ring->locredit);
1861}
1862
1863static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1864 bool enable)
1865{
1866 struct igb_ring *ring;
1867
1868 if (queue < 0 || queue > adapter->num_tx_queues)
1869 return -EINVAL;
1870
1871 ring = adapter->tx_ring[queue];
1872 ring->launchtime_enable = enable;
1873
1874 return 0;
1875}
1876
1877static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1878 bool enable, int idleslope, int sendslope,
1879 int hicredit, int locredit)
1880{
1881 struct igb_ring *ring;
1882
1883 if (queue < 0 || queue > adapter->num_tx_queues)
1884 return -EINVAL;
1885
1886 ring = adapter->tx_ring[queue];
1887
1888 ring->cbs_enable = enable;
1889 ring->idleslope = idleslope;
1890 ring->sendslope = sendslope;
1891 ring->hicredit = hicredit;
1892 ring->locredit = locredit;
1893
1894 return 0;
1895}
1896
1897/**
1898 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1899 * @adapter: pointer to adapter struct
1900 *
1901 * Configure TQAVCTRL register switching the controller's Tx mode
1902 * if FQTSS mode is enabled or disabled. Additionally, will issue
1903 * a call to igb_config_tx_modes() per queue so any previously saved
1904 * Tx parameters are applied.
1905 **/
1906static void igb_setup_tx_mode(struct igb_adapter *adapter)
1907{
1908 struct net_device *netdev = adapter->netdev;
1909 struct e1000_hw *hw = &adapter->hw;
1910 u32 val;
1911
1912 /* Only i210 controller supports changing the transmission mode. */
1913 if (hw->mac.type != e1000_i210)
1914 return;
1915
1916 if (is_fqtss_enabled(adapter)) {
1917 int i, max_queue;
1918
1919 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1920 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1921 * so SP queues wait for SR ones.
1922 */
1923 val = rd32(E1000_I210_TQAVCTRL);
1924 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1925 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1926 wr32(E1000_I210_TQAVCTRL, val);
1927
1928 /* Configure Tx and Rx packet buffers sizes as described in
1929 * i210 datasheet section 7.2.7.7.
1930 */
1931 val = rd32(E1000_TXPBS);
1932 val &= ~I210_TXPBSIZE_MASK;
1933 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1934 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1935 wr32(E1000_TXPBS, val);
1936
1937 val = rd32(E1000_RXPBS);
1938 val &= ~I210_RXPBSIZE_MASK;
1939 val |= I210_RXPBSIZE_PB_30KB;
1940 wr32(E1000_RXPBS, val);
1941
1942 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1943 * register should not exceed the buffer size programmed in
1944 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1945 * so according to the datasheet we should set MAX_TPKT_SIZE to
1946 * 4kB / 64.
1947 *
1948 * However, when we do so, no frame from queue 2 and 3 are
1949 * transmitted. It seems the MAX_TPKT_SIZE should not be great
1950 * or _equal_ to the buffer size programmed in TXPBS. For this
1951 * reason, we set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1952 */
1953 val = (4096 - 1) / 64;
1954 wr32(E1000_I210_DTXMXPKTSZ, val);
1955
1956 /* Since FQTSS mode is enabled, apply any CBS configuration
1957 * previously set. If no previous CBS configuration has been
1958 * done, then the initial configuration is applied, which means
1959 * CBS is disabled.
1960 */
1961 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1962 adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1963
1964 for (i = 0; i < max_queue; i++) {
1965 igb_config_tx_modes(adapter, i);
1966 }
1967 } else {
1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1971
1972 val = rd32(E1000_I210_TQAVCTRL);
1973 /* According to Section 8.12.21, the other flags we've set when
1974 * enabling FQTSS are not relevant when disabling FQTSS so we
1975 * don't set they here.
1976 */
1977 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1978 wr32(E1000_I210_TQAVCTRL, val);
1979 }
1980
1981 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1982 "enabled" : "disabled");
1983}
1984
1985/**
1986 * igb_configure - configure the hardware for RX and TX
1987 * @adapter: private board structure
1988 **/
1989static void igb_configure(struct igb_adapter *adapter)
1990{
1991 struct net_device *netdev = adapter->netdev;
1992 int i;
1993
1994 igb_get_hw_control(adapter);
1995 igb_set_rx_mode(netdev);
1996 igb_setup_tx_mode(adapter);
1997
1998 igb_restore_vlan(adapter);
1999
2000 igb_setup_tctl(adapter);
2001 igb_setup_mrqc(adapter);
2002 igb_setup_rctl(adapter);
2003
2004 igb_nfc_filter_restore(adapter);
2005 igb_configure_tx(adapter);
2006 igb_configure_rx(adapter);
2007
2008 igb_rx_fifo_flush_82575(&adapter->hw);
2009
2010 /* call igb_desc_unused which always leaves
2011 * at least 1 descriptor unused to make sure
2012 * next_to_use != next_to_clean
2013 */
2014 for (i = 0; i < adapter->num_rx_queues; i++) {
2015 struct igb_ring *ring = adapter->rx_ring[i];
2016 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2017 }
2018}
2019
2020/**
2021 * igb_power_up_link - Power up the phy/serdes link
2022 * @adapter: address of board private structure
2023 **/
2024void igb_power_up_link(struct igb_adapter *adapter)
2025{
2026 igb_reset_phy(&adapter->hw);
2027
2028 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2029 igb_power_up_phy_copper(&adapter->hw);
2030 else
2031 igb_power_up_serdes_link_82575(&adapter->hw);
2032
2033 igb_setup_link(&adapter->hw);
2034}
2035
2036/**
2037 * igb_power_down_link - Power down the phy/serdes link
2038 * @adapter: address of board private structure
2039 */
2040static void igb_power_down_link(struct igb_adapter *adapter)
2041{
2042 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2043 igb_power_down_phy_copper_82575(&adapter->hw);
2044 else
2045 igb_shutdown_serdes_link_82575(&adapter->hw);
2046}
2047
2048/**
2049 * igb_check_swap_media - Detect and switch function for Media Auto Sense
2050 * @adapter: address of the board private structure
2051 **/
2052static void igb_check_swap_media(struct igb_adapter *adapter)
2053{
2054 struct e1000_hw *hw = &adapter->hw;
2055 u32 ctrl_ext, connsw;
2056 bool swap_now = false;
2057
2058 ctrl_ext = rd32(E1000_CTRL_EXT);
2059 connsw = rd32(E1000_CONNSW);
2060
2061 /* need to live swap if current media is copper and we have fiber/serdes
2062 * to go to.
2063 */
2064
2065 if ((hw->phy.media_type == e1000_media_type_copper) &&
2066 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2067 swap_now = true;
2068 } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2069 !(connsw & E1000_CONNSW_SERDESD)) {
2070 /* copper signal takes time to appear */
2071 if (adapter->copper_tries < 4) {
2072 adapter->copper_tries++;
2073 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2074 wr32(E1000_CONNSW, connsw);
2075 return;
2076 } else {
2077 adapter->copper_tries = 0;
2078 if ((connsw & E1000_CONNSW_PHYSD) &&
2079 (!(connsw & E1000_CONNSW_PHY_PDN))) {
2080 swap_now = true;
2081 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2082 wr32(E1000_CONNSW, connsw);
2083 }
2084 }
2085 }
2086
2087 if (!swap_now)
2088 return;
2089
2090 switch (hw->phy.media_type) {
2091 case e1000_media_type_copper:
2092 netdev_info(adapter->netdev,
2093 "MAS: changing media to fiber/serdes\n");
2094 ctrl_ext |=
2095 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2096 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2097 adapter->copper_tries = 0;
2098 break;
2099 case e1000_media_type_internal_serdes:
2100 case e1000_media_type_fiber:
2101 netdev_info(adapter->netdev,
2102 "MAS: changing media to copper\n");
2103 ctrl_ext &=
2104 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2105 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2106 break;
2107 default:
2108 /* shouldn't get here during regular operation */
2109 netdev_err(adapter->netdev,
2110 "AMS: Invalid media type found, returning\n");
2111 break;
2112 }
2113 wr32(E1000_CTRL_EXT, ctrl_ext);
2114}
2115
2116/**
2117 * igb_up - Open the interface and prepare it to handle traffic
2118 * @adapter: board private structure
2119 **/
2120int igb_up(struct igb_adapter *adapter)
2121{
2122 struct e1000_hw *hw = &adapter->hw;
2123 int i;
2124
2125 /* hardware has been reset, we need to reload some things */
2126 igb_configure(adapter);
2127
2128 clear_bit(__IGB_DOWN, &adapter->state);
2129
2130 for (i = 0; i < adapter->num_q_vectors; i++)
2131 napi_enable(&(adapter->q_vector[i]->napi));
2132
2133 if (adapter->flags & IGB_FLAG_HAS_MSIX)
2134 igb_configure_msix(adapter);
2135 else
2136 igb_assign_vector(adapter->q_vector[0], 0);
2137
2138 /* Clear any pending interrupts. */
2139 rd32(E1000_TSICR);
2140 rd32(E1000_ICR);
2141 igb_irq_enable(adapter);
2142
2143 /* notify VFs that reset has been completed */
2144 if (adapter->vfs_allocated_count) {
2145 u32 reg_data = rd32(E1000_CTRL_EXT);
2146
2147 reg_data |= E1000_CTRL_EXT_PFRSTD;
2148 wr32(E1000_CTRL_EXT, reg_data);
2149 }
2150
2151 netif_tx_start_all_queues(adapter->netdev);
2152
2153 /* start the watchdog. */
2154 hw->mac.get_link_status = 1;
2155 schedule_work(&adapter->watchdog_task);
2156
2157 if ((adapter->flags & IGB_FLAG_EEE) &&
2158 (!hw->dev_spec._82575.eee_disable))
2159 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2160
2161 return 0;
2162}
2163
2164void igb_down(struct igb_adapter *adapter)
2165{
2166 struct net_device *netdev = adapter->netdev;
2167 struct e1000_hw *hw = &adapter->hw;
2168 u32 tctl, rctl;
2169 int i;
2170
2171 /* signal that we're down so the interrupt handler does not
2172 * reschedule our watchdog timer
2173 */
2174 set_bit(__IGB_DOWN, &adapter->state);
2175
2176 /* disable receives in the hardware */
2177 rctl = rd32(E1000_RCTL);
2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2179 /* flush and sleep below */
2180
2181 igb_nfc_filter_exit(adapter);
2182
2183 netif_carrier_off(netdev);
2184 netif_tx_stop_all_queues(netdev);
2185
2186 /* disable transmits in the hardware */
2187 tctl = rd32(E1000_TCTL);
2188 tctl &= ~E1000_TCTL_EN;
2189 wr32(E1000_TCTL, tctl);
2190 /* flush both disables and wait for them to finish */
2191 wrfl();
2192 usleep_range(10000, 11000);
2193
2194 igb_irq_disable(adapter);
2195
2196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2197
2198 for (i = 0; i < adapter->num_q_vectors; i++) {
2199 if (adapter->q_vector[i]) {
2200 napi_synchronize(&adapter->q_vector[i]->napi);
2201 napi_disable(&adapter->q_vector[i]->napi);
2202 }
2203 }
2204
2205 del_timer_sync(&adapter->watchdog_timer);
2206 del_timer_sync(&adapter->phy_info_timer);
2207
2208 /* record the stats before reset*/
2209 spin_lock(&adapter->stats64_lock);
2210 igb_update_stats(adapter);
2211 spin_unlock(&adapter->stats64_lock);
2212
2213 adapter->link_speed = 0;
2214 adapter->link_duplex = 0;
2215
2216 if (!pci_channel_offline(adapter->pdev))
2217 igb_reset(adapter);
2218
2219 /* clear VLAN promisc flag so VFTA will be updated if necessary */
2220 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2221
2222 igb_clean_all_tx_rings(adapter);
2223 igb_clean_all_rx_rings(adapter);
2224#ifdef CONFIG_IGB_DCA
2225
2226 /* since we reset the hardware DCA settings were cleared */
2227 igb_setup_dca(adapter);
2228#endif
2229}
2230
2231void igb_reinit_locked(struct igb_adapter *adapter)
2232{
2233 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2234 usleep_range(1000, 2000);
2235 igb_down(adapter);
2236 igb_up(adapter);
2237 clear_bit(__IGB_RESETTING, &adapter->state);
2238}
2239
2240/** igb_enable_mas - Media Autosense re-enable after swap
2241 *
2242 * @adapter: adapter struct
2243 **/
2244static void igb_enable_mas(struct igb_adapter *adapter)
2245{
2246 struct e1000_hw *hw = &adapter->hw;
2247 u32 connsw = rd32(E1000_CONNSW);
2248
2249 /* configure for SerDes media detect */
2250 if ((hw->phy.media_type == e1000_media_type_copper) &&
2251 (!(connsw & E1000_CONNSW_SERDESD))) {
2252 connsw |= E1000_CONNSW_ENRGSRC;
2253 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2254 wr32(E1000_CONNSW, connsw);
2255 wrfl();
2256 }
2257}
2258
2259#ifdef CONFIG_IGB_HWMON
2260/**
2261 * igb_set_i2c_bb - Init I2C interface
2262 * @hw: pointer to hardware structure
2263 **/
2264static void igb_set_i2c_bb(struct e1000_hw *hw)
2265{
2266 u32 ctrl_ext;
2267 s32 i2cctl;
2268
2269 ctrl_ext = rd32(E1000_CTRL_EXT);
2270 ctrl_ext |= E1000_CTRL_I2C_ENA;
2271 wr32(E1000_CTRL_EXT, ctrl_ext);
2272 wrfl();
2273
2274 i2cctl = rd32(E1000_I2CPARAMS);
2275 i2cctl |= E1000_I2CBB_EN
2276 | E1000_I2C_CLK_OE_N
2277 | E1000_I2C_DATA_OE_N;
2278 wr32(E1000_I2CPARAMS, i2cctl);
2279 wrfl();
2280}
2281#endif
2282
2283void igb_reset(struct igb_adapter *adapter)
2284{
2285 struct pci_dev *pdev = adapter->pdev;
2286 struct e1000_hw *hw = &adapter->hw;
2287 struct e1000_mac_info *mac = &hw->mac;
2288 struct e1000_fc_info *fc = &hw->fc;
2289 u32 pba, hwm;
2290
2291 /* Repartition Pba for greater than 9k mtu
2292 * To take effect CTRL.RST is required.
2293 */
2294 switch (mac->type) {
2295 case e1000_i350:
2296 case e1000_i354:
2297 case e1000_82580:
2298 pba = rd32(E1000_RXPBS);
2299 pba = igb_rxpbs_adjust_82580(pba);
2300 break;
2301 case e1000_82576:
2302 pba = rd32(E1000_RXPBS);
2303 pba &= E1000_RXPBS_SIZE_MASK_82576;
2304 break;
2305 case e1000_82575:
2306 case e1000_i210:
2307 case e1000_i211:
2308 default:
2309 pba = E1000_PBA_34K;
2310 break;
2311 }
2312
2313 if (mac->type == e1000_82575) {
2314 u32 min_rx_space, min_tx_space, needed_tx_space;
2315
2316 /* write Rx PBA so that hardware can report correct Tx PBA */
2317 wr32(E1000_PBA, pba);
2318
2319 /* To maintain wire speed transmits, the Tx FIFO should be
2320 * large enough to accommodate two full transmit packets,
2321 * rounded up to the next 1KB and expressed in KB. Likewise,
2322 * the Rx FIFO should be large enough to accommodate at least
2323 * one full receive packet and is similarly rounded up and
2324 * expressed in KB.
2325 */
2326 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2327
2328 /* The Tx FIFO also stores 16 bytes of information about the Tx
2329 * but don't include Ethernet FCS because hardware appends it.
2330 * We only need to round down to the nearest 512 byte block
2331 * count since the value we care about is 2 frames, not 1.
2332 */
2333 min_tx_space = adapter->max_frame_size;
2334 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2335 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2336
2337 /* upper 16 bits has Tx packet buffer allocation size in KB */
2338 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2339
2340 /* If current Tx allocation is less than the min Tx FIFO size,
2341 * and the min Tx FIFO size is less than the current Rx FIFO
2342 * allocation, take space away from current Rx allocation.
2343 */
2344 if (needed_tx_space < pba) {
2345 pba -= needed_tx_space;
2346
2347 /* if short on Rx space, Rx wins and must trump Tx
2348 * adjustment
2349 */
2350 if (pba < min_rx_space)
2351 pba = min_rx_space;
2352 }
2353
2354 /* adjust PBA for jumbo frames */
2355 wr32(E1000_PBA, pba);
2356 }
2357
2358 /* flow control settings
2359 * The high water mark must be low enough to fit one full frame
2360 * after transmitting the pause frame. As such we must have enough
2361 * space to allow for us to complete our current transmit and then
2362 * receive the frame that is in progress from the link partner.
2363 * Set it to:
2364 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2365 */
2366 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2367
2368 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
2369 fc->low_water = fc->high_water - 16;
2370 fc->pause_time = 0xFFFF;
2371 fc->send_xon = 1;
2372 fc->current_mode = fc->requested_mode;
2373
2374 /* disable receive for all VFs and wait one second */
2375 if (adapter->vfs_allocated_count) {
2376 int i;
2377
2378 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2379 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2380
2381 /* ping all the active vfs to let them know we are going down */
2382 igb_ping_all_vfs(adapter);
2383
2384 /* disable transmits and receives */
2385 wr32(E1000_VFRE, 0);
2386 wr32(E1000_VFTE, 0);
2387 }
2388
2389 /* Allow time for pending master requests to run */
2390 hw->mac.ops.reset_hw(hw);
2391 wr32(E1000_WUC, 0);
2392
2393 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2394 /* need to resetup here after media swap */
2395 adapter->ei.get_invariants(hw);
2396 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2397 }
2398 if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2399 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2400 igb_enable_mas(adapter);
2401 }
2402 if (hw->mac.ops.init_hw(hw))
2403 dev_err(&pdev->dev, "Hardware Error\n");
2404
2405 /* RAR registers were cleared during init_hw, clear mac table */
2406 igb_flush_mac_table(adapter);
2407 __dev_uc_unsync(adapter->netdev, NULL);
2408
2409 /* Recover default RAR entry */
2410 igb_set_default_mac_filter(adapter);
2411
2412 /* Flow control settings reset on hardware reset, so guarantee flow
2413 * control is off when forcing speed.
2414 */
2415 if (!hw->mac.autoneg)
2416 igb_force_mac_fc(hw);
2417
2418 igb_init_dmac(adapter, pba);
2419#ifdef CONFIG_IGB_HWMON
2420 /* Re-initialize the thermal sensor on i350 devices. */
2421 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2422 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2423 /* If present, re-initialize the external thermal sensor
2424 * interface.
2425 */
2426 if (adapter->ets)
2427 igb_set_i2c_bb(hw);
2428 mac->ops.init_thermal_sensor_thresh(hw);
2429 }
2430 }
2431#endif
2432 /* Re-establish EEE setting */
2433 if (hw->phy.media_type == e1000_media_type_copper) {
2434 switch (mac->type) {
2435 case e1000_i350:
2436 case e1000_i210:
2437 case e1000_i211:
2438 igb_set_eee_i350(hw, true, true);
2439 break;
2440 case e1000_i354:
2441 igb_set_eee_i354(hw, true, true);
2442 break;
2443 default:
2444 break;
2445 }
2446 }
2447 if (!netif_running(adapter->netdev))
2448 igb_power_down_link(adapter);
2449
2450 igb_update_mng_vlan(adapter);
2451
2452 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2453 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2454
2455 /* Re-enable PTP, where applicable. */
2456 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2457 igb_ptp_reset(adapter);
2458
2459 igb_get_phy_info(hw);
2460}
2461
2462static netdev_features_t igb_fix_features(struct net_device *netdev,
2463 netdev_features_t features)
2464{
2465 /* Since there is no support for separate Rx/Tx vlan accel
2466 * enable/disable make sure Tx flag is always in same state as Rx.
2467 */
2468 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2469 features |= NETIF_F_HW_VLAN_CTAG_TX;
2470 else
2471 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2472
2473 return features;
2474}
2475
2476static int igb_set_features(struct net_device *netdev,
2477 netdev_features_t features)
2478{
2479 netdev_features_t changed = netdev->features ^ features;
2480 struct igb_adapter *adapter = netdev_priv(netdev);
2481
2482 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2483 igb_vlan_mode(netdev, features);
2484
2485 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2486 return 0;
2487
2488 if (!(features & NETIF_F_NTUPLE)) {
2489 struct hlist_node *node2;
2490 struct igb_nfc_filter *rule;
2491
2492 spin_lock(&adapter->nfc_lock);
2493 hlist_for_each_entry_safe(rule, node2,
2494 &adapter->nfc_filter_list, nfc_node) {
2495 igb_erase_filter(adapter, rule);
2496 hlist_del(&rule->nfc_node);
2497 kfree(rule);
2498 }
2499 spin_unlock(&adapter->nfc_lock);
2500 adapter->nfc_filter_count = 0;
2501 }
2502
2503 netdev->features = features;
2504
2505 if (netif_running(netdev))
2506 igb_reinit_locked(adapter);
2507 else
2508 igb_reset(adapter);
2509
2510 return 1;
2511}
2512
2513static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2514 struct net_device *dev,
2515 const unsigned char *addr, u16 vid,
2516 u16 flags,
2517 struct netlink_ext_ack *extack)
2518{
2519 /* guarantee we can provide a unique filter for the unicast address */
2520 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2521 struct igb_adapter *adapter = netdev_priv(dev);
2522 int vfn = adapter->vfs_allocated_count;
2523
2524 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2525 return -ENOMEM;
2526 }
2527
2528 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2529}
2530
2531#define IGB_MAX_MAC_HDR_LEN 127
2532#define IGB_MAX_NETWORK_HDR_LEN 511
2533
2534static netdev_features_t
2535igb_features_check(struct sk_buff *skb, struct net_device *dev,
2536 netdev_features_t features)
2537{
2538 unsigned int network_hdr_len, mac_hdr_len;
2539
2540 /* Make certain the headers can be described by a context descriptor */
2541 mac_hdr_len = skb_network_header(skb) - skb->data;
2542 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2543 return features & ~(NETIF_F_HW_CSUM |
2544 NETIF_F_SCTP_CRC |
2545 NETIF_F_GSO_UDP_L4 |
2546 NETIF_F_HW_VLAN_CTAG_TX |
2547 NETIF_F_TSO |
2548 NETIF_F_TSO6);
2549
2550 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2551 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2552 return features & ~(NETIF_F_HW_CSUM |
2553 NETIF_F_SCTP_CRC |
2554 NETIF_F_GSO_UDP_L4 |
2555 NETIF_F_TSO |
2556 NETIF_F_TSO6);
2557
2558 /* We can only support IPV4 TSO in tunnels if we can mangle the
2559 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2560 */
2561 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2562 features &= ~NETIF_F_TSO;
2563
2564 return features;
2565}
2566
2567static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2568{
2569 if (!is_fqtss_enabled(adapter)) {
2570 enable_fqtss(adapter, true);
2571 return;
2572 }
2573
2574 igb_config_tx_modes(adapter, queue);
2575
2576 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2577 enable_fqtss(adapter, false);
2578}
2579
2580static int igb_offload_cbs(struct igb_adapter *adapter,
2581 struct tc_cbs_qopt_offload *qopt)
2582{
2583 struct e1000_hw *hw = &adapter->hw;
2584 int err;
2585
2586 /* CBS offloading is only supported by i210 controller. */
2587 if (hw->mac.type != e1000_i210)
2588 return -EOPNOTSUPP;
2589
2590 /* CBS offloading is only supported by queue 0 and queue 1. */
2591 if (qopt->queue < 0 || qopt->queue > 1)
2592 return -EINVAL;
2593
2594 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2595 qopt->idleslope, qopt->sendslope,
2596 qopt->hicredit, qopt->locredit);
2597 if (err)
2598 return err;
2599
2600 igb_offload_apply(adapter, qopt->queue);
2601
2602 return 0;
2603}
2604
2605#define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2606#define VLAN_PRIO_FULL_MASK (0x07)
2607
2608static int igb_parse_cls_flower(struct igb_adapter *adapter,
2609 struct flow_cls_offload *f,
2610 int traffic_class,
2611 struct igb_nfc_filter *input)
2612{
2613 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2614 struct flow_dissector *dissector = rule->match.dissector;
2615 struct netlink_ext_ack *extack = f->common.extack;
2616
2617 if (dissector->used_keys &
2618 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2619 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2620 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2621 BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2622 NL_SET_ERR_MSG_MOD(extack,
2623 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2624 return -EOPNOTSUPP;
2625 }
2626
2627 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2628 struct flow_match_eth_addrs match;
2629
2630 flow_rule_match_eth_addrs(rule, &match);
2631 if (!is_zero_ether_addr(match.mask->dst)) {
2632 if (!is_broadcast_ether_addr(match.mask->dst)) {
2633 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2634 return -EINVAL;
2635 }
2636
2637 input->filter.match_flags |=
2638 IGB_FILTER_FLAG_DST_MAC_ADDR;
2639 ether_addr_copy(input->filter.dst_addr, match.key->dst);
2640 }
2641
2642 if (!is_zero_ether_addr(match.mask->src)) {
2643 if (!is_broadcast_ether_addr(match.mask->src)) {
2644 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2645 return -EINVAL;
2646 }
2647
2648 input->filter.match_flags |=
2649 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2650 ether_addr_copy(input->filter.src_addr, match.key->src);
2651 }
2652 }
2653
2654 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2655 struct flow_match_basic match;
2656
2657 flow_rule_match_basic(rule, &match);
2658 if (match.mask->n_proto) {
2659 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2660 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2661 return -EINVAL;
2662 }
2663
2664 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2665 input->filter.etype = match.key->n_proto;
2666 }
2667 }
2668
2669 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2670 struct flow_match_vlan match;
2671
2672 flow_rule_match_vlan(rule, &match);
2673 if (match.mask->vlan_priority) {
2674 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2675 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2676 return -EINVAL;
2677 }
2678
2679 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2680 input->filter.vlan_tci =
2681 (__force __be16)match.key->vlan_priority;
2682 }
2683 }
2684
2685 input->action = traffic_class;
2686 input->cookie = f->cookie;
2687
2688 return 0;
2689}
2690
2691static int igb_configure_clsflower(struct igb_adapter *adapter,
2692 struct flow_cls_offload *cls_flower)
2693{
2694 struct netlink_ext_ack *extack = cls_flower->common.extack;
2695 struct igb_nfc_filter *filter, *f;
2696 int err, tc;
2697
2698 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2699 if (tc < 0) {
2700 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2701 return -EINVAL;
2702 }
2703
2704 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2705 if (!filter)
2706 return -ENOMEM;
2707
2708 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2709 if (err < 0)
2710 goto err_parse;
2711
2712 spin_lock(&adapter->nfc_lock);
2713
2714 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2715 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2716 err = -EEXIST;
2717 NL_SET_ERR_MSG_MOD(extack,
2718 "This filter is already set in ethtool");
2719 goto err_locked;
2720 }
2721 }
2722
2723 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2724 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2725 err = -EEXIST;
2726 NL_SET_ERR_MSG_MOD(extack,
2727 "This filter is already set in cls_flower");
2728 goto err_locked;
2729 }
2730 }
2731
2732 err = igb_add_filter(adapter, filter);
2733 if (err < 0) {
2734 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2735 goto err_locked;
2736 }
2737
2738 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2739
2740 spin_unlock(&adapter->nfc_lock);
2741
2742 return 0;
2743
2744err_locked:
2745 spin_unlock(&adapter->nfc_lock);
2746
2747err_parse:
2748 kfree(filter);
2749
2750 return err;
2751}
2752
2753static int igb_delete_clsflower(struct igb_adapter *adapter,
2754 struct flow_cls_offload *cls_flower)
2755{
2756 struct igb_nfc_filter *filter;
2757 int err;
2758
2759 spin_lock(&adapter->nfc_lock);
2760
2761 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2762 if (filter->cookie == cls_flower->cookie)
2763 break;
2764
2765 if (!filter) {
2766 err = -ENOENT;
2767 goto out;
2768 }
2769
2770 err = igb_erase_filter(adapter, filter);
2771 if (err < 0)
2772 goto out;
2773
2774 hlist_del(&filter->nfc_node);
2775 kfree(filter);
2776
2777out:
2778 spin_unlock(&adapter->nfc_lock);
2779
2780 return err;
2781}
2782
2783static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2784 struct flow_cls_offload *cls_flower)
2785{
2786 switch (cls_flower->command) {
2787 case FLOW_CLS_REPLACE:
2788 return igb_configure_clsflower(adapter, cls_flower);
2789 case FLOW_CLS_DESTROY:
2790 return igb_delete_clsflower(adapter, cls_flower);
2791 case FLOW_CLS_STATS:
2792 return -EOPNOTSUPP;
2793 default:
2794 return -EOPNOTSUPP;
2795 }
2796}
2797
2798static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2799 void *cb_priv)
2800{
2801 struct igb_adapter *adapter = cb_priv;
2802
2803 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2804 return -EOPNOTSUPP;
2805
2806 switch (type) {
2807 case TC_SETUP_CLSFLOWER:
2808 return igb_setup_tc_cls_flower(adapter, type_data);
2809
2810 default:
2811 return -EOPNOTSUPP;
2812 }
2813}
2814
2815static int igb_offload_txtime(struct igb_adapter *adapter,
2816 struct tc_etf_qopt_offload *qopt)
2817{
2818 struct e1000_hw *hw = &adapter->hw;
2819 int err;
2820
2821 /* Launchtime offloading is only supported by i210 controller. */
2822 if (hw->mac.type != e1000_i210)
2823 return -EOPNOTSUPP;
2824
2825 /* Launchtime offloading is only supported by queues 0 and 1. */
2826 if (qopt->queue < 0 || qopt->queue > 1)
2827 return -EINVAL;
2828
2829 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2830 if (err)
2831 return err;
2832
2833 igb_offload_apply(adapter, qopt->queue);
2834
2835 return 0;
2836}
2837
2838static LIST_HEAD(igb_block_cb_list);
2839
2840static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2841 void *type_data)
2842{
2843 struct igb_adapter *adapter = netdev_priv(dev);
2844
2845 switch (type) {
2846 case TC_SETUP_QDISC_CBS:
2847 return igb_offload_cbs(adapter, type_data);
2848 case TC_SETUP_BLOCK:
2849 return flow_block_cb_setup_simple(type_data,
2850 &igb_block_cb_list,
2851 igb_setup_tc_block_cb,
2852 adapter, adapter, true);
2853
2854 case TC_SETUP_QDISC_ETF:
2855 return igb_offload_txtime(adapter, type_data);
2856
2857 default:
2858 return -EOPNOTSUPP;
2859 }
2860}
2861
2862static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2863{
2864 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2865 struct igb_adapter *adapter = netdev_priv(dev);
2866 struct bpf_prog *prog = bpf->prog, *old_prog;
2867 bool running = netif_running(dev);
2868 bool need_reset;
2869
2870 /* verify igb ring attributes are sufficient for XDP */
2871 for (i = 0; i < adapter->num_rx_queues; i++) {
2872 struct igb_ring *ring = adapter->rx_ring[i];
2873
2874 if (frame_size > igb_rx_bufsz(ring)) {
2875 NL_SET_ERR_MSG_MOD(bpf->extack,
2876 "The RX buffer size is too small for the frame size");
2877 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2878 igb_rx_bufsz(ring), frame_size);
2879 return -EINVAL;
2880 }
2881 }
2882
2883 old_prog = xchg(&adapter->xdp_prog, prog);
2884 need_reset = (!!prog != !!old_prog);
2885
2886 /* device is up and bpf is added/removed, must setup the RX queues */
2887 if (need_reset && running) {
2888 igb_close(dev);
2889 } else {
2890 for (i = 0; i < adapter->num_rx_queues; i++)
2891 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2892 adapter->xdp_prog);
2893 }
2894
2895 if (old_prog)
2896 bpf_prog_put(old_prog);
2897
2898 /* bpf is just replaced, RXQ and MTU are already setup */
2899 if (!need_reset)
2900 return 0;
2901
2902 if (running)
2903 igb_open(dev);
2904
2905 return 0;
2906}
2907
2908static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2909{
2910 switch (xdp->command) {
2911 case XDP_SETUP_PROG:
2912 return igb_xdp_setup(dev, xdp);
2913 default:
2914 return -EINVAL;
2915 }
2916}
2917
2918static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2919{
2920 /* Force memory writes to complete before letting h/w know there
2921 * are new descriptors to fetch.
2922 */
2923 wmb();
2924 writel(ring->next_to_use, ring->tail);
2925}
2926
2927static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2928{
2929 unsigned int r_idx = smp_processor_id();
2930
2931 if (r_idx >= adapter->num_tx_queues)
2932 r_idx = r_idx % adapter->num_tx_queues;
2933
2934 return adapter->tx_ring[r_idx];
2935}
2936
2937static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2938{
2939 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2940 int cpu = smp_processor_id();
2941 struct igb_ring *tx_ring;
2942 struct netdev_queue *nq;
2943 u32 ret;
2944
2945 if (unlikely(!xdpf))
2946 return IGB_XDP_CONSUMED;
2947
2948 /* During program transitions its possible adapter->xdp_prog is assigned
2949 * but ring has not been configured yet. In this case simply abort xmit.
2950 */
2951 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2952 if (unlikely(!tx_ring))
2953 return IGB_XDP_CONSUMED;
2954
2955 nq = txring_txq(tx_ring);
2956 __netif_tx_lock(nq, cpu);
2957 /* Avoid transmit queue timeout since we share it with the slow path */
2958 txq_trans_cond_update(nq);
2959 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2960 __netif_tx_unlock(nq);
2961
2962 return ret;
2963}
2964
2965static int igb_xdp_xmit(struct net_device *dev, int n,
2966 struct xdp_frame **frames, u32 flags)
2967{
2968 struct igb_adapter *adapter = netdev_priv(dev);
2969 int cpu = smp_processor_id();
2970 struct igb_ring *tx_ring;
2971 struct netdev_queue *nq;
2972 int nxmit = 0;
2973 int i;
2974
2975 if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2976 return -ENETDOWN;
2977
2978 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2979 return -EINVAL;
2980
2981 /* During program transitions its possible adapter->xdp_prog is assigned
2982 * but ring has not been configured yet. In this case simply abort xmit.
2983 */
2984 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2985 if (unlikely(!tx_ring))
2986 return -ENXIO;
2987
2988 nq = txring_txq(tx_ring);
2989 __netif_tx_lock(nq, cpu);
2990
2991 /* Avoid transmit queue timeout since we share it with the slow path */
2992 txq_trans_cond_update(nq);
2993
2994 for (i = 0; i < n; i++) {
2995 struct xdp_frame *xdpf = frames[i];
2996 int err;
2997
2998 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2999 if (err != IGB_XDP_TX)
3000 break;
3001 nxmit++;
3002 }
3003
3004 __netif_tx_unlock(nq);
3005
3006 if (unlikely(flags & XDP_XMIT_FLUSH))
3007 igb_xdp_ring_update_tail(tx_ring);
3008
3009 return nxmit;
3010}
3011
3012static const struct net_device_ops igb_netdev_ops = {
3013 .ndo_open = igb_open,
3014 .ndo_stop = igb_close,
3015 .ndo_start_xmit = igb_xmit_frame,
3016 .ndo_get_stats64 = igb_get_stats64,
3017 .ndo_set_rx_mode = igb_set_rx_mode,
3018 .ndo_set_mac_address = igb_set_mac,
3019 .ndo_change_mtu = igb_change_mtu,
3020 .ndo_eth_ioctl = igb_ioctl,
3021 .ndo_tx_timeout = igb_tx_timeout,
3022 .ndo_validate_addr = eth_validate_addr,
3023 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
3024 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
3025 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
3026 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
3027 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
3028 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
3029 .ndo_set_vf_trust = igb_ndo_set_vf_trust,
3030 .ndo_get_vf_config = igb_ndo_get_vf_config,
3031 .ndo_fix_features = igb_fix_features,
3032 .ndo_set_features = igb_set_features,
3033 .ndo_fdb_add = igb_ndo_fdb_add,
3034 .ndo_features_check = igb_features_check,
3035 .ndo_setup_tc = igb_setup_tc,
3036 .ndo_bpf = igb_xdp,
3037 .ndo_xdp_xmit = igb_xdp_xmit,
3038};
3039
3040/**
3041 * igb_set_fw_version - Configure version string for ethtool
3042 * @adapter: adapter struct
3043 **/
3044void igb_set_fw_version(struct igb_adapter *adapter)
3045{
3046 struct e1000_hw *hw = &adapter->hw;
3047 struct e1000_fw_version fw;
3048
3049 igb_get_fw_version(hw, &fw);
3050
3051 switch (hw->mac.type) {
3052 case e1000_i210:
3053 case e1000_i211:
3054 if (!(igb_get_flash_presence_i210(hw))) {
3055 snprintf(adapter->fw_version,
3056 sizeof(adapter->fw_version),
3057 "%2d.%2d-%d",
3058 fw.invm_major, fw.invm_minor,
3059 fw.invm_img_type);
3060 break;
3061 }
3062 fallthrough;
3063 default:
3064 /* if option is rom valid, display its version too */
3065 if (fw.or_valid) {
3066 snprintf(adapter->fw_version,
3067 sizeof(adapter->fw_version),
3068 "%d.%d, 0x%08x, %d.%d.%d",
3069 fw.eep_major, fw.eep_minor, fw.etrack_id,
3070 fw.or_major, fw.or_build, fw.or_patch);
3071 /* no option rom */
3072 } else if (fw.etrack_id != 0X0000) {
3073 snprintf(adapter->fw_version,
3074 sizeof(adapter->fw_version),
3075 "%d.%d, 0x%08x",
3076 fw.eep_major, fw.eep_minor, fw.etrack_id);
3077 } else {
3078 snprintf(adapter->fw_version,
3079 sizeof(adapter->fw_version),
3080 "%d.%d.%d",
3081 fw.eep_major, fw.eep_minor, fw.eep_build);
3082 }
3083 break;
3084 }
3085}
3086
3087/**
3088 * igb_init_mas - init Media Autosense feature if enabled in the NVM
3089 *
3090 * @adapter: adapter struct
3091 **/
3092static void igb_init_mas(struct igb_adapter *adapter)
3093{
3094 struct e1000_hw *hw = &adapter->hw;
3095 u16 eeprom_data;
3096
3097 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3098 switch (hw->bus.func) {
3099 case E1000_FUNC_0:
3100 if (eeprom_data & IGB_MAS_ENABLE_0) {
3101 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3102 netdev_info(adapter->netdev,
3103 "MAS: Enabling Media Autosense for port %d\n",
3104 hw->bus.func);
3105 }
3106 break;
3107 case E1000_FUNC_1:
3108 if (eeprom_data & IGB_MAS_ENABLE_1) {
3109 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3110 netdev_info(adapter->netdev,
3111 "MAS: Enabling Media Autosense for port %d\n",
3112 hw->bus.func);
3113 }
3114 break;
3115 case E1000_FUNC_2:
3116 if (eeprom_data & IGB_MAS_ENABLE_2) {
3117 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3118 netdev_info(adapter->netdev,
3119 "MAS: Enabling Media Autosense for port %d\n",
3120 hw->bus.func);
3121 }
3122 break;
3123 case E1000_FUNC_3:
3124 if (eeprom_data & IGB_MAS_ENABLE_3) {
3125 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3126 netdev_info(adapter->netdev,
3127 "MAS: Enabling Media Autosense for port %d\n",
3128 hw->bus.func);
3129 }
3130 break;
3131 default:
3132 /* Shouldn't get here */
3133 netdev_err(adapter->netdev,
3134 "MAS: Invalid port configuration, returning\n");
3135 break;
3136 }
3137}
3138
3139/**
3140 * igb_init_i2c - Init I2C interface
3141 * @adapter: pointer to adapter structure
3142 **/
3143static s32 igb_init_i2c(struct igb_adapter *adapter)
3144{
3145 s32 status = 0;
3146
3147 /* I2C interface supported on i350 devices */
3148 if (adapter->hw.mac.type != e1000_i350)
3149 return 0;
3150
3151 /* Initialize the i2c bus which is controlled by the registers.
3152 * This bus will use the i2c_algo_bit structure that implements
3153 * the protocol through toggling of the 4 bits in the register.
3154 */
3155 adapter->i2c_adap.owner = THIS_MODULE;
3156 adapter->i2c_algo = igb_i2c_algo;
3157 adapter->i2c_algo.data = adapter;
3158 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3159 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3160 strscpy(adapter->i2c_adap.name, "igb BB",
3161 sizeof(adapter->i2c_adap.name));
3162 status = i2c_bit_add_bus(&adapter->i2c_adap);
3163 return status;
3164}
3165
3166/**
3167 * igb_probe - Device Initialization Routine
3168 * @pdev: PCI device information struct
3169 * @ent: entry in igb_pci_tbl
3170 *
3171 * Returns 0 on success, negative on failure
3172 *
3173 * igb_probe initializes an adapter identified by a pci_dev structure.
3174 * The OS initialization, configuring of the adapter private structure,
3175 * and a hardware reset occur.
3176 **/
3177static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3178{
3179 struct net_device *netdev;
3180 struct igb_adapter *adapter;
3181 struct e1000_hw *hw;
3182 u16 eeprom_data = 0;
3183 s32 ret_val;
3184 static int global_quad_port_a; /* global quad port a indication */
3185 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3186 u8 part_str[E1000_PBANUM_LENGTH];
3187 int err;
3188
3189 /* Catch broken hardware that put the wrong VF device ID in
3190 * the PCIe SR-IOV capability.
3191 */
3192 if (pdev->is_virtfn) {
3193 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3194 pci_name(pdev), pdev->vendor, pdev->device);
3195 return -EINVAL;
3196 }
3197
3198 err = pci_enable_device_mem(pdev);
3199 if (err)
3200 return err;
3201
3202 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3203 if (err) {
3204 dev_err(&pdev->dev,
3205 "No usable DMA configuration, aborting\n");
3206 goto err_dma;
3207 }
3208
3209 err = pci_request_mem_regions(pdev, igb_driver_name);
3210 if (err)
3211 goto err_pci_reg;
3212
3213 pci_enable_pcie_error_reporting(pdev);
3214
3215 pci_set_master(pdev);
3216 pci_save_state(pdev);
3217
3218 err = -ENOMEM;
3219 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3220 IGB_MAX_TX_QUEUES);
3221 if (!netdev)
3222 goto err_alloc_etherdev;
3223
3224 SET_NETDEV_DEV(netdev, &pdev->dev);
3225
3226 pci_set_drvdata(pdev, netdev);
3227 adapter = netdev_priv(netdev);
3228 adapter->netdev = netdev;
3229 adapter->pdev = pdev;
3230 hw = &adapter->hw;
3231 hw->back = adapter;
3232 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3233
3234 err = -EIO;
3235 adapter->io_addr = pci_iomap(pdev, 0, 0);
3236 if (!adapter->io_addr)
3237 goto err_ioremap;
3238 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3239 hw->hw_addr = adapter->io_addr;
3240
3241 netdev->netdev_ops = &igb_netdev_ops;
3242 igb_set_ethtool_ops(netdev);
3243 netdev->watchdog_timeo = 5 * HZ;
3244
3245 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3246
3247 netdev->mem_start = pci_resource_start(pdev, 0);
3248 netdev->mem_end = pci_resource_end(pdev, 0);
3249
3250 /* PCI config space info */
3251 hw->vendor_id = pdev->vendor;
3252 hw->device_id = pdev->device;
3253 hw->revision_id = pdev->revision;
3254 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3255 hw->subsystem_device_id = pdev->subsystem_device;
3256
3257 /* Copy the default MAC, PHY and NVM function pointers */
3258 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3259 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3260 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3261 /* Initialize skew-specific constants */
3262 err = ei->get_invariants(hw);
3263 if (err)
3264 goto err_sw_init;
3265
3266 /* setup the private structure */
3267 err = igb_sw_init(adapter);
3268 if (err)
3269 goto err_sw_init;
3270
3271 igb_get_bus_info_pcie(hw);
3272
3273 hw->phy.autoneg_wait_to_complete = false;
3274
3275 /* Copper options */
3276 if (hw->phy.media_type == e1000_media_type_copper) {
3277 hw->phy.mdix = AUTO_ALL_MODES;
3278 hw->phy.disable_polarity_correction = false;
3279 hw->phy.ms_type = e1000_ms_hw_default;
3280 }
3281
3282 if (igb_check_reset_block(hw))
3283 dev_info(&pdev->dev,
3284 "PHY reset is blocked due to SOL/IDER session.\n");
3285
3286 /* features is initialized to 0 in allocation, it might have bits
3287 * set by igb_sw_init so we should use an or instead of an
3288 * assignment.
3289 */
3290 netdev->features |= NETIF_F_SG |
3291 NETIF_F_TSO |
3292 NETIF_F_TSO6 |
3293 NETIF_F_RXHASH |
3294 NETIF_F_RXCSUM |
3295 NETIF_F_HW_CSUM;
3296
3297 if (hw->mac.type >= e1000_82576)
3298 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3299
3300 if (hw->mac.type >= e1000_i350)
3301 netdev->features |= NETIF_F_HW_TC;
3302
3303#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3304 NETIF_F_GSO_GRE_CSUM | \
3305 NETIF_F_GSO_IPXIP4 | \
3306 NETIF_F_GSO_IPXIP6 | \
3307 NETIF_F_GSO_UDP_TUNNEL | \
3308 NETIF_F_GSO_UDP_TUNNEL_CSUM)
3309
3310 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3311 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3312
3313 /* copy netdev features into list of user selectable features */
3314 netdev->hw_features |= netdev->features |
3315 NETIF_F_HW_VLAN_CTAG_RX |
3316 NETIF_F_HW_VLAN_CTAG_TX |
3317 NETIF_F_RXALL;
3318
3319 if (hw->mac.type >= e1000_i350)
3320 netdev->hw_features |= NETIF_F_NTUPLE;
3321
3322 netdev->features |= NETIF_F_HIGHDMA;
3323
3324 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3325 netdev->mpls_features |= NETIF_F_HW_CSUM;
3326 netdev->hw_enc_features |= netdev->vlan_features;
3327
3328 /* set this bit last since it cannot be part of vlan_features */
3329 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3330 NETIF_F_HW_VLAN_CTAG_RX |
3331 NETIF_F_HW_VLAN_CTAG_TX;
3332
3333 netdev->priv_flags |= IFF_SUPP_NOFCS;
3334
3335 netdev->priv_flags |= IFF_UNICAST_FLT;
3336
3337 /* MTU range: 68 - 9216 */
3338 netdev->min_mtu = ETH_MIN_MTU;
3339 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3340
3341 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3342
3343 /* before reading the NVM, reset the controller to put the device in a
3344 * known good starting state
3345 */
3346 hw->mac.ops.reset_hw(hw);
3347
3348 /* make sure the NVM is good , i211/i210 parts can have special NVM
3349 * that doesn't contain a checksum
3350 */
3351 switch (hw->mac.type) {
3352 case e1000_i210:
3353 case e1000_i211:
3354 if (igb_get_flash_presence_i210(hw)) {
3355 if (hw->nvm.ops.validate(hw) < 0) {
3356 dev_err(&pdev->dev,
3357 "The NVM Checksum Is Not Valid\n");
3358 err = -EIO;
3359 goto err_eeprom;
3360 }
3361 }
3362 break;
3363 default:
3364 if (hw->nvm.ops.validate(hw) < 0) {
3365 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3366 err = -EIO;
3367 goto err_eeprom;
3368 }
3369 break;
3370 }
3371
3372 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3373 /* copy the MAC address out of the NVM */
3374 if (hw->mac.ops.read_mac_addr(hw))
3375 dev_err(&pdev->dev, "NVM Read Error\n");
3376 }
3377
3378 eth_hw_addr_set(netdev, hw->mac.addr);
3379
3380 if (!is_valid_ether_addr(netdev->dev_addr)) {
3381 dev_err(&pdev->dev, "Invalid MAC Address\n");
3382 err = -EIO;
3383 goto err_eeprom;
3384 }
3385
3386 igb_set_default_mac_filter(adapter);
3387
3388 /* get firmware version for ethtool -i */
3389 igb_set_fw_version(adapter);
3390
3391 /* configure RXPBSIZE and TXPBSIZE */
3392 if (hw->mac.type == e1000_i210) {
3393 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3394 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3395 }
3396
3397 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3398 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3399
3400 INIT_WORK(&adapter->reset_task, igb_reset_task);
3401 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3402
3403 /* Initialize link properties that are user-changeable */
3404 adapter->fc_autoneg = true;
3405 hw->mac.autoneg = true;
3406 hw->phy.autoneg_advertised = 0x2f;
3407
3408 hw->fc.requested_mode = e1000_fc_default;
3409 hw->fc.current_mode = e1000_fc_default;
3410
3411 igb_validate_mdi_setting(hw);
3412
3413 /* By default, support wake on port A */
3414 if (hw->bus.func == 0)
3415 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3416
3417 /* Check the NVM for wake support on non-port A ports */
3418 if (hw->mac.type >= e1000_82580)
3419 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3420 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3421 &eeprom_data);
3422 else if (hw->bus.func == 1)
3423 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3424
3425 if (eeprom_data & IGB_EEPROM_APME)
3426 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3427
3428 /* now that we have the eeprom settings, apply the special cases where
3429 * the eeprom may be wrong or the board simply won't support wake on
3430 * lan on a particular port
3431 */
3432 switch (pdev->device) {
3433 case E1000_DEV_ID_82575GB_QUAD_COPPER:
3434 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3435 break;
3436 case E1000_DEV_ID_82575EB_FIBER_SERDES:
3437 case E1000_DEV_ID_82576_FIBER:
3438 case E1000_DEV_ID_82576_SERDES:
3439 /* Wake events only supported on port A for dual fiber
3440 * regardless of eeprom setting
3441 */
3442 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3443 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3444 break;
3445 case E1000_DEV_ID_82576_QUAD_COPPER:
3446 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3447 /* if quad port adapter, disable WoL on all but port A */
3448 if (global_quad_port_a != 0)
3449 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3450 else
3451 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3452 /* Reset for multiple quad port adapters */
3453 if (++global_quad_port_a == 4)
3454 global_quad_port_a = 0;
3455 break;
3456 default:
3457 /* If the device can't wake, don't set software support */
3458 if (!device_can_wakeup(&adapter->pdev->dev))
3459 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3460 }
3461
3462 /* initialize the wol settings based on the eeprom settings */
3463 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3464 adapter->wol |= E1000_WUFC_MAG;
3465
3466 /* Some vendors want WoL disabled by default, but still supported */
3467 if ((hw->mac.type == e1000_i350) &&
3468 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3469 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3470 adapter->wol = 0;
3471 }
3472
3473 /* Some vendors want the ability to Use the EEPROM setting as
3474 * enable/disable only, and not for capability
3475 */
3476 if (((hw->mac.type == e1000_i350) ||
3477 (hw->mac.type == e1000_i354)) &&
3478 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3479 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3480 adapter->wol = 0;
3481 }
3482 if (hw->mac.type == e1000_i350) {
3483 if (((pdev->subsystem_device == 0x5001) ||
3484 (pdev->subsystem_device == 0x5002)) &&
3485 (hw->bus.func == 0)) {
3486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3487 adapter->wol = 0;
3488 }
3489 if (pdev->subsystem_device == 0x1F52)
3490 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3491 }
3492
3493 device_set_wakeup_enable(&adapter->pdev->dev,
3494 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3495
3496 /* reset the hardware with the new settings */
3497 igb_reset(adapter);
3498
3499 /* Init the I2C interface */
3500 err = igb_init_i2c(adapter);
3501 if (err) {
3502 dev_err(&pdev->dev, "failed to init i2c interface\n");
3503 goto err_eeprom;
3504 }
3505
3506 /* let the f/w know that the h/w is now under the control of the
3507 * driver.
3508 */
3509 igb_get_hw_control(adapter);
3510
3511 strcpy(netdev->name, "eth%d");
3512 err = register_netdev(netdev);
3513 if (err)
3514 goto err_register;
3515
3516 /* carrier off reporting is important to ethtool even BEFORE open */
3517 netif_carrier_off(netdev);
3518
3519#ifdef CONFIG_IGB_DCA
3520 if (dca_add_requester(&pdev->dev) == 0) {
3521 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3522 dev_info(&pdev->dev, "DCA enabled\n");
3523 igb_setup_dca(adapter);
3524 }
3525
3526#endif
3527#ifdef CONFIG_IGB_HWMON
3528 /* Initialize the thermal sensor on i350 devices. */
3529 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3530 u16 ets_word;
3531
3532 /* Read the NVM to determine if this i350 device supports an
3533 * external thermal sensor.
3534 */
3535 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3536 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3537 adapter->ets = true;
3538 else
3539 adapter->ets = false;
3540 /* Only enable I2C bit banging if an external thermal
3541 * sensor is supported.
3542 */
3543 if (adapter->ets)
3544 igb_set_i2c_bb(hw);
3545 hw->mac.ops.init_thermal_sensor_thresh(hw);
3546 if (igb_sysfs_init(adapter))
3547 dev_err(&pdev->dev,
3548 "failed to allocate sysfs resources\n");
3549 } else {
3550 adapter->ets = false;
3551 }
3552#endif
3553 /* Check if Media Autosense is enabled */
3554 adapter->ei = *ei;
3555 if (hw->dev_spec._82575.mas_capable)
3556 igb_init_mas(adapter);
3557
3558 /* do hw tstamp init after resetting */
3559 igb_ptp_init(adapter);
3560
3561 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3562 /* print bus type/speed/width info, not applicable to i354 */
3563 if (hw->mac.type != e1000_i354) {
3564 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3565 netdev->name,
3566 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3567 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3568 "unknown"),
3569 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3570 "Width x4" :
3571 (hw->bus.width == e1000_bus_width_pcie_x2) ?
3572 "Width x2" :
3573 (hw->bus.width == e1000_bus_width_pcie_x1) ?
3574 "Width x1" : "unknown"), netdev->dev_addr);
3575 }
3576
3577 if ((hw->mac.type == e1000_82576 &&
3578 rd32(E1000_EECD) & E1000_EECD_PRES) ||
3579 (hw->mac.type >= e1000_i210 ||
3580 igb_get_flash_presence_i210(hw))) {
3581 ret_val = igb_read_part_string(hw, part_str,
3582 E1000_PBANUM_LENGTH);
3583 } else {
3584 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3585 }
3586
3587 if (ret_val)
3588 strcpy(part_str, "Unknown");
3589 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3590 dev_info(&pdev->dev,
3591 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3592 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3593 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3594 adapter->num_rx_queues, adapter->num_tx_queues);
3595 if (hw->phy.media_type == e1000_media_type_copper) {
3596 switch (hw->mac.type) {
3597 case e1000_i350:
3598 case e1000_i210:
3599 case e1000_i211:
3600 /* Enable EEE for internal copper PHY devices */
3601 err = igb_set_eee_i350(hw, true, true);
3602 if ((!err) &&
3603 (!hw->dev_spec._82575.eee_disable)) {
3604 adapter->eee_advert =
3605 MDIO_EEE_100TX | MDIO_EEE_1000T;
3606 adapter->flags |= IGB_FLAG_EEE;
3607 }
3608 break;
3609 case e1000_i354:
3610 if ((rd32(E1000_CTRL_EXT) &
3611 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3612 err = igb_set_eee_i354(hw, true, true);
3613 if ((!err) &&
3614 (!hw->dev_spec._82575.eee_disable)) {
3615 adapter->eee_advert =
3616 MDIO_EEE_100TX | MDIO_EEE_1000T;
3617 adapter->flags |= IGB_FLAG_EEE;
3618 }
3619 }
3620 break;
3621 default:
3622 break;
3623 }
3624 }
3625
3626 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3627
3628 pm_runtime_put_noidle(&pdev->dev);
3629 return 0;
3630
3631err_register:
3632 igb_release_hw_control(adapter);
3633 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3634err_eeprom:
3635 if (!igb_check_reset_block(hw))
3636 igb_reset_phy(hw);
3637
3638 if (hw->flash_address)
3639 iounmap(hw->flash_address);
3640err_sw_init:
3641 kfree(adapter->mac_table);
3642 kfree(adapter->shadow_vfta);
3643 igb_clear_interrupt_scheme(adapter);
3644#ifdef CONFIG_PCI_IOV
3645 igb_disable_sriov(pdev);
3646#endif
3647 pci_iounmap(pdev, adapter->io_addr);
3648err_ioremap:
3649 free_netdev(netdev);
3650err_alloc_etherdev:
3651 pci_disable_pcie_error_reporting(pdev);
3652 pci_release_mem_regions(pdev);
3653err_pci_reg:
3654err_dma:
3655 pci_disable_device(pdev);
3656 return err;
3657}
3658
3659#ifdef CONFIG_PCI_IOV
3660static int igb_disable_sriov(struct pci_dev *pdev)
3661{
3662 struct net_device *netdev = pci_get_drvdata(pdev);
3663 struct igb_adapter *adapter = netdev_priv(netdev);
3664 struct e1000_hw *hw = &adapter->hw;
3665 unsigned long flags;
3666
3667 /* reclaim resources allocated to VFs */
3668 if (adapter->vf_data) {
3669 /* disable iov and allow time for transactions to clear */
3670 if (pci_vfs_assigned(pdev)) {
3671 dev_warn(&pdev->dev,
3672 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3673 return -EPERM;
3674 } else {
3675 pci_disable_sriov(pdev);
3676 msleep(500);
3677 }
3678 spin_lock_irqsave(&adapter->vfs_lock, flags);
3679 kfree(adapter->vf_mac_list);
3680 adapter->vf_mac_list = NULL;
3681 kfree(adapter->vf_data);
3682 adapter->vf_data = NULL;
3683 adapter->vfs_allocated_count = 0;
3684 spin_unlock_irqrestore(&adapter->vfs_lock, flags);
3685 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3686 wrfl();
3687 msleep(100);
3688 dev_info(&pdev->dev, "IOV Disabled\n");
3689
3690 /* Re-enable DMA Coalescing flag since IOV is turned off */
3691 adapter->flags |= IGB_FLAG_DMAC;
3692 }
3693
3694 return 0;
3695}
3696
3697static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3698{
3699 struct net_device *netdev = pci_get_drvdata(pdev);
3700 struct igb_adapter *adapter = netdev_priv(netdev);
3701 int old_vfs = pci_num_vf(pdev);
3702 struct vf_mac_filter *mac_list;
3703 int err = 0;
3704 int num_vf_mac_filters, i;
3705
3706 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3707 err = -EPERM;
3708 goto out;
3709 }
3710 if (!num_vfs)
3711 goto out;
3712
3713 if (old_vfs) {
3714 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3715 old_vfs, max_vfs);
3716 adapter->vfs_allocated_count = old_vfs;
3717 } else
3718 adapter->vfs_allocated_count = num_vfs;
3719
3720 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3721 sizeof(struct vf_data_storage), GFP_KERNEL);
3722
3723 /* if allocation failed then we do not support SR-IOV */
3724 if (!adapter->vf_data) {
3725 adapter->vfs_allocated_count = 0;
3726 err = -ENOMEM;
3727 goto out;
3728 }
3729
3730 /* Due to the limited number of RAR entries calculate potential
3731 * number of MAC filters available for the VFs. Reserve entries
3732 * for PF default MAC, PF MAC filters and at least one RAR entry
3733 * for each VF for VF MAC.
3734 */
3735 num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3736 (1 + IGB_PF_MAC_FILTERS_RESERVED +
3737 adapter->vfs_allocated_count);
3738
3739 adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3740 sizeof(struct vf_mac_filter),
3741 GFP_KERNEL);
3742
3743 mac_list = adapter->vf_mac_list;
3744 INIT_LIST_HEAD(&adapter->vf_macs.l);
3745
3746 if (adapter->vf_mac_list) {
3747 /* Initialize list of VF MAC filters */
3748 for (i = 0; i < num_vf_mac_filters; i++) {
3749 mac_list->vf = -1;
3750 mac_list->free = true;
3751 list_add(&mac_list->l, &adapter->vf_macs.l);
3752 mac_list++;
3753 }
3754 } else {
3755 /* If we could not allocate memory for the VF MAC filters
3756 * we can continue without this feature but warn user.
3757 */
3758 dev_err(&pdev->dev,
3759 "Unable to allocate memory for VF MAC filter list\n");
3760 }
3761
3762 /* only call pci_enable_sriov() if no VFs are allocated already */
3763 if (!old_vfs) {
3764 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3765 if (err)
3766 goto err_out;
3767 }
3768 dev_info(&pdev->dev, "%d VFs allocated\n",
3769 adapter->vfs_allocated_count);
3770 for (i = 0; i < adapter->vfs_allocated_count; i++)
3771 igb_vf_configure(adapter, i);
3772
3773 /* DMA Coalescing is not supported in IOV mode. */
3774 adapter->flags &= ~IGB_FLAG_DMAC;
3775 goto out;
3776
3777err_out:
3778 kfree(adapter->vf_mac_list);
3779 adapter->vf_mac_list = NULL;
3780 kfree(adapter->vf_data);
3781 adapter->vf_data = NULL;
3782 adapter->vfs_allocated_count = 0;
3783out:
3784 return err;
3785}
3786
3787#endif
3788/**
3789 * igb_remove_i2c - Cleanup I2C interface
3790 * @adapter: pointer to adapter structure
3791 **/
3792static void igb_remove_i2c(struct igb_adapter *adapter)
3793{
3794 /* free the adapter bus structure */
3795 i2c_del_adapter(&adapter->i2c_adap);
3796}
3797
3798/**
3799 * igb_remove - Device Removal Routine
3800 * @pdev: PCI device information struct
3801 *
3802 * igb_remove is called by the PCI subsystem to alert the driver
3803 * that it should release a PCI device. The could be caused by a
3804 * Hot-Plug event, or because the driver is going to be removed from
3805 * memory.
3806 **/
3807static void igb_remove(struct pci_dev *pdev)
3808{
3809 struct net_device *netdev = pci_get_drvdata(pdev);
3810 struct igb_adapter *adapter = netdev_priv(netdev);
3811 struct e1000_hw *hw = &adapter->hw;
3812
3813 pm_runtime_get_noresume(&pdev->dev);
3814#ifdef CONFIG_IGB_HWMON
3815 igb_sysfs_exit(adapter);
3816#endif
3817 igb_remove_i2c(adapter);
3818 igb_ptp_stop(adapter);
3819 /* The watchdog timer may be rescheduled, so explicitly
3820 * disable watchdog from being rescheduled.
3821 */
3822 set_bit(__IGB_DOWN, &adapter->state);
3823 del_timer_sync(&adapter->watchdog_timer);
3824 del_timer_sync(&adapter->phy_info_timer);
3825
3826 cancel_work_sync(&adapter->reset_task);
3827 cancel_work_sync(&adapter->watchdog_task);
3828
3829#ifdef CONFIG_IGB_DCA
3830 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3831 dev_info(&pdev->dev, "DCA disabled\n");
3832 dca_remove_requester(&pdev->dev);
3833 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3834 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3835 }
3836#endif
3837
3838 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3839 * would have already happened in close and is redundant.
3840 */
3841 igb_release_hw_control(adapter);
3842
3843#ifdef CONFIG_PCI_IOV
3844 rtnl_lock();
3845 igb_disable_sriov(pdev);
3846 rtnl_unlock();
3847#endif
3848
3849 unregister_netdev(netdev);
3850
3851 igb_clear_interrupt_scheme(adapter);
3852
3853 pci_iounmap(pdev, adapter->io_addr);
3854 if (hw->flash_address)
3855 iounmap(hw->flash_address);
3856 pci_release_mem_regions(pdev);
3857
3858 kfree(adapter->mac_table);
3859 kfree(adapter->shadow_vfta);
3860 free_netdev(netdev);
3861
3862 pci_disable_pcie_error_reporting(pdev);
3863
3864 pci_disable_device(pdev);
3865}
3866
3867/**
3868 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3869 * @adapter: board private structure to initialize
3870 *
3871 * This function initializes the vf specific data storage and then attempts to
3872 * allocate the VFs. The reason for ordering it this way is because it is much
3873 * mor expensive time wise to disable SR-IOV than it is to allocate and free
3874 * the memory for the VFs.
3875 **/
3876static void igb_probe_vfs(struct igb_adapter *adapter)
3877{
3878#ifdef CONFIG_PCI_IOV
3879 struct pci_dev *pdev = adapter->pdev;
3880 struct e1000_hw *hw = &adapter->hw;
3881
3882 /* Virtualization features not supported on i210 family. */
3883 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3884 return;
3885
3886 /* Of the below we really only want the effect of getting
3887 * IGB_FLAG_HAS_MSIX set (if available), without which
3888 * igb_enable_sriov() has no effect.
3889 */
3890 igb_set_interrupt_capability(adapter, true);
3891 igb_reset_interrupt_capability(adapter);
3892
3893 pci_sriov_set_totalvfs(pdev, 7);
3894 igb_enable_sriov(pdev, max_vfs);
3895
3896#endif /* CONFIG_PCI_IOV */
3897}
3898
3899unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3900{
3901 struct e1000_hw *hw = &adapter->hw;
3902 unsigned int max_rss_queues;
3903
3904 /* Determine the maximum number of RSS queues supported. */
3905 switch (hw->mac.type) {
3906 case e1000_i211:
3907 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3908 break;
3909 case e1000_82575:
3910 case e1000_i210:
3911 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3912 break;
3913 case e1000_i350:
3914 /* I350 cannot do RSS and SR-IOV at the same time */
3915 if (!!adapter->vfs_allocated_count) {
3916 max_rss_queues = 1;
3917 break;
3918 }
3919 fallthrough;
3920 case e1000_82576:
3921 if (!!adapter->vfs_allocated_count) {
3922 max_rss_queues = 2;
3923 break;
3924 }
3925 fallthrough;
3926 case e1000_82580:
3927 case e1000_i354:
3928 default:
3929 max_rss_queues = IGB_MAX_RX_QUEUES;
3930 break;
3931 }
3932
3933 return max_rss_queues;
3934}
3935
3936static void igb_init_queue_configuration(struct igb_adapter *adapter)
3937{
3938 u32 max_rss_queues;
3939
3940 max_rss_queues = igb_get_max_rss_queues(adapter);
3941 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3942
3943 igb_set_flag_queue_pairs(adapter, max_rss_queues);
3944}
3945
3946void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3947 const u32 max_rss_queues)
3948{
3949 struct e1000_hw *hw = &adapter->hw;
3950
3951 /* Determine if we need to pair queues. */
3952 switch (hw->mac.type) {
3953 case e1000_82575:
3954 case e1000_i211:
3955 /* Device supports enough interrupts without queue pairing. */
3956 break;
3957 case e1000_82576:
3958 case e1000_82580:
3959 case e1000_i350:
3960 case e1000_i354:
3961 case e1000_i210:
3962 default:
3963 /* If rss_queues > half of max_rss_queues, pair the queues in
3964 * order to conserve interrupts due to limited supply.
3965 */
3966 if (adapter->rss_queues > (max_rss_queues / 2))
3967 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3968 else
3969 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3970 break;
3971 }
3972}
3973
3974/**
3975 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3976 * @adapter: board private structure to initialize
3977 *
3978 * igb_sw_init initializes the Adapter private data structure.
3979 * Fields are initialized based on PCI device information and
3980 * OS network device settings (MTU size).
3981 **/
3982static int igb_sw_init(struct igb_adapter *adapter)
3983{
3984 struct e1000_hw *hw = &adapter->hw;
3985 struct net_device *netdev = adapter->netdev;
3986 struct pci_dev *pdev = adapter->pdev;
3987
3988 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3989
3990 /* set default ring sizes */
3991 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3992 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3993
3994 /* set default ITR values */
3995 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3996 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3997
3998 /* set default work limits */
3999 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
4000
4001 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
4002 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4003
4004 spin_lock_init(&adapter->nfc_lock);
4005 spin_lock_init(&adapter->stats64_lock);
4006
4007 /* init spinlock to avoid concurrency of VF resources */
4008 spin_lock_init(&adapter->vfs_lock);
4009#ifdef CONFIG_PCI_IOV
4010 switch (hw->mac.type) {
4011 case e1000_82576:
4012 case e1000_i350:
4013 if (max_vfs > 7) {
4014 dev_warn(&pdev->dev,
4015 "Maximum of 7 VFs per PF, using max\n");
4016 max_vfs = adapter->vfs_allocated_count = 7;
4017 } else
4018 adapter->vfs_allocated_count = max_vfs;
4019 if (adapter->vfs_allocated_count)
4020 dev_warn(&pdev->dev,
4021 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
4022 break;
4023 default:
4024 break;
4025 }
4026#endif /* CONFIG_PCI_IOV */
4027
4028 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
4029 adapter->flags |= IGB_FLAG_HAS_MSIX;
4030
4031 adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4032 sizeof(struct igb_mac_addr),
4033 GFP_KERNEL);
4034 if (!adapter->mac_table)
4035 return -ENOMEM;
4036
4037 igb_probe_vfs(adapter);
4038
4039 igb_init_queue_configuration(adapter);
4040
4041 /* Setup and initialize a copy of the hw vlan table array */
4042 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4043 GFP_KERNEL);
4044 if (!adapter->shadow_vfta)
4045 return -ENOMEM;
4046
4047 /* This call may decrease the number of queues */
4048 if (igb_init_interrupt_scheme(adapter, true)) {
4049 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4050 return -ENOMEM;
4051 }
4052
4053 /* Explicitly disable IRQ since the NIC can be in any state. */
4054 igb_irq_disable(adapter);
4055
4056 if (hw->mac.type >= e1000_i350)
4057 adapter->flags &= ~IGB_FLAG_DMAC;
4058
4059 set_bit(__IGB_DOWN, &adapter->state);
4060 return 0;
4061}
4062
4063/**
4064 * __igb_open - Called when a network interface is made active
4065 * @netdev: network interface device structure
4066 * @resuming: indicates whether we are in a resume call
4067 *
4068 * Returns 0 on success, negative value on failure
4069 *
4070 * The open entry point is called when a network interface is made
4071 * active by the system (IFF_UP). At this point all resources needed
4072 * for transmit and receive operations are allocated, the interrupt
4073 * handler is registered with the OS, the watchdog timer is started,
4074 * and the stack is notified that the interface is ready.
4075 **/
4076static int __igb_open(struct net_device *netdev, bool resuming)
4077{
4078 struct igb_adapter *adapter = netdev_priv(netdev);
4079 struct e1000_hw *hw = &adapter->hw;
4080 struct pci_dev *pdev = adapter->pdev;
4081 int err;
4082 int i;
4083
4084 /* disallow open during test */
4085 if (test_bit(__IGB_TESTING, &adapter->state)) {
4086 WARN_ON(resuming);
4087 return -EBUSY;
4088 }
4089
4090 if (!resuming)
4091 pm_runtime_get_sync(&pdev->dev);
4092
4093 netif_carrier_off(netdev);
4094
4095 /* allocate transmit descriptors */
4096 err = igb_setup_all_tx_resources(adapter);
4097 if (err)
4098 goto err_setup_tx;
4099
4100 /* allocate receive descriptors */
4101 err = igb_setup_all_rx_resources(adapter);
4102 if (err)
4103 goto err_setup_rx;
4104
4105 igb_power_up_link(adapter);
4106
4107 /* before we allocate an interrupt, we must be ready to handle it.
4108 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4109 * as soon as we call pci_request_irq, so we have to setup our
4110 * clean_rx handler before we do so.
4111 */
4112 igb_configure(adapter);
4113
4114 err = igb_request_irq(adapter);
4115 if (err)
4116 goto err_req_irq;
4117
4118 /* Notify the stack of the actual queue counts. */
4119 err = netif_set_real_num_tx_queues(adapter->netdev,
4120 adapter->num_tx_queues);
4121 if (err)
4122 goto err_set_queues;
4123
4124 err = netif_set_real_num_rx_queues(adapter->netdev,
4125 adapter->num_rx_queues);
4126 if (err)
4127 goto err_set_queues;
4128
4129 /* From here on the code is the same as igb_up() */
4130 clear_bit(__IGB_DOWN, &adapter->state);
4131
4132 for (i = 0; i < adapter->num_q_vectors; i++)
4133 napi_enable(&(adapter->q_vector[i]->napi));
4134
4135 /* Clear any pending interrupts. */
4136 rd32(E1000_TSICR);
4137 rd32(E1000_ICR);
4138
4139 igb_irq_enable(adapter);
4140
4141 /* notify VFs that reset has been completed */
4142 if (adapter->vfs_allocated_count) {
4143 u32 reg_data = rd32(E1000_CTRL_EXT);
4144
4145 reg_data |= E1000_CTRL_EXT_PFRSTD;
4146 wr32(E1000_CTRL_EXT, reg_data);
4147 }
4148
4149 netif_tx_start_all_queues(netdev);
4150
4151 if (!resuming)
4152 pm_runtime_put(&pdev->dev);
4153
4154 /* start the watchdog. */
4155 hw->mac.get_link_status = 1;
4156 schedule_work(&adapter->watchdog_task);
4157
4158 return 0;
4159
4160err_set_queues:
4161 igb_free_irq(adapter);
4162err_req_irq:
4163 igb_release_hw_control(adapter);
4164 igb_power_down_link(adapter);
4165 igb_free_all_rx_resources(adapter);
4166err_setup_rx:
4167 igb_free_all_tx_resources(adapter);
4168err_setup_tx:
4169 igb_reset(adapter);
4170 if (!resuming)
4171 pm_runtime_put(&pdev->dev);
4172
4173 return err;
4174}
4175
4176int igb_open(struct net_device *netdev)
4177{
4178 return __igb_open(netdev, false);
4179}
4180
4181/**
4182 * __igb_close - Disables a network interface
4183 * @netdev: network interface device structure
4184 * @suspending: indicates we are in a suspend call
4185 *
4186 * Returns 0, this is not allowed to fail
4187 *
4188 * The close entry point is called when an interface is de-activated
4189 * by the OS. The hardware is still under the driver's control, but
4190 * needs to be disabled. A global MAC reset is issued to stop the
4191 * hardware, and all transmit and receive resources are freed.
4192 **/
4193static int __igb_close(struct net_device *netdev, bool suspending)
4194{
4195 struct igb_adapter *adapter = netdev_priv(netdev);
4196 struct pci_dev *pdev = adapter->pdev;
4197
4198 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4199
4200 if (!suspending)
4201 pm_runtime_get_sync(&pdev->dev);
4202
4203 igb_down(adapter);
4204 igb_free_irq(adapter);
4205
4206 igb_free_all_tx_resources(adapter);
4207 igb_free_all_rx_resources(adapter);
4208
4209 if (!suspending)
4210 pm_runtime_put_sync(&pdev->dev);
4211 return 0;
4212}
4213
4214int igb_close(struct net_device *netdev)
4215{
4216 if (netif_device_present(netdev) || netdev->dismantle)
4217 return __igb_close(netdev, false);
4218 return 0;
4219}
4220
4221/**
4222 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
4223 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4224 *
4225 * Return 0 on success, negative on failure
4226 **/
4227int igb_setup_tx_resources(struct igb_ring *tx_ring)
4228{
4229 struct device *dev = tx_ring->dev;
4230 int size;
4231
4232 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4233
4234 tx_ring->tx_buffer_info = vmalloc(size);
4235 if (!tx_ring->tx_buffer_info)
4236 goto err;
4237
4238 /* round up to nearest 4K */
4239 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4240 tx_ring->size = ALIGN(tx_ring->size, 4096);
4241
4242 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4243 &tx_ring->dma, GFP_KERNEL);
4244 if (!tx_ring->desc)
4245 goto err;
4246
4247 tx_ring->next_to_use = 0;
4248 tx_ring->next_to_clean = 0;
4249
4250 return 0;
4251
4252err:
4253 vfree(tx_ring->tx_buffer_info);
4254 tx_ring->tx_buffer_info = NULL;
4255 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4256 return -ENOMEM;
4257}
4258
4259/**
4260 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
4261 * (Descriptors) for all queues
4262 * @adapter: board private structure
4263 *
4264 * Return 0 on success, negative on failure
4265 **/
4266static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4267{
4268 struct pci_dev *pdev = adapter->pdev;
4269 int i, err = 0;
4270
4271 for (i = 0; i < adapter->num_tx_queues; i++) {
4272 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4273 if (err) {
4274 dev_err(&pdev->dev,
4275 "Allocation for Tx Queue %u failed\n", i);
4276 for (i--; i >= 0; i--)
4277 igb_free_tx_resources(adapter->tx_ring[i]);
4278 break;
4279 }
4280 }
4281
4282 return err;
4283}
4284
4285/**
4286 * igb_setup_tctl - configure the transmit control registers
4287 * @adapter: Board private structure
4288 **/
4289void igb_setup_tctl(struct igb_adapter *adapter)
4290{
4291 struct e1000_hw *hw = &adapter->hw;
4292 u32 tctl;
4293
4294 /* disable queue 0 which is enabled by default on 82575 and 82576 */
4295 wr32(E1000_TXDCTL(0), 0);
4296
4297 /* Program the Transmit Control Register */
4298 tctl = rd32(E1000_TCTL);
4299 tctl &= ~E1000_TCTL_CT;
4300 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4301 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4302
4303 igb_config_collision_dist(hw);
4304
4305 /* Enable transmits */
4306 tctl |= E1000_TCTL_EN;
4307
4308 wr32(E1000_TCTL, tctl);
4309}
4310
4311/**
4312 * igb_configure_tx_ring - Configure transmit ring after Reset
4313 * @adapter: board private structure
4314 * @ring: tx ring to configure
4315 *
4316 * Configure a transmit ring after a reset.
4317 **/
4318void igb_configure_tx_ring(struct igb_adapter *adapter,
4319 struct igb_ring *ring)
4320{
4321 struct e1000_hw *hw = &adapter->hw;
4322 u32 txdctl = 0;
4323 u64 tdba = ring->dma;
4324 int reg_idx = ring->reg_idx;
4325
4326 wr32(E1000_TDLEN(reg_idx),
4327 ring->count * sizeof(union e1000_adv_tx_desc));
4328 wr32(E1000_TDBAL(reg_idx),
4329 tdba & 0x00000000ffffffffULL);
4330 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4331
4332 ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4333 wr32(E1000_TDH(reg_idx), 0);
4334 writel(0, ring->tail);
4335
4336 txdctl |= IGB_TX_PTHRESH;
4337 txdctl |= IGB_TX_HTHRESH << 8;
4338 txdctl |= IGB_TX_WTHRESH << 16;
4339
4340 /* reinitialize tx_buffer_info */
4341 memset(ring->tx_buffer_info, 0,
4342 sizeof(struct igb_tx_buffer) * ring->count);
4343
4344 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4345 wr32(E1000_TXDCTL(reg_idx), txdctl);
4346}
4347
4348/**
4349 * igb_configure_tx - Configure transmit Unit after Reset
4350 * @adapter: board private structure
4351 *
4352 * Configure the Tx unit of the MAC after a reset.
4353 **/
4354static void igb_configure_tx(struct igb_adapter *adapter)
4355{
4356 struct e1000_hw *hw = &adapter->hw;
4357 int i;
4358
4359 /* disable the queues */
4360 for (i = 0; i < adapter->num_tx_queues; i++)
4361 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4362
4363 wrfl();
4364 usleep_range(10000, 20000);
4365
4366 for (i = 0; i < adapter->num_tx_queues; i++)
4367 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4368}
4369
4370/**
4371 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
4372 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
4373 *
4374 * Returns 0 on success, negative on failure
4375 **/
4376int igb_setup_rx_resources(struct igb_ring *rx_ring)
4377{
4378 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4379 struct device *dev = rx_ring->dev;
4380 int size, res;
4381
4382 /* XDP RX-queue info */
4383 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq))
4384 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4385 res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4386 rx_ring->queue_index, 0);
4387 if (res < 0) {
4388 dev_err(dev, "Failed to register xdp_rxq index %u\n",
4389 rx_ring->queue_index);
4390 return res;
4391 }
4392
4393 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4394
4395 rx_ring->rx_buffer_info = vmalloc(size);
4396 if (!rx_ring->rx_buffer_info)
4397 goto err;
4398
4399 /* Round up to nearest 4K */
4400 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4401 rx_ring->size = ALIGN(rx_ring->size, 4096);
4402
4403 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4404 &rx_ring->dma, GFP_KERNEL);
4405 if (!rx_ring->desc)
4406 goto err;
4407
4408 rx_ring->next_to_alloc = 0;
4409 rx_ring->next_to_clean = 0;
4410 rx_ring->next_to_use = 0;
4411
4412 rx_ring->xdp_prog = adapter->xdp_prog;
4413
4414 return 0;
4415
4416err:
4417 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4418 vfree(rx_ring->rx_buffer_info);
4419 rx_ring->rx_buffer_info = NULL;
4420 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4421 return -ENOMEM;
4422}
4423
4424/**
4425 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
4426 * (Descriptors) for all queues
4427 * @adapter: board private structure
4428 *
4429 * Return 0 on success, negative on failure
4430 **/
4431static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4432{
4433 struct pci_dev *pdev = adapter->pdev;
4434 int i, err = 0;
4435
4436 for (i = 0; i < adapter->num_rx_queues; i++) {
4437 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4438 if (err) {
4439 dev_err(&pdev->dev,
4440 "Allocation for Rx Queue %u failed\n", i);
4441 for (i--; i >= 0; i--)
4442 igb_free_rx_resources(adapter->rx_ring[i]);
4443 break;
4444 }
4445 }
4446
4447 return err;
4448}
4449
4450/**
4451 * igb_setup_mrqc - configure the multiple receive queue control registers
4452 * @adapter: Board private structure
4453 **/
4454static void igb_setup_mrqc(struct igb_adapter *adapter)
4455{
4456 struct e1000_hw *hw = &adapter->hw;
4457 u32 mrqc, rxcsum;
4458 u32 j, num_rx_queues;
4459 u32 rss_key[10];
4460
4461 netdev_rss_key_fill(rss_key, sizeof(rss_key));
4462 for (j = 0; j < 10; j++)
4463 wr32(E1000_RSSRK(j), rss_key[j]);
4464
4465 num_rx_queues = adapter->rss_queues;
4466
4467 switch (hw->mac.type) {
4468 case e1000_82576:
4469 /* 82576 supports 2 RSS queues for SR-IOV */
4470 if (adapter->vfs_allocated_count)
4471 num_rx_queues = 2;
4472 break;
4473 default:
4474 break;
4475 }
4476
4477 if (adapter->rss_indir_tbl_init != num_rx_queues) {
4478 for (j = 0; j < IGB_RETA_SIZE; j++)
4479 adapter->rss_indir_tbl[j] =
4480 (j * num_rx_queues) / IGB_RETA_SIZE;
4481 adapter->rss_indir_tbl_init = num_rx_queues;
4482 }
4483 igb_write_rss_indir_tbl(adapter);
4484
4485 /* Disable raw packet checksumming so that RSS hash is placed in
4486 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
4487 * offloads as they are enabled by default
4488 */
4489 rxcsum = rd32(E1000_RXCSUM);
4490 rxcsum |= E1000_RXCSUM_PCSD;
4491
4492 if (adapter->hw.mac.type >= e1000_82576)
4493 /* Enable Receive Checksum Offload for SCTP */
4494 rxcsum |= E1000_RXCSUM_CRCOFL;
4495
4496 /* Don't need to set TUOFL or IPOFL, they default to 1 */
4497 wr32(E1000_RXCSUM, rxcsum);
4498
4499 /* Generate RSS hash based on packet types, TCP/UDP
4500 * port numbers and/or IPv4/v6 src and dst addresses
4501 */
4502 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4503 E1000_MRQC_RSS_FIELD_IPV4_TCP |
4504 E1000_MRQC_RSS_FIELD_IPV6 |
4505 E1000_MRQC_RSS_FIELD_IPV6_TCP |
4506 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4507
4508 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4509 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4510 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4511 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4512
4513 /* If VMDq is enabled then we set the appropriate mode for that, else
4514 * we default to RSS so that an RSS hash is calculated per packet even
4515 * if we are only using one queue
4516 */
4517 if (adapter->vfs_allocated_count) {
4518 if (hw->mac.type > e1000_82575) {
4519 /* Set the default pool for the PF's first queue */
4520 u32 vtctl = rd32(E1000_VT_CTL);
4521
4522 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4523 E1000_VT_CTL_DISABLE_DEF_POOL);
4524 vtctl |= adapter->vfs_allocated_count <<
4525 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4526 wr32(E1000_VT_CTL, vtctl);
4527 }
4528 if (adapter->rss_queues > 1)
4529 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4530 else
4531 mrqc |= E1000_MRQC_ENABLE_VMDQ;
4532 } else {
4533 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4534 }
4535 igb_vmm_control(adapter);
4536
4537 wr32(E1000_MRQC, mrqc);
4538}
4539
4540/**
4541 * igb_setup_rctl - configure the receive control registers
4542 * @adapter: Board private structure
4543 **/
4544void igb_setup_rctl(struct igb_adapter *adapter)
4545{
4546 struct e1000_hw *hw = &adapter->hw;
4547 u32 rctl;
4548
4549 rctl = rd32(E1000_RCTL);
4550
4551 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4552 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4553
4554 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4555 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4556
4557 /* enable stripping of CRC. It's unlikely this will break BMC
4558 * redirection as it did with e1000. Newer features require
4559 * that the HW strips the CRC.
4560 */
4561 rctl |= E1000_RCTL_SECRC;
4562
4563 /* disable store bad packets and clear size bits. */
4564 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4565
4566 /* enable LPE to allow for reception of jumbo frames */
4567 rctl |= E1000_RCTL_LPE;
4568
4569 /* disable queue 0 to prevent tail write w/o re-config */
4570 wr32(E1000_RXDCTL(0), 0);
4571
4572 /* Attention!!! For SR-IOV PF driver operations you must enable
4573 * queue drop for all VF and PF queues to prevent head of line blocking
4574 * if an un-trusted VF does not provide descriptors to hardware.
4575 */
4576 if (adapter->vfs_allocated_count) {
4577 /* set all queue drop enable bits */
4578 wr32(E1000_QDE, ALL_QUEUES);
4579 }
4580
4581 /* This is useful for sniffing bad packets. */
4582 if (adapter->netdev->features & NETIF_F_RXALL) {
4583 /* UPE and MPE will be handled by normal PROMISC logic
4584 * in e1000e_set_rx_mode
4585 */
4586 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4587 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4588 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4589
4590 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4591 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4592 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4593 * and that breaks VLANs.
4594 */
4595 }
4596
4597 wr32(E1000_RCTL, rctl);
4598}
4599
4600static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4601 int vfn)
4602{
4603 struct e1000_hw *hw = &adapter->hw;
4604 u32 vmolr;
4605
4606 if (size > MAX_JUMBO_FRAME_SIZE)
4607 size = MAX_JUMBO_FRAME_SIZE;
4608
4609 vmolr = rd32(E1000_VMOLR(vfn));
4610 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4611 vmolr |= size | E1000_VMOLR_LPE;
4612 wr32(E1000_VMOLR(vfn), vmolr);
4613
4614 return 0;
4615}
4616
4617static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4618 int vfn, bool enable)
4619{
4620 struct e1000_hw *hw = &adapter->hw;
4621 u32 val, reg;
4622
4623 if (hw->mac.type < e1000_82576)
4624 return;
4625
4626 if (hw->mac.type == e1000_i350)
4627 reg = E1000_DVMOLR(vfn);
4628 else
4629 reg = E1000_VMOLR(vfn);
4630
4631 val = rd32(reg);
4632 if (enable)
4633 val |= E1000_VMOLR_STRVLAN;
4634 else
4635 val &= ~(E1000_VMOLR_STRVLAN);
4636 wr32(reg, val);
4637}
4638
4639static inline void igb_set_vmolr(struct igb_adapter *adapter,
4640 int vfn, bool aupe)
4641{
4642 struct e1000_hw *hw = &adapter->hw;
4643 u32 vmolr;
4644
4645 /* This register exists only on 82576 and newer so if we are older then
4646 * we should exit and do nothing
4647 */
4648 if (hw->mac.type < e1000_82576)
4649 return;
4650
4651 vmolr = rd32(E1000_VMOLR(vfn));
4652 if (aupe)
4653 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4654 else
4655 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4656
4657 /* clear all bits that might not be set */
4658 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4659
4660 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4661 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4662 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4663 * multicast packets
4664 */
4665 if (vfn <= adapter->vfs_allocated_count)
4666 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4667
4668 wr32(E1000_VMOLR(vfn), vmolr);
4669}
4670
4671/**
4672 * igb_setup_srrctl - configure the split and replication receive control
4673 * registers
4674 * @adapter: Board private structure
4675 * @ring: receive ring to be configured
4676 **/
4677void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4678{
4679 struct e1000_hw *hw = &adapter->hw;
4680 int reg_idx = ring->reg_idx;
4681 u32 srrctl = 0;
4682
4683 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4684 if (ring_uses_large_buffer(ring))
4685 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4686 else
4687 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4688 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4689 if (hw->mac.type >= e1000_82580)
4690 srrctl |= E1000_SRRCTL_TIMESTAMP;
4691 /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4692 * queues and rx flow control is disabled
4693 */
4694 if (adapter->vfs_allocated_count ||
4695 (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4696 adapter->num_rx_queues > 1))
4697 srrctl |= E1000_SRRCTL_DROP_EN;
4698
4699 wr32(E1000_SRRCTL(reg_idx), srrctl);
4700}
4701
4702/**
4703 * igb_configure_rx_ring - Configure a receive ring after Reset
4704 * @adapter: board private structure
4705 * @ring: receive ring to be configured
4706 *
4707 * Configure the Rx unit of the MAC after a reset.
4708 **/
4709void igb_configure_rx_ring(struct igb_adapter *adapter,
4710 struct igb_ring *ring)
4711{
4712 struct e1000_hw *hw = &adapter->hw;
4713 union e1000_adv_rx_desc *rx_desc;
4714 u64 rdba = ring->dma;
4715 int reg_idx = ring->reg_idx;
4716 u32 rxdctl = 0;
4717
4718 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4719 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4720 MEM_TYPE_PAGE_SHARED, NULL));
4721
4722 /* disable the queue */
4723 wr32(E1000_RXDCTL(reg_idx), 0);
4724
4725 /* Set DMA base address registers */
4726 wr32(E1000_RDBAL(reg_idx),
4727 rdba & 0x00000000ffffffffULL);
4728 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4729 wr32(E1000_RDLEN(reg_idx),
4730 ring->count * sizeof(union e1000_adv_rx_desc));
4731
4732 /* initialize head and tail */
4733 ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4734 wr32(E1000_RDH(reg_idx), 0);
4735 writel(0, ring->tail);
4736
4737 /* set descriptor configuration */
4738 igb_setup_srrctl(adapter, ring);
4739
4740 /* set filtering for VMDQ pools */
4741 igb_set_vmolr(adapter, reg_idx & 0x7, true);
4742
4743 rxdctl |= IGB_RX_PTHRESH;
4744 rxdctl |= IGB_RX_HTHRESH << 8;
4745 rxdctl |= IGB_RX_WTHRESH << 16;
4746
4747 /* initialize rx_buffer_info */
4748 memset(ring->rx_buffer_info, 0,
4749 sizeof(struct igb_rx_buffer) * ring->count);
4750
4751 /* initialize Rx descriptor 0 */
4752 rx_desc = IGB_RX_DESC(ring, 0);
4753 rx_desc->wb.upper.length = 0;
4754
4755 /* enable receive descriptor fetching */
4756 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4757 wr32(E1000_RXDCTL(reg_idx), rxdctl);
4758}
4759
4760static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4761 struct igb_ring *rx_ring)
4762{
4763 /* set build_skb and buffer size flags */
4764 clear_ring_build_skb_enabled(rx_ring);
4765 clear_ring_uses_large_buffer(rx_ring);
4766
4767 if (adapter->flags & IGB_FLAG_RX_LEGACY)
4768 return;
4769
4770 set_ring_build_skb_enabled(rx_ring);
4771
4772#if (PAGE_SIZE < 8192)
4773 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4774 return;
4775
4776 set_ring_uses_large_buffer(rx_ring);
4777#endif
4778}
4779
4780/**
4781 * igb_configure_rx - Configure receive Unit after Reset
4782 * @adapter: board private structure
4783 *
4784 * Configure the Rx unit of the MAC after a reset.
4785 **/
4786static void igb_configure_rx(struct igb_adapter *adapter)
4787{
4788 int i;
4789
4790 /* set the correct pool for the PF default MAC address in entry 0 */
4791 igb_set_default_mac_filter(adapter);
4792
4793 /* Setup the HW Rx Head and Tail Descriptor Pointers and
4794 * the Base and Length of the Rx Descriptor Ring
4795 */
4796 for (i = 0; i < adapter->num_rx_queues; i++) {
4797 struct igb_ring *rx_ring = adapter->rx_ring[i];
4798
4799 igb_set_rx_buffer_len(adapter, rx_ring);
4800 igb_configure_rx_ring(adapter, rx_ring);
4801 }
4802}
4803
4804/**
4805 * igb_free_tx_resources - Free Tx Resources per Queue
4806 * @tx_ring: Tx descriptor ring for a specific queue
4807 *
4808 * Free all transmit software resources
4809 **/
4810void igb_free_tx_resources(struct igb_ring *tx_ring)
4811{
4812 igb_clean_tx_ring(tx_ring);
4813
4814 vfree(tx_ring->tx_buffer_info);
4815 tx_ring->tx_buffer_info = NULL;
4816
4817 /* if not set, then don't free */
4818 if (!tx_ring->desc)
4819 return;
4820
4821 dma_free_coherent(tx_ring->dev, tx_ring->size,
4822 tx_ring->desc, tx_ring->dma);
4823
4824 tx_ring->desc = NULL;
4825}
4826
4827/**
4828 * igb_free_all_tx_resources - Free Tx Resources for All Queues
4829 * @adapter: board private structure
4830 *
4831 * Free all transmit software resources
4832 **/
4833static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4834{
4835 int i;
4836
4837 for (i = 0; i < adapter->num_tx_queues; i++)
4838 if (adapter->tx_ring[i])
4839 igb_free_tx_resources(adapter->tx_ring[i]);
4840}
4841
4842/**
4843 * igb_clean_tx_ring - Free Tx Buffers
4844 * @tx_ring: ring to be cleaned
4845 **/
4846static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4847{
4848 u16 i = tx_ring->next_to_clean;
4849 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4850
4851 while (i != tx_ring->next_to_use) {
4852 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4853
4854 /* Free all the Tx ring sk_buffs or xdp frames */
4855 if (tx_buffer->type == IGB_TYPE_SKB)
4856 dev_kfree_skb_any(tx_buffer->skb);
4857 else
4858 xdp_return_frame(tx_buffer->xdpf);
4859
4860 /* unmap skb header data */
4861 dma_unmap_single(tx_ring->dev,
4862 dma_unmap_addr(tx_buffer, dma),
4863 dma_unmap_len(tx_buffer, len),
4864 DMA_TO_DEVICE);
4865
4866 /* check for eop_desc to determine the end of the packet */
4867 eop_desc = tx_buffer->next_to_watch;
4868 tx_desc = IGB_TX_DESC(tx_ring, i);
4869
4870 /* unmap remaining buffers */
4871 while (tx_desc != eop_desc) {
4872 tx_buffer++;
4873 tx_desc++;
4874 i++;
4875 if (unlikely(i == tx_ring->count)) {
4876 i = 0;
4877 tx_buffer = tx_ring->tx_buffer_info;
4878 tx_desc = IGB_TX_DESC(tx_ring, 0);
4879 }
4880
4881 /* unmap any remaining paged data */
4882 if (dma_unmap_len(tx_buffer, len))
4883 dma_unmap_page(tx_ring->dev,
4884 dma_unmap_addr(tx_buffer, dma),
4885 dma_unmap_len(tx_buffer, len),
4886 DMA_TO_DEVICE);
4887 }
4888
4889 tx_buffer->next_to_watch = NULL;
4890
4891 /* move us one more past the eop_desc for start of next pkt */
4892 tx_buffer++;
4893 i++;
4894 if (unlikely(i == tx_ring->count)) {
4895 i = 0;
4896 tx_buffer = tx_ring->tx_buffer_info;
4897 }
4898 }
4899
4900 /* reset BQL for queue */
4901 netdev_tx_reset_queue(txring_txq(tx_ring));
4902
4903 /* reset next_to_use and next_to_clean */
4904 tx_ring->next_to_use = 0;
4905 tx_ring->next_to_clean = 0;
4906}
4907
4908/**
4909 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
4910 * @adapter: board private structure
4911 **/
4912static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4913{
4914 int i;
4915
4916 for (i = 0; i < adapter->num_tx_queues; i++)
4917 if (adapter->tx_ring[i])
4918 igb_clean_tx_ring(adapter->tx_ring[i]);
4919}
4920
4921/**
4922 * igb_free_rx_resources - Free Rx Resources
4923 * @rx_ring: ring to clean the resources from
4924 *
4925 * Free all receive software resources
4926 **/
4927void igb_free_rx_resources(struct igb_ring *rx_ring)
4928{
4929 igb_clean_rx_ring(rx_ring);
4930
4931 rx_ring->xdp_prog = NULL;
4932 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4933 vfree(rx_ring->rx_buffer_info);
4934 rx_ring->rx_buffer_info = NULL;
4935
4936 /* if not set, then don't free */
4937 if (!rx_ring->desc)
4938 return;
4939
4940 dma_free_coherent(rx_ring->dev, rx_ring->size,
4941 rx_ring->desc, rx_ring->dma);
4942
4943 rx_ring->desc = NULL;
4944}
4945
4946/**
4947 * igb_free_all_rx_resources - Free Rx Resources for All Queues
4948 * @adapter: board private structure
4949 *
4950 * Free all receive software resources
4951 **/
4952static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4953{
4954 int i;
4955
4956 for (i = 0; i < adapter->num_rx_queues; i++)
4957 if (adapter->rx_ring[i])
4958 igb_free_rx_resources(adapter->rx_ring[i]);
4959}
4960
4961/**
4962 * igb_clean_rx_ring - Free Rx Buffers per Queue
4963 * @rx_ring: ring to free buffers from
4964 **/
4965static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4966{
4967 u16 i = rx_ring->next_to_clean;
4968
4969 dev_kfree_skb(rx_ring->skb);
4970 rx_ring->skb = NULL;
4971
4972 /* Free all the Rx ring sk_buffs */
4973 while (i != rx_ring->next_to_alloc) {
4974 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4975
4976 /* Invalidate cache lines that may have been written to by
4977 * device so that we avoid corrupting memory.
4978 */
4979 dma_sync_single_range_for_cpu(rx_ring->dev,
4980 buffer_info->dma,
4981 buffer_info->page_offset,
4982 igb_rx_bufsz(rx_ring),
4983 DMA_FROM_DEVICE);
4984
4985 /* free resources associated with mapping */
4986 dma_unmap_page_attrs(rx_ring->dev,
4987 buffer_info->dma,
4988 igb_rx_pg_size(rx_ring),
4989 DMA_FROM_DEVICE,
4990 IGB_RX_DMA_ATTR);
4991 __page_frag_cache_drain(buffer_info->page,
4992 buffer_info->pagecnt_bias);
4993
4994 i++;
4995 if (i == rx_ring->count)
4996 i = 0;
4997 }
4998
4999 rx_ring->next_to_alloc = 0;
5000 rx_ring->next_to_clean = 0;
5001 rx_ring->next_to_use = 0;
5002}
5003
5004/**
5005 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
5006 * @adapter: board private structure
5007 **/
5008static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
5009{
5010 int i;
5011
5012 for (i = 0; i < adapter->num_rx_queues; i++)
5013 if (adapter->rx_ring[i])
5014 igb_clean_rx_ring(adapter->rx_ring[i]);
5015}
5016
5017/**
5018 * igb_set_mac - Change the Ethernet Address of the NIC
5019 * @netdev: network interface device structure
5020 * @p: pointer to an address structure
5021 *
5022 * Returns 0 on success, negative on failure
5023 **/
5024static int igb_set_mac(struct net_device *netdev, void *p)
5025{
5026 struct igb_adapter *adapter = netdev_priv(netdev);
5027 struct e1000_hw *hw = &adapter->hw;
5028 struct sockaddr *addr = p;
5029
5030 if (!is_valid_ether_addr(addr->sa_data))
5031 return -EADDRNOTAVAIL;
5032
5033 eth_hw_addr_set(netdev, addr->sa_data);
5034 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5035
5036 /* set the correct pool for the new PF MAC address in entry 0 */
5037 igb_set_default_mac_filter(adapter);
5038
5039 return 0;
5040}
5041
5042/**
5043 * igb_write_mc_addr_list - write multicast addresses to MTA
5044 * @netdev: network interface device structure
5045 *
5046 * Writes multicast address list to the MTA hash table.
5047 * Returns: -ENOMEM on failure
5048 * 0 on no addresses written
5049 * X on writing X addresses to MTA
5050 **/
5051static int igb_write_mc_addr_list(struct net_device *netdev)
5052{
5053 struct igb_adapter *adapter = netdev_priv(netdev);
5054 struct e1000_hw *hw = &adapter->hw;
5055 struct netdev_hw_addr *ha;
5056 u8 *mta_list;
5057 int i;
5058
5059 if (netdev_mc_empty(netdev)) {
5060 /* nothing to program, so clear mc list */
5061 igb_update_mc_addr_list(hw, NULL, 0);
5062 igb_restore_vf_multicasts(adapter);
5063 return 0;
5064 }
5065
5066 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5067 if (!mta_list)
5068 return -ENOMEM;
5069
5070 /* The shared function expects a packed array of only addresses. */
5071 i = 0;
5072 netdev_for_each_mc_addr(ha, netdev)
5073 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5074
5075 igb_update_mc_addr_list(hw, mta_list, i);
5076 kfree(mta_list);
5077
5078 return netdev_mc_count(netdev);
5079}
5080
5081static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5082{
5083 struct e1000_hw *hw = &adapter->hw;
5084 u32 i, pf_id;
5085
5086 switch (hw->mac.type) {
5087 case e1000_i210:
5088 case e1000_i211:
5089 case e1000_i350:
5090 /* VLAN filtering needed for VLAN prio filter */
5091 if (adapter->netdev->features & NETIF_F_NTUPLE)
5092 break;
5093 fallthrough;
5094 case e1000_82576:
5095 case e1000_82580:
5096 case e1000_i354:
5097 /* VLAN filtering needed for pool filtering */
5098 if (adapter->vfs_allocated_count)
5099 break;
5100 fallthrough;
5101 default:
5102 return 1;
5103 }
5104
5105 /* We are already in VLAN promisc, nothing to do */
5106 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5107 return 0;
5108
5109 if (!adapter->vfs_allocated_count)
5110 goto set_vfta;
5111
5112 /* Add PF to all active pools */
5113 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5114
5115 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5116 u32 vlvf = rd32(E1000_VLVF(i));
5117
5118 vlvf |= BIT(pf_id);
5119 wr32(E1000_VLVF(i), vlvf);
5120 }
5121
5122set_vfta:
5123 /* Set all bits in the VLAN filter table array */
5124 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5125 hw->mac.ops.write_vfta(hw, i, ~0U);
5126
5127 /* Set flag so we don't redo unnecessary work */
5128 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5129
5130 return 0;
5131}
5132
5133#define VFTA_BLOCK_SIZE 8
5134static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5135{
5136 struct e1000_hw *hw = &adapter->hw;
5137 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5138 u32 vid_start = vfta_offset * 32;
5139 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5140 u32 i, vid, word, bits, pf_id;
5141
5142 /* guarantee that we don't scrub out management VLAN */
5143 vid = adapter->mng_vlan_id;
5144 if (vid >= vid_start && vid < vid_end)
5145 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5146
5147 if (!adapter->vfs_allocated_count)
5148 goto set_vfta;
5149
5150 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5151
5152 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5153 u32 vlvf = rd32(E1000_VLVF(i));
5154
5155 /* pull VLAN ID from VLVF */
5156 vid = vlvf & VLAN_VID_MASK;
5157
5158 /* only concern ourselves with a certain range */
5159 if (vid < vid_start || vid >= vid_end)
5160 continue;
5161
5162 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5163 /* record VLAN ID in VFTA */
5164 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5165
5166 /* if PF is part of this then continue */
5167 if (test_bit(vid, adapter->active_vlans))
5168 continue;
5169 }
5170
5171 /* remove PF from the pool */
5172 bits = ~BIT(pf_id);
5173 bits &= rd32(E1000_VLVF(i));
5174 wr32(E1000_VLVF(i), bits);
5175 }
5176
5177set_vfta:
5178 /* extract values from active_vlans and write back to VFTA */
5179 for (i = VFTA_BLOCK_SIZE; i--;) {
5180 vid = (vfta_offset + i) * 32;
5181 word = vid / BITS_PER_LONG;
5182 bits = vid % BITS_PER_LONG;
5183
5184 vfta[i] |= adapter->active_vlans[word] >> bits;
5185
5186 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5187 }
5188}
5189
5190static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5191{
5192 u32 i;
5193
5194 /* We are not in VLAN promisc, nothing to do */
5195 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5196 return;
5197
5198 /* Set flag so we don't redo unnecessary work */
5199 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5200
5201 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5202 igb_scrub_vfta(adapter, i);
5203}
5204
5205/**
5206 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5207 * @netdev: network interface device structure
5208 *
5209 * The set_rx_mode entry point is called whenever the unicast or multicast
5210 * address lists or the network interface flags are updated. This routine is
5211 * responsible for configuring the hardware for proper unicast, multicast,
5212 * promiscuous mode, and all-multi behavior.
5213 **/
5214static void igb_set_rx_mode(struct net_device *netdev)
5215{
5216 struct igb_adapter *adapter = netdev_priv(netdev);
5217 struct e1000_hw *hw = &adapter->hw;
5218 unsigned int vfn = adapter->vfs_allocated_count;
5219 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5220 int count;
5221
5222 /* Check for Promiscuous and All Multicast modes */
5223 if (netdev->flags & IFF_PROMISC) {
5224 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5225 vmolr |= E1000_VMOLR_MPME;
5226
5227 /* enable use of UTA filter to force packets to default pool */
5228 if (hw->mac.type == e1000_82576)
5229 vmolr |= E1000_VMOLR_ROPE;
5230 } else {
5231 if (netdev->flags & IFF_ALLMULTI) {
5232 rctl |= E1000_RCTL_MPE;
5233 vmolr |= E1000_VMOLR_MPME;
5234 } else {
5235 /* Write addresses to the MTA, if the attempt fails
5236 * then we should just turn on promiscuous mode so
5237 * that we can at least receive multicast traffic
5238 */
5239 count = igb_write_mc_addr_list(netdev);
5240 if (count < 0) {
5241 rctl |= E1000_RCTL_MPE;
5242 vmolr |= E1000_VMOLR_MPME;
5243 } else if (count) {
5244 vmolr |= E1000_VMOLR_ROMPE;
5245 }
5246 }
5247 }
5248
5249 /* Write addresses to available RAR registers, if there is not
5250 * sufficient space to store all the addresses then enable
5251 * unicast promiscuous mode
5252 */
5253 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5254 rctl |= E1000_RCTL_UPE;
5255 vmolr |= E1000_VMOLR_ROPE;
5256 }
5257
5258 /* enable VLAN filtering by default */
5259 rctl |= E1000_RCTL_VFE;
5260
5261 /* disable VLAN filtering for modes that require it */
5262 if ((netdev->flags & IFF_PROMISC) ||
5263 (netdev->features & NETIF_F_RXALL)) {
5264 /* if we fail to set all rules then just clear VFE */
5265 if (igb_vlan_promisc_enable(adapter))
5266 rctl &= ~E1000_RCTL_VFE;
5267 } else {
5268 igb_vlan_promisc_disable(adapter);
5269 }
5270
5271 /* update state of unicast, multicast, and VLAN filtering modes */
5272 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5273 E1000_RCTL_VFE);
5274 wr32(E1000_RCTL, rctl);
5275
5276#if (PAGE_SIZE < 8192)
5277 if (!adapter->vfs_allocated_count) {
5278 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5279 rlpml = IGB_MAX_FRAME_BUILD_SKB;
5280 }
5281#endif
5282 wr32(E1000_RLPML, rlpml);
5283
5284 /* In order to support SR-IOV and eventually VMDq it is necessary to set
5285 * the VMOLR to enable the appropriate modes. Without this workaround
5286 * we will have issues with VLAN tag stripping not being done for frames
5287 * that are only arriving because we are the default pool
5288 */
5289 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5290 return;
5291
5292 /* set UTA to appropriate mode */
5293 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5294
5295 vmolr |= rd32(E1000_VMOLR(vfn)) &
5296 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5297
5298 /* enable Rx jumbo frames, restrict as needed to support build_skb */
5299 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5300#if (PAGE_SIZE < 8192)
5301 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5302 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5303 else
5304#endif
5305 vmolr |= MAX_JUMBO_FRAME_SIZE;
5306 vmolr |= E1000_VMOLR_LPE;
5307
5308 wr32(E1000_VMOLR(vfn), vmolr);
5309
5310 igb_restore_vf_multicasts(adapter);
5311}
5312
5313static void igb_check_wvbr(struct igb_adapter *adapter)
5314{
5315 struct e1000_hw *hw = &adapter->hw;
5316 u32 wvbr = 0;
5317
5318 switch (hw->mac.type) {
5319 case e1000_82576:
5320 case e1000_i350:
5321 wvbr = rd32(E1000_WVBR);
5322 if (!wvbr)
5323 return;
5324 break;
5325 default:
5326 break;
5327 }
5328
5329 adapter->wvbr |= wvbr;
5330}
5331
5332#define IGB_STAGGERED_QUEUE_OFFSET 8
5333
5334static void igb_spoof_check(struct igb_adapter *adapter)
5335{
5336 int j;
5337
5338 if (!adapter->wvbr)
5339 return;
5340
5341 for (j = 0; j < adapter->vfs_allocated_count; j++) {
5342 if (adapter->wvbr & BIT(j) ||
5343 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5344 dev_warn(&adapter->pdev->dev,
5345 "Spoof event(s) detected on VF %d\n", j);
5346 adapter->wvbr &=
5347 ~(BIT(j) |
5348 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5349 }
5350 }
5351}
5352
5353/* Need to wait a few seconds after link up to get diagnostic information from
5354 * the phy
5355 */
5356static void igb_update_phy_info(struct timer_list *t)
5357{
5358 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5359 igb_get_phy_info(&adapter->hw);
5360}
5361
5362/**
5363 * igb_has_link - check shared code for link and determine up/down
5364 * @adapter: pointer to driver private info
5365 **/
5366bool igb_has_link(struct igb_adapter *adapter)
5367{
5368 struct e1000_hw *hw = &adapter->hw;
5369 bool link_active = false;
5370
5371 /* get_link_status is set on LSC (link status) interrupt or
5372 * rx sequence error interrupt. get_link_status will stay
5373 * false until the e1000_check_for_link establishes link
5374 * for copper adapters ONLY
5375 */
5376 switch (hw->phy.media_type) {
5377 case e1000_media_type_copper:
5378 if (!hw->mac.get_link_status)
5379 return true;
5380 fallthrough;
5381 case e1000_media_type_internal_serdes:
5382 hw->mac.ops.check_for_link(hw);
5383 link_active = !hw->mac.get_link_status;
5384 break;
5385 default:
5386 case e1000_media_type_unknown:
5387 break;
5388 }
5389
5390 if (((hw->mac.type == e1000_i210) ||
5391 (hw->mac.type == e1000_i211)) &&
5392 (hw->phy.id == I210_I_PHY_ID)) {
5393 if (!netif_carrier_ok(adapter->netdev)) {
5394 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5395 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5396 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5397 adapter->link_check_timeout = jiffies;
5398 }
5399 }
5400
5401 return link_active;
5402}
5403
5404static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5405{
5406 bool ret = false;
5407 u32 ctrl_ext, thstat;
5408
5409 /* check for thermal sensor event on i350 copper only */
5410 if (hw->mac.type == e1000_i350) {
5411 thstat = rd32(E1000_THSTAT);
5412 ctrl_ext = rd32(E1000_CTRL_EXT);
5413
5414 if ((hw->phy.media_type == e1000_media_type_copper) &&
5415 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5416 ret = !!(thstat & event);
5417 }
5418
5419 return ret;
5420}
5421
5422/**
5423 * igb_check_lvmmc - check for malformed packets received
5424 * and indicated in LVMMC register
5425 * @adapter: pointer to adapter
5426 **/
5427static void igb_check_lvmmc(struct igb_adapter *adapter)
5428{
5429 struct e1000_hw *hw = &adapter->hw;
5430 u32 lvmmc;
5431
5432 lvmmc = rd32(E1000_LVMMC);
5433 if (lvmmc) {
5434 if (unlikely(net_ratelimit())) {
5435 netdev_warn(adapter->netdev,
5436 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5437 lvmmc);
5438 }
5439 }
5440}
5441
5442/**
5443 * igb_watchdog - Timer Call-back
5444 * @t: pointer to timer_list containing our private info pointer
5445 **/
5446static void igb_watchdog(struct timer_list *t)
5447{
5448 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5449 /* Do the rest outside of interrupt context */
5450 schedule_work(&adapter->watchdog_task);
5451}
5452
5453static void igb_watchdog_task(struct work_struct *work)
5454{
5455 struct igb_adapter *adapter = container_of(work,
5456 struct igb_adapter,
5457 watchdog_task);
5458 struct e1000_hw *hw = &adapter->hw;
5459 struct e1000_phy_info *phy = &hw->phy;
5460 struct net_device *netdev = adapter->netdev;
5461 u32 link;
5462 int i;
5463 u32 connsw;
5464 u16 phy_data, retry_count = 20;
5465
5466 link = igb_has_link(adapter);
5467
5468 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5469 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5470 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5471 else
5472 link = false;
5473 }
5474
5475 /* Force link down if we have fiber to swap to */
5476 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5477 if (hw->phy.media_type == e1000_media_type_copper) {
5478 connsw = rd32(E1000_CONNSW);
5479 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5480 link = 0;
5481 }
5482 }
5483 if (link) {
5484 /* Perform a reset if the media type changed. */
5485 if (hw->dev_spec._82575.media_changed) {
5486 hw->dev_spec._82575.media_changed = false;
5487 adapter->flags |= IGB_FLAG_MEDIA_RESET;
5488 igb_reset(adapter);
5489 }
5490 /* Cancel scheduled suspend requests. */
5491 pm_runtime_resume(netdev->dev.parent);
5492
5493 if (!netif_carrier_ok(netdev)) {
5494 u32 ctrl;
5495
5496 hw->mac.ops.get_speed_and_duplex(hw,
5497 &adapter->link_speed,
5498 &adapter->link_duplex);
5499
5500 ctrl = rd32(E1000_CTRL);
5501 /* Links status message must follow this format */
5502 netdev_info(netdev,
5503 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5504 netdev->name,
5505 adapter->link_speed,
5506 adapter->link_duplex == FULL_DUPLEX ?
5507 "Full" : "Half",
5508 (ctrl & E1000_CTRL_TFCE) &&
5509 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5510 (ctrl & E1000_CTRL_RFCE) ? "RX" :
5511 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
5512
5513 /* disable EEE if enabled */
5514 if ((adapter->flags & IGB_FLAG_EEE) &&
5515 (adapter->link_duplex == HALF_DUPLEX)) {
5516 dev_info(&adapter->pdev->dev,
5517 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5518 adapter->hw.dev_spec._82575.eee_disable = true;
5519 adapter->flags &= ~IGB_FLAG_EEE;
5520 }
5521
5522 /* check if SmartSpeed worked */
5523 igb_check_downshift(hw);
5524 if (phy->speed_downgraded)
5525 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5526
5527 /* check for thermal sensor event */
5528 if (igb_thermal_sensor_event(hw,
5529 E1000_THSTAT_LINK_THROTTLE))
5530 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5531
5532 /* adjust timeout factor according to speed/duplex */
5533 adapter->tx_timeout_factor = 1;
5534 switch (adapter->link_speed) {
5535 case SPEED_10:
5536 adapter->tx_timeout_factor = 14;
5537 break;
5538 case SPEED_100:
5539 /* maybe add some timeout factor ? */
5540 break;
5541 }
5542
5543 if (adapter->link_speed != SPEED_1000 ||
5544 !hw->phy.ops.read_reg)
5545 goto no_wait;
5546
5547 /* wait for Remote receiver status OK */
5548retry_read_status:
5549 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5550 &phy_data)) {
5551 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5552 retry_count) {
5553 msleep(100);
5554 retry_count--;
5555 goto retry_read_status;
5556 } else if (!retry_count) {
5557 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5558 }
5559 } else {
5560 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5561 }
5562no_wait:
5563 netif_carrier_on(netdev);
5564
5565 igb_ping_all_vfs(adapter);
5566 igb_check_vf_rate_limit(adapter);
5567
5568 /* link state has changed, schedule phy info update */
5569 if (!test_bit(__IGB_DOWN, &adapter->state))
5570 mod_timer(&adapter->phy_info_timer,
5571 round_jiffies(jiffies + 2 * HZ));
5572 }
5573 } else {
5574 if (netif_carrier_ok(netdev)) {
5575 adapter->link_speed = 0;
5576 adapter->link_duplex = 0;
5577
5578 /* check for thermal sensor event */
5579 if (igb_thermal_sensor_event(hw,
5580 E1000_THSTAT_PWR_DOWN)) {
5581 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5582 }
5583
5584 /* Links status message must follow this format */
5585 netdev_info(netdev, "igb: %s NIC Link is Down\n",
5586 netdev->name);
5587 netif_carrier_off(netdev);
5588
5589 igb_ping_all_vfs(adapter);
5590
5591 /* link state has changed, schedule phy info update */
5592 if (!test_bit(__IGB_DOWN, &adapter->state))
5593 mod_timer(&adapter->phy_info_timer,
5594 round_jiffies(jiffies + 2 * HZ));
5595
5596 /* link is down, time to check for alternate media */
5597 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5598 igb_check_swap_media(adapter);
5599 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5600 schedule_work(&adapter->reset_task);
5601 /* return immediately */
5602 return;
5603 }
5604 }
5605 pm_schedule_suspend(netdev->dev.parent,
5606 MSEC_PER_SEC * 5);
5607
5608 /* also check for alternate media here */
5609 } else if (!netif_carrier_ok(netdev) &&
5610 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5611 igb_check_swap_media(adapter);
5612 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5613 schedule_work(&adapter->reset_task);
5614 /* return immediately */
5615 return;
5616 }
5617 }
5618 }
5619
5620 spin_lock(&adapter->stats64_lock);
5621 igb_update_stats(adapter);
5622 spin_unlock(&adapter->stats64_lock);
5623
5624 for (i = 0; i < adapter->num_tx_queues; i++) {
5625 struct igb_ring *tx_ring = adapter->tx_ring[i];
5626 if (!netif_carrier_ok(netdev)) {
5627 /* We've lost link, so the controller stops DMA,
5628 * but we've got queued Tx work that's never going
5629 * to get done, so reset controller to flush Tx.
5630 * (Do the reset outside of interrupt context).
5631 */
5632 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5633 adapter->tx_timeout_count++;
5634 schedule_work(&adapter->reset_task);
5635 /* return immediately since reset is imminent */
5636 return;
5637 }
5638 }
5639
5640 /* Force detection of hung controller every watchdog period */
5641 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5642 }
5643
5644 /* Cause software interrupt to ensure Rx ring is cleaned */
5645 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5646 u32 eics = 0;
5647
5648 for (i = 0; i < adapter->num_q_vectors; i++)
5649 eics |= adapter->q_vector[i]->eims_value;
5650 wr32(E1000_EICS, eics);
5651 } else {
5652 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5653 }
5654
5655 igb_spoof_check(adapter);
5656 igb_ptp_rx_hang(adapter);
5657 igb_ptp_tx_hang(adapter);
5658
5659 /* Check LVMMC register on i350/i354 only */
5660 if ((adapter->hw.mac.type == e1000_i350) ||
5661 (adapter->hw.mac.type == e1000_i354))
5662 igb_check_lvmmc(adapter);
5663
5664 /* Reset the timer */
5665 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5666 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5667 mod_timer(&adapter->watchdog_timer,
5668 round_jiffies(jiffies + HZ));
5669 else
5670 mod_timer(&adapter->watchdog_timer,
5671 round_jiffies(jiffies + 2 * HZ));
5672 }
5673}
5674
5675enum latency_range {
5676 lowest_latency = 0,
5677 low_latency = 1,
5678 bulk_latency = 2,
5679 latency_invalid = 255
5680};
5681
5682/**
5683 * igb_update_ring_itr - update the dynamic ITR value based on packet size
5684 * @q_vector: pointer to q_vector
5685 *
5686 * Stores a new ITR value based on strictly on packet size. This
5687 * algorithm is less sophisticated than that used in igb_update_itr,
5688 * due to the difficulty of synchronizing statistics across multiple
5689 * receive rings. The divisors and thresholds used by this function
5690 * were determined based on theoretical maximum wire speed and testing
5691 * data, in order to minimize response time while increasing bulk
5692 * throughput.
5693 * This functionality is controlled by ethtool's coalescing settings.
5694 * NOTE: This function is called only when operating in a multiqueue
5695 * receive environment.
5696 **/
5697static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5698{
5699 int new_val = q_vector->itr_val;
5700 int avg_wire_size = 0;
5701 struct igb_adapter *adapter = q_vector->adapter;
5702 unsigned int packets;
5703
5704 /* For non-gigabit speeds, just fix the interrupt rate at 4000
5705 * ints/sec - ITR timer value of 120 ticks.
5706 */
5707 if (adapter->link_speed != SPEED_1000) {
5708 new_val = IGB_4K_ITR;
5709 goto set_itr_val;
5710 }
5711
5712 packets = q_vector->rx.total_packets;
5713 if (packets)
5714 avg_wire_size = q_vector->rx.total_bytes / packets;
5715
5716 packets = q_vector->tx.total_packets;
5717 if (packets)
5718 avg_wire_size = max_t(u32, avg_wire_size,
5719 q_vector->tx.total_bytes / packets);
5720
5721 /* if avg_wire_size isn't set no work was done */
5722 if (!avg_wire_size)
5723 goto clear_counts;
5724
5725 /* Add 24 bytes to size to account for CRC, preamble, and gap */
5726 avg_wire_size += 24;
5727
5728 /* Don't starve jumbo frames */
5729 avg_wire_size = min(avg_wire_size, 3000);
5730
5731 /* Give a little boost to mid-size frames */
5732 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5733 new_val = avg_wire_size / 3;
5734 else
5735 new_val = avg_wire_size / 2;
5736
5737 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5738 if (new_val < IGB_20K_ITR &&
5739 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5740 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5741 new_val = IGB_20K_ITR;
5742
5743set_itr_val:
5744 if (new_val != q_vector->itr_val) {
5745 q_vector->itr_val = new_val;
5746 q_vector->set_itr = 1;
5747 }
5748clear_counts:
5749 q_vector->rx.total_bytes = 0;
5750 q_vector->rx.total_packets = 0;
5751 q_vector->tx.total_bytes = 0;
5752 q_vector->tx.total_packets = 0;
5753}
5754
5755/**
5756 * igb_update_itr - update the dynamic ITR value based on statistics
5757 * @q_vector: pointer to q_vector
5758 * @ring_container: ring info to update the itr for
5759 *
5760 * Stores a new ITR value based on packets and byte
5761 * counts during the last interrupt. The advantage of per interrupt
5762 * computation is faster updates and more accurate ITR for the current
5763 * traffic pattern. Constants in this function were computed
5764 * based on theoretical maximum wire speed and thresholds were set based
5765 * on testing data as well as attempting to minimize response time
5766 * while increasing bulk throughput.
5767 * This functionality is controlled by ethtool's coalescing settings.
5768 * NOTE: These calculations are only valid when operating in a single-
5769 * queue environment.
5770 **/
5771static void igb_update_itr(struct igb_q_vector *q_vector,
5772 struct igb_ring_container *ring_container)
5773{
5774 unsigned int packets = ring_container->total_packets;
5775 unsigned int bytes = ring_container->total_bytes;
5776 u8 itrval = ring_container->itr;
5777
5778 /* no packets, exit with status unchanged */
5779 if (packets == 0)
5780 return;
5781
5782 switch (itrval) {
5783 case lowest_latency:
5784 /* handle TSO and jumbo frames */
5785 if (bytes/packets > 8000)
5786 itrval = bulk_latency;
5787 else if ((packets < 5) && (bytes > 512))
5788 itrval = low_latency;
5789 break;
5790 case low_latency: /* 50 usec aka 20000 ints/s */
5791 if (bytes > 10000) {
5792 /* this if handles the TSO accounting */
5793 if (bytes/packets > 8000)
5794 itrval = bulk_latency;
5795 else if ((packets < 10) || ((bytes/packets) > 1200))
5796 itrval = bulk_latency;
5797 else if ((packets > 35))
5798 itrval = lowest_latency;
5799 } else if (bytes/packets > 2000) {
5800 itrval = bulk_latency;
5801 } else if (packets <= 2 && bytes < 512) {
5802 itrval = lowest_latency;
5803 }
5804 break;
5805 case bulk_latency: /* 250 usec aka 4000 ints/s */
5806 if (bytes > 25000) {
5807 if (packets > 35)
5808 itrval = low_latency;
5809 } else if (bytes < 1500) {
5810 itrval = low_latency;
5811 }
5812 break;
5813 }
5814
5815 /* clear work counters since we have the values we need */
5816 ring_container->total_bytes = 0;
5817 ring_container->total_packets = 0;
5818
5819 /* write updated itr to ring container */
5820 ring_container->itr = itrval;
5821}
5822
5823static void igb_set_itr(struct igb_q_vector *q_vector)
5824{
5825 struct igb_adapter *adapter = q_vector->adapter;
5826 u32 new_itr = q_vector->itr_val;
5827 u8 current_itr = 0;
5828
5829 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5830 if (adapter->link_speed != SPEED_1000) {
5831 current_itr = 0;
5832 new_itr = IGB_4K_ITR;
5833 goto set_itr_now;
5834 }
5835
5836 igb_update_itr(q_vector, &q_vector->tx);
5837 igb_update_itr(q_vector, &q_vector->rx);
5838
5839 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5840
5841 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5842 if (current_itr == lowest_latency &&
5843 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5844 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5845 current_itr = low_latency;
5846
5847 switch (current_itr) {
5848 /* counts and packets in update_itr are dependent on these numbers */
5849 case lowest_latency:
5850 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5851 break;
5852 case low_latency:
5853 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5854 break;
5855 case bulk_latency:
5856 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
5857 break;
5858 default:
5859 break;
5860 }
5861
5862set_itr_now:
5863 if (new_itr != q_vector->itr_val) {
5864 /* this attempts to bias the interrupt rate towards Bulk
5865 * by adding intermediate steps when interrupt rate is
5866 * increasing
5867 */
5868 new_itr = new_itr > q_vector->itr_val ?
5869 max((new_itr * q_vector->itr_val) /
5870 (new_itr + (q_vector->itr_val >> 2)),
5871 new_itr) : new_itr;
5872 /* Don't write the value here; it resets the adapter's
5873 * internal timer, and causes us to delay far longer than
5874 * we should between interrupts. Instead, we write the ITR
5875 * value at the beginning of the next interrupt so the timing
5876 * ends up being correct.
5877 */
5878 q_vector->itr_val = new_itr;
5879 q_vector->set_itr = 1;
5880 }
5881}
5882
5883static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5884 struct igb_tx_buffer *first,
5885 u32 vlan_macip_lens, u32 type_tucmd,
5886 u32 mss_l4len_idx)
5887{
5888 struct e1000_adv_tx_context_desc *context_desc;
5889 u16 i = tx_ring->next_to_use;
5890 struct timespec64 ts;
5891
5892 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5893
5894 i++;
5895 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5896
5897 /* set bits to identify this as an advanced context descriptor */
5898 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5899
5900 /* For 82575, context index must be unique per ring. */
5901 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5902 mss_l4len_idx |= tx_ring->reg_idx << 4;
5903
5904 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5905 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5906 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5907
5908 /* We assume there is always a valid tx time available. Invalid times
5909 * should have been handled by the upper layers.
5910 */
5911 if (tx_ring->launchtime_enable) {
5912 ts = ktime_to_timespec64(first->skb->tstamp);
5913 skb_txtime_consumed(first->skb);
5914 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5915 } else {
5916 context_desc->seqnum_seed = 0;
5917 }
5918}
5919
5920static int igb_tso(struct igb_ring *tx_ring,
5921 struct igb_tx_buffer *first,
5922 u8 *hdr_len)
5923{
5924 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5925 struct sk_buff *skb = first->skb;
5926 union {
5927 struct iphdr *v4;
5928 struct ipv6hdr *v6;
5929 unsigned char *hdr;
5930 } ip;
5931 union {
5932 struct tcphdr *tcp;
5933 struct udphdr *udp;
5934 unsigned char *hdr;
5935 } l4;
5936 u32 paylen, l4_offset;
5937 int err;
5938
5939 if (skb->ip_summed != CHECKSUM_PARTIAL)
5940 return 0;
5941
5942 if (!skb_is_gso(skb))
5943 return 0;
5944
5945 err = skb_cow_head(skb, 0);
5946 if (err < 0)
5947 return err;
5948
5949 ip.hdr = skb_network_header(skb);
5950 l4.hdr = skb_checksum_start(skb);
5951
5952 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5953 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5954 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
5955
5956 /* initialize outer IP header fields */
5957 if (ip.v4->version == 4) {
5958 unsigned char *csum_start = skb_checksum_start(skb);
5959 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5960
5961 /* IP header will have to cancel out any data that
5962 * is not a part of the outer IP header
5963 */
5964 ip.v4->check = csum_fold(csum_partial(trans_start,
5965 csum_start - trans_start,
5966 0));
5967 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5968
5969 ip.v4->tot_len = 0;
5970 first->tx_flags |= IGB_TX_FLAGS_TSO |
5971 IGB_TX_FLAGS_CSUM |
5972 IGB_TX_FLAGS_IPV4;
5973 } else {
5974 ip.v6->payload_len = 0;
5975 first->tx_flags |= IGB_TX_FLAGS_TSO |
5976 IGB_TX_FLAGS_CSUM;
5977 }
5978
5979 /* determine offset of inner transport header */
5980 l4_offset = l4.hdr - skb->data;
5981
5982 /* remove payload length from inner checksum */
5983 paylen = skb->len - l4_offset;
5984 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
5985 /* compute length of segmentation header */
5986 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5987 csum_replace_by_diff(&l4.tcp->check,
5988 (__force __wsum)htonl(paylen));
5989 } else {
5990 /* compute length of segmentation header */
5991 *hdr_len = sizeof(*l4.udp) + l4_offset;
5992 csum_replace_by_diff(&l4.udp->check,
5993 (__force __wsum)htonl(paylen));
5994 }
5995
5996 /* update gso size and bytecount with header size */
5997 first->gso_segs = skb_shinfo(skb)->gso_segs;
5998 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5999
6000 /* MSS L4LEN IDX */
6001 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
6002 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
6003
6004 /* VLAN MACLEN IPLEN */
6005 vlan_macip_lens = l4.hdr - ip.hdr;
6006 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
6007 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6008
6009 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
6010 type_tucmd, mss_l4len_idx);
6011
6012 return 1;
6013}
6014
6015static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
6016{
6017 struct sk_buff *skb = first->skb;
6018 u32 vlan_macip_lens = 0;
6019 u32 type_tucmd = 0;
6020
6021 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6022csum_failed:
6023 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
6024 !tx_ring->launchtime_enable)
6025 return;
6026 goto no_csum;
6027 }
6028
6029 switch (skb->csum_offset) {
6030 case offsetof(struct tcphdr, check):
6031 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
6032 fallthrough;
6033 case offsetof(struct udphdr, check):
6034 break;
6035 case offsetof(struct sctphdr, checksum):
6036 /* validate that this is actually an SCTP request */
6037 if (skb_csum_is_sctp(skb)) {
6038 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6039 break;
6040 }
6041 fallthrough;
6042 default:
6043 skb_checksum_help(skb);
6044 goto csum_failed;
6045 }
6046
6047 /* update TX checksum flag */
6048 first->tx_flags |= IGB_TX_FLAGS_CSUM;
6049 vlan_macip_lens = skb_checksum_start_offset(skb) -
6050 skb_network_offset(skb);
6051no_csum:
6052 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6053 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6054
6055 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6056}
6057
6058#define IGB_SET_FLAG(_input, _flag, _result) \
6059 ((_flag <= _result) ? \
6060 ((u32)(_input & _flag) * (_result / _flag)) : \
6061 ((u32)(_input & _flag) / (_flag / _result)))
6062
6063static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6064{
6065 /* set type for advanced descriptor with frame checksum insertion */
6066 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6067 E1000_ADVTXD_DCMD_DEXT |
6068 E1000_ADVTXD_DCMD_IFCS;
6069
6070 /* set HW vlan bit if vlan is present */
6071 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6072 (E1000_ADVTXD_DCMD_VLE));
6073
6074 /* set segmentation bits for TSO */
6075 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6076 (E1000_ADVTXD_DCMD_TSE));
6077
6078 /* set timestamp bit if present */
6079 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6080 (E1000_ADVTXD_MAC_TSTAMP));
6081
6082 /* insert frame checksum */
6083 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6084
6085 return cmd_type;
6086}
6087
6088static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6089 union e1000_adv_tx_desc *tx_desc,
6090 u32 tx_flags, unsigned int paylen)
6091{
6092 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6093
6094 /* 82575 requires a unique index per ring */
6095 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6096 olinfo_status |= tx_ring->reg_idx << 4;
6097
6098 /* insert L4 checksum */
6099 olinfo_status |= IGB_SET_FLAG(tx_flags,
6100 IGB_TX_FLAGS_CSUM,
6101 (E1000_TXD_POPTS_TXSM << 8));
6102
6103 /* insert IPv4 checksum */
6104 olinfo_status |= IGB_SET_FLAG(tx_flags,
6105 IGB_TX_FLAGS_IPV4,
6106 (E1000_TXD_POPTS_IXSM << 8));
6107
6108 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6109}
6110
6111static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6112{
6113 struct net_device *netdev = tx_ring->netdev;
6114
6115 netif_stop_subqueue(netdev, tx_ring->queue_index);
6116
6117 /* Herbert's original patch had:
6118 * smp_mb__after_netif_stop_queue();
6119 * but since that doesn't exist yet, just open code it.
6120 */
6121 smp_mb();
6122
6123 /* We need to check again in a case another CPU has just
6124 * made room available.
6125 */
6126 if (igb_desc_unused(tx_ring) < size)
6127 return -EBUSY;
6128
6129 /* A reprieve! */
6130 netif_wake_subqueue(netdev, tx_ring->queue_index);
6131
6132 u64_stats_update_begin(&tx_ring->tx_syncp2);
6133 tx_ring->tx_stats.restart_queue2++;
6134 u64_stats_update_end(&tx_ring->tx_syncp2);
6135
6136 return 0;
6137}
6138
6139static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6140{
6141 if (igb_desc_unused(tx_ring) >= size)
6142 return 0;
6143 return __igb_maybe_stop_tx(tx_ring, size);
6144}
6145
6146static int igb_tx_map(struct igb_ring *tx_ring,
6147 struct igb_tx_buffer *first,
6148 const u8 hdr_len)
6149{
6150 struct sk_buff *skb = first->skb;
6151 struct igb_tx_buffer *tx_buffer;
6152 union e1000_adv_tx_desc *tx_desc;
6153 skb_frag_t *frag;
6154 dma_addr_t dma;
6155 unsigned int data_len, size;
6156 u32 tx_flags = first->tx_flags;
6157 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6158 u16 i = tx_ring->next_to_use;
6159
6160 tx_desc = IGB_TX_DESC(tx_ring, i);
6161
6162 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6163
6164 size = skb_headlen(skb);
6165 data_len = skb->data_len;
6166
6167 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6168
6169 tx_buffer = first;
6170
6171 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6172 if (dma_mapping_error(tx_ring->dev, dma))
6173 goto dma_error;
6174
6175 /* record length, and DMA address */
6176 dma_unmap_len_set(tx_buffer, len, size);
6177 dma_unmap_addr_set(tx_buffer, dma, dma);
6178
6179 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6180
6181 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6182 tx_desc->read.cmd_type_len =
6183 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6184
6185 i++;
6186 tx_desc++;
6187 if (i == tx_ring->count) {
6188 tx_desc = IGB_TX_DESC(tx_ring, 0);
6189 i = 0;
6190 }
6191 tx_desc->read.olinfo_status = 0;
6192
6193 dma += IGB_MAX_DATA_PER_TXD;
6194 size -= IGB_MAX_DATA_PER_TXD;
6195
6196 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6197 }
6198
6199 if (likely(!data_len))
6200 break;
6201
6202 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6203
6204 i++;
6205 tx_desc++;
6206 if (i == tx_ring->count) {
6207 tx_desc = IGB_TX_DESC(tx_ring, 0);
6208 i = 0;
6209 }
6210 tx_desc->read.olinfo_status = 0;
6211
6212 size = skb_frag_size(frag);
6213 data_len -= size;
6214
6215 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6216 size, DMA_TO_DEVICE);
6217
6218 tx_buffer = &tx_ring->tx_buffer_info[i];
6219 }
6220
6221 /* write last descriptor with RS and EOP bits */
6222 cmd_type |= size | IGB_TXD_DCMD;
6223 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6224
6225 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6226
6227 /* set the timestamp */
6228 first->time_stamp = jiffies;
6229
6230 skb_tx_timestamp(skb);
6231
6232 /* Force memory writes to complete before letting h/w know there
6233 * are new descriptors to fetch. (Only applicable for weak-ordered
6234 * memory model archs, such as IA-64).
6235 *
6236 * We also need this memory barrier to make certain all of the
6237 * status bits have been updated before next_to_watch is written.
6238 */
6239 dma_wmb();
6240
6241 /* set next_to_watch value indicating a packet is present */
6242 first->next_to_watch = tx_desc;
6243
6244 i++;
6245 if (i == tx_ring->count)
6246 i = 0;
6247
6248 tx_ring->next_to_use = i;
6249
6250 /* Make sure there is space in the ring for the next send. */
6251 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6252
6253 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6254 writel(i, tx_ring->tail);
6255 }
6256 return 0;
6257
6258dma_error:
6259 dev_err(tx_ring->dev, "TX DMA map failed\n");
6260 tx_buffer = &tx_ring->tx_buffer_info[i];
6261
6262 /* clear dma mappings for failed tx_buffer_info map */
6263 while (tx_buffer != first) {
6264 if (dma_unmap_len(tx_buffer, len))
6265 dma_unmap_page(tx_ring->dev,
6266 dma_unmap_addr(tx_buffer, dma),
6267 dma_unmap_len(tx_buffer, len),
6268 DMA_TO_DEVICE);
6269 dma_unmap_len_set(tx_buffer, len, 0);
6270
6271 if (i-- == 0)
6272 i += tx_ring->count;
6273 tx_buffer = &tx_ring->tx_buffer_info[i];
6274 }
6275
6276 if (dma_unmap_len(tx_buffer, len))
6277 dma_unmap_single(tx_ring->dev,
6278 dma_unmap_addr(tx_buffer, dma),
6279 dma_unmap_len(tx_buffer, len),
6280 DMA_TO_DEVICE);
6281 dma_unmap_len_set(tx_buffer, len, 0);
6282
6283 dev_kfree_skb_any(tx_buffer->skb);
6284 tx_buffer->skb = NULL;
6285
6286 tx_ring->next_to_use = i;
6287
6288 return -1;
6289}
6290
6291int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6292 struct igb_ring *tx_ring,
6293 struct xdp_frame *xdpf)
6294{
6295 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
6296 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
6297 u16 count, i, index = tx_ring->next_to_use;
6298 struct igb_tx_buffer *tx_head = &tx_ring->tx_buffer_info[index];
6299 struct igb_tx_buffer *tx_buffer = tx_head;
6300 union e1000_adv_tx_desc *tx_desc = IGB_TX_DESC(tx_ring, index);
6301 u32 len = xdpf->len, cmd_type, olinfo_status;
6302 void *data = xdpf->data;
6303
6304 count = TXD_USE_COUNT(len);
6305 for (i = 0; i < nr_frags; i++)
6306 count += TXD_USE_COUNT(skb_frag_size(&sinfo->frags[i]));
6307
6308 if (igb_maybe_stop_tx(tx_ring, count + 3))
6309 return IGB_XDP_CONSUMED;
6310
6311 i = 0;
6312 /* record the location of the first descriptor for this packet */
6313 tx_head->bytecount = xdp_get_frame_len(xdpf);
6314 tx_head->type = IGB_TYPE_XDP;
6315 tx_head->gso_segs = 1;
6316 tx_head->xdpf = xdpf;
6317
6318 olinfo_status = tx_head->bytecount << E1000_ADVTXD_PAYLEN_SHIFT;
6319 /* 82575 requires a unique index per ring */
6320 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6321 olinfo_status |= tx_ring->reg_idx << 4;
6322 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6323
6324 for (;;) {
6325 dma_addr_t dma;
6326
6327 dma = dma_map_single(tx_ring->dev, data, len, DMA_TO_DEVICE);
6328 if (dma_mapping_error(tx_ring->dev, dma))
6329 goto unmap;
6330
6331 /* record length, and DMA address */
6332 dma_unmap_len_set(tx_buffer, len, len);
6333 dma_unmap_addr_set(tx_buffer, dma, dma);
6334
6335 /* put descriptor type bits */
6336 cmd_type = E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_DEXT |
6337 E1000_ADVTXD_DCMD_IFCS | len;
6338
6339 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6340 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6341
6342 tx_buffer->protocol = 0;
6343
6344 if (++index == tx_ring->count)
6345 index = 0;
6346
6347 if (i == nr_frags)
6348 break;
6349
6350 tx_buffer = &tx_ring->tx_buffer_info[index];
6351 tx_desc = IGB_TX_DESC(tx_ring, index);
6352 tx_desc->read.olinfo_status = 0;
6353
6354 data = skb_frag_address(&sinfo->frags[i]);
6355 len = skb_frag_size(&sinfo->frags[i]);
6356 i++;
6357 }
6358 tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_TXD_DCMD);
6359
6360 netdev_tx_sent_queue(txring_txq(tx_ring), tx_head->bytecount);
6361 /* set the timestamp */
6362 tx_head->time_stamp = jiffies;
6363
6364 /* Avoid any potential race with xdp_xmit and cleanup */
6365 smp_wmb();
6366
6367 /* set next_to_watch value indicating a packet is present */
6368 tx_head->next_to_watch = tx_desc;
6369 tx_ring->next_to_use = index;
6370
6371 /* Make sure there is space in the ring for the next send. */
6372 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6373
6374 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6375 writel(index, tx_ring->tail);
6376
6377 return IGB_XDP_TX;
6378
6379unmap:
6380 for (;;) {
6381 tx_buffer = &tx_ring->tx_buffer_info[index];
6382 if (dma_unmap_len(tx_buffer, len))
6383 dma_unmap_page(tx_ring->dev,
6384 dma_unmap_addr(tx_buffer, dma),
6385 dma_unmap_len(tx_buffer, len),
6386 DMA_TO_DEVICE);
6387 dma_unmap_len_set(tx_buffer, len, 0);
6388 if (tx_buffer == tx_head)
6389 break;
6390
6391 if (!index)
6392 index += tx_ring->count;
6393 index--;
6394 }
6395
6396 return IGB_XDP_CONSUMED;
6397}
6398
6399netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6400 struct igb_ring *tx_ring)
6401{
6402 struct igb_tx_buffer *first;
6403 int tso;
6404 u32 tx_flags = 0;
6405 unsigned short f;
6406 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6407 __be16 protocol = vlan_get_protocol(skb);
6408 u8 hdr_len = 0;
6409
6410 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6411 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6412 * + 2 desc gap to keep tail from touching head,
6413 * + 1 desc for context descriptor,
6414 * otherwise try next time
6415 */
6416 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6417 count += TXD_USE_COUNT(skb_frag_size(
6418 &skb_shinfo(skb)->frags[f]));
6419
6420 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6421 /* this is a hard error */
6422 return NETDEV_TX_BUSY;
6423 }
6424
6425 /* record the location of the first descriptor for this packet */
6426 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6427 first->type = IGB_TYPE_SKB;
6428 first->skb = skb;
6429 first->bytecount = skb->len;
6430 first->gso_segs = 1;
6431
6432 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6433 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6434
6435 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6436 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6437 &adapter->state)) {
6438 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6439 tx_flags |= IGB_TX_FLAGS_TSTAMP;
6440
6441 adapter->ptp_tx_skb = skb_get(skb);
6442 adapter->ptp_tx_start = jiffies;
6443 if (adapter->hw.mac.type == e1000_82576)
6444 schedule_work(&adapter->ptp_tx_work);
6445 } else {
6446 adapter->tx_hwtstamp_skipped++;
6447 }
6448 }
6449
6450 if (skb_vlan_tag_present(skb)) {
6451 tx_flags |= IGB_TX_FLAGS_VLAN;
6452 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6453 }
6454
6455 /* record initial flags and protocol */
6456 first->tx_flags = tx_flags;
6457 first->protocol = protocol;
6458
6459 tso = igb_tso(tx_ring, first, &hdr_len);
6460 if (tso < 0)
6461 goto out_drop;
6462 else if (!tso)
6463 igb_tx_csum(tx_ring, first);
6464
6465 if (igb_tx_map(tx_ring, first, hdr_len))
6466 goto cleanup_tx_tstamp;
6467
6468 return NETDEV_TX_OK;
6469
6470out_drop:
6471 dev_kfree_skb_any(first->skb);
6472 first->skb = NULL;
6473cleanup_tx_tstamp:
6474 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6475 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6476
6477 dev_kfree_skb_any(adapter->ptp_tx_skb);
6478 adapter->ptp_tx_skb = NULL;
6479 if (adapter->hw.mac.type == e1000_82576)
6480 cancel_work_sync(&adapter->ptp_tx_work);
6481 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6482 }
6483
6484 return NETDEV_TX_OK;
6485}
6486
6487static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6488 struct sk_buff *skb)
6489{
6490 unsigned int r_idx = skb->queue_mapping;
6491
6492 if (r_idx >= adapter->num_tx_queues)
6493 r_idx = r_idx % adapter->num_tx_queues;
6494
6495 return adapter->tx_ring[r_idx];
6496}
6497
6498static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6499 struct net_device *netdev)
6500{
6501 struct igb_adapter *adapter = netdev_priv(netdev);
6502
6503 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6504 * in order to meet this minimum size requirement.
6505 */
6506 if (skb_put_padto(skb, 17))
6507 return NETDEV_TX_OK;
6508
6509 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6510}
6511
6512/**
6513 * igb_tx_timeout - Respond to a Tx Hang
6514 * @netdev: network interface device structure
6515 * @txqueue: number of the Tx queue that hung (unused)
6516 **/
6517static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6518{
6519 struct igb_adapter *adapter = netdev_priv(netdev);
6520 struct e1000_hw *hw = &adapter->hw;
6521
6522 /* Do the reset outside of interrupt context */
6523 adapter->tx_timeout_count++;
6524
6525 if (hw->mac.type >= e1000_82580)
6526 hw->dev_spec._82575.global_device_reset = true;
6527
6528 schedule_work(&adapter->reset_task);
6529 wr32(E1000_EICS,
6530 (adapter->eims_enable_mask & ~adapter->eims_other));
6531}
6532
6533static void igb_reset_task(struct work_struct *work)
6534{
6535 struct igb_adapter *adapter;
6536 adapter = container_of(work, struct igb_adapter, reset_task);
6537
6538 rtnl_lock();
6539 /* If we're already down or resetting, just bail */
6540 if (test_bit(__IGB_DOWN, &adapter->state) ||
6541 test_bit(__IGB_RESETTING, &adapter->state)) {
6542 rtnl_unlock();
6543 return;
6544 }
6545
6546 igb_dump(adapter);
6547 netdev_err(adapter->netdev, "Reset adapter\n");
6548 igb_reinit_locked(adapter);
6549 rtnl_unlock();
6550}
6551
6552/**
6553 * igb_get_stats64 - Get System Network Statistics
6554 * @netdev: network interface device structure
6555 * @stats: rtnl_link_stats64 pointer
6556 **/
6557static void igb_get_stats64(struct net_device *netdev,
6558 struct rtnl_link_stats64 *stats)
6559{
6560 struct igb_adapter *adapter = netdev_priv(netdev);
6561
6562 spin_lock(&adapter->stats64_lock);
6563 igb_update_stats(adapter);
6564 memcpy(stats, &adapter->stats64, sizeof(*stats));
6565 spin_unlock(&adapter->stats64_lock);
6566}
6567
6568/**
6569 * igb_change_mtu - Change the Maximum Transfer Unit
6570 * @netdev: network interface device structure
6571 * @new_mtu: new value for maximum frame size
6572 *
6573 * Returns 0 on success, negative on failure
6574 **/
6575static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6576{
6577 struct igb_adapter *adapter = netdev_priv(netdev);
6578 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6579
6580 if (adapter->xdp_prog) {
6581 int i;
6582
6583 for (i = 0; i < adapter->num_rx_queues; i++) {
6584 struct igb_ring *ring = adapter->rx_ring[i];
6585
6586 if (max_frame > igb_rx_bufsz(ring)) {
6587 netdev_warn(adapter->netdev,
6588 "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6589 max_frame);
6590 return -EINVAL;
6591 }
6592 }
6593 }
6594
6595 /* adjust max frame to be at least the size of a standard frame */
6596 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6597 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6598
6599 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6600 usleep_range(1000, 2000);
6601
6602 /* igb_down has a dependency on max_frame_size */
6603 adapter->max_frame_size = max_frame;
6604
6605 if (netif_running(netdev))
6606 igb_down(adapter);
6607
6608 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6609 netdev->mtu, new_mtu);
6610 netdev->mtu = new_mtu;
6611
6612 if (netif_running(netdev))
6613 igb_up(adapter);
6614 else
6615 igb_reset(adapter);
6616
6617 clear_bit(__IGB_RESETTING, &adapter->state);
6618
6619 return 0;
6620}
6621
6622/**
6623 * igb_update_stats - Update the board statistics counters
6624 * @adapter: board private structure
6625 **/
6626void igb_update_stats(struct igb_adapter *adapter)
6627{
6628 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6629 struct e1000_hw *hw = &adapter->hw;
6630 struct pci_dev *pdev = adapter->pdev;
6631 u32 reg, mpc;
6632 int i;
6633 u64 bytes, packets;
6634 unsigned int start;
6635 u64 _bytes, _packets;
6636
6637 /* Prevent stats update while adapter is being reset, or if the pci
6638 * connection is down.
6639 */
6640 if (adapter->link_speed == 0)
6641 return;
6642 if (pci_channel_offline(pdev))
6643 return;
6644
6645 bytes = 0;
6646 packets = 0;
6647
6648 rcu_read_lock();
6649 for (i = 0; i < adapter->num_rx_queues; i++) {
6650 struct igb_ring *ring = adapter->rx_ring[i];
6651 u32 rqdpc = rd32(E1000_RQDPC(i));
6652 if (hw->mac.type >= e1000_i210)
6653 wr32(E1000_RQDPC(i), 0);
6654
6655 if (rqdpc) {
6656 ring->rx_stats.drops += rqdpc;
6657 net_stats->rx_fifo_errors += rqdpc;
6658 }
6659
6660 do {
6661 start = u64_stats_fetch_begin(&ring->rx_syncp);
6662 _bytes = ring->rx_stats.bytes;
6663 _packets = ring->rx_stats.packets;
6664 } while (u64_stats_fetch_retry(&ring->rx_syncp, start));
6665 bytes += _bytes;
6666 packets += _packets;
6667 }
6668
6669 net_stats->rx_bytes = bytes;
6670 net_stats->rx_packets = packets;
6671
6672 bytes = 0;
6673 packets = 0;
6674 for (i = 0; i < adapter->num_tx_queues; i++) {
6675 struct igb_ring *ring = adapter->tx_ring[i];
6676 do {
6677 start = u64_stats_fetch_begin(&ring->tx_syncp);
6678 _bytes = ring->tx_stats.bytes;
6679 _packets = ring->tx_stats.packets;
6680 } while (u64_stats_fetch_retry(&ring->tx_syncp, start));
6681 bytes += _bytes;
6682 packets += _packets;
6683 }
6684 net_stats->tx_bytes = bytes;
6685 net_stats->tx_packets = packets;
6686 rcu_read_unlock();
6687
6688 /* read stats registers */
6689 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6690 adapter->stats.gprc += rd32(E1000_GPRC);
6691 adapter->stats.gorc += rd32(E1000_GORCL);
6692 rd32(E1000_GORCH); /* clear GORCL */
6693 adapter->stats.bprc += rd32(E1000_BPRC);
6694 adapter->stats.mprc += rd32(E1000_MPRC);
6695 adapter->stats.roc += rd32(E1000_ROC);
6696
6697 adapter->stats.prc64 += rd32(E1000_PRC64);
6698 adapter->stats.prc127 += rd32(E1000_PRC127);
6699 adapter->stats.prc255 += rd32(E1000_PRC255);
6700 adapter->stats.prc511 += rd32(E1000_PRC511);
6701 adapter->stats.prc1023 += rd32(E1000_PRC1023);
6702 adapter->stats.prc1522 += rd32(E1000_PRC1522);
6703 adapter->stats.symerrs += rd32(E1000_SYMERRS);
6704 adapter->stats.sec += rd32(E1000_SEC);
6705
6706 mpc = rd32(E1000_MPC);
6707 adapter->stats.mpc += mpc;
6708 net_stats->rx_fifo_errors += mpc;
6709 adapter->stats.scc += rd32(E1000_SCC);
6710 adapter->stats.ecol += rd32(E1000_ECOL);
6711 adapter->stats.mcc += rd32(E1000_MCC);
6712 adapter->stats.latecol += rd32(E1000_LATECOL);
6713 adapter->stats.dc += rd32(E1000_DC);
6714 adapter->stats.rlec += rd32(E1000_RLEC);
6715 adapter->stats.xonrxc += rd32(E1000_XONRXC);
6716 adapter->stats.xontxc += rd32(E1000_XONTXC);
6717 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6718 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6719 adapter->stats.fcruc += rd32(E1000_FCRUC);
6720 adapter->stats.gptc += rd32(E1000_GPTC);
6721 adapter->stats.gotc += rd32(E1000_GOTCL);
6722 rd32(E1000_GOTCH); /* clear GOTCL */
6723 adapter->stats.rnbc += rd32(E1000_RNBC);
6724 adapter->stats.ruc += rd32(E1000_RUC);
6725 adapter->stats.rfc += rd32(E1000_RFC);
6726 adapter->stats.rjc += rd32(E1000_RJC);
6727 adapter->stats.tor += rd32(E1000_TORH);
6728 adapter->stats.tot += rd32(E1000_TOTH);
6729 adapter->stats.tpr += rd32(E1000_TPR);
6730
6731 adapter->stats.ptc64 += rd32(E1000_PTC64);
6732 adapter->stats.ptc127 += rd32(E1000_PTC127);
6733 adapter->stats.ptc255 += rd32(E1000_PTC255);
6734 adapter->stats.ptc511 += rd32(E1000_PTC511);
6735 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6736 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6737
6738 adapter->stats.mptc += rd32(E1000_MPTC);
6739 adapter->stats.bptc += rd32(E1000_BPTC);
6740
6741 adapter->stats.tpt += rd32(E1000_TPT);
6742 adapter->stats.colc += rd32(E1000_COLC);
6743
6744 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6745 /* read internal phy specific stats */
6746 reg = rd32(E1000_CTRL_EXT);
6747 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6748 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6749
6750 /* this stat has invalid values on i210/i211 */
6751 if ((hw->mac.type != e1000_i210) &&
6752 (hw->mac.type != e1000_i211))
6753 adapter->stats.tncrs += rd32(E1000_TNCRS);
6754 }
6755
6756 adapter->stats.tsctc += rd32(E1000_TSCTC);
6757 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6758
6759 adapter->stats.iac += rd32(E1000_IAC);
6760 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6761 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6762 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6763 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6764 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6765 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6766 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6767 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6768
6769 /* Fill out the OS statistics structure */
6770 net_stats->multicast = adapter->stats.mprc;
6771 net_stats->collisions = adapter->stats.colc;
6772
6773 /* Rx Errors */
6774
6775 /* RLEC on some newer hardware can be incorrect so build
6776 * our own version based on RUC and ROC
6777 */
6778 net_stats->rx_errors = adapter->stats.rxerrc +
6779 adapter->stats.crcerrs + adapter->stats.algnerrc +
6780 adapter->stats.ruc + adapter->stats.roc +
6781 adapter->stats.cexterr;
6782 net_stats->rx_length_errors = adapter->stats.ruc +
6783 adapter->stats.roc;
6784 net_stats->rx_crc_errors = adapter->stats.crcerrs;
6785 net_stats->rx_frame_errors = adapter->stats.algnerrc;
6786 net_stats->rx_missed_errors = adapter->stats.mpc;
6787
6788 /* Tx Errors */
6789 net_stats->tx_errors = adapter->stats.ecol +
6790 adapter->stats.latecol;
6791 net_stats->tx_aborted_errors = adapter->stats.ecol;
6792 net_stats->tx_window_errors = adapter->stats.latecol;
6793 net_stats->tx_carrier_errors = adapter->stats.tncrs;
6794
6795 /* Tx Dropped needs to be maintained elsewhere */
6796
6797 /* Management Stats */
6798 adapter->stats.mgptc += rd32(E1000_MGTPTC);
6799 adapter->stats.mgprc += rd32(E1000_MGTPRC);
6800 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6801
6802 /* OS2BMC Stats */
6803 reg = rd32(E1000_MANC);
6804 if (reg & E1000_MANC_EN_BMC2OS) {
6805 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6806 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6807 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6808 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6809 }
6810}
6811
6812static void igb_perout(struct igb_adapter *adapter, int tsintr_tt)
6813{
6814 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_PEROUT, tsintr_tt);
6815 struct e1000_hw *hw = &adapter->hw;
6816 struct timespec64 ts;
6817 u32 tsauxc;
6818
6819 if (pin < 0 || pin >= IGB_N_SDP)
6820 return;
6821
6822 spin_lock(&adapter->tmreg_lock);
6823
6824 if (hw->mac.type == e1000_82580 ||
6825 hw->mac.type == e1000_i354 ||
6826 hw->mac.type == e1000_i350) {
6827 s64 ns = timespec64_to_ns(&adapter->perout[tsintr_tt].period);
6828 u32 systiml, systimh, level_mask, level, rem;
6829 u64 systim, now;
6830
6831 /* read systim registers in sequence */
6832 rd32(E1000_SYSTIMR);
6833 systiml = rd32(E1000_SYSTIML);
6834 systimh = rd32(E1000_SYSTIMH);
6835 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
6836 now = timecounter_cyc2time(&adapter->tc, systim);
6837
6838 if (pin < 2) {
6839 level_mask = (tsintr_tt == 1) ? 0x80000 : 0x40000;
6840 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
6841 } else {
6842 level_mask = (tsintr_tt == 1) ? 0x80 : 0x40;
6843 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
6844 }
6845
6846 div_u64_rem(now, ns, &rem);
6847 systim = systim + (ns - rem);
6848
6849 /* synchronize pin level with rising/falling edges */
6850 div_u64_rem(now, ns << 1, &rem);
6851 if (rem < ns) {
6852 /* first half of period */
6853 if (level == 0) {
6854 /* output is already low, skip this period */
6855 systim += ns;
6856 pr_notice("igb: periodic output on %s missed falling edge\n",
6857 adapter->sdp_config[pin].name);
6858 }
6859 } else {
6860 /* second half of period */
6861 if (level == 1) {
6862 /* output is already high, skip this period */
6863 systim += ns;
6864 pr_notice("igb: periodic output on %s missed rising edge\n",
6865 adapter->sdp_config[pin].name);
6866 }
6867 }
6868
6869 /* for this chip family tv_sec is the upper part of the binary value,
6870 * so not seconds
6871 */
6872 ts.tv_nsec = (u32)systim;
6873 ts.tv_sec = ((u32)(systim >> 32)) & 0xFF;
6874 } else {
6875 ts = timespec64_add(adapter->perout[tsintr_tt].start,
6876 adapter->perout[tsintr_tt].period);
6877 }
6878
6879 /* u32 conversion of tv_sec is safe until y2106 */
6880 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec);
6881 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec);
6882 tsauxc = rd32(E1000_TSAUXC);
6883 tsauxc |= TSAUXC_EN_TT0;
6884 wr32(E1000_TSAUXC, tsauxc);
6885 adapter->perout[tsintr_tt].start = ts;
6886
6887 spin_unlock(&adapter->tmreg_lock);
6888}
6889
6890static void igb_extts(struct igb_adapter *adapter, int tsintr_tt)
6891{
6892 int pin = ptp_find_pin(adapter->ptp_clock, PTP_PF_EXTTS, tsintr_tt);
6893 int auxstmpl = (tsintr_tt == 1) ? E1000_AUXSTMPL1 : E1000_AUXSTMPL0;
6894 int auxstmph = (tsintr_tt == 1) ? E1000_AUXSTMPH1 : E1000_AUXSTMPH0;
6895 struct e1000_hw *hw = &adapter->hw;
6896 struct ptp_clock_event event;
6897 struct timespec64 ts;
6898
6899 if (pin < 0 || pin >= IGB_N_SDP)
6900 return;
6901
6902 if (hw->mac.type == e1000_82580 ||
6903 hw->mac.type == e1000_i354 ||
6904 hw->mac.type == e1000_i350) {
6905 s64 ns = rd32(auxstmpl);
6906
6907 ns += ((s64)(rd32(auxstmph) & 0xFF)) << 32;
6908 ts = ns_to_timespec64(ns);
6909 } else {
6910 ts.tv_nsec = rd32(auxstmpl);
6911 ts.tv_sec = rd32(auxstmph);
6912 }
6913
6914 event.type = PTP_CLOCK_EXTTS;
6915 event.index = tsintr_tt;
6916 event.timestamp = ts.tv_sec * 1000000000ULL + ts.tv_nsec;
6917 ptp_clock_event(adapter->ptp_clock, &event);
6918}
6919
6920static void igb_tsync_interrupt(struct igb_adapter *adapter)
6921{
6922 struct e1000_hw *hw = &adapter->hw;
6923 u32 ack = 0, tsicr = rd32(E1000_TSICR);
6924 struct ptp_clock_event event;
6925
6926 if (tsicr & TSINTR_SYS_WRAP) {
6927 event.type = PTP_CLOCK_PPS;
6928 if (adapter->ptp_caps.pps)
6929 ptp_clock_event(adapter->ptp_clock, &event);
6930 ack |= TSINTR_SYS_WRAP;
6931 }
6932
6933 if (tsicr & E1000_TSICR_TXTS) {
6934 /* retrieve hardware timestamp */
6935 schedule_work(&adapter->ptp_tx_work);
6936 ack |= E1000_TSICR_TXTS;
6937 }
6938
6939 if (tsicr & TSINTR_TT0) {
6940 igb_perout(adapter, 0);
6941 ack |= TSINTR_TT0;
6942 }
6943
6944 if (tsicr & TSINTR_TT1) {
6945 igb_perout(adapter, 1);
6946 ack |= TSINTR_TT1;
6947 }
6948
6949 if (tsicr & TSINTR_AUTT0) {
6950 igb_extts(adapter, 0);
6951 ack |= TSINTR_AUTT0;
6952 }
6953
6954 if (tsicr & TSINTR_AUTT1) {
6955 igb_extts(adapter, 1);
6956 ack |= TSINTR_AUTT1;
6957 }
6958
6959 /* acknowledge the interrupts */
6960 wr32(E1000_TSICR, ack);
6961}
6962
6963static irqreturn_t igb_msix_other(int irq, void *data)
6964{
6965 struct igb_adapter *adapter = data;
6966 struct e1000_hw *hw = &adapter->hw;
6967 u32 icr = rd32(E1000_ICR);
6968 /* reading ICR causes bit 31 of EICR to be cleared */
6969
6970 if (icr & E1000_ICR_DRSTA)
6971 schedule_work(&adapter->reset_task);
6972
6973 if (icr & E1000_ICR_DOUTSYNC) {
6974 /* HW is reporting DMA is out of sync */
6975 adapter->stats.doosync++;
6976 /* The DMA Out of Sync is also indication of a spoof event
6977 * in IOV mode. Check the Wrong VM Behavior register to
6978 * see if it is really a spoof event.
6979 */
6980 igb_check_wvbr(adapter);
6981 }
6982
6983 /* Check for a mailbox event */
6984 if (icr & E1000_ICR_VMMB)
6985 igb_msg_task(adapter);
6986
6987 if (icr & E1000_ICR_LSC) {
6988 hw->mac.get_link_status = 1;
6989 /* guard against interrupt when we're going down */
6990 if (!test_bit(__IGB_DOWN, &adapter->state))
6991 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6992 }
6993
6994 if (icr & E1000_ICR_TS)
6995 igb_tsync_interrupt(adapter);
6996
6997 wr32(E1000_EIMS, adapter->eims_other);
6998
6999 return IRQ_HANDLED;
7000}
7001
7002static void igb_write_itr(struct igb_q_vector *q_vector)
7003{
7004 struct igb_adapter *adapter = q_vector->adapter;
7005 u32 itr_val = q_vector->itr_val & 0x7FFC;
7006
7007 if (!q_vector->set_itr)
7008 return;
7009
7010 if (!itr_val)
7011 itr_val = 0x4;
7012
7013 if (adapter->hw.mac.type == e1000_82575)
7014 itr_val |= itr_val << 16;
7015 else
7016 itr_val |= E1000_EITR_CNT_IGNR;
7017
7018 writel(itr_val, q_vector->itr_register);
7019 q_vector->set_itr = 0;
7020}
7021
7022static irqreturn_t igb_msix_ring(int irq, void *data)
7023{
7024 struct igb_q_vector *q_vector = data;
7025
7026 /* Write the ITR value calculated from the previous interrupt. */
7027 igb_write_itr(q_vector);
7028
7029 napi_schedule(&q_vector->napi);
7030
7031 return IRQ_HANDLED;
7032}
7033
7034#ifdef CONFIG_IGB_DCA
7035static void igb_update_tx_dca(struct igb_adapter *adapter,
7036 struct igb_ring *tx_ring,
7037 int cpu)
7038{
7039 struct e1000_hw *hw = &adapter->hw;
7040 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
7041
7042 if (hw->mac.type != e1000_82575)
7043 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
7044
7045 /* We can enable relaxed ordering for reads, but not writes when
7046 * DCA is enabled. This is due to a known issue in some chipsets
7047 * which will cause the DCA tag to be cleared.
7048 */
7049 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
7050 E1000_DCA_TXCTRL_DATA_RRO_EN |
7051 E1000_DCA_TXCTRL_DESC_DCA_EN;
7052
7053 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
7054}
7055
7056static void igb_update_rx_dca(struct igb_adapter *adapter,
7057 struct igb_ring *rx_ring,
7058 int cpu)
7059{
7060 struct e1000_hw *hw = &adapter->hw;
7061 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
7062
7063 if (hw->mac.type != e1000_82575)
7064 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
7065
7066 /* We can enable relaxed ordering for reads, but not writes when
7067 * DCA is enabled. This is due to a known issue in some chipsets
7068 * which will cause the DCA tag to be cleared.
7069 */
7070 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
7071 E1000_DCA_RXCTRL_DESC_DCA_EN;
7072
7073 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
7074}
7075
7076static void igb_update_dca(struct igb_q_vector *q_vector)
7077{
7078 struct igb_adapter *adapter = q_vector->adapter;
7079 int cpu = get_cpu();
7080
7081 if (q_vector->cpu == cpu)
7082 goto out_no_update;
7083
7084 if (q_vector->tx.ring)
7085 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
7086
7087 if (q_vector->rx.ring)
7088 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
7089
7090 q_vector->cpu = cpu;
7091out_no_update:
7092 put_cpu();
7093}
7094
7095static void igb_setup_dca(struct igb_adapter *adapter)
7096{
7097 struct e1000_hw *hw = &adapter->hw;
7098 int i;
7099
7100 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
7101 return;
7102
7103 /* Always use CB2 mode, difference is masked in the CB driver. */
7104 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
7105
7106 for (i = 0; i < adapter->num_q_vectors; i++) {
7107 adapter->q_vector[i]->cpu = -1;
7108 igb_update_dca(adapter->q_vector[i]);
7109 }
7110}
7111
7112static int __igb_notify_dca(struct device *dev, void *data)
7113{
7114 struct net_device *netdev = dev_get_drvdata(dev);
7115 struct igb_adapter *adapter = netdev_priv(netdev);
7116 struct pci_dev *pdev = adapter->pdev;
7117 struct e1000_hw *hw = &adapter->hw;
7118 unsigned long event = *(unsigned long *)data;
7119
7120 switch (event) {
7121 case DCA_PROVIDER_ADD:
7122 /* if already enabled, don't do it again */
7123 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
7124 break;
7125 if (dca_add_requester(dev) == 0) {
7126 adapter->flags |= IGB_FLAG_DCA_ENABLED;
7127 dev_info(&pdev->dev, "DCA enabled\n");
7128 igb_setup_dca(adapter);
7129 break;
7130 }
7131 fallthrough; /* since DCA is disabled. */
7132 case DCA_PROVIDER_REMOVE:
7133 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
7134 /* without this a class_device is left
7135 * hanging around in the sysfs model
7136 */
7137 dca_remove_requester(dev);
7138 dev_info(&pdev->dev, "DCA disabled\n");
7139 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
7140 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
7141 }
7142 break;
7143 }
7144
7145 return 0;
7146}
7147
7148static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
7149 void *p)
7150{
7151 int ret_val;
7152
7153 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7154 __igb_notify_dca);
7155
7156 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7157}
7158#endif /* CONFIG_IGB_DCA */
7159
7160#ifdef CONFIG_PCI_IOV
7161static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7162{
7163 unsigned char mac_addr[ETH_ALEN];
7164
7165 eth_zero_addr(mac_addr);
7166 igb_set_vf_mac(adapter, vf, mac_addr);
7167
7168 /* By default spoof check is enabled for all VFs */
7169 adapter->vf_data[vf].spoofchk_enabled = true;
7170
7171 /* By default VFs are not trusted */
7172 adapter->vf_data[vf].trusted = false;
7173
7174 return 0;
7175}
7176
7177#endif
7178static void igb_ping_all_vfs(struct igb_adapter *adapter)
7179{
7180 struct e1000_hw *hw = &adapter->hw;
7181 u32 ping;
7182 int i;
7183
7184 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7185 ping = E1000_PF_CONTROL_MSG;
7186 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7187 ping |= E1000_VT_MSGTYPE_CTS;
7188 igb_write_mbx(hw, &ping, 1, i);
7189 }
7190}
7191
7192static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7193{
7194 struct e1000_hw *hw = &adapter->hw;
7195 u32 vmolr = rd32(E1000_VMOLR(vf));
7196 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7197
7198 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7199 IGB_VF_FLAG_MULTI_PROMISC);
7200 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7201
7202 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7203 vmolr |= E1000_VMOLR_MPME;
7204 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7205 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7206 } else {
7207 /* if we have hashes and we are clearing a multicast promisc
7208 * flag we need to write the hashes to the MTA as this step
7209 * was previously skipped
7210 */
7211 if (vf_data->num_vf_mc_hashes > 30) {
7212 vmolr |= E1000_VMOLR_MPME;
7213 } else if (vf_data->num_vf_mc_hashes) {
7214 int j;
7215
7216 vmolr |= E1000_VMOLR_ROMPE;
7217 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7218 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7219 }
7220 }
7221
7222 wr32(E1000_VMOLR(vf), vmolr);
7223
7224 /* there are flags left unprocessed, likely not supported */
7225 if (*msgbuf & E1000_VT_MSGINFO_MASK)
7226 return -EINVAL;
7227
7228 return 0;
7229}
7230
7231static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7232 u32 *msgbuf, u32 vf)
7233{
7234 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7235 u16 *hash_list = (u16 *)&msgbuf[1];
7236 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7237 int i;
7238
7239 /* salt away the number of multicast addresses assigned
7240 * to this VF for later use to restore when the PF multi cast
7241 * list changes
7242 */
7243 vf_data->num_vf_mc_hashes = n;
7244
7245 /* only up to 30 hash values supported */
7246 if (n > 30)
7247 n = 30;
7248
7249 /* store the hashes for later use */
7250 for (i = 0; i < n; i++)
7251 vf_data->vf_mc_hashes[i] = hash_list[i];
7252
7253 /* Flush and reset the mta with the new values */
7254 igb_set_rx_mode(adapter->netdev);
7255
7256 return 0;
7257}
7258
7259static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7260{
7261 struct e1000_hw *hw = &adapter->hw;
7262 struct vf_data_storage *vf_data;
7263 int i, j;
7264
7265 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7266 u32 vmolr = rd32(E1000_VMOLR(i));
7267
7268 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7269
7270 vf_data = &adapter->vf_data[i];
7271
7272 if ((vf_data->num_vf_mc_hashes > 30) ||
7273 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7274 vmolr |= E1000_VMOLR_MPME;
7275 } else if (vf_data->num_vf_mc_hashes) {
7276 vmolr |= E1000_VMOLR_ROMPE;
7277 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7278 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7279 }
7280 wr32(E1000_VMOLR(i), vmolr);
7281 }
7282}
7283
7284static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7285{
7286 struct e1000_hw *hw = &adapter->hw;
7287 u32 pool_mask, vlvf_mask, i;
7288
7289 /* create mask for VF and other pools */
7290 pool_mask = E1000_VLVF_POOLSEL_MASK;
7291 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7292
7293 /* drop PF from pool bits */
7294 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7295 adapter->vfs_allocated_count);
7296
7297 /* Find the vlan filter for this id */
7298 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7299 u32 vlvf = rd32(E1000_VLVF(i));
7300 u32 vfta_mask, vid, vfta;
7301
7302 /* remove the vf from the pool */
7303 if (!(vlvf & vlvf_mask))
7304 continue;
7305
7306 /* clear out bit from VLVF */
7307 vlvf ^= vlvf_mask;
7308
7309 /* if other pools are present, just remove ourselves */
7310 if (vlvf & pool_mask)
7311 goto update_vlvfb;
7312
7313 /* if PF is present, leave VFTA */
7314 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7315 goto update_vlvf;
7316
7317 vid = vlvf & E1000_VLVF_VLANID_MASK;
7318 vfta_mask = BIT(vid % 32);
7319
7320 /* clear bit from VFTA */
7321 vfta = adapter->shadow_vfta[vid / 32];
7322 if (vfta & vfta_mask)
7323 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7324update_vlvf:
7325 /* clear pool selection enable */
7326 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7327 vlvf &= E1000_VLVF_POOLSEL_MASK;
7328 else
7329 vlvf = 0;
7330update_vlvfb:
7331 /* clear pool bits */
7332 wr32(E1000_VLVF(i), vlvf);
7333 }
7334}
7335
7336static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7337{
7338 u32 vlvf;
7339 int idx;
7340
7341 /* short cut the special case */
7342 if (vlan == 0)
7343 return 0;
7344
7345 /* Search for the VLAN id in the VLVF entries */
7346 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7347 vlvf = rd32(E1000_VLVF(idx));
7348 if ((vlvf & VLAN_VID_MASK) == vlan)
7349 break;
7350 }
7351
7352 return idx;
7353}
7354
7355static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7356{
7357 struct e1000_hw *hw = &adapter->hw;
7358 u32 bits, pf_id;
7359 int idx;
7360
7361 idx = igb_find_vlvf_entry(hw, vid);
7362 if (!idx)
7363 return;
7364
7365 /* See if any other pools are set for this VLAN filter
7366 * entry other than the PF.
7367 */
7368 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7369 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7370 bits &= rd32(E1000_VLVF(idx));
7371
7372 /* Disable the filter so this falls into the default pool. */
7373 if (!bits) {
7374 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7375 wr32(E1000_VLVF(idx), BIT(pf_id));
7376 else
7377 wr32(E1000_VLVF(idx), 0);
7378 }
7379}
7380
7381static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7382 bool add, u32 vf)
7383{
7384 int pf_id = adapter->vfs_allocated_count;
7385 struct e1000_hw *hw = &adapter->hw;
7386 int err;
7387
7388 /* If VLAN overlaps with one the PF is currently monitoring make
7389 * sure that we are able to allocate a VLVF entry. This may be
7390 * redundant but it guarantees PF will maintain visibility to
7391 * the VLAN.
7392 */
7393 if (add && test_bit(vid, adapter->active_vlans)) {
7394 err = igb_vfta_set(hw, vid, pf_id, true, false);
7395 if (err)
7396 return err;
7397 }
7398
7399 err = igb_vfta_set(hw, vid, vf, add, false);
7400
7401 if (add && !err)
7402 return err;
7403
7404 /* If we failed to add the VF VLAN or we are removing the VF VLAN
7405 * we may need to drop the PF pool bit in order to allow us to free
7406 * up the VLVF resources.
7407 */
7408 if (test_bit(vid, adapter->active_vlans) ||
7409 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7410 igb_update_pf_vlvf(adapter, vid);
7411
7412 return err;
7413}
7414
7415static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7416{
7417 struct e1000_hw *hw = &adapter->hw;
7418
7419 if (vid)
7420 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7421 else
7422 wr32(E1000_VMVIR(vf), 0);
7423}
7424
7425static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7426 u16 vlan, u8 qos)
7427{
7428 int err;
7429
7430 err = igb_set_vf_vlan(adapter, vlan, true, vf);
7431 if (err)
7432 return err;
7433
7434 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7435 igb_set_vmolr(adapter, vf, !vlan);
7436
7437 /* revoke access to previous VLAN */
7438 if (vlan != adapter->vf_data[vf].pf_vlan)
7439 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7440 false, vf);
7441
7442 adapter->vf_data[vf].pf_vlan = vlan;
7443 adapter->vf_data[vf].pf_qos = qos;
7444 igb_set_vf_vlan_strip(adapter, vf, true);
7445 dev_info(&adapter->pdev->dev,
7446 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7447 if (test_bit(__IGB_DOWN, &adapter->state)) {
7448 dev_warn(&adapter->pdev->dev,
7449 "The VF VLAN has been set, but the PF device is not up.\n");
7450 dev_warn(&adapter->pdev->dev,
7451 "Bring the PF device up before attempting to use the VF device.\n");
7452 }
7453
7454 return err;
7455}
7456
7457static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7458{
7459 /* Restore tagless access via VLAN 0 */
7460 igb_set_vf_vlan(adapter, 0, true, vf);
7461
7462 igb_set_vmvir(adapter, 0, vf);
7463 igb_set_vmolr(adapter, vf, true);
7464
7465 /* Remove any PF assigned VLAN */
7466 if (adapter->vf_data[vf].pf_vlan)
7467 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7468 false, vf);
7469
7470 adapter->vf_data[vf].pf_vlan = 0;
7471 adapter->vf_data[vf].pf_qos = 0;
7472 igb_set_vf_vlan_strip(adapter, vf, false);
7473
7474 return 0;
7475}
7476
7477static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7478 u16 vlan, u8 qos, __be16 vlan_proto)
7479{
7480 struct igb_adapter *adapter = netdev_priv(netdev);
7481
7482 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7483 return -EINVAL;
7484
7485 if (vlan_proto != htons(ETH_P_8021Q))
7486 return -EPROTONOSUPPORT;
7487
7488 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7489 igb_disable_port_vlan(adapter, vf);
7490}
7491
7492static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7493{
7494 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7495 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7496 int ret;
7497
7498 if (adapter->vf_data[vf].pf_vlan)
7499 return -1;
7500
7501 /* VLAN 0 is a special case, don't allow it to be removed */
7502 if (!vid && !add)
7503 return 0;
7504
7505 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7506 if (!ret)
7507 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7508 return ret;
7509}
7510
7511static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7512{
7513 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7514
7515 /* clear flags - except flag that indicates PF has set the MAC */
7516 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7517 vf_data->last_nack = jiffies;
7518
7519 /* reset vlans for device */
7520 igb_clear_vf_vfta(adapter, vf);
7521 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7522 igb_set_vmvir(adapter, vf_data->pf_vlan |
7523 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7524 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7525 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7526
7527 /* reset multicast table array for vf */
7528 adapter->vf_data[vf].num_vf_mc_hashes = 0;
7529
7530 /* Flush and reset the mta with the new values */
7531 igb_set_rx_mode(adapter->netdev);
7532}
7533
7534static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7535{
7536 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7537
7538 /* clear mac address as we were hotplug removed/added */
7539 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7540 eth_zero_addr(vf_mac);
7541
7542 /* process remaining reset events */
7543 igb_vf_reset(adapter, vf);
7544}
7545
7546static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7547{
7548 struct e1000_hw *hw = &adapter->hw;
7549 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7550 u32 reg, msgbuf[3] = {};
7551 u8 *addr = (u8 *)(&msgbuf[1]);
7552
7553 /* process all the same items cleared in a function level reset */
7554 igb_vf_reset(adapter, vf);
7555
7556 /* set vf mac address */
7557 igb_set_vf_mac(adapter, vf, vf_mac);
7558
7559 /* enable transmit and receive for vf */
7560 reg = rd32(E1000_VFTE);
7561 wr32(E1000_VFTE, reg | BIT(vf));
7562 reg = rd32(E1000_VFRE);
7563 wr32(E1000_VFRE, reg | BIT(vf));
7564
7565 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7566
7567 /* reply to reset with ack and vf mac address */
7568 if (!is_zero_ether_addr(vf_mac)) {
7569 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7570 memcpy(addr, vf_mac, ETH_ALEN);
7571 } else {
7572 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7573 }
7574 igb_write_mbx(hw, msgbuf, 3, vf);
7575}
7576
7577static void igb_flush_mac_table(struct igb_adapter *adapter)
7578{
7579 struct e1000_hw *hw = &adapter->hw;
7580 int i;
7581
7582 for (i = 0; i < hw->mac.rar_entry_count; i++) {
7583 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7584 eth_zero_addr(adapter->mac_table[i].addr);
7585 adapter->mac_table[i].queue = 0;
7586 igb_rar_set_index(adapter, i);
7587 }
7588}
7589
7590static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7591{
7592 struct e1000_hw *hw = &adapter->hw;
7593 /* do not count rar entries reserved for VFs MAC addresses */
7594 int rar_entries = hw->mac.rar_entry_count -
7595 adapter->vfs_allocated_count;
7596 int i, count = 0;
7597
7598 for (i = 0; i < rar_entries; i++) {
7599 /* do not count default entries */
7600 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7601 continue;
7602
7603 /* do not count "in use" entries for different queues */
7604 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7605 (adapter->mac_table[i].queue != queue))
7606 continue;
7607
7608 count++;
7609 }
7610
7611 return count;
7612}
7613
7614/* Set default MAC address for the PF in the first RAR entry */
7615static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7616{
7617 struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7618
7619 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7620 mac_table->queue = adapter->vfs_allocated_count;
7621 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7622
7623 igb_rar_set_index(adapter, 0);
7624}
7625
7626/* If the filter to be added and an already existing filter express
7627 * the same address and address type, it should be possible to only
7628 * override the other configurations, for example the queue to steer
7629 * traffic.
7630 */
7631static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7632 const u8 *addr, const u8 flags)
7633{
7634 if (!(entry->state & IGB_MAC_STATE_IN_USE))
7635 return true;
7636
7637 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7638 (flags & IGB_MAC_STATE_SRC_ADDR))
7639 return false;
7640
7641 if (!ether_addr_equal(addr, entry->addr))
7642 return false;
7643
7644 return true;
7645}
7646
7647/* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7648 * 'flags' is used to indicate what kind of match is made, match is by
7649 * default for the destination address, if matching by source address
7650 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7651 */
7652static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7653 const u8 *addr, const u8 queue,
7654 const u8 flags)
7655{
7656 struct e1000_hw *hw = &adapter->hw;
7657 int rar_entries = hw->mac.rar_entry_count -
7658 adapter->vfs_allocated_count;
7659 int i;
7660
7661 if (is_zero_ether_addr(addr))
7662 return -EINVAL;
7663
7664 /* Search for the first empty entry in the MAC table.
7665 * Do not touch entries at the end of the table reserved for the VF MAC
7666 * addresses.
7667 */
7668 for (i = 0; i < rar_entries; i++) {
7669 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7670 addr, flags))
7671 continue;
7672
7673 ether_addr_copy(adapter->mac_table[i].addr, addr);
7674 adapter->mac_table[i].queue = queue;
7675 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7676
7677 igb_rar_set_index(adapter, i);
7678 return i;
7679 }
7680
7681 return -ENOSPC;
7682}
7683
7684static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7685 const u8 queue)
7686{
7687 return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7688}
7689
7690/* Remove a MAC filter for 'addr' directing matching traffic to
7691 * 'queue', 'flags' is used to indicate what kind of match need to be
7692 * removed, match is by default for the destination address, if
7693 * matching by source address is to be removed the flag
7694 * IGB_MAC_STATE_SRC_ADDR can be used.
7695 */
7696static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7697 const u8 *addr, const u8 queue,
7698 const u8 flags)
7699{
7700 struct e1000_hw *hw = &adapter->hw;
7701 int rar_entries = hw->mac.rar_entry_count -
7702 adapter->vfs_allocated_count;
7703 int i;
7704
7705 if (is_zero_ether_addr(addr))
7706 return -EINVAL;
7707
7708 /* Search for matching entry in the MAC table based on given address
7709 * and queue. Do not touch entries at the end of the table reserved
7710 * for the VF MAC addresses.
7711 */
7712 for (i = 0; i < rar_entries; i++) {
7713 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7714 continue;
7715 if ((adapter->mac_table[i].state & flags) != flags)
7716 continue;
7717 if (adapter->mac_table[i].queue != queue)
7718 continue;
7719 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7720 continue;
7721
7722 /* When a filter for the default address is "deleted",
7723 * we return it to its initial configuration
7724 */
7725 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7726 adapter->mac_table[i].state =
7727 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7728 adapter->mac_table[i].queue =
7729 adapter->vfs_allocated_count;
7730 } else {
7731 adapter->mac_table[i].state = 0;
7732 adapter->mac_table[i].queue = 0;
7733 eth_zero_addr(adapter->mac_table[i].addr);
7734 }
7735
7736 igb_rar_set_index(adapter, i);
7737 return 0;
7738 }
7739
7740 return -ENOENT;
7741}
7742
7743static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7744 const u8 queue)
7745{
7746 return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7747}
7748
7749int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7750 const u8 *addr, u8 queue, u8 flags)
7751{
7752 struct e1000_hw *hw = &adapter->hw;
7753
7754 /* In theory, this should be supported on 82575 as well, but
7755 * that part wasn't easily accessible during development.
7756 */
7757 if (hw->mac.type != e1000_i210)
7758 return -EOPNOTSUPP;
7759
7760 return igb_add_mac_filter_flags(adapter, addr, queue,
7761 IGB_MAC_STATE_QUEUE_STEERING | flags);
7762}
7763
7764int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7765 const u8 *addr, u8 queue, u8 flags)
7766{
7767 return igb_del_mac_filter_flags(adapter, addr, queue,
7768 IGB_MAC_STATE_QUEUE_STEERING | flags);
7769}
7770
7771static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7772{
7773 struct igb_adapter *adapter = netdev_priv(netdev);
7774 int ret;
7775
7776 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7777
7778 return min_t(int, ret, 0);
7779}
7780
7781static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7782{
7783 struct igb_adapter *adapter = netdev_priv(netdev);
7784
7785 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7786
7787 return 0;
7788}
7789
7790static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7791 const u32 info, const u8 *addr)
7792{
7793 struct pci_dev *pdev = adapter->pdev;
7794 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7795 struct list_head *pos;
7796 struct vf_mac_filter *entry = NULL;
7797 int ret = 0;
7798
7799 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7800 !vf_data->trusted) {
7801 dev_warn(&pdev->dev,
7802 "VF %d requested MAC filter but is administratively denied\n",
7803 vf);
7804 return -EINVAL;
7805 }
7806 if (!is_valid_ether_addr(addr)) {
7807 dev_warn(&pdev->dev,
7808 "VF %d attempted to set invalid MAC filter\n",
7809 vf);
7810 return -EINVAL;
7811 }
7812
7813 switch (info) {
7814 case E1000_VF_MAC_FILTER_CLR:
7815 /* remove all unicast MAC filters related to the current VF */
7816 list_for_each(pos, &adapter->vf_macs.l) {
7817 entry = list_entry(pos, struct vf_mac_filter, l);
7818 if (entry->vf == vf) {
7819 entry->vf = -1;
7820 entry->free = true;
7821 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7822 }
7823 }
7824 break;
7825 case E1000_VF_MAC_FILTER_ADD:
7826 /* try to find empty slot in the list */
7827 list_for_each(pos, &adapter->vf_macs.l) {
7828 entry = list_entry(pos, struct vf_mac_filter, l);
7829 if (entry->free)
7830 break;
7831 }
7832
7833 if (entry && entry->free) {
7834 entry->free = false;
7835 entry->vf = vf;
7836 ether_addr_copy(entry->vf_mac, addr);
7837
7838 ret = igb_add_mac_filter(adapter, addr, vf);
7839 ret = min_t(int, ret, 0);
7840 } else {
7841 ret = -ENOSPC;
7842 }
7843
7844 if (ret == -ENOSPC)
7845 dev_warn(&pdev->dev,
7846 "VF %d has requested MAC filter but there is no space for it\n",
7847 vf);
7848 break;
7849 default:
7850 ret = -EINVAL;
7851 break;
7852 }
7853
7854 return ret;
7855}
7856
7857static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7858{
7859 struct pci_dev *pdev = adapter->pdev;
7860 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7861 u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7862
7863 /* The VF MAC Address is stored in a packed array of bytes
7864 * starting at the second 32 bit word of the msg array
7865 */
7866 unsigned char *addr = (unsigned char *)&msg[1];
7867 int ret = 0;
7868
7869 if (!info) {
7870 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7871 !vf_data->trusted) {
7872 dev_warn(&pdev->dev,
7873 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7874 vf);
7875 return -EINVAL;
7876 }
7877
7878 if (!is_valid_ether_addr(addr)) {
7879 dev_warn(&pdev->dev,
7880 "VF %d attempted to set invalid MAC\n",
7881 vf);
7882 return -EINVAL;
7883 }
7884
7885 ret = igb_set_vf_mac(adapter, vf, addr);
7886 } else {
7887 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7888 }
7889
7890 return ret;
7891}
7892
7893static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7894{
7895 struct e1000_hw *hw = &adapter->hw;
7896 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7897 u32 msg = E1000_VT_MSGTYPE_NACK;
7898
7899 /* if device isn't clear to send it shouldn't be reading either */
7900 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7901 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7902 igb_write_mbx(hw, &msg, 1, vf);
7903 vf_data->last_nack = jiffies;
7904 }
7905}
7906
7907static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7908{
7909 struct pci_dev *pdev = adapter->pdev;
7910 u32 msgbuf[E1000_VFMAILBOX_SIZE];
7911 struct e1000_hw *hw = &adapter->hw;
7912 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7913 s32 retval;
7914
7915 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7916
7917 if (retval) {
7918 /* if receive failed revoke VF CTS stats and restart init */
7919 dev_err(&pdev->dev, "Error receiving message from VF\n");
7920 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7921 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7922 goto unlock;
7923 goto out;
7924 }
7925
7926 /* this is a message we already processed, do nothing */
7927 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7928 goto unlock;
7929
7930 /* until the vf completes a reset it should not be
7931 * allowed to start any configuration.
7932 */
7933 if (msgbuf[0] == E1000_VF_RESET) {
7934 /* unlocks mailbox */
7935 igb_vf_reset_msg(adapter, vf);
7936 return;
7937 }
7938
7939 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7940 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7941 goto unlock;
7942 retval = -1;
7943 goto out;
7944 }
7945
7946 switch ((msgbuf[0] & 0xFFFF)) {
7947 case E1000_VF_SET_MAC_ADDR:
7948 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7949 break;
7950 case E1000_VF_SET_PROMISC:
7951 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7952 break;
7953 case E1000_VF_SET_MULTICAST:
7954 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7955 break;
7956 case E1000_VF_SET_LPE:
7957 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7958 break;
7959 case E1000_VF_SET_VLAN:
7960 retval = -1;
7961 if (vf_data->pf_vlan)
7962 dev_warn(&pdev->dev,
7963 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7964 vf);
7965 else
7966 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7967 break;
7968 default:
7969 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7970 retval = -1;
7971 break;
7972 }
7973
7974 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7975out:
7976 /* notify the VF of the results of what it sent us */
7977 if (retval)
7978 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7979 else
7980 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7981
7982 /* unlocks mailbox */
7983 igb_write_mbx(hw, msgbuf, 1, vf);
7984 return;
7985
7986unlock:
7987 igb_unlock_mbx(hw, vf);
7988}
7989
7990static void igb_msg_task(struct igb_adapter *adapter)
7991{
7992 struct e1000_hw *hw = &adapter->hw;
7993 unsigned long flags;
7994 u32 vf;
7995
7996 spin_lock_irqsave(&adapter->vfs_lock, flags);
7997 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7998 /* process any reset requests */
7999 if (!igb_check_for_rst(hw, vf))
8000 igb_vf_reset_event(adapter, vf);
8001
8002 /* process any messages pending */
8003 if (!igb_check_for_msg(hw, vf))
8004 igb_rcv_msg_from_vf(adapter, vf);
8005
8006 /* process any acks */
8007 if (!igb_check_for_ack(hw, vf))
8008 igb_rcv_ack_from_vf(adapter, vf);
8009 }
8010 spin_unlock_irqrestore(&adapter->vfs_lock, flags);
8011}
8012
8013/**
8014 * igb_set_uta - Set unicast filter table address
8015 * @adapter: board private structure
8016 * @set: boolean indicating if we are setting or clearing bits
8017 *
8018 * The unicast table address is a register array of 32-bit registers.
8019 * The table is meant to be used in a way similar to how the MTA is used
8020 * however due to certain limitations in the hardware it is necessary to
8021 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
8022 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
8023 **/
8024static void igb_set_uta(struct igb_adapter *adapter, bool set)
8025{
8026 struct e1000_hw *hw = &adapter->hw;
8027 u32 uta = set ? ~0 : 0;
8028 int i;
8029
8030 /* we only need to do this if VMDq is enabled */
8031 if (!adapter->vfs_allocated_count)
8032 return;
8033
8034 for (i = hw->mac.uta_reg_count; i--;)
8035 array_wr32(E1000_UTA, i, uta);
8036}
8037
8038/**
8039 * igb_intr_msi - Interrupt Handler
8040 * @irq: interrupt number
8041 * @data: pointer to a network interface device structure
8042 **/
8043static irqreturn_t igb_intr_msi(int irq, void *data)
8044{
8045 struct igb_adapter *adapter = data;
8046 struct igb_q_vector *q_vector = adapter->q_vector[0];
8047 struct e1000_hw *hw = &adapter->hw;
8048 /* read ICR disables interrupts using IAM */
8049 u32 icr = rd32(E1000_ICR);
8050
8051 igb_write_itr(q_vector);
8052
8053 if (icr & E1000_ICR_DRSTA)
8054 schedule_work(&adapter->reset_task);
8055
8056 if (icr & E1000_ICR_DOUTSYNC) {
8057 /* HW is reporting DMA is out of sync */
8058 adapter->stats.doosync++;
8059 }
8060
8061 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8062 hw->mac.get_link_status = 1;
8063 if (!test_bit(__IGB_DOWN, &adapter->state))
8064 mod_timer(&adapter->watchdog_timer, jiffies + 1);
8065 }
8066
8067 if (icr & E1000_ICR_TS)
8068 igb_tsync_interrupt(adapter);
8069
8070 napi_schedule(&q_vector->napi);
8071
8072 return IRQ_HANDLED;
8073}
8074
8075/**
8076 * igb_intr - Legacy Interrupt Handler
8077 * @irq: interrupt number
8078 * @data: pointer to a network interface device structure
8079 **/
8080static irqreturn_t igb_intr(int irq, void *data)
8081{
8082 struct igb_adapter *adapter = data;
8083 struct igb_q_vector *q_vector = adapter->q_vector[0];
8084 struct e1000_hw *hw = &adapter->hw;
8085 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
8086 * need for the IMC write
8087 */
8088 u32 icr = rd32(E1000_ICR);
8089
8090 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
8091 * not set, then the adapter didn't send an interrupt
8092 */
8093 if (!(icr & E1000_ICR_INT_ASSERTED))
8094 return IRQ_NONE;
8095
8096 igb_write_itr(q_vector);
8097
8098 if (icr & E1000_ICR_DRSTA)
8099 schedule_work(&adapter->reset_task);
8100
8101 if (icr & E1000_ICR_DOUTSYNC) {
8102 /* HW is reporting DMA is out of sync */
8103 adapter->stats.doosync++;
8104 }
8105
8106 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
8107 hw->mac.get_link_status = 1;
8108 /* guard against interrupt when we're going down */
8109 if (!test_bit(__IGB_DOWN, &adapter->state))
8110 mod_timer(&adapter->watchdog_timer, jiffies + 1);
8111 }
8112
8113 if (icr & E1000_ICR_TS)
8114 igb_tsync_interrupt(adapter);
8115
8116 napi_schedule(&q_vector->napi);
8117
8118 return IRQ_HANDLED;
8119}
8120
8121static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
8122{
8123 struct igb_adapter *adapter = q_vector->adapter;
8124 struct e1000_hw *hw = &adapter->hw;
8125
8126 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
8127 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
8128 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
8129 igb_set_itr(q_vector);
8130 else
8131 igb_update_ring_itr(q_vector);
8132 }
8133
8134 if (!test_bit(__IGB_DOWN, &adapter->state)) {
8135 if (adapter->flags & IGB_FLAG_HAS_MSIX)
8136 wr32(E1000_EIMS, q_vector->eims_value);
8137 else
8138 igb_irq_enable(adapter);
8139 }
8140}
8141
8142/**
8143 * igb_poll - NAPI Rx polling callback
8144 * @napi: napi polling structure
8145 * @budget: count of how many packets we should handle
8146 **/
8147static int igb_poll(struct napi_struct *napi, int budget)
8148{
8149 struct igb_q_vector *q_vector = container_of(napi,
8150 struct igb_q_vector,
8151 napi);
8152 bool clean_complete = true;
8153 int work_done = 0;
8154
8155#ifdef CONFIG_IGB_DCA
8156 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
8157 igb_update_dca(q_vector);
8158#endif
8159 if (q_vector->tx.ring)
8160 clean_complete = igb_clean_tx_irq(q_vector, budget);
8161
8162 if (q_vector->rx.ring) {
8163 int cleaned = igb_clean_rx_irq(q_vector, budget);
8164
8165 work_done += cleaned;
8166 if (cleaned >= budget)
8167 clean_complete = false;
8168 }
8169
8170 /* If all work not completed, return budget and keep polling */
8171 if (!clean_complete)
8172 return budget;
8173
8174 /* Exit the polling mode, but don't re-enable interrupts if stack might
8175 * poll us due to busy-polling
8176 */
8177 if (likely(napi_complete_done(napi, work_done)))
8178 igb_ring_irq_enable(q_vector);
8179
8180 return work_done;
8181}
8182
8183/**
8184 * igb_clean_tx_irq - Reclaim resources after transmit completes
8185 * @q_vector: pointer to q_vector containing needed info
8186 * @napi_budget: Used to determine if we are in netpoll
8187 *
8188 * returns true if ring is completely cleaned
8189 **/
8190static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8191{
8192 struct igb_adapter *adapter = q_vector->adapter;
8193 struct igb_ring *tx_ring = q_vector->tx.ring;
8194 struct igb_tx_buffer *tx_buffer;
8195 union e1000_adv_tx_desc *tx_desc;
8196 unsigned int total_bytes = 0, total_packets = 0;
8197 unsigned int budget = q_vector->tx.work_limit;
8198 unsigned int i = tx_ring->next_to_clean;
8199
8200 if (test_bit(__IGB_DOWN, &adapter->state))
8201 return true;
8202
8203 tx_buffer = &tx_ring->tx_buffer_info[i];
8204 tx_desc = IGB_TX_DESC(tx_ring, i);
8205 i -= tx_ring->count;
8206
8207 do {
8208 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8209
8210 /* if next_to_watch is not set then there is no work pending */
8211 if (!eop_desc)
8212 break;
8213
8214 /* prevent any other reads prior to eop_desc */
8215 smp_rmb();
8216
8217 /* if DD is not set pending work has not been completed */
8218 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8219 break;
8220
8221 /* clear next_to_watch to prevent false hangs */
8222 tx_buffer->next_to_watch = NULL;
8223
8224 /* update the statistics for this packet */
8225 total_bytes += tx_buffer->bytecount;
8226 total_packets += tx_buffer->gso_segs;
8227
8228 /* free the skb */
8229 if (tx_buffer->type == IGB_TYPE_SKB)
8230 napi_consume_skb(tx_buffer->skb, napi_budget);
8231 else
8232 xdp_return_frame(tx_buffer->xdpf);
8233
8234 /* unmap skb header data */
8235 dma_unmap_single(tx_ring->dev,
8236 dma_unmap_addr(tx_buffer, dma),
8237 dma_unmap_len(tx_buffer, len),
8238 DMA_TO_DEVICE);
8239
8240 /* clear tx_buffer data */
8241 dma_unmap_len_set(tx_buffer, len, 0);
8242
8243 /* clear last DMA location and unmap remaining buffers */
8244 while (tx_desc != eop_desc) {
8245 tx_buffer++;
8246 tx_desc++;
8247 i++;
8248 if (unlikely(!i)) {
8249 i -= tx_ring->count;
8250 tx_buffer = tx_ring->tx_buffer_info;
8251 tx_desc = IGB_TX_DESC(tx_ring, 0);
8252 }
8253
8254 /* unmap any remaining paged data */
8255 if (dma_unmap_len(tx_buffer, len)) {
8256 dma_unmap_page(tx_ring->dev,
8257 dma_unmap_addr(tx_buffer, dma),
8258 dma_unmap_len(tx_buffer, len),
8259 DMA_TO_DEVICE);
8260 dma_unmap_len_set(tx_buffer, len, 0);
8261 }
8262 }
8263
8264 /* move us one more past the eop_desc for start of next pkt */
8265 tx_buffer++;
8266 tx_desc++;
8267 i++;
8268 if (unlikely(!i)) {
8269 i -= tx_ring->count;
8270 tx_buffer = tx_ring->tx_buffer_info;
8271 tx_desc = IGB_TX_DESC(tx_ring, 0);
8272 }
8273
8274 /* issue prefetch for next Tx descriptor */
8275 prefetch(tx_desc);
8276
8277 /* update budget accounting */
8278 budget--;
8279 } while (likely(budget));
8280
8281 netdev_tx_completed_queue(txring_txq(tx_ring),
8282 total_packets, total_bytes);
8283 i += tx_ring->count;
8284 tx_ring->next_to_clean = i;
8285 u64_stats_update_begin(&tx_ring->tx_syncp);
8286 tx_ring->tx_stats.bytes += total_bytes;
8287 tx_ring->tx_stats.packets += total_packets;
8288 u64_stats_update_end(&tx_ring->tx_syncp);
8289 q_vector->tx.total_bytes += total_bytes;
8290 q_vector->tx.total_packets += total_packets;
8291
8292 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8293 struct e1000_hw *hw = &adapter->hw;
8294
8295 /* Detect a transmit hang in hardware, this serializes the
8296 * check with the clearing of time_stamp and movement of i
8297 */
8298 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8299 if (tx_buffer->next_to_watch &&
8300 time_after(jiffies, tx_buffer->time_stamp +
8301 (adapter->tx_timeout_factor * HZ)) &&
8302 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8303
8304 /* detected Tx unit hang */
8305 dev_err(tx_ring->dev,
8306 "Detected Tx Unit Hang\n"
8307 " Tx Queue <%d>\n"
8308 " TDH <%x>\n"
8309 " TDT <%x>\n"
8310 " next_to_use <%x>\n"
8311 " next_to_clean <%x>\n"
8312 "buffer_info[next_to_clean]\n"
8313 " time_stamp <%lx>\n"
8314 " next_to_watch <%p>\n"
8315 " jiffies <%lx>\n"
8316 " desc.status <%x>\n",
8317 tx_ring->queue_index,
8318 rd32(E1000_TDH(tx_ring->reg_idx)),
8319 readl(tx_ring->tail),
8320 tx_ring->next_to_use,
8321 tx_ring->next_to_clean,
8322 tx_buffer->time_stamp,
8323 tx_buffer->next_to_watch,
8324 jiffies,
8325 tx_buffer->next_to_watch->wb.status);
8326 netif_stop_subqueue(tx_ring->netdev,
8327 tx_ring->queue_index);
8328
8329 /* we are about to reset, no point in enabling stuff */
8330 return true;
8331 }
8332 }
8333
8334#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8335 if (unlikely(total_packets &&
8336 netif_carrier_ok(tx_ring->netdev) &&
8337 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8338 /* Make sure that anybody stopping the queue after this
8339 * sees the new next_to_clean.
8340 */
8341 smp_mb();
8342 if (__netif_subqueue_stopped(tx_ring->netdev,
8343 tx_ring->queue_index) &&
8344 !(test_bit(__IGB_DOWN, &adapter->state))) {
8345 netif_wake_subqueue(tx_ring->netdev,
8346 tx_ring->queue_index);
8347
8348 u64_stats_update_begin(&tx_ring->tx_syncp);
8349 tx_ring->tx_stats.restart_queue++;
8350 u64_stats_update_end(&tx_ring->tx_syncp);
8351 }
8352 }
8353
8354 return !!budget;
8355}
8356
8357/**
8358 * igb_reuse_rx_page - page flip buffer and store it back on the ring
8359 * @rx_ring: rx descriptor ring to store buffers on
8360 * @old_buff: donor buffer to have page reused
8361 *
8362 * Synchronizes page for reuse by the adapter
8363 **/
8364static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8365 struct igb_rx_buffer *old_buff)
8366{
8367 struct igb_rx_buffer *new_buff;
8368 u16 nta = rx_ring->next_to_alloc;
8369
8370 new_buff = &rx_ring->rx_buffer_info[nta];
8371
8372 /* update, and store next to alloc */
8373 nta++;
8374 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8375
8376 /* Transfer page from old buffer to new buffer.
8377 * Move each member individually to avoid possible store
8378 * forwarding stalls.
8379 */
8380 new_buff->dma = old_buff->dma;
8381 new_buff->page = old_buff->page;
8382 new_buff->page_offset = old_buff->page_offset;
8383 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
8384}
8385
8386static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8387 int rx_buf_pgcnt)
8388{
8389 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8390 struct page *page = rx_buffer->page;
8391
8392 /* avoid re-using remote and pfmemalloc pages */
8393 if (!dev_page_is_reusable(page))
8394 return false;
8395
8396#if (PAGE_SIZE < 8192)
8397 /* if we are only owner of page we can reuse it */
8398 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8399 return false;
8400#else
8401#define IGB_LAST_OFFSET \
8402 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8403
8404 if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8405 return false;
8406#endif
8407
8408 /* If we have drained the page fragment pool we need to update
8409 * the pagecnt_bias and page count so that we fully restock the
8410 * number of references the driver holds.
8411 */
8412 if (unlikely(pagecnt_bias == 1)) {
8413 page_ref_add(page, USHRT_MAX - 1);
8414 rx_buffer->pagecnt_bias = USHRT_MAX;
8415 }
8416
8417 return true;
8418}
8419
8420/**
8421 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8422 * @rx_ring: rx descriptor ring to transact packets on
8423 * @rx_buffer: buffer containing page to add
8424 * @skb: sk_buff to place the data into
8425 * @size: size of buffer to be added
8426 *
8427 * This function will add the data contained in rx_buffer->page to the skb.
8428 **/
8429static void igb_add_rx_frag(struct igb_ring *rx_ring,
8430 struct igb_rx_buffer *rx_buffer,
8431 struct sk_buff *skb,
8432 unsigned int size)
8433{
8434#if (PAGE_SIZE < 8192)
8435 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8436#else
8437 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8438 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8439 SKB_DATA_ALIGN(size);
8440#endif
8441 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8442 rx_buffer->page_offset, size, truesize);
8443#if (PAGE_SIZE < 8192)
8444 rx_buffer->page_offset ^= truesize;
8445#else
8446 rx_buffer->page_offset += truesize;
8447#endif
8448}
8449
8450static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8451 struct igb_rx_buffer *rx_buffer,
8452 struct xdp_buff *xdp,
8453 ktime_t timestamp)
8454{
8455#if (PAGE_SIZE < 8192)
8456 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8457#else
8458 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8459 xdp->data_hard_start);
8460#endif
8461 unsigned int size = xdp->data_end - xdp->data;
8462 unsigned int headlen;
8463 struct sk_buff *skb;
8464
8465 /* prefetch first cache line of first page */
8466 net_prefetch(xdp->data);
8467
8468 /* allocate a skb to store the frags */
8469 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8470 if (unlikely(!skb))
8471 return NULL;
8472
8473 if (timestamp)
8474 skb_hwtstamps(skb)->hwtstamp = timestamp;
8475
8476 /* Determine available headroom for copy */
8477 headlen = size;
8478 if (headlen > IGB_RX_HDR_LEN)
8479 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8480
8481 /* align pull length to size of long to optimize memcpy performance */
8482 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8483
8484 /* update all of the pointers */
8485 size -= headlen;
8486 if (size) {
8487 skb_add_rx_frag(skb, 0, rx_buffer->page,
8488 (xdp->data + headlen) - page_address(rx_buffer->page),
8489 size, truesize);
8490#if (PAGE_SIZE < 8192)
8491 rx_buffer->page_offset ^= truesize;
8492#else
8493 rx_buffer->page_offset += truesize;
8494#endif
8495 } else {
8496 rx_buffer->pagecnt_bias++;
8497 }
8498
8499 return skb;
8500}
8501
8502static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8503 struct igb_rx_buffer *rx_buffer,
8504 struct xdp_buff *xdp,
8505 ktime_t timestamp)
8506{
8507#if (PAGE_SIZE < 8192)
8508 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8509#else
8510 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8511 SKB_DATA_ALIGN(xdp->data_end -
8512 xdp->data_hard_start);
8513#endif
8514 unsigned int metasize = xdp->data - xdp->data_meta;
8515 struct sk_buff *skb;
8516
8517 /* prefetch first cache line of first page */
8518 net_prefetch(xdp->data_meta);
8519
8520 /* build an skb around the page buffer */
8521 skb = napi_build_skb(xdp->data_hard_start, truesize);
8522 if (unlikely(!skb))
8523 return NULL;
8524
8525 /* update pointers within the skb to store the data */
8526 skb_reserve(skb, xdp->data - xdp->data_hard_start);
8527 __skb_put(skb, xdp->data_end - xdp->data);
8528
8529 if (metasize)
8530 skb_metadata_set(skb, metasize);
8531
8532 if (timestamp)
8533 skb_hwtstamps(skb)->hwtstamp = timestamp;
8534
8535 /* update buffer offset */
8536#if (PAGE_SIZE < 8192)
8537 rx_buffer->page_offset ^= truesize;
8538#else
8539 rx_buffer->page_offset += truesize;
8540#endif
8541
8542 return skb;
8543}
8544
8545static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8546 struct igb_ring *rx_ring,
8547 struct xdp_buff *xdp)
8548{
8549 int err, result = IGB_XDP_PASS;
8550 struct bpf_prog *xdp_prog;
8551 u32 act;
8552
8553 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8554
8555 if (!xdp_prog)
8556 goto xdp_out;
8557
8558 prefetchw(xdp->data_hard_start); /* xdp_frame write */
8559
8560 act = bpf_prog_run_xdp(xdp_prog, xdp);
8561 switch (act) {
8562 case XDP_PASS:
8563 break;
8564 case XDP_TX:
8565 result = igb_xdp_xmit_back(adapter, xdp);
8566 if (result == IGB_XDP_CONSUMED)
8567 goto out_failure;
8568 break;
8569 case XDP_REDIRECT:
8570 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8571 if (err)
8572 goto out_failure;
8573 result = IGB_XDP_REDIR;
8574 break;
8575 default:
8576 bpf_warn_invalid_xdp_action(adapter->netdev, xdp_prog, act);
8577 fallthrough;
8578 case XDP_ABORTED:
8579out_failure:
8580 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8581 fallthrough;
8582 case XDP_DROP:
8583 result = IGB_XDP_CONSUMED;
8584 break;
8585 }
8586xdp_out:
8587 return ERR_PTR(-result);
8588}
8589
8590static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8591 unsigned int size)
8592{
8593 unsigned int truesize;
8594
8595#if (PAGE_SIZE < 8192)
8596 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8597#else
8598 truesize = ring_uses_build_skb(rx_ring) ?
8599 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8600 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8601 SKB_DATA_ALIGN(size);
8602#endif
8603 return truesize;
8604}
8605
8606static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8607 struct igb_rx_buffer *rx_buffer,
8608 unsigned int size)
8609{
8610 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8611#if (PAGE_SIZE < 8192)
8612 rx_buffer->page_offset ^= truesize;
8613#else
8614 rx_buffer->page_offset += truesize;
8615#endif
8616}
8617
8618static inline void igb_rx_checksum(struct igb_ring *ring,
8619 union e1000_adv_rx_desc *rx_desc,
8620 struct sk_buff *skb)
8621{
8622 skb_checksum_none_assert(skb);
8623
8624 /* Ignore Checksum bit is set */
8625 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8626 return;
8627
8628 /* Rx checksum disabled via ethtool */
8629 if (!(ring->netdev->features & NETIF_F_RXCSUM))
8630 return;
8631
8632 /* TCP/UDP checksum error bit is set */
8633 if (igb_test_staterr(rx_desc,
8634 E1000_RXDEXT_STATERR_TCPE |
8635 E1000_RXDEXT_STATERR_IPE)) {
8636 /* work around errata with sctp packets where the TCPE aka
8637 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8638 * packets, (aka let the stack check the crc32c)
8639 */
8640 if (!((skb->len == 60) &&
8641 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8642 u64_stats_update_begin(&ring->rx_syncp);
8643 ring->rx_stats.csum_err++;
8644 u64_stats_update_end(&ring->rx_syncp);
8645 }
8646 /* let the stack verify checksum errors */
8647 return;
8648 }
8649 /* It must be a TCP or UDP packet with a valid checksum */
8650 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8651 E1000_RXD_STAT_UDPCS))
8652 skb->ip_summed = CHECKSUM_UNNECESSARY;
8653
8654 dev_dbg(ring->dev, "cksum success: bits %08X\n",
8655 le32_to_cpu(rx_desc->wb.upper.status_error));
8656}
8657
8658static inline void igb_rx_hash(struct igb_ring *ring,
8659 union e1000_adv_rx_desc *rx_desc,
8660 struct sk_buff *skb)
8661{
8662 if (ring->netdev->features & NETIF_F_RXHASH)
8663 skb_set_hash(skb,
8664 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8665 PKT_HASH_TYPE_L3);
8666}
8667
8668/**
8669 * igb_is_non_eop - process handling of non-EOP buffers
8670 * @rx_ring: Rx ring being processed
8671 * @rx_desc: Rx descriptor for current buffer
8672 *
8673 * This function updates next to clean. If the buffer is an EOP buffer
8674 * this function exits returning false, otherwise it will place the
8675 * sk_buff in the next buffer to be chained and return true indicating
8676 * that this is in fact a non-EOP buffer.
8677 **/
8678static bool igb_is_non_eop(struct igb_ring *rx_ring,
8679 union e1000_adv_rx_desc *rx_desc)
8680{
8681 u32 ntc = rx_ring->next_to_clean + 1;
8682
8683 /* fetch, update, and store next to clean */
8684 ntc = (ntc < rx_ring->count) ? ntc : 0;
8685 rx_ring->next_to_clean = ntc;
8686
8687 prefetch(IGB_RX_DESC(rx_ring, ntc));
8688
8689 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8690 return false;
8691
8692 return true;
8693}
8694
8695/**
8696 * igb_cleanup_headers - Correct corrupted or empty headers
8697 * @rx_ring: rx descriptor ring packet is being transacted on
8698 * @rx_desc: pointer to the EOP Rx descriptor
8699 * @skb: pointer to current skb being fixed
8700 *
8701 * Address the case where we are pulling data in on pages only
8702 * and as such no data is present in the skb header.
8703 *
8704 * In addition if skb is not at least 60 bytes we need to pad it so that
8705 * it is large enough to qualify as a valid Ethernet frame.
8706 *
8707 * Returns true if an error was encountered and skb was freed.
8708 **/
8709static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8710 union e1000_adv_rx_desc *rx_desc,
8711 struct sk_buff *skb)
8712{
8713 /* XDP packets use error pointer so abort at this point */
8714 if (IS_ERR(skb))
8715 return true;
8716
8717 if (unlikely((igb_test_staterr(rx_desc,
8718 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8719 struct net_device *netdev = rx_ring->netdev;
8720 if (!(netdev->features & NETIF_F_RXALL)) {
8721 dev_kfree_skb_any(skb);
8722 return true;
8723 }
8724 }
8725
8726 /* if eth_skb_pad returns an error the skb was freed */
8727 if (eth_skb_pad(skb))
8728 return true;
8729
8730 return false;
8731}
8732
8733/**
8734 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
8735 * @rx_ring: rx descriptor ring packet is being transacted on
8736 * @rx_desc: pointer to the EOP Rx descriptor
8737 * @skb: pointer to current skb being populated
8738 *
8739 * This function checks the ring, descriptor, and packet information in
8740 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
8741 * other fields within the skb.
8742 **/
8743static void igb_process_skb_fields(struct igb_ring *rx_ring,
8744 union e1000_adv_rx_desc *rx_desc,
8745 struct sk_buff *skb)
8746{
8747 struct net_device *dev = rx_ring->netdev;
8748
8749 igb_rx_hash(rx_ring, rx_desc, skb);
8750
8751 igb_rx_checksum(rx_ring, rx_desc, skb);
8752
8753 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8754 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8755 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8756
8757 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8758 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8759 u16 vid;
8760
8761 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8762 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8763 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8764 else
8765 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8766
8767 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8768 }
8769
8770 skb_record_rx_queue(skb, rx_ring->queue_index);
8771
8772 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8773}
8774
8775static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8776{
8777 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8778}
8779
8780static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8781 const unsigned int size, int *rx_buf_pgcnt)
8782{
8783 struct igb_rx_buffer *rx_buffer;
8784
8785 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8786 *rx_buf_pgcnt =
8787#if (PAGE_SIZE < 8192)
8788 page_count(rx_buffer->page);
8789#else
8790 0;
8791#endif
8792 prefetchw(rx_buffer->page);
8793
8794 /* we are reusing so sync this buffer for CPU use */
8795 dma_sync_single_range_for_cpu(rx_ring->dev,
8796 rx_buffer->dma,
8797 rx_buffer->page_offset,
8798 size,
8799 DMA_FROM_DEVICE);
8800
8801 rx_buffer->pagecnt_bias--;
8802
8803 return rx_buffer;
8804}
8805
8806static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8807 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8808{
8809 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8810 /* hand second half of page back to the ring */
8811 igb_reuse_rx_page(rx_ring, rx_buffer);
8812 } else {
8813 /* We are not reusing the buffer so unmap it and free
8814 * any references we are holding to it
8815 */
8816 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8817 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8818 IGB_RX_DMA_ATTR);
8819 __page_frag_cache_drain(rx_buffer->page,
8820 rx_buffer->pagecnt_bias);
8821 }
8822
8823 /* clear contents of rx_buffer */
8824 rx_buffer->page = NULL;
8825}
8826
8827static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8828{
8829 struct igb_adapter *adapter = q_vector->adapter;
8830 struct igb_ring *rx_ring = q_vector->rx.ring;
8831 struct sk_buff *skb = rx_ring->skb;
8832 unsigned int total_bytes = 0, total_packets = 0;
8833 u16 cleaned_count = igb_desc_unused(rx_ring);
8834 unsigned int xdp_xmit = 0;
8835 struct xdp_buff xdp;
8836 u32 frame_sz = 0;
8837 int rx_buf_pgcnt;
8838
8839 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8840#if (PAGE_SIZE < 8192)
8841 frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8842#endif
8843 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8844
8845 while (likely(total_packets < budget)) {
8846 union e1000_adv_rx_desc *rx_desc;
8847 struct igb_rx_buffer *rx_buffer;
8848 ktime_t timestamp = 0;
8849 int pkt_offset = 0;
8850 unsigned int size;
8851 void *pktbuf;
8852
8853 /* return some buffers to hardware, one at a time is too slow */
8854 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8855 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8856 cleaned_count = 0;
8857 }
8858
8859 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8860 size = le16_to_cpu(rx_desc->wb.upper.length);
8861 if (!size)
8862 break;
8863
8864 /* This memory barrier is needed to keep us from reading
8865 * any other fields out of the rx_desc until we know the
8866 * descriptor has been written back
8867 */
8868 dma_rmb();
8869
8870 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8871 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8872
8873 /* pull rx packet timestamp if available and valid */
8874 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8875 int ts_hdr_len;
8876
8877 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8878 pktbuf, ×tamp);
8879
8880 pkt_offset += ts_hdr_len;
8881 size -= ts_hdr_len;
8882 }
8883
8884 /* retrieve a buffer from the ring */
8885 if (!skb) {
8886 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8887 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8888
8889 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8890 xdp_buff_clear_frags_flag(&xdp);
8891#if (PAGE_SIZE > 4096)
8892 /* At larger PAGE_SIZE, frame_sz depend on len size */
8893 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8894#endif
8895 skb = igb_run_xdp(adapter, rx_ring, &xdp);
8896 }
8897
8898 if (IS_ERR(skb)) {
8899 unsigned int xdp_res = -PTR_ERR(skb);
8900
8901 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8902 xdp_xmit |= xdp_res;
8903 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8904 } else {
8905 rx_buffer->pagecnt_bias++;
8906 }
8907 total_packets++;
8908 total_bytes += size;
8909 } else if (skb)
8910 igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8911 else if (ring_uses_build_skb(rx_ring))
8912 skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8913 timestamp);
8914 else
8915 skb = igb_construct_skb(rx_ring, rx_buffer,
8916 &xdp, timestamp);
8917
8918 /* exit if we failed to retrieve a buffer */
8919 if (!skb) {
8920 rx_ring->rx_stats.alloc_failed++;
8921 rx_buffer->pagecnt_bias++;
8922 break;
8923 }
8924
8925 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8926 cleaned_count++;
8927
8928 /* fetch next buffer in frame if non-eop */
8929 if (igb_is_non_eop(rx_ring, rx_desc))
8930 continue;
8931
8932 /* verify the packet layout is correct */
8933 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8934 skb = NULL;
8935 continue;
8936 }
8937
8938 /* probably a little skewed due to removing CRC */
8939 total_bytes += skb->len;
8940
8941 /* populate checksum, timestamp, VLAN, and protocol */
8942 igb_process_skb_fields(rx_ring, rx_desc, skb);
8943
8944 napi_gro_receive(&q_vector->napi, skb);
8945
8946 /* reset skb pointer */
8947 skb = NULL;
8948
8949 /* update budget accounting */
8950 total_packets++;
8951 }
8952
8953 /* place incomplete frames back on ring for completion */
8954 rx_ring->skb = skb;
8955
8956 if (xdp_xmit & IGB_XDP_REDIR)
8957 xdp_do_flush();
8958
8959 if (xdp_xmit & IGB_XDP_TX) {
8960 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
8961
8962 igb_xdp_ring_update_tail(tx_ring);
8963 }
8964
8965 u64_stats_update_begin(&rx_ring->rx_syncp);
8966 rx_ring->rx_stats.packets += total_packets;
8967 rx_ring->rx_stats.bytes += total_bytes;
8968 u64_stats_update_end(&rx_ring->rx_syncp);
8969 q_vector->rx.total_packets += total_packets;
8970 q_vector->rx.total_bytes += total_bytes;
8971
8972 if (cleaned_count)
8973 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8974
8975 return total_packets;
8976}
8977
8978static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8979 struct igb_rx_buffer *bi)
8980{
8981 struct page *page = bi->page;
8982 dma_addr_t dma;
8983
8984 /* since we are recycling buffers we should seldom need to alloc */
8985 if (likely(page))
8986 return true;
8987
8988 /* alloc new page for storage */
8989 page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8990 if (unlikely(!page)) {
8991 rx_ring->rx_stats.alloc_failed++;
8992 return false;
8993 }
8994
8995 /* map page for use */
8996 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8997 igb_rx_pg_size(rx_ring),
8998 DMA_FROM_DEVICE,
8999 IGB_RX_DMA_ATTR);
9000
9001 /* if mapping failed free memory back to system since
9002 * there isn't much point in holding memory we can't use
9003 */
9004 if (dma_mapping_error(rx_ring->dev, dma)) {
9005 __free_pages(page, igb_rx_pg_order(rx_ring));
9006
9007 rx_ring->rx_stats.alloc_failed++;
9008 return false;
9009 }
9010
9011 bi->dma = dma;
9012 bi->page = page;
9013 bi->page_offset = igb_rx_offset(rx_ring);
9014 page_ref_add(page, USHRT_MAX - 1);
9015 bi->pagecnt_bias = USHRT_MAX;
9016
9017 return true;
9018}
9019
9020/**
9021 * igb_alloc_rx_buffers - Replace used receive buffers
9022 * @rx_ring: rx descriptor ring to allocate new receive buffers
9023 * @cleaned_count: count of buffers to allocate
9024 **/
9025void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9026{
9027 union e1000_adv_rx_desc *rx_desc;
9028 struct igb_rx_buffer *bi;
9029 u16 i = rx_ring->next_to_use;
9030 u16 bufsz;
9031
9032 /* nothing to do */
9033 if (!cleaned_count)
9034 return;
9035
9036 rx_desc = IGB_RX_DESC(rx_ring, i);
9037 bi = &rx_ring->rx_buffer_info[i];
9038 i -= rx_ring->count;
9039
9040 bufsz = igb_rx_bufsz(rx_ring);
9041
9042 do {
9043 if (!igb_alloc_mapped_page(rx_ring, bi))
9044 break;
9045
9046 /* sync the buffer for use by the device */
9047 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
9048 bi->page_offset, bufsz,
9049 DMA_FROM_DEVICE);
9050
9051 /* Refresh the desc even if buffer_addrs didn't change
9052 * because each write-back erases this info.
9053 */
9054 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9055
9056 rx_desc++;
9057 bi++;
9058 i++;
9059 if (unlikely(!i)) {
9060 rx_desc = IGB_RX_DESC(rx_ring, 0);
9061 bi = rx_ring->rx_buffer_info;
9062 i -= rx_ring->count;
9063 }
9064
9065 /* clear the length for the next_to_use descriptor */
9066 rx_desc->wb.upper.length = 0;
9067
9068 cleaned_count--;
9069 } while (cleaned_count);
9070
9071 i += rx_ring->count;
9072
9073 if (rx_ring->next_to_use != i) {
9074 /* record the next descriptor to use */
9075 rx_ring->next_to_use = i;
9076
9077 /* update next to alloc since we have filled the ring */
9078 rx_ring->next_to_alloc = i;
9079
9080 /* Force memory writes to complete before letting h/w
9081 * know there are new descriptors to fetch. (Only
9082 * applicable for weak-ordered memory model archs,
9083 * such as IA-64).
9084 */
9085 dma_wmb();
9086 writel(i, rx_ring->tail);
9087 }
9088}
9089
9090/**
9091 * igb_mii_ioctl -
9092 * @netdev: pointer to netdev struct
9093 * @ifr: interface structure
9094 * @cmd: ioctl command to execute
9095 **/
9096static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9097{
9098 struct igb_adapter *adapter = netdev_priv(netdev);
9099 struct mii_ioctl_data *data = if_mii(ifr);
9100
9101 if (adapter->hw.phy.media_type != e1000_media_type_copper)
9102 return -EOPNOTSUPP;
9103
9104 switch (cmd) {
9105 case SIOCGMIIPHY:
9106 data->phy_id = adapter->hw.phy.addr;
9107 break;
9108 case SIOCGMIIREG:
9109 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9110 &data->val_out))
9111 return -EIO;
9112 break;
9113 case SIOCSMIIREG:
9114 default:
9115 return -EOPNOTSUPP;
9116 }
9117 return 0;
9118}
9119
9120/**
9121 * igb_ioctl -
9122 * @netdev: pointer to netdev struct
9123 * @ifr: interface structure
9124 * @cmd: ioctl command to execute
9125 **/
9126static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
9127{
9128 switch (cmd) {
9129 case SIOCGMIIPHY:
9130 case SIOCGMIIREG:
9131 case SIOCSMIIREG:
9132 return igb_mii_ioctl(netdev, ifr, cmd);
9133 case SIOCGHWTSTAMP:
9134 return igb_ptp_get_ts_config(netdev, ifr);
9135 case SIOCSHWTSTAMP:
9136 return igb_ptp_set_ts_config(netdev, ifr);
9137 default:
9138 return -EOPNOTSUPP;
9139 }
9140}
9141
9142void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9143{
9144 struct igb_adapter *adapter = hw->back;
9145
9146 pci_read_config_word(adapter->pdev, reg, value);
9147}
9148
9149void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
9150{
9151 struct igb_adapter *adapter = hw->back;
9152
9153 pci_write_config_word(adapter->pdev, reg, *value);
9154}
9155
9156s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9157{
9158 struct igb_adapter *adapter = hw->back;
9159
9160 if (pcie_capability_read_word(adapter->pdev, reg, value))
9161 return -E1000_ERR_CONFIG;
9162
9163 return 0;
9164}
9165
9166s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9167{
9168 struct igb_adapter *adapter = hw->back;
9169
9170 if (pcie_capability_write_word(adapter->pdev, reg, *value))
9171 return -E1000_ERR_CONFIG;
9172
9173 return 0;
9174}
9175
9176static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9177{
9178 struct igb_adapter *adapter = netdev_priv(netdev);
9179 struct e1000_hw *hw = &adapter->hw;
9180 u32 ctrl, rctl;
9181 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9182
9183 if (enable) {
9184 /* enable VLAN tag insert/strip */
9185 ctrl = rd32(E1000_CTRL);
9186 ctrl |= E1000_CTRL_VME;
9187 wr32(E1000_CTRL, ctrl);
9188
9189 /* Disable CFI check */
9190 rctl = rd32(E1000_RCTL);
9191 rctl &= ~E1000_RCTL_CFIEN;
9192 wr32(E1000_RCTL, rctl);
9193 } else {
9194 /* disable VLAN tag insert/strip */
9195 ctrl = rd32(E1000_CTRL);
9196 ctrl &= ~E1000_CTRL_VME;
9197 wr32(E1000_CTRL, ctrl);
9198 }
9199
9200 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9201}
9202
9203static int igb_vlan_rx_add_vid(struct net_device *netdev,
9204 __be16 proto, u16 vid)
9205{
9206 struct igb_adapter *adapter = netdev_priv(netdev);
9207 struct e1000_hw *hw = &adapter->hw;
9208 int pf_id = adapter->vfs_allocated_count;
9209
9210 /* add the filter since PF can receive vlans w/o entry in vlvf */
9211 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9212 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9213
9214 set_bit(vid, adapter->active_vlans);
9215
9216 return 0;
9217}
9218
9219static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9220 __be16 proto, u16 vid)
9221{
9222 struct igb_adapter *adapter = netdev_priv(netdev);
9223 int pf_id = adapter->vfs_allocated_count;
9224 struct e1000_hw *hw = &adapter->hw;
9225
9226 /* remove VID from filter table */
9227 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9228 igb_vfta_set(hw, vid, pf_id, false, true);
9229
9230 clear_bit(vid, adapter->active_vlans);
9231
9232 return 0;
9233}
9234
9235static void igb_restore_vlan(struct igb_adapter *adapter)
9236{
9237 u16 vid = 1;
9238
9239 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9240 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9241
9242 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9243 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9244}
9245
9246int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9247{
9248 struct pci_dev *pdev = adapter->pdev;
9249 struct e1000_mac_info *mac = &adapter->hw.mac;
9250
9251 mac->autoneg = 0;
9252
9253 /* Make sure dplx is at most 1 bit and lsb of speed is not set
9254 * for the switch() below to work
9255 */
9256 if ((spd & 1) || (dplx & ~1))
9257 goto err_inval;
9258
9259 /* Fiber NIC's only allow 1000 gbps Full duplex
9260 * and 100Mbps Full duplex for 100baseFx sfp
9261 */
9262 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9263 switch (spd + dplx) {
9264 case SPEED_10 + DUPLEX_HALF:
9265 case SPEED_10 + DUPLEX_FULL:
9266 case SPEED_100 + DUPLEX_HALF:
9267 goto err_inval;
9268 default:
9269 break;
9270 }
9271 }
9272
9273 switch (spd + dplx) {
9274 case SPEED_10 + DUPLEX_HALF:
9275 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9276 break;
9277 case SPEED_10 + DUPLEX_FULL:
9278 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9279 break;
9280 case SPEED_100 + DUPLEX_HALF:
9281 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9282 break;
9283 case SPEED_100 + DUPLEX_FULL:
9284 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9285 break;
9286 case SPEED_1000 + DUPLEX_FULL:
9287 mac->autoneg = 1;
9288 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9289 break;
9290 case SPEED_1000 + DUPLEX_HALF: /* not supported */
9291 default:
9292 goto err_inval;
9293 }
9294
9295 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9296 adapter->hw.phy.mdix = AUTO_ALL_MODES;
9297
9298 return 0;
9299
9300err_inval:
9301 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9302 return -EINVAL;
9303}
9304
9305static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9306 bool runtime)
9307{
9308 struct net_device *netdev = pci_get_drvdata(pdev);
9309 struct igb_adapter *adapter = netdev_priv(netdev);
9310 struct e1000_hw *hw = &adapter->hw;
9311 u32 ctrl, rctl, status;
9312 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9313 bool wake;
9314
9315 rtnl_lock();
9316 netif_device_detach(netdev);
9317
9318 if (netif_running(netdev))
9319 __igb_close(netdev, true);
9320
9321 igb_ptp_suspend(adapter);
9322
9323 igb_clear_interrupt_scheme(adapter);
9324 rtnl_unlock();
9325
9326 status = rd32(E1000_STATUS);
9327 if (status & E1000_STATUS_LU)
9328 wufc &= ~E1000_WUFC_LNKC;
9329
9330 if (wufc) {
9331 igb_setup_rctl(adapter);
9332 igb_set_rx_mode(netdev);
9333
9334 /* turn on all-multi mode if wake on multicast is enabled */
9335 if (wufc & E1000_WUFC_MC) {
9336 rctl = rd32(E1000_RCTL);
9337 rctl |= E1000_RCTL_MPE;
9338 wr32(E1000_RCTL, rctl);
9339 }
9340
9341 ctrl = rd32(E1000_CTRL);
9342 ctrl |= E1000_CTRL_ADVD3WUC;
9343 wr32(E1000_CTRL, ctrl);
9344
9345 /* Allow time for pending master requests to run */
9346 igb_disable_pcie_master(hw);
9347
9348 wr32(E1000_WUC, E1000_WUC_PME_EN);
9349 wr32(E1000_WUFC, wufc);
9350 } else {
9351 wr32(E1000_WUC, 0);
9352 wr32(E1000_WUFC, 0);
9353 }
9354
9355 wake = wufc || adapter->en_mng_pt;
9356 if (!wake)
9357 igb_power_down_link(adapter);
9358 else
9359 igb_power_up_link(adapter);
9360
9361 if (enable_wake)
9362 *enable_wake = wake;
9363
9364 /* Release control of h/w to f/w. If f/w is AMT enabled, this
9365 * would have already happened in close and is redundant.
9366 */
9367 igb_release_hw_control(adapter);
9368
9369 pci_disable_device(pdev);
9370
9371 return 0;
9372}
9373
9374static void igb_deliver_wake_packet(struct net_device *netdev)
9375{
9376 struct igb_adapter *adapter = netdev_priv(netdev);
9377 struct e1000_hw *hw = &adapter->hw;
9378 struct sk_buff *skb;
9379 u32 wupl;
9380
9381 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9382
9383 /* WUPM stores only the first 128 bytes of the wake packet.
9384 * Read the packet only if we have the whole thing.
9385 */
9386 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9387 return;
9388
9389 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9390 if (!skb)
9391 return;
9392
9393 skb_put(skb, wupl);
9394
9395 /* Ensure reads are 32-bit aligned */
9396 wupl = roundup(wupl, 4);
9397
9398 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9399
9400 skb->protocol = eth_type_trans(skb, netdev);
9401 netif_rx(skb);
9402}
9403
9404static int __maybe_unused igb_suspend(struct device *dev)
9405{
9406 return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9407}
9408
9409static int __maybe_unused __igb_resume(struct device *dev, bool rpm)
9410{
9411 struct pci_dev *pdev = to_pci_dev(dev);
9412 struct net_device *netdev = pci_get_drvdata(pdev);
9413 struct igb_adapter *adapter = netdev_priv(netdev);
9414 struct e1000_hw *hw = &adapter->hw;
9415 u32 err, val;
9416
9417 pci_set_power_state(pdev, PCI_D0);
9418 pci_restore_state(pdev);
9419 pci_save_state(pdev);
9420
9421 if (!pci_device_is_present(pdev))
9422 return -ENODEV;
9423 err = pci_enable_device_mem(pdev);
9424 if (err) {
9425 dev_err(&pdev->dev,
9426 "igb: Cannot enable PCI device from suspend\n");
9427 return err;
9428 }
9429 pci_set_master(pdev);
9430
9431 pci_enable_wake(pdev, PCI_D3hot, 0);
9432 pci_enable_wake(pdev, PCI_D3cold, 0);
9433
9434 if (igb_init_interrupt_scheme(adapter, true)) {
9435 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9436 return -ENOMEM;
9437 }
9438
9439 igb_reset(adapter);
9440
9441 /* let the f/w know that the h/w is now under the control of the
9442 * driver.
9443 */
9444 igb_get_hw_control(adapter);
9445
9446 val = rd32(E1000_WUS);
9447 if (val & WAKE_PKT_WUS)
9448 igb_deliver_wake_packet(netdev);
9449
9450 wr32(E1000_WUS, ~0);
9451
9452 if (!rpm)
9453 rtnl_lock();
9454 if (!err && netif_running(netdev))
9455 err = __igb_open(netdev, true);
9456
9457 if (!err)
9458 netif_device_attach(netdev);
9459 if (!rpm)
9460 rtnl_unlock();
9461
9462 return err;
9463}
9464
9465static int __maybe_unused igb_resume(struct device *dev)
9466{
9467 return __igb_resume(dev, false);
9468}
9469
9470static int __maybe_unused igb_runtime_idle(struct device *dev)
9471{
9472 struct net_device *netdev = dev_get_drvdata(dev);
9473 struct igb_adapter *adapter = netdev_priv(netdev);
9474
9475 if (!igb_has_link(adapter))
9476 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9477
9478 return -EBUSY;
9479}
9480
9481static int __maybe_unused igb_runtime_suspend(struct device *dev)
9482{
9483 return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9484}
9485
9486static int __maybe_unused igb_runtime_resume(struct device *dev)
9487{
9488 return __igb_resume(dev, true);
9489}
9490
9491static void igb_shutdown(struct pci_dev *pdev)
9492{
9493 bool wake;
9494
9495 __igb_shutdown(pdev, &wake, 0);
9496
9497 if (system_state == SYSTEM_POWER_OFF) {
9498 pci_wake_from_d3(pdev, wake);
9499 pci_set_power_state(pdev, PCI_D3hot);
9500 }
9501}
9502
9503#ifdef CONFIG_PCI_IOV
9504static int igb_sriov_reinit(struct pci_dev *dev)
9505{
9506 struct net_device *netdev = pci_get_drvdata(dev);
9507 struct igb_adapter *adapter = netdev_priv(netdev);
9508 struct pci_dev *pdev = adapter->pdev;
9509
9510 rtnl_lock();
9511
9512 if (netif_running(netdev))
9513 igb_close(netdev);
9514 else
9515 igb_reset(adapter);
9516
9517 igb_clear_interrupt_scheme(adapter);
9518
9519 igb_init_queue_configuration(adapter);
9520
9521 if (igb_init_interrupt_scheme(adapter, true)) {
9522 rtnl_unlock();
9523 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9524 return -ENOMEM;
9525 }
9526
9527 if (netif_running(netdev))
9528 igb_open(netdev);
9529
9530 rtnl_unlock();
9531
9532 return 0;
9533}
9534
9535static int igb_pci_disable_sriov(struct pci_dev *dev)
9536{
9537 int err = igb_disable_sriov(dev);
9538
9539 if (!err)
9540 err = igb_sriov_reinit(dev);
9541
9542 return err;
9543}
9544
9545static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9546{
9547 int err = igb_enable_sriov(dev, num_vfs);
9548
9549 if (err)
9550 goto out;
9551
9552 err = igb_sriov_reinit(dev);
9553 if (!err)
9554 return num_vfs;
9555
9556out:
9557 return err;
9558}
9559
9560#endif
9561static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9562{
9563#ifdef CONFIG_PCI_IOV
9564 if (num_vfs == 0)
9565 return igb_pci_disable_sriov(dev);
9566 else
9567 return igb_pci_enable_sriov(dev, num_vfs);
9568#endif
9569 return 0;
9570}
9571
9572/**
9573 * igb_io_error_detected - called when PCI error is detected
9574 * @pdev: Pointer to PCI device
9575 * @state: The current pci connection state
9576 *
9577 * This function is called after a PCI bus error affecting
9578 * this device has been detected.
9579 **/
9580static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9581 pci_channel_state_t state)
9582{
9583 struct net_device *netdev = pci_get_drvdata(pdev);
9584 struct igb_adapter *adapter = netdev_priv(netdev);
9585
9586 netif_device_detach(netdev);
9587
9588 if (state == pci_channel_io_perm_failure)
9589 return PCI_ERS_RESULT_DISCONNECT;
9590
9591 if (netif_running(netdev))
9592 igb_down(adapter);
9593 pci_disable_device(pdev);
9594
9595 /* Request a slot reset. */
9596 return PCI_ERS_RESULT_NEED_RESET;
9597}
9598
9599/**
9600 * igb_io_slot_reset - called after the pci bus has been reset.
9601 * @pdev: Pointer to PCI device
9602 *
9603 * Restart the card from scratch, as if from a cold-boot. Implementation
9604 * resembles the first-half of the __igb_resume routine.
9605 **/
9606static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9607{
9608 struct net_device *netdev = pci_get_drvdata(pdev);
9609 struct igb_adapter *adapter = netdev_priv(netdev);
9610 struct e1000_hw *hw = &adapter->hw;
9611 pci_ers_result_t result;
9612
9613 if (pci_enable_device_mem(pdev)) {
9614 dev_err(&pdev->dev,
9615 "Cannot re-enable PCI device after reset.\n");
9616 result = PCI_ERS_RESULT_DISCONNECT;
9617 } else {
9618 pci_set_master(pdev);
9619 pci_restore_state(pdev);
9620 pci_save_state(pdev);
9621
9622 pci_enable_wake(pdev, PCI_D3hot, 0);
9623 pci_enable_wake(pdev, PCI_D3cold, 0);
9624
9625 /* In case of PCI error, adapter lose its HW address
9626 * so we should re-assign it here.
9627 */
9628 hw->hw_addr = adapter->io_addr;
9629
9630 igb_reset(adapter);
9631 wr32(E1000_WUS, ~0);
9632 result = PCI_ERS_RESULT_RECOVERED;
9633 }
9634
9635 return result;
9636}
9637
9638/**
9639 * igb_io_resume - called when traffic can start flowing again.
9640 * @pdev: Pointer to PCI device
9641 *
9642 * This callback is called when the error recovery driver tells us that
9643 * its OK to resume normal operation. Implementation resembles the
9644 * second-half of the __igb_resume routine.
9645 */
9646static void igb_io_resume(struct pci_dev *pdev)
9647{
9648 struct net_device *netdev = pci_get_drvdata(pdev);
9649 struct igb_adapter *adapter = netdev_priv(netdev);
9650
9651 if (netif_running(netdev)) {
9652 if (igb_up(adapter)) {
9653 dev_err(&pdev->dev, "igb_up failed after reset\n");
9654 return;
9655 }
9656 }
9657
9658 netif_device_attach(netdev);
9659
9660 /* let the f/w know that the h/w is now under the control of the
9661 * driver.
9662 */
9663 igb_get_hw_control(adapter);
9664}
9665
9666/**
9667 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9668 * @adapter: Pointer to adapter structure
9669 * @index: Index of the RAR entry which need to be synced with MAC table
9670 **/
9671static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9672{
9673 struct e1000_hw *hw = &adapter->hw;
9674 u32 rar_low, rar_high;
9675 u8 *addr = adapter->mac_table[index].addr;
9676
9677 /* HW expects these to be in network order when they are plugged
9678 * into the registers which are little endian. In order to guarantee
9679 * that ordering we need to do an leXX_to_cpup here in order to be
9680 * ready for the byteswap that occurs with writel
9681 */
9682 rar_low = le32_to_cpup((__le32 *)(addr));
9683 rar_high = le16_to_cpup((__le16 *)(addr + 4));
9684
9685 /* Indicate to hardware the Address is Valid. */
9686 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9687 if (is_valid_ether_addr(addr))
9688 rar_high |= E1000_RAH_AV;
9689
9690 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9691 rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9692
9693 switch (hw->mac.type) {
9694 case e1000_82575:
9695 case e1000_i210:
9696 if (adapter->mac_table[index].state &
9697 IGB_MAC_STATE_QUEUE_STEERING)
9698 rar_high |= E1000_RAH_QSEL_ENABLE;
9699
9700 rar_high |= E1000_RAH_POOL_1 *
9701 adapter->mac_table[index].queue;
9702 break;
9703 default:
9704 rar_high |= E1000_RAH_POOL_1 <<
9705 adapter->mac_table[index].queue;
9706 break;
9707 }
9708 }
9709
9710 wr32(E1000_RAL(index), rar_low);
9711 wrfl();
9712 wr32(E1000_RAH(index), rar_high);
9713 wrfl();
9714}
9715
9716static int igb_set_vf_mac(struct igb_adapter *adapter,
9717 int vf, unsigned char *mac_addr)
9718{
9719 struct e1000_hw *hw = &adapter->hw;
9720 /* VF MAC addresses start at end of receive addresses and moves
9721 * towards the first, as a result a collision should not be possible
9722 */
9723 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9724 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9725
9726 ether_addr_copy(vf_mac_addr, mac_addr);
9727 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9728 adapter->mac_table[rar_entry].queue = vf;
9729 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9730 igb_rar_set_index(adapter, rar_entry);
9731
9732 return 0;
9733}
9734
9735static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9736{
9737 struct igb_adapter *adapter = netdev_priv(netdev);
9738
9739 if (vf >= adapter->vfs_allocated_count)
9740 return -EINVAL;
9741
9742 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9743 * flag and allows to overwrite the MAC via VF netdev. This
9744 * is necessary to allow libvirt a way to restore the original
9745 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9746 * down a VM.
9747 */
9748 if (is_zero_ether_addr(mac)) {
9749 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9750 dev_info(&adapter->pdev->dev,
9751 "remove administratively set MAC on VF %d\n",
9752 vf);
9753 } else if (is_valid_ether_addr(mac)) {
9754 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9755 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9756 mac, vf);
9757 dev_info(&adapter->pdev->dev,
9758 "Reload the VF driver to make this change effective.");
9759 /* Generate additional warning if PF is down */
9760 if (test_bit(__IGB_DOWN, &adapter->state)) {
9761 dev_warn(&adapter->pdev->dev,
9762 "The VF MAC address has been set, but the PF device is not up.\n");
9763 dev_warn(&adapter->pdev->dev,
9764 "Bring the PF device up before attempting to use the VF device.\n");
9765 }
9766 } else {
9767 return -EINVAL;
9768 }
9769 return igb_set_vf_mac(adapter, vf, mac);
9770}
9771
9772static int igb_link_mbps(int internal_link_speed)
9773{
9774 switch (internal_link_speed) {
9775 case SPEED_100:
9776 return 100;
9777 case SPEED_1000:
9778 return 1000;
9779 default:
9780 return 0;
9781 }
9782}
9783
9784static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9785 int link_speed)
9786{
9787 int rf_dec, rf_int;
9788 u32 bcnrc_val;
9789
9790 if (tx_rate != 0) {
9791 /* Calculate the rate factor values to set */
9792 rf_int = link_speed / tx_rate;
9793 rf_dec = (link_speed - (rf_int * tx_rate));
9794 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9795 tx_rate;
9796
9797 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9798 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9799 E1000_RTTBCNRC_RF_INT_MASK);
9800 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9801 } else {
9802 bcnrc_val = 0;
9803 }
9804
9805 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9806 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9807 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9808 */
9809 wr32(E1000_RTTBCNRM, 0x14);
9810 wr32(E1000_RTTBCNRC, bcnrc_val);
9811}
9812
9813static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9814{
9815 int actual_link_speed, i;
9816 bool reset_rate = false;
9817
9818 /* VF TX rate limit was not set or not supported */
9819 if ((adapter->vf_rate_link_speed == 0) ||
9820 (adapter->hw.mac.type != e1000_82576))
9821 return;
9822
9823 actual_link_speed = igb_link_mbps(adapter->link_speed);
9824 if (actual_link_speed != adapter->vf_rate_link_speed) {
9825 reset_rate = true;
9826 adapter->vf_rate_link_speed = 0;
9827 dev_info(&adapter->pdev->dev,
9828 "Link speed has been changed. VF Transmit rate is disabled\n");
9829 }
9830
9831 for (i = 0; i < adapter->vfs_allocated_count; i++) {
9832 if (reset_rate)
9833 adapter->vf_data[i].tx_rate = 0;
9834
9835 igb_set_vf_rate_limit(&adapter->hw, i,
9836 adapter->vf_data[i].tx_rate,
9837 actual_link_speed);
9838 }
9839}
9840
9841static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9842 int min_tx_rate, int max_tx_rate)
9843{
9844 struct igb_adapter *adapter = netdev_priv(netdev);
9845 struct e1000_hw *hw = &adapter->hw;
9846 int actual_link_speed;
9847
9848 if (hw->mac.type != e1000_82576)
9849 return -EOPNOTSUPP;
9850
9851 if (min_tx_rate)
9852 return -EINVAL;
9853
9854 actual_link_speed = igb_link_mbps(adapter->link_speed);
9855 if ((vf >= adapter->vfs_allocated_count) ||
9856 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9857 (max_tx_rate < 0) ||
9858 (max_tx_rate > actual_link_speed))
9859 return -EINVAL;
9860
9861 adapter->vf_rate_link_speed = actual_link_speed;
9862 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9863 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9864
9865 return 0;
9866}
9867
9868static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9869 bool setting)
9870{
9871 struct igb_adapter *adapter = netdev_priv(netdev);
9872 struct e1000_hw *hw = &adapter->hw;
9873 u32 reg_val, reg_offset;
9874
9875 if (!adapter->vfs_allocated_count)
9876 return -EOPNOTSUPP;
9877
9878 if (vf >= adapter->vfs_allocated_count)
9879 return -EINVAL;
9880
9881 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9882 reg_val = rd32(reg_offset);
9883 if (setting)
9884 reg_val |= (BIT(vf) |
9885 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9886 else
9887 reg_val &= ~(BIT(vf) |
9888 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9889 wr32(reg_offset, reg_val);
9890
9891 adapter->vf_data[vf].spoofchk_enabled = setting;
9892 return 0;
9893}
9894
9895static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9896{
9897 struct igb_adapter *adapter = netdev_priv(netdev);
9898
9899 if (vf >= adapter->vfs_allocated_count)
9900 return -EINVAL;
9901 if (adapter->vf_data[vf].trusted == setting)
9902 return 0;
9903
9904 adapter->vf_data[vf].trusted = setting;
9905
9906 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9907 vf, setting ? "" : "not ");
9908 return 0;
9909}
9910
9911static int igb_ndo_get_vf_config(struct net_device *netdev,
9912 int vf, struct ifla_vf_info *ivi)
9913{
9914 struct igb_adapter *adapter = netdev_priv(netdev);
9915 if (vf >= adapter->vfs_allocated_count)
9916 return -EINVAL;
9917 ivi->vf = vf;
9918 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9919 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9920 ivi->min_tx_rate = 0;
9921 ivi->vlan = adapter->vf_data[vf].pf_vlan;
9922 ivi->qos = adapter->vf_data[vf].pf_qos;
9923 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9924 ivi->trusted = adapter->vf_data[vf].trusted;
9925 return 0;
9926}
9927
9928static void igb_vmm_control(struct igb_adapter *adapter)
9929{
9930 struct e1000_hw *hw = &adapter->hw;
9931 u32 reg;
9932
9933 switch (hw->mac.type) {
9934 case e1000_82575:
9935 case e1000_i210:
9936 case e1000_i211:
9937 case e1000_i354:
9938 default:
9939 /* replication is not supported for 82575 */
9940 return;
9941 case e1000_82576:
9942 /* notify HW that the MAC is adding vlan tags */
9943 reg = rd32(E1000_DTXCTL);
9944 reg |= E1000_DTXCTL_VLAN_ADDED;
9945 wr32(E1000_DTXCTL, reg);
9946 fallthrough;
9947 case e1000_82580:
9948 /* enable replication vlan tag stripping */
9949 reg = rd32(E1000_RPLOLR);
9950 reg |= E1000_RPLOLR_STRVLAN;
9951 wr32(E1000_RPLOLR, reg);
9952 fallthrough;
9953 case e1000_i350:
9954 /* none of the above registers are supported by i350 */
9955 break;
9956 }
9957
9958 if (adapter->vfs_allocated_count) {
9959 igb_vmdq_set_loopback_pf(hw, true);
9960 igb_vmdq_set_replication_pf(hw, true);
9961 igb_vmdq_set_anti_spoofing_pf(hw, true,
9962 adapter->vfs_allocated_count);
9963 } else {
9964 igb_vmdq_set_loopback_pf(hw, false);
9965 igb_vmdq_set_replication_pf(hw, false);
9966 }
9967}
9968
9969static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9970{
9971 struct e1000_hw *hw = &adapter->hw;
9972 u32 dmac_thr;
9973 u16 hwm;
9974 u32 reg;
9975
9976 if (hw->mac.type > e1000_82580) {
9977 if (adapter->flags & IGB_FLAG_DMAC) {
9978 /* force threshold to 0. */
9979 wr32(E1000_DMCTXTH, 0);
9980
9981 /* DMA Coalescing high water mark needs to be greater
9982 * than the Rx threshold. Set hwm to PBA - max frame
9983 * size in 16B units, capping it at PBA - 6KB.
9984 */
9985 hwm = 64 * (pba - 6);
9986 reg = rd32(E1000_FCRTC);
9987 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9988 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9989 & E1000_FCRTC_RTH_COAL_MASK);
9990 wr32(E1000_FCRTC, reg);
9991
9992 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9993 * frame size, capping it at PBA - 10KB.
9994 */
9995 dmac_thr = pba - 10;
9996 reg = rd32(E1000_DMACR);
9997 reg &= ~E1000_DMACR_DMACTHR_MASK;
9998 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9999 & E1000_DMACR_DMACTHR_MASK);
10000
10001 /* transition to L0x or L1 if available..*/
10002 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
10003
10004 /* watchdog timer= +-1000 usec in 32usec intervals */
10005 reg |= (1000 >> 5);
10006
10007 /* Disable BMC-to-OS Watchdog Enable */
10008 if (hw->mac.type != e1000_i354)
10009 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
10010 wr32(E1000_DMACR, reg);
10011
10012 /* no lower threshold to disable
10013 * coalescing(smart fifb)-UTRESH=0
10014 */
10015 wr32(E1000_DMCRTRH, 0);
10016
10017 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
10018
10019 wr32(E1000_DMCTLX, reg);
10020
10021 /* free space in tx packet buffer to wake from
10022 * DMA coal
10023 */
10024 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
10025 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
10026 }
10027
10028 if (hw->mac.type >= e1000_i210 ||
10029 (adapter->flags & IGB_FLAG_DMAC)) {
10030 reg = rd32(E1000_PCIEMISC);
10031 reg |= E1000_PCIEMISC_LX_DECISION;
10032 wr32(E1000_PCIEMISC, reg);
10033 } /* endif adapter->dmac is not disabled */
10034 } else if (hw->mac.type == e1000_82580) {
10035 u32 reg = rd32(E1000_PCIEMISC);
10036
10037 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
10038 wr32(E1000_DMACR, 0);
10039 }
10040}
10041
10042/**
10043 * igb_read_i2c_byte - Reads 8 bit word over I2C
10044 * @hw: pointer to hardware structure
10045 * @byte_offset: byte offset to read
10046 * @dev_addr: device address
10047 * @data: value read
10048 *
10049 * Performs byte read operation over I2C interface at
10050 * a specified device address.
10051 **/
10052s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10053 u8 dev_addr, u8 *data)
10054{
10055 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10056 struct i2c_client *this_client = adapter->i2c_client;
10057 s32 status;
10058 u16 swfw_mask = 0;
10059
10060 if (!this_client)
10061 return E1000_ERR_I2C;
10062
10063 swfw_mask = E1000_SWFW_PHY0_SM;
10064
10065 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10066 return E1000_ERR_SWFW_SYNC;
10067
10068 status = i2c_smbus_read_byte_data(this_client, byte_offset);
10069 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10070
10071 if (status < 0)
10072 return E1000_ERR_I2C;
10073 else {
10074 *data = status;
10075 return 0;
10076 }
10077}
10078
10079/**
10080 * igb_write_i2c_byte - Writes 8 bit word over I2C
10081 * @hw: pointer to hardware structure
10082 * @byte_offset: byte offset to write
10083 * @dev_addr: device address
10084 * @data: value to write
10085 *
10086 * Performs byte write operation over I2C interface at
10087 * a specified device address.
10088 **/
10089s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
10090 u8 dev_addr, u8 data)
10091{
10092 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
10093 struct i2c_client *this_client = adapter->i2c_client;
10094 s32 status;
10095 u16 swfw_mask = E1000_SWFW_PHY0_SM;
10096
10097 if (!this_client)
10098 return E1000_ERR_I2C;
10099
10100 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
10101 return E1000_ERR_SWFW_SYNC;
10102 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
10103 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
10104
10105 if (status)
10106 return E1000_ERR_I2C;
10107 else
10108 return 0;
10109
10110}
10111
10112int igb_reinit_queues(struct igb_adapter *adapter)
10113{
10114 struct net_device *netdev = adapter->netdev;
10115 struct pci_dev *pdev = adapter->pdev;
10116 int err = 0;
10117
10118 if (netif_running(netdev))
10119 igb_close(netdev);
10120
10121 igb_reset_interrupt_capability(adapter);
10122
10123 if (igb_init_interrupt_scheme(adapter, true)) {
10124 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
10125 return -ENOMEM;
10126 }
10127
10128 if (netif_running(netdev))
10129 err = igb_open(netdev);
10130
10131 return err;
10132}
10133
10134static void igb_nfc_filter_exit(struct igb_adapter *adapter)
10135{
10136 struct igb_nfc_filter *rule;
10137
10138 spin_lock(&adapter->nfc_lock);
10139
10140 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10141 igb_erase_filter(adapter, rule);
10142
10143 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
10144 igb_erase_filter(adapter, rule);
10145
10146 spin_unlock(&adapter->nfc_lock);
10147}
10148
10149static void igb_nfc_filter_restore(struct igb_adapter *adapter)
10150{
10151 struct igb_nfc_filter *rule;
10152
10153 spin_lock(&adapter->nfc_lock);
10154
10155 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
10156 igb_add_filter(adapter, rule);
10157
10158 spin_unlock(&adapter->nfc_lock);
10159}
10160/* igb_main.c */