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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is the ADC part of the STM32 DFSDM driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
7 */
8
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/iio/adc/stm32-dfsdm-adc.h>
12#include <linux/iio/buffer.h>
13#include <linux/iio/hw-consumer.h>
14#include <linux/iio/sysfs.h>
15#include <linux/iio/timer/stm32-lptim-trigger.h>
16#include <linux/iio/timer/stm32-timer-trigger.h>
17#include <linux/iio/trigger.h>
18#include <linux/iio/trigger_consumer.h>
19#include <linux/iio/triggered_buffer.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26
27#include "stm32-dfsdm.h"
28
29#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
30
31/* Conversion timeout */
32#define DFSDM_TIMEOUT_US 100000
33#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
34
35/* Oversampling attribute default */
36#define DFSDM_DEFAULT_OVERSAMPLING 100
37
38/* Oversampling max values */
39#define DFSDM_MAX_INT_OVERSAMPLING 256
40#define DFSDM_MAX_FL_OVERSAMPLING 1024
41
42/* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
43#define DFSDM_DATA_MAX BIT(30)
44/*
45 * Data are output as two's complement data in a 24 bit field.
46 * Data from filters are in the range +/-2^(n-1)
47 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
48 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
49 * So, the resolution of samples from filter is actually limited to 23 bits
50 */
51#define DFSDM_DATA_RES 24
52
53/* Filter configuration */
54#define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
55 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
56 DFSDM_CR1_JSCAN_MASK)
57
58enum sd_converter_type {
59 DFSDM_AUDIO,
60 DFSDM_IIO,
61};
62
63struct stm32_dfsdm_dev_data {
64 int type;
65 int (*init)(struct device *dev, struct iio_dev *indio_dev);
66 unsigned int num_channels;
67 const struct regmap_config *regmap_cfg;
68};
69
70struct stm32_dfsdm_adc {
71 struct stm32_dfsdm *dfsdm;
72 const struct stm32_dfsdm_dev_data *dev_data;
73 unsigned int fl_id;
74 unsigned int nconv;
75 unsigned long smask;
76
77 /* ADC specific */
78 unsigned int oversamp;
79 struct iio_hw_consumer *hwc;
80 struct completion completion;
81 u32 *buffer;
82
83 /* Audio specific */
84 unsigned int spi_freq; /* SPI bus clock frequency */
85 unsigned int sample_freq; /* Sample frequency after filter decimation */
86 int (*cb)(const void *data, size_t size, void *cb_priv);
87 void *cb_priv;
88
89 /* DMA */
90 u8 *rx_buf;
91 unsigned int bufi; /* Buffer current position */
92 unsigned int buf_sz; /* Buffer size */
93 struct dma_chan *dma_chan;
94 dma_addr_t dma_buf;
95};
96
97struct stm32_dfsdm_str2field {
98 const char *name;
99 unsigned int val;
100};
101
102/* DFSDM channel serial interface type */
103static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
104 { "SPI_R", 0 }, /* SPI with data on rising edge */
105 { "SPI_F", 1 }, /* SPI with data on falling edge */
106 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
107 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
108 {},
109};
110
111/* DFSDM channel clock source */
112static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
113 /* External SPI clock (CLKIN x) */
114 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
115 /* Internal SPI clock (CLKOUT) */
116 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
117 /* Internal SPI clock divided by 2 (falling edge) */
118 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
119 /* Internal SPI clock divided by 2 (falling edge) */
120 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
121 {},
122};
123
124static int stm32_dfsdm_str2val(const char *str,
125 const struct stm32_dfsdm_str2field *list)
126{
127 const struct stm32_dfsdm_str2field *p = list;
128
129 for (p = list; p && p->name; p++)
130 if (!strcmp(p->name, str))
131 return p->val;
132
133 return -EINVAL;
134}
135
136/**
137 * struct stm32_dfsdm_trig_info - DFSDM trigger info
138 * @name: name of the trigger, corresponding to its source
139 * @jextsel: trigger signal selection
140 */
141struct stm32_dfsdm_trig_info {
142 const char *name;
143 unsigned int jextsel;
144};
145
146/* hardware injected trigger enable, edge selection */
147enum stm32_dfsdm_jexten {
148 STM32_DFSDM_JEXTEN_DISABLED,
149 STM32_DFSDM_JEXTEN_RISING_EDGE,
150 STM32_DFSDM_JEXTEN_FALLING_EDGE,
151 STM32_DFSDM_EXTEN_BOTH_EDGES,
152};
153
154static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
155 { TIM1_TRGO, 0 },
156 { TIM1_TRGO2, 1 },
157 { TIM8_TRGO, 2 },
158 { TIM8_TRGO2, 3 },
159 { TIM3_TRGO, 4 },
160 { TIM4_TRGO, 5 },
161 { TIM16_OC1, 6 },
162 { TIM6_TRGO, 7 },
163 { TIM7_TRGO, 8 },
164 { LPTIM1_OUT, 26 },
165 { LPTIM2_OUT, 27 },
166 { LPTIM3_OUT, 28 },
167 {},
168};
169
170static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
171 struct iio_trigger *trig)
172{
173 int i;
174
175 /* lookup triggers registered by stm32 timer trigger driver */
176 for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
177 /**
178 * Checking both stm32 timer trigger type and trig name
179 * should be safe against arbitrary trigger names.
180 */
181 if ((is_stm32_timer_trigger(trig) ||
182 is_stm32_lptim_trigger(trig)) &&
183 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
184 return stm32_dfsdm_trigs[i].jextsel;
185 }
186 }
187
188 return -EINVAL;
189}
190
191static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
192 unsigned int fast, unsigned int oversamp)
193{
194 unsigned int i, d, fosr, iosr;
195 u64 res, max;
196 int bits, shift;
197 unsigned int m = 1; /* multiplication factor */
198 unsigned int p = fl->ford; /* filter order (ford) */
199 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
200
201 pr_debug("Requested oversampling: %d\n", oversamp);
202 /*
203 * This function tries to compute filter oversampling and integrator
204 * oversampling, base on oversampling ratio requested by user.
205 *
206 * Decimation d depends on the filter order and the oversampling ratios.
207 * ford: filter order
208 * fosr: filter over sampling ratio
209 * iosr: integrator over sampling ratio
210 */
211 if (fl->ford == DFSDM_FASTSINC_ORDER) {
212 m = 2;
213 p = 2;
214 }
215
216 /*
217 * Look for filter and integrator oversampling ratios which allows
218 * to maximize data output resolution.
219 */
220 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
221 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
222 if (fast)
223 d = fosr * iosr;
224 else if (fl->ford == DFSDM_FASTSINC_ORDER)
225 d = fosr * (iosr + 3) + 2;
226 else
227 d = fosr * (iosr - 1 + p) + p;
228
229 if (d > oversamp)
230 break;
231 else if (d != oversamp)
232 continue;
233 /*
234 * Check resolution (limited to signed 32 bits)
235 * res <= 2^31
236 * Sincx filters:
237 * res = m * fosr^p x iosr (with m=1, p=ford)
238 * FastSinc filter
239 * res = m * fosr^p x iosr (with m=2, p=2)
240 */
241 res = fosr;
242 for (i = p - 1; i > 0; i--) {
243 res = res * (u64)fosr;
244 if (res > DFSDM_DATA_MAX)
245 break;
246 }
247 if (res > DFSDM_DATA_MAX)
248 continue;
249
250 res = res * (u64)m * (u64)iosr;
251 if (res > DFSDM_DATA_MAX)
252 continue;
253
254 if (res >= flo->res) {
255 flo->res = res;
256 flo->fosr = fosr;
257 flo->iosr = iosr;
258
259 bits = fls(flo->res);
260 /* 8 LBSs in data register contain chan info */
261 max = flo->res << 8;
262
263 /* if resolution is not a power of two */
264 if (flo->res > BIT(bits - 1))
265 bits++;
266 else
267 max--;
268
269 shift = DFSDM_DATA_RES - bits;
270 /*
271 * Compute right/left shift
272 * Right shift is performed by hardware
273 * when transferring samples to data register.
274 * Left shift is done by software on buffer
275 */
276 if (shift > 0) {
277 /* Resolution is lower than 24 bits */
278 flo->rshift = 0;
279 flo->lshift = shift;
280 } else {
281 /*
282 * If resolution is 24 bits or more,
283 * max positive value may be ambiguous
284 * (equal to max negative value as sign
285 * bit is dropped).
286 * Reduce resolution to 23 bits (rshift)
287 * to keep the sign on bit 23 and treat
288 * saturation before rescaling on 24
289 * bits (lshift).
290 */
291 flo->rshift = 1 - shift;
292 flo->lshift = 1;
293 max >>= flo->rshift;
294 }
295 flo->max = (s32)max;
296 flo->bits = bits;
297
298 pr_debug("fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
299 fast, flo->fosr, flo->iosr,
300 flo->res, bits, flo->rshift,
301 flo->lshift);
302 }
303 }
304 }
305
306 if (!flo->res)
307 return -EINVAL;
308
309 return 0;
310}
311
312static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
313 unsigned int oversamp)
314{
315 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
316 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
317 int ret0, ret1;
318
319 memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
320 memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
321
322 ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
323 ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
324 if (ret0 < 0 && ret1 < 0) {
325 dev_err(&indio_dev->dev,
326 "Filter parameters not found: errors %d/%d\n",
327 ret0, ret1);
328 return -EINVAL;
329 }
330
331 return 0;
332}
333
334static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
335{
336 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
337 struct regmap *regmap = adc->dfsdm->regmap;
338 const struct iio_chan_spec *chan;
339 unsigned int bit;
340 int ret;
341
342 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
343 chan = indio_dev->channels + bit;
344 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
345 DFSDM_CHCFGR1_CHEN_MASK,
346 DFSDM_CHCFGR1_CHEN(1));
347 if (ret < 0)
348 return ret;
349 }
350
351 return 0;
352}
353
354static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
355{
356 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
357 struct regmap *regmap = adc->dfsdm->regmap;
358 const struct iio_chan_spec *chan;
359 unsigned int bit;
360
361 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
362 chan = indio_dev->channels + bit;
363 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
364 DFSDM_CHCFGR1_CHEN_MASK,
365 DFSDM_CHCFGR1_CHEN(0));
366 }
367}
368
369static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
370 struct stm32_dfsdm_channel *ch)
371{
372 unsigned int id = ch->id;
373 struct regmap *regmap = dfsdm->regmap;
374 int ret;
375
376 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
377 DFSDM_CHCFGR1_SITP_MASK,
378 DFSDM_CHCFGR1_SITP(ch->type));
379 if (ret < 0)
380 return ret;
381 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
382 DFSDM_CHCFGR1_SPICKSEL_MASK,
383 DFSDM_CHCFGR1_SPICKSEL(ch->src));
384 if (ret < 0)
385 return ret;
386 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
387 DFSDM_CHCFGR1_CHINSEL_MASK,
388 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
389}
390
391static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
392 unsigned int fl_id,
393 struct iio_trigger *trig)
394{
395 struct stm32_dfsdm *dfsdm = adc->dfsdm;
396 int ret;
397
398 /* Enable filter */
399 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
400 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
401 if (ret < 0)
402 return ret;
403
404 /* Nothing more to do for injected (scan mode/triggered) conversions */
405 if (adc->nconv > 1 || trig)
406 return 0;
407
408 /* Software start (single or continuous) regular conversion */
409 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
410 DFSDM_CR1_RSWSTART_MASK,
411 DFSDM_CR1_RSWSTART(1));
412}
413
414static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
415 unsigned int fl_id)
416{
417 /* Disable conversion */
418 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
419 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
420}
421
422static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
423 unsigned int fl_id,
424 struct iio_trigger *trig)
425{
426 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
427 struct regmap *regmap = adc->dfsdm->regmap;
428 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
429 int ret;
430
431 if (trig) {
432 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
433 if (ret < 0)
434 return ret;
435
436 /* set trigger source and polarity (default to rising edge) */
437 jextsel = ret;
438 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
439 }
440
441 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
442 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
443 DFSDM_CR1_JEXTSEL(jextsel) |
444 DFSDM_CR1_JEXTEN(jexten));
445 if (ret < 0)
446 return ret;
447
448 return 0;
449}
450
451static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
452 unsigned int fl_id,
453 struct iio_trigger *trig)
454{
455 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
456 struct regmap *regmap = adc->dfsdm->regmap;
457 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
458 struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
459 const struct iio_chan_spec *chan;
460 unsigned int bit;
461 int ret;
462
463 fl->fast = 0;
464
465 /*
466 * In continuous mode, use fast mode configuration,
467 * if it provides a better resolution.
468 */
469 if (adc->nconv == 1 && !trig && iio_buffer_enabled(indio_dev)) {
470 if (fl->flo[1].res >= fl->flo[0].res) {
471 fl->fast = 1;
472 flo = &fl->flo[1];
473 }
474 }
475
476 if (!flo->res)
477 return -EINVAL;
478
479 dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
480 min(flo->bits, (u32)DFSDM_DATA_RES - 1));
481
482 for_each_set_bit(bit, &adc->smask,
483 sizeof(adc->smask) * BITS_PER_BYTE) {
484 chan = indio_dev->channels + bit;
485
486 ret = regmap_update_bits(regmap,
487 DFSDM_CHCFGR2(chan->channel),
488 DFSDM_CHCFGR2_DTRBS_MASK,
489 DFSDM_CHCFGR2_DTRBS(flo->rshift));
490 if (ret)
491 return ret;
492 }
493
494 return 0;
495}
496
497static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
498 unsigned int fl_id,
499 struct iio_trigger *trig)
500{
501 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
502 struct regmap *regmap = adc->dfsdm->regmap;
503 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
504 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
505 u32 cr1;
506 const struct iio_chan_spec *chan;
507 unsigned int bit, jchg = 0;
508 int ret;
509
510 /* Average integrator oversampling */
511 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
512 DFSDM_FCR_IOSR(flo->iosr - 1));
513 if (ret)
514 return ret;
515
516 /* Filter order and Oversampling */
517 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
518 DFSDM_FCR_FOSR(flo->fosr - 1));
519 if (ret)
520 return ret;
521
522 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
523 DFSDM_FCR_FORD(fl->ford));
524 if (ret)
525 return ret;
526
527 ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
528 if (ret)
529 return ret;
530
531 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
532 DFSDM_CR1_FAST_MASK,
533 DFSDM_CR1_FAST(fl->fast));
534 if (ret)
535 return ret;
536
537 /*
538 * DFSDM modes configuration W.R.T audio/iio type modes
539 * ----------------------------------------------------------------
540 * Modes | regular | regular | injected | injected |
541 * | | continuous | | + scan |
542 * --------------|---------|--------------|----------|------------|
543 * single conv | x | | | |
544 * (1 chan) | | | | |
545 * --------------|---------|--------------|----------|------------|
546 * 1 Audio chan | | sample freq | | |
547 * | | or sync_mode | | |
548 * --------------|---------|--------------|----------|------------|
549 * 1 IIO chan | | sample freq | trigger | |
550 * | | or sync_mode | | |
551 * --------------|---------|--------------|----------|------------|
552 * 2+ IIO chans | | | | trigger or |
553 * | | | | sync_mode |
554 * ----------------------------------------------------------------
555 */
556 if (adc->nconv == 1 && !trig) {
557 bit = __ffs(adc->smask);
558 chan = indio_dev->channels + bit;
559
560 /* Use regular conversion for single channel without trigger */
561 cr1 = DFSDM_CR1_RCH(chan->channel);
562
563 /* Continuous conversions triggered by SPI clk in buffer mode */
564 if (iio_buffer_enabled(indio_dev))
565 cr1 |= DFSDM_CR1_RCONT(1);
566
567 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
568 } else {
569 /* Use injected conversion for multiple channels */
570 for_each_set_bit(bit, &adc->smask,
571 sizeof(adc->smask) * BITS_PER_BYTE) {
572 chan = indio_dev->channels + bit;
573 jchg |= BIT(chan->channel);
574 }
575 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
576 if (ret < 0)
577 return ret;
578
579 /* Use scan mode for multiple channels */
580 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
581
582 /*
583 * Continuous conversions not supported in injected mode,
584 * either use:
585 * - conversions in sync with filter 0
586 * - triggered conversions
587 */
588 if (!fl->sync_mode && !trig)
589 return -EINVAL;
590 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
591 }
592
593 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
594 cr1);
595}
596
597static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
598 struct iio_dev *indio_dev,
599 struct iio_chan_spec *ch)
600{
601 struct stm32_dfsdm_channel *df_ch;
602 const char *of_str;
603 int chan_idx = ch->scan_index;
604 int ret, val;
605
606 ret = of_property_read_u32_index(indio_dev->dev.of_node,
607 "st,adc-channels", chan_idx,
608 &ch->channel);
609 if (ret < 0) {
610 dev_err(&indio_dev->dev,
611 " Error parsing 'st,adc-channels' for idx %d\n",
612 chan_idx);
613 return ret;
614 }
615 if (ch->channel >= dfsdm->num_chs) {
616 dev_err(&indio_dev->dev,
617 " Error bad channel number %d (max = %d)\n",
618 ch->channel, dfsdm->num_chs);
619 return -EINVAL;
620 }
621
622 ret = of_property_read_string_index(indio_dev->dev.of_node,
623 "st,adc-channel-names", chan_idx,
624 &ch->datasheet_name);
625 if (ret < 0) {
626 dev_err(&indio_dev->dev,
627 " Error parsing 'st,adc-channel-names' for idx %d\n",
628 chan_idx);
629 return ret;
630 }
631
632 df_ch = &dfsdm->ch_list[ch->channel];
633 df_ch->id = ch->channel;
634
635 ret = of_property_read_string_index(indio_dev->dev.of_node,
636 "st,adc-channel-types", chan_idx,
637 &of_str);
638 if (!ret) {
639 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
640 if (val < 0)
641 return val;
642 } else {
643 val = 0;
644 }
645 df_ch->type = val;
646
647 ret = of_property_read_string_index(indio_dev->dev.of_node,
648 "st,adc-channel-clk-src", chan_idx,
649 &of_str);
650 if (!ret) {
651 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
652 if (val < 0)
653 return val;
654 } else {
655 val = 0;
656 }
657 df_ch->src = val;
658
659 ret = of_property_read_u32_index(indio_dev->dev.of_node,
660 "st,adc-alt-channel", chan_idx,
661 &df_ch->alt_si);
662 if (ret < 0)
663 df_ch->alt_si = 0;
664
665 return 0;
666}
667
668static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
669 uintptr_t priv,
670 const struct iio_chan_spec *chan,
671 char *buf)
672{
673 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
674
675 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
676}
677
678static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
679 unsigned int sample_freq,
680 unsigned int spi_freq)
681{
682 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
683 unsigned int oversamp;
684 int ret;
685
686 oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
687 if (spi_freq % sample_freq)
688 dev_dbg(&indio_dev->dev,
689 "Rate not accurate. requested (%u), actual (%u)\n",
690 sample_freq, spi_freq / oversamp);
691
692 ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
693 if (ret < 0)
694 return ret;
695
696 adc->sample_freq = spi_freq / oversamp;
697 adc->oversamp = oversamp;
698
699 return 0;
700}
701
702static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
703 uintptr_t priv,
704 const struct iio_chan_spec *chan,
705 const char *buf, size_t len)
706{
707 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
708 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
709 unsigned int sample_freq = adc->sample_freq;
710 unsigned int spi_freq;
711 int ret;
712
713 dev_err(&indio_dev->dev, "enter %s\n", __func__);
714 /* If DFSDM is master on SPI, SPI freq can not be updated */
715 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
716 return -EPERM;
717
718 ret = kstrtoint(buf, 0, &spi_freq);
719 if (ret)
720 return ret;
721
722 if (!spi_freq)
723 return -EINVAL;
724
725 if (sample_freq) {
726 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
727 if (ret < 0)
728 return ret;
729 }
730 adc->spi_freq = spi_freq;
731
732 return len;
733}
734
735static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
736 struct iio_trigger *trig)
737{
738 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
739 struct regmap *regmap = adc->dfsdm->regmap;
740 int ret;
741
742 ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
743 if (ret < 0)
744 return ret;
745
746 ret = stm32_dfsdm_start_channel(indio_dev);
747 if (ret < 0)
748 return ret;
749
750 ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
751 if (ret < 0)
752 goto stop_channels;
753
754 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
755 if (ret < 0)
756 goto filter_unconfigure;
757
758 return 0;
759
760filter_unconfigure:
761 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
762 DFSDM_CR1_CFG_MASK, 0);
763stop_channels:
764 stm32_dfsdm_stop_channel(indio_dev);
765
766 return ret;
767}
768
769static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
770{
771 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
772 struct regmap *regmap = adc->dfsdm->regmap;
773
774 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
775
776 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
777 DFSDM_CR1_CFG_MASK, 0);
778
779 stm32_dfsdm_stop_channel(indio_dev);
780}
781
782static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
783 unsigned int val)
784{
785 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
786 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
787 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
788
789 /*
790 * DMA cyclic transfers are used, buffer is split into two periods.
791 * There should be :
792 * - always one buffer (period) DMA is working on
793 * - one buffer (period) driver pushed to ASoC side.
794 */
795 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
796 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
797
798 return 0;
799}
800
801static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
802{
803 struct dma_tx_state state;
804 enum dma_status status;
805
806 status = dmaengine_tx_status(adc->dma_chan,
807 adc->dma_chan->cookie,
808 &state);
809 if (status == DMA_IN_PROGRESS) {
810 /* Residue is size in bytes from end of buffer */
811 unsigned int i = adc->buf_sz - state.residue;
812 unsigned int size;
813
814 /* Return available bytes */
815 if (i >= adc->bufi)
816 size = i - adc->bufi;
817 else
818 size = adc->buf_sz + i - adc->bufi;
819
820 return size;
821 }
822
823 return 0;
824}
825
826static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
827 s32 *buffer)
828{
829 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
830 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
831 unsigned int i = adc->nconv;
832 s32 *ptr = buffer;
833
834 while (i--) {
835 /* Mask 8 LSB that contains the channel ID */
836 *ptr &= 0xFFFFFF00;
837 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
838 if (*ptr > flo->max)
839 *ptr -= 1;
840 /*
841 * Samples from filter are retrieved with 23 bits resolution
842 * or less. Shift left to align MSB on 24 bits.
843 */
844 *ptr <<= flo->lshift;
845
846 ptr++;
847 }
848}
849
850static void stm32_dfsdm_dma_buffer_done(void *data)
851{
852 struct iio_dev *indio_dev = data;
853 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
854 int available = stm32_dfsdm_adc_dma_residue(adc);
855 size_t old_pos;
856
857 /*
858 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
859 * offers only an interface to push data samples per samples.
860 * For this reason IIO buffer interface is not used and interface is
861 * bypassed using a private callback registered by ASoC.
862 * This should be a temporary solution waiting a cyclic DMA engine
863 * support in IIO.
864 */
865
866 dev_dbg(&indio_dev->dev, "pos = %d, available = %d\n",
867 adc->bufi, available);
868 old_pos = adc->bufi;
869
870 while (available >= indio_dev->scan_bytes) {
871 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
872
873 stm32_dfsdm_process_data(adc, buffer);
874
875 available -= indio_dev->scan_bytes;
876 adc->bufi += indio_dev->scan_bytes;
877 if (adc->bufi >= adc->buf_sz) {
878 if (adc->cb)
879 adc->cb(&adc->rx_buf[old_pos],
880 adc->buf_sz - old_pos, adc->cb_priv);
881 adc->bufi = 0;
882 old_pos = 0;
883 }
884 /*
885 * In DMA mode the trigger services of IIO are not used
886 * (e.g. no call to iio_trigger_poll).
887 * Calling irq handler associated to the hardware trigger is not
888 * relevant as the conversions have already been done. Data
889 * transfers are performed directly in DMA callback instead.
890 * This implementation avoids to call trigger irq handler that
891 * may sleep, in an atomic context (DMA irq handler context).
892 */
893 if (adc->dev_data->type == DFSDM_IIO)
894 iio_push_to_buffers(indio_dev, buffer);
895 }
896 if (adc->cb)
897 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
898 adc->cb_priv);
899}
900
901static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
902{
903 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
904 /*
905 * The DFSDM supports half-word transfers. However, for 16 bits record,
906 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
907 * shift is required.
908 */
909 struct dma_slave_config config = {
910 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
911 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
912 };
913 struct dma_async_tx_descriptor *desc;
914 dma_cookie_t cookie;
915 int ret;
916
917 if (!adc->dma_chan)
918 return -EINVAL;
919
920 dev_dbg(&indio_dev->dev, "size=%d watermark=%d\n",
921 adc->buf_sz, adc->buf_sz / 2);
922
923 if (adc->nconv == 1 && !indio_dev->trig)
924 config.src_addr += DFSDM_RDATAR(adc->fl_id);
925 else
926 config.src_addr += DFSDM_JDATAR(adc->fl_id);
927 ret = dmaengine_slave_config(adc->dma_chan, &config);
928 if (ret)
929 return ret;
930
931 /* Prepare a DMA cyclic transaction */
932 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
933 adc->dma_buf,
934 adc->buf_sz, adc->buf_sz / 2,
935 DMA_DEV_TO_MEM,
936 DMA_PREP_INTERRUPT);
937 if (!desc)
938 return -EBUSY;
939
940 desc->callback = stm32_dfsdm_dma_buffer_done;
941 desc->callback_param = indio_dev;
942
943 cookie = dmaengine_submit(desc);
944 ret = dma_submit_error(cookie);
945 if (ret)
946 goto err_stop_dma;
947
948 /* Issue pending DMA requests */
949 dma_async_issue_pending(adc->dma_chan);
950
951 if (adc->nconv == 1 && !indio_dev->trig) {
952 /* Enable regular DMA transfer*/
953 ret = regmap_update_bits(adc->dfsdm->regmap,
954 DFSDM_CR1(adc->fl_id),
955 DFSDM_CR1_RDMAEN_MASK,
956 DFSDM_CR1_RDMAEN_MASK);
957 } else {
958 /* Enable injected DMA transfer*/
959 ret = regmap_update_bits(adc->dfsdm->regmap,
960 DFSDM_CR1(adc->fl_id),
961 DFSDM_CR1_JDMAEN_MASK,
962 DFSDM_CR1_JDMAEN_MASK);
963 }
964
965 if (ret < 0)
966 goto err_stop_dma;
967
968 return 0;
969
970err_stop_dma:
971 dmaengine_terminate_all(adc->dma_chan);
972
973 return ret;
974}
975
976static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
977{
978 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
979
980 if (!adc->dma_chan)
981 return;
982
983 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
984 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
985 dmaengine_terminate_all(adc->dma_chan);
986}
987
988static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
989 const unsigned long *scan_mask)
990{
991 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
992
993 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
994 adc->smask = *scan_mask;
995
996 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
997
998 return 0;
999}
1000
1001static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1002{
1003 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1004 int ret;
1005
1006 /* Reset adc buffer index */
1007 adc->bufi = 0;
1008
1009 if (adc->hwc) {
1010 ret = iio_hw_consumer_enable(adc->hwc);
1011 if (ret < 0)
1012 return ret;
1013 }
1014
1015 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1016 if (ret < 0)
1017 goto err_stop_hwc;
1018
1019 ret = stm32_dfsdm_adc_dma_start(indio_dev);
1020 if (ret) {
1021 dev_err(&indio_dev->dev, "Can't start DMA\n");
1022 goto stop_dfsdm;
1023 }
1024
1025 ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
1026 if (ret) {
1027 dev_err(&indio_dev->dev, "Can't start conversion\n");
1028 goto err_stop_dma;
1029 }
1030
1031 return 0;
1032
1033err_stop_dma:
1034 stm32_dfsdm_adc_dma_stop(indio_dev);
1035stop_dfsdm:
1036 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1037err_stop_hwc:
1038 if (adc->hwc)
1039 iio_hw_consumer_disable(adc->hwc);
1040
1041 return ret;
1042}
1043
1044static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1045{
1046 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1047
1048 stm32_dfsdm_stop_conv(indio_dev);
1049
1050 stm32_dfsdm_adc_dma_stop(indio_dev);
1051
1052 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1053
1054 if (adc->hwc)
1055 iio_hw_consumer_disable(adc->hwc);
1056
1057 return 0;
1058}
1059
1060static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1061 .postenable = &stm32_dfsdm_postenable,
1062 .predisable = &stm32_dfsdm_predisable,
1063};
1064
1065/**
1066 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1067 * DMA transfer period is achieved.
1068 *
1069 * @iio_dev: Handle to IIO device.
1070 * @cb: Pointer to callback function:
1071 * - data: pointer to data buffer
1072 * - size: size in byte of the data buffer
1073 * - private: pointer to consumer private structure.
1074 * @private: Pointer to consumer private structure.
1075 */
1076int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1077 int (*cb)(const void *data, size_t size,
1078 void *private),
1079 void *private)
1080{
1081 struct stm32_dfsdm_adc *adc;
1082
1083 if (!iio_dev)
1084 return -EINVAL;
1085 adc = iio_priv(iio_dev);
1086
1087 adc->cb = cb;
1088 adc->cb_priv = private;
1089
1090 return 0;
1091}
1092EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1093
1094/**
1095 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1096 *
1097 * @iio_dev: Handle to IIO device.
1098 */
1099int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1100{
1101 struct stm32_dfsdm_adc *adc;
1102
1103 if (!iio_dev)
1104 return -EINVAL;
1105 adc = iio_priv(iio_dev);
1106
1107 adc->cb = NULL;
1108 adc->cb_priv = NULL;
1109
1110 return 0;
1111}
1112EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1113
1114static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1115 const struct iio_chan_spec *chan, int *res)
1116{
1117 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1118 long timeout;
1119 int ret;
1120
1121 reinit_completion(&adc->completion);
1122
1123 adc->buffer = res;
1124
1125 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1126 if (ret < 0)
1127 return ret;
1128
1129 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1130 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1131 if (ret < 0)
1132 goto stop_dfsdm;
1133
1134 adc->nconv = 1;
1135 adc->smask = BIT(chan->scan_index);
1136 ret = stm32_dfsdm_start_conv(indio_dev, NULL);
1137 if (ret < 0) {
1138 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1139 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1140 goto stop_dfsdm;
1141 }
1142
1143 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1144 DFSDM_TIMEOUT);
1145
1146 /* Mask IRQ for regular conversion achievement*/
1147 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1148 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1149
1150 if (timeout == 0)
1151 ret = -ETIMEDOUT;
1152 else if (timeout < 0)
1153 ret = timeout;
1154 else
1155 ret = IIO_VAL_INT;
1156
1157 stm32_dfsdm_stop_conv(indio_dev);
1158
1159 stm32_dfsdm_process_data(adc, res);
1160
1161stop_dfsdm:
1162 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1163
1164 return ret;
1165}
1166
1167static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1168 struct iio_chan_spec const *chan,
1169 int val, int val2, long mask)
1170{
1171 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1172 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1173 unsigned int spi_freq;
1174 int ret = -EINVAL;
1175
1176 switch (ch->src) {
1177 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1178 spi_freq = adc->dfsdm->spi_master_freq;
1179 break;
1180 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1181 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1182 spi_freq = adc->dfsdm->spi_master_freq / 2;
1183 break;
1184 default:
1185 spi_freq = adc->spi_freq;
1186 }
1187
1188 switch (mask) {
1189 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1190 ret = iio_device_claim_direct_mode(indio_dev);
1191 if (ret)
1192 return ret;
1193
1194 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1195 if (!ret) {
1196 dev_dbg(&indio_dev->dev,
1197 "Sampling rate changed from (%u) to (%u)\n",
1198 adc->sample_freq, spi_freq / val);
1199 adc->oversamp = val;
1200 adc->sample_freq = spi_freq / val;
1201 }
1202 iio_device_release_direct_mode(indio_dev);
1203 return ret;
1204
1205 case IIO_CHAN_INFO_SAMP_FREQ:
1206 if (!val)
1207 return -EINVAL;
1208
1209 ret = iio_device_claim_direct_mode(indio_dev);
1210 if (ret)
1211 return ret;
1212
1213 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1214 iio_device_release_direct_mode(indio_dev);
1215 return ret;
1216 }
1217
1218 return -EINVAL;
1219}
1220
1221static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1222 struct iio_chan_spec const *chan, int *val,
1223 int *val2, long mask)
1224{
1225 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1226 int ret;
1227
1228 switch (mask) {
1229 case IIO_CHAN_INFO_RAW:
1230 ret = iio_device_claim_direct_mode(indio_dev);
1231 if (ret)
1232 return ret;
1233 ret = iio_hw_consumer_enable(adc->hwc);
1234 if (ret < 0) {
1235 dev_err(&indio_dev->dev,
1236 "%s: IIO enable failed (channel %d)\n",
1237 __func__, chan->channel);
1238 iio_device_release_direct_mode(indio_dev);
1239 return ret;
1240 }
1241 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1242 iio_hw_consumer_disable(adc->hwc);
1243 if (ret < 0) {
1244 dev_err(&indio_dev->dev,
1245 "%s: Conversion failed (channel %d)\n",
1246 __func__, chan->channel);
1247 iio_device_release_direct_mode(indio_dev);
1248 return ret;
1249 }
1250 iio_device_release_direct_mode(indio_dev);
1251 return IIO_VAL_INT;
1252
1253 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1254 *val = adc->oversamp;
1255
1256 return IIO_VAL_INT;
1257
1258 case IIO_CHAN_INFO_SAMP_FREQ:
1259 *val = adc->sample_freq;
1260
1261 return IIO_VAL_INT;
1262 }
1263
1264 return -EINVAL;
1265}
1266
1267static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1268 struct iio_trigger *trig)
1269{
1270 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1271}
1272
1273static const struct iio_info stm32_dfsdm_info_audio = {
1274 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1275 .read_raw = stm32_dfsdm_read_raw,
1276 .write_raw = stm32_dfsdm_write_raw,
1277 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1278};
1279
1280static const struct iio_info stm32_dfsdm_info_adc = {
1281 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1282 .read_raw = stm32_dfsdm_read_raw,
1283 .write_raw = stm32_dfsdm_write_raw,
1284 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1285 .validate_trigger = stm32_dfsdm_validate_trigger,
1286};
1287
1288static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1289{
1290 struct iio_dev *indio_dev = arg;
1291 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1292 struct regmap *regmap = adc->dfsdm->regmap;
1293 unsigned int status, int_en;
1294
1295 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1296 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1297
1298 if (status & DFSDM_ISR_REOCF_MASK) {
1299 /* Read the data register clean the IRQ status */
1300 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1301 complete(&adc->completion);
1302 }
1303
1304 if (status & DFSDM_ISR_ROVRF_MASK) {
1305 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1306 dev_warn(&indio_dev->dev, "Overrun detected\n");
1307 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1308 DFSDM_ICR_CLRROVRF_MASK,
1309 DFSDM_ICR_CLRROVRF_MASK);
1310 }
1311
1312 return IRQ_HANDLED;
1313}
1314
1315/*
1316 * Define external info for SPI Frequency and audio sampling rate that can be
1317 * configured by ASoC driver through consumer.h API
1318 */
1319static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1320 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1321 {
1322 .name = "spi_clk_freq",
1323 .shared = IIO_SHARED_BY_TYPE,
1324 .read = dfsdm_adc_audio_get_spiclk,
1325 .write = dfsdm_adc_audio_set_spiclk,
1326 },
1327 {},
1328};
1329
1330static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1331{
1332 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1333
1334 if (adc->dma_chan) {
1335 dma_free_coherent(adc->dma_chan->device->dev,
1336 DFSDM_DMA_BUFFER_SIZE,
1337 adc->rx_buf, adc->dma_buf);
1338 dma_release_channel(adc->dma_chan);
1339 }
1340}
1341
1342static int stm32_dfsdm_dma_request(struct device *dev,
1343 struct iio_dev *indio_dev)
1344{
1345 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1346
1347 adc->dma_chan = dma_request_chan(dev, "rx");
1348 if (IS_ERR(adc->dma_chan)) {
1349 int ret = PTR_ERR(adc->dma_chan);
1350
1351 adc->dma_chan = NULL;
1352 return ret;
1353 }
1354
1355 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1356 DFSDM_DMA_BUFFER_SIZE,
1357 &adc->dma_buf, GFP_KERNEL);
1358 if (!adc->rx_buf) {
1359 dma_release_channel(adc->dma_chan);
1360 return -ENOMEM;
1361 }
1362
1363 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1364 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1365
1366 return 0;
1367}
1368
1369static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1370 struct iio_chan_spec *ch)
1371{
1372 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1373 int ret;
1374
1375 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1376 if (ret < 0)
1377 return ret;
1378
1379 ch->type = IIO_VOLTAGE;
1380 ch->indexed = 1;
1381
1382 /*
1383 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1384 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1385 */
1386 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1387 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1388 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1389
1390 if (adc->dev_data->type == DFSDM_AUDIO) {
1391 ch->ext_info = dfsdm_adc_audio_ext_info;
1392 } else {
1393 ch->scan_type.shift = 8;
1394 }
1395 ch->scan_type.sign = 's';
1396 ch->scan_type.realbits = 24;
1397 ch->scan_type.storagebits = 32;
1398
1399 return stm32_dfsdm_chan_configure(adc->dfsdm,
1400 &adc->dfsdm->ch_list[ch->channel]);
1401}
1402
1403static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1404{
1405 struct iio_chan_spec *ch;
1406 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1407 struct stm32_dfsdm_channel *d_ch;
1408 int ret;
1409
1410 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1411 if (!ch)
1412 return -ENOMEM;
1413
1414 ch->scan_index = 0;
1415
1416 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1417 if (ret < 0) {
1418 dev_err(&indio_dev->dev, "Channels init failed\n");
1419 return ret;
1420 }
1421 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1422
1423 d_ch = &adc->dfsdm->ch_list[ch->channel];
1424 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1425 adc->spi_freq = adc->dfsdm->spi_master_freq;
1426
1427 indio_dev->num_channels = 1;
1428 indio_dev->channels = ch;
1429
1430 return stm32_dfsdm_dma_request(dev, indio_dev);
1431}
1432
1433static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1434{
1435 struct iio_chan_spec *ch;
1436 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1437 int num_ch;
1438 int ret, chan_idx;
1439
1440 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1441 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1442 if (ret < 0)
1443 return ret;
1444
1445 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1446 "st,adc-channels");
1447 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1448 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1449 return num_ch < 0 ? num_ch : -EINVAL;
1450 }
1451
1452 /* Bind to SD modulator IIO device */
1453 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1454 if (IS_ERR(adc->hwc))
1455 return -EPROBE_DEFER;
1456
1457 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1458 GFP_KERNEL);
1459 if (!ch)
1460 return -ENOMEM;
1461
1462 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1463 ch[chan_idx].scan_index = chan_idx;
1464 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1465 if (ret < 0) {
1466 dev_err(&indio_dev->dev, "Channels init failed\n");
1467 return ret;
1468 }
1469 }
1470
1471 indio_dev->num_channels = num_ch;
1472 indio_dev->channels = ch;
1473
1474 init_completion(&adc->completion);
1475
1476 /* Optionally request DMA */
1477 ret = stm32_dfsdm_dma_request(dev, indio_dev);
1478 if (ret) {
1479 if (ret != -ENODEV)
1480 return dev_err_probe(dev, ret,
1481 "DMA channel request failed with\n");
1482
1483 dev_dbg(dev, "No DMA support\n");
1484 return 0;
1485 }
1486
1487 ret = iio_triggered_buffer_setup(indio_dev,
1488 &iio_pollfunc_store_time, NULL,
1489 &stm32_dfsdm_buffer_setup_ops);
1490 if (ret) {
1491 stm32_dfsdm_dma_release(indio_dev);
1492 dev_err(&indio_dev->dev, "buffer setup failed\n");
1493 return ret;
1494 }
1495
1496 /* lptimer/timer hardware triggers */
1497 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1498
1499 return 0;
1500}
1501
1502static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1503 .type = DFSDM_IIO,
1504 .init = stm32_dfsdm_adc_init,
1505};
1506
1507static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1508 .type = DFSDM_AUDIO,
1509 .init = stm32_dfsdm_audio_init,
1510};
1511
1512static const struct of_device_id stm32_dfsdm_adc_match[] = {
1513 {
1514 .compatible = "st,stm32-dfsdm-adc",
1515 .data = &stm32h7_dfsdm_adc_data,
1516 },
1517 {
1518 .compatible = "st,stm32-dfsdm-dmic",
1519 .data = &stm32h7_dfsdm_audio_data,
1520 },
1521 {}
1522};
1523MODULE_DEVICE_TABLE(of, stm32_dfsdm_adc_match);
1524
1525static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1526{
1527 struct device *dev = &pdev->dev;
1528 struct stm32_dfsdm_adc *adc;
1529 struct device_node *np = dev->of_node;
1530 const struct stm32_dfsdm_dev_data *dev_data;
1531 struct iio_dev *iio;
1532 char *name;
1533 int ret, irq, val;
1534
1535 dev_data = of_device_get_match_data(dev);
1536 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1537 if (!iio) {
1538 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1539 return -ENOMEM;
1540 }
1541
1542 adc = iio_priv(iio);
1543 adc->dfsdm = dev_get_drvdata(dev->parent);
1544
1545 iio->dev.of_node = np;
1546 iio->modes = INDIO_DIRECT_MODE;
1547
1548 platform_set_drvdata(pdev, iio);
1549
1550 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1551 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1552 dev_err(dev, "Missing or bad reg property\n");
1553 return -EINVAL;
1554 }
1555
1556 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1557 if (!name)
1558 return -ENOMEM;
1559 if (dev_data->type == DFSDM_AUDIO) {
1560 iio->info = &stm32_dfsdm_info_audio;
1561 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1562 } else {
1563 iio->info = &stm32_dfsdm_info_adc;
1564 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1565 }
1566 iio->name = name;
1567
1568 /*
1569 * In a first step IRQs generated for channels are not treated.
1570 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1571 */
1572 irq = platform_get_irq(pdev, 0);
1573 if (irq < 0)
1574 return irq;
1575
1576 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1577 0, pdev->name, iio);
1578 if (ret < 0) {
1579 dev_err(dev, "Failed to request IRQ\n");
1580 return ret;
1581 }
1582
1583 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1584 if (ret < 0) {
1585 dev_err(dev, "Failed to set filter order\n");
1586 return ret;
1587 }
1588
1589 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1590
1591 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1592 if (!ret)
1593 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1594
1595 adc->dev_data = dev_data;
1596 ret = dev_data->init(dev, iio);
1597 if (ret < 0)
1598 return ret;
1599
1600 ret = iio_device_register(iio);
1601 if (ret < 0)
1602 goto err_cleanup;
1603
1604 if (dev_data->type == DFSDM_AUDIO) {
1605 ret = of_platform_populate(np, NULL, NULL, dev);
1606 if (ret < 0) {
1607 dev_err(dev, "Failed to find an audio DAI\n");
1608 goto err_unregister;
1609 }
1610 }
1611
1612 return 0;
1613
1614err_unregister:
1615 iio_device_unregister(iio);
1616err_cleanup:
1617 stm32_dfsdm_dma_release(iio);
1618
1619 return ret;
1620}
1621
1622static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1623{
1624 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1625 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1626
1627 if (adc->dev_data->type == DFSDM_AUDIO)
1628 of_platform_depopulate(&pdev->dev);
1629 iio_device_unregister(indio_dev);
1630 stm32_dfsdm_dma_release(indio_dev);
1631
1632 return 0;
1633}
1634
1635static int stm32_dfsdm_adc_suspend(struct device *dev)
1636{
1637 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1638
1639 if (iio_buffer_enabled(indio_dev))
1640 stm32_dfsdm_predisable(indio_dev);
1641
1642 return 0;
1643}
1644
1645static int stm32_dfsdm_adc_resume(struct device *dev)
1646{
1647 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1648 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1649 const struct iio_chan_spec *chan;
1650 struct stm32_dfsdm_channel *ch;
1651 int i, ret;
1652
1653 /* restore channels configuration */
1654 for (i = 0; i < indio_dev->num_channels; i++) {
1655 chan = indio_dev->channels + i;
1656 ch = &adc->dfsdm->ch_list[chan->channel];
1657 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1658 if (ret)
1659 return ret;
1660 }
1661
1662 if (iio_buffer_enabled(indio_dev))
1663 stm32_dfsdm_postenable(indio_dev);
1664
1665 return 0;
1666}
1667
1668static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1669 stm32_dfsdm_adc_suspend,
1670 stm32_dfsdm_adc_resume);
1671
1672static struct platform_driver stm32_dfsdm_adc_driver = {
1673 .driver = {
1674 .name = "stm32-dfsdm-adc",
1675 .of_match_table = stm32_dfsdm_adc_match,
1676 .pm = pm_sleep_ptr(&stm32_dfsdm_adc_pm_ops),
1677 },
1678 .probe = stm32_dfsdm_adc_probe,
1679 .remove = stm32_dfsdm_adc_remove,
1680};
1681module_platform_driver(stm32_dfsdm_adc_driver);
1682
1683MODULE_DESCRIPTION("STM32 sigma delta ADC");
1684MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1685MODULE_LICENSE("GPL v2");