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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is the ADC part of the STM32 DFSDM driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
7 */
8
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/iio/adc/stm32-dfsdm-adc.h>
12#include <linux/iio/buffer.h>
13#include <linux/iio/hw-consumer.h>
14#include <linux/iio/sysfs.h>
15#include <linux/iio/timer/stm32-lptim-trigger.h>
16#include <linux/iio/timer/stm32-timer-trigger.h>
17#include <linux/iio/trigger.h>
18#include <linux/iio/trigger_consumer.h>
19#include <linux/iio/triggered_buffer.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26
27#include "stm32-dfsdm.h"
28
29#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
30
31/* Conversion timeout */
32#define DFSDM_TIMEOUT_US 100000
33#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
34
35/* Oversampling attribute default */
36#define DFSDM_DEFAULT_OVERSAMPLING 100
37
38/* Oversampling max values */
39#define DFSDM_MAX_INT_OVERSAMPLING 256
40#define DFSDM_MAX_FL_OVERSAMPLING 1024
41
42/* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
43#define DFSDM_DATA_MAX BIT(30)
44/*
45 * Data are output as two's complement data in a 24 bit field.
46 * Data from filters are in the range +/-2^(n-1)
47 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
48 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
49 * So, the resolution of samples from filter is actually limited to 23 bits
50 */
51#define DFSDM_DATA_RES 24
52
53/* Filter configuration */
54#define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
55 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
56 DFSDM_CR1_JSCAN_MASK)
57
58enum sd_converter_type {
59 DFSDM_AUDIO,
60 DFSDM_IIO,
61};
62
63struct stm32_dfsdm_dev_data {
64 int type;
65 int (*init)(struct device *dev, struct iio_dev *indio_dev);
66 unsigned int num_channels;
67 const struct regmap_config *regmap_cfg;
68};
69
70struct stm32_dfsdm_adc {
71 struct stm32_dfsdm *dfsdm;
72 const struct stm32_dfsdm_dev_data *dev_data;
73 unsigned int fl_id;
74 unsigned int nconv;
75 unsigned long smask;
76
77 /* ADC specific */
78 unsigned int oversamp;
79 struct iio_hw_consumer *hwc;
80 struct completion completion;
81 u32 *buffer;
82
83 /* Audio specific */
84 unsigned int spi_freq; /* SPI bus clock frequency */
85 unsigned int sample_freq; /* Sample frequency after filter decimation */
86 int (*cb)(const void *data, size_t size, void *cb_priv);
87 void *cb_priv;
88
89 /* DMA */
90 u8 *rx_buf;
91 unsigned int bufi; /* Buffer current position */
92 unsigned int buf_sz; /* Buffer size */
93 struct dma_chan *dma_chan;
94 dma_addr_t dma_buf;
95};
96
97struct stm32_dfsdm_str2field {
98 const char *name;
99 unsigned int val;
100};
101
102/* DFSDM channel serial interface type */
103static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
104 { "SPI_R", 0 }, /* SPI with data on rising edge */
105 { "SPI_F", 1 }, /* SPI with data on falling edge */
106 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
107 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
108 {},
109};
110
111/* DFSDM channel clock source */
112static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
113 /* External SPI clock (CLKIN x) */
114 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
115 /* Internal SPI clock (CLKOUT) */
116 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
117 /* Internal SPI clock divided by 2 (falling edge) */
118 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
119 /* Internal SPI clock divided by 2 (falling edge) */
120 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
121 {},
122};
123
124static int stm32_dfsdm_str2val(const char *str,
125 const struct stm32_dfsdm_str2field *list)
126{
127 const struct stm32_dfsdm_str2field *p = list;
128
129 for (p = list; p && p->name; p++)
130 if (!strcmp(p->name, str))
131 return p->val;
132
133 return -EINVAL;
134}
135
136/**
137 * struct stm32_dfsdm_trig_info - DFSDM trigger info
138 * @name: name of the trigger, corresponding to its source
139 * @jextsel: trigger signal selection
140 */
141struct stm32_dfsdm_trig_info {
142 const char *name;
143 unsigned int jextsel;
144};
145
146/* hardware injected trigger enable, edge selection */
147enum stm32_dfsdm_jexten {
148 STM32_DFSDM_JEXTEN_DISABLED,
149 STM32_DFSDM_JEXTEN_RISING_EDGE,
150 STM32_DFSDM_JEXTEN_FALLING_EDGE,
151 STM32_DFSDM_EXTEN_BOTH_EDGES,
152};
153
154static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
155 { TIM1_TRGO, 0 },
156 { TIM1_TRGO2, 1 },
157 { TIM8_TRGO, 2 },
158 { TIM8_TRGO2, 3 },
159 { TIM3_TRGO, 4 },
160 { TIM4_TRGO, 5 },
161 { TIM16_OC1, 6 },
162 { TIM6_TRGO, 7 },
163 { TIM7_TRGO, 8 },
164 { LPTIM1_OUT, 26 },
165 { LPTIM2_OUT, 27 },
166 { LPTIM3_OUT, 28 },
167 {},
168};
169
170static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
171 struct iio_trigger *trig)
172{
173 int i;
174
175 /* lookup triggers registered by stm32 timer trigger driver */
176 for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
177 /**
178 * Checking both stm32 timer trigger type and trig name
179 * should be safe against arbitrary trigger names.
180 */
181 if ((is_stm32_timer_trigger(trig) ||
182 is_stm32_lptim_trigger(trig)) &&
183 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
184 return stm32_dfsdm_trigs[i].jextsel;
185 }
186 }
187
188 return -EINVAL;
189}
190
191static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
192 unsigned int fast, unsigned int oversamp)
193{
194 unsigned int i, d, fosr, iosr;
195 u64 res, max;
196 int bits, shift;
197 unsigned int m = 1; /* multiplication factor */
198 unsigned int p = fl->ford; /* filter order (ford) */
199 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
200
201 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
202 /*
203 * This function tries to compute filter oversampling and integrator
204 * oversampling, base on oversampling ratio requested by user.
205 *
206 * Decimation d depends on the filter order and the oversampling ratios.
207 * ford: filter order
208 * fosr: filter over sampling ratio
209 * iosr: integrator over sampling ratio
210 */
211 if (fl->ford == DFSDM_FASTSINC_ORDER) {
212 m = 2;
213 p = 2;
214 }
215
216 /*
217 * Look for filter and integrator oversampling ratios which allows
218 * to maximize data output resolution.
219 */
220 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
221 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
222 if (fast)
223 d = fosr * iosr;
224 else if (fl->ford == DFSDM_FASTSINC_ORDER)
225 d = fosr * (iosr + 3) + 2;
226 else
227 d = fosr * (iosr - 1 + p) + p;
228
229 if (d > oversamp)
230 break;
231 else if (d != oversamp)
232 continue;
233 /*
234 * Check resolution (limited to signed 32 bits)
235 * res <= 2^31
236 * Sincx filters:
237 * res = m * fosr^p x iosr (with m=1, p=ford)
238 * FastSinc filter
239 * res = m * fosr^p x iosr (with m=2, p=2)
240 */
241 res = fosr;
242 for (i = p - 1; i > 0; i--) {
243 res = res * (u64)fosr;
244 if (res > DFSDM_DATA_MAX)
245 break;
246 }
247 if (res > DFSDM_DATA_MAX)
248 continue;
249
250 res = res * (u64)m * (u64)iosr;
251 if (res > DFSDM_DATA_MAX)
252 continue;
253
254 if (res >= flo->res) {
255 flo->res = res;
256 flo->fosr = fosr;
257 flo->iosr = iosr;
258
259 bits = fls(flo->res);
260 /* 8 LBSs in data register contain chan info */
261 max = flo->res << 8;
262
263 /* if resolution is not a power of two */
264 if (flo->res > BIT(bits - 1))
265 bits++;
266 else
267 max--;
268
269 shift = DFSDM_DATA_RES - bits;
270 /*
271 * Compute right/left shift
272 * Right shift is performed by hardware
273 * when transferring samples to data register.
274 * Left shift is done by software on buffer
275 */
276 if (shift > 0) {
277 /* Resolution is lower than 24 bits */
278 flo->rshift = 0;
279 flo->lshift = shift;
280 } else {
281 /*
282 * If resolution is 24 bits or more,
283 * max positive value may be ambiguous
284 * (equal to max negative value as sign
285 * bit is dropped).
286 * Reduce resolution to 23 bits (rshift)
287 * to keep the sign on bit 23 and treat
288 * saturation before rescaling on 24
289 * bits (lshift).
290 */
291 flo->rshift = 1 - shift;
292 flo->lshift = 1;
293 max >>= flo->rshift;
294 }
295 flo->max = (s32)max;
296
297 pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
298 __func__, fast, flo->fosr, flo->iosr,
299 flo->res, bits, flo->rshift,
300 flo->lshift);
301 }
302 }
303 }
304
305 if (!flo->res)
306 return -EINVAL;
307
308 return 0;
309}
310
311static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
312 unsigned int oversamp)
313{
314 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
315 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
316 int ret0, ret1;
317
318 memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
319 memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
320
321 ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
322 ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
323 if (ret0 < 0 && ret1 < 0) {
324 dev_err(&indio_dev->dev,
325 "Filter parameters not found: errors %d/%d\n",
326 ret0, ret1);
327 return -EINVAL;
328 }
329
330 return 0;
331}
332
333static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
334{
335 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
336 struct regmap *regmap = adc->dfsdm->regmap;
337 const struct iio_chan_spec *chan;
338 unsigned int bit;
339 int ret;
340
341 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
342 chan = indio_dev->channels + bit;
343 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
344 DFSDM_CHCFGR1_CHEN_MASK,
345 DFSDM_CHCFGR1_CHEN(1));
346 if (ret < 0)
347 return ret;
348 }
349
350 return 0;
351}
352
353static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
354{
355 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
356 struct regmap *regmap = adc->dfsdm->regmap;
357 const struct iio_chan_spec *chan;
358 unsigned int bit;
359
360 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
361 chan = indio_dev->channels + bit;
362 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
363 DFSDM_CHCFGR1_CHEN_MASK,
364 DFSDM_CHCFGR1_CHEN(0));
365 }
366}
367
368static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
369 struct stm32_dfsdm_channel *ch)
370{
371 unsigned int id = ch->id;
372 struct regmap *regmap = dfsdm->regmap;
373 int ret;
374
375 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
376 DFSDM_CHCFGR1_SITP_MASK,
377 DFSDM_CHCFGR1_SITP(ch->type));
378 if (ret < 0)
379 return ret;
380 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
381 DFSDM_CHCFGR1_SPICKSEL_MASK,
382 DFSDM_CHCFGR1_SPICKSEL(ch->src));
383 if (ret < 0)
384 return ret;
385 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
386 DFSDM_CHCFGR1_CHINSEL_MASK,
387 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
388}
389
390static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
391 unsigned int fl_id,
392 struct iio_trigger *trig)
393{
394 struct stm32_dfsdm *dfsdm = adc->dfsdm;
395 int ret;
396
397 /* Enable filter */
398 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
399 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
400 if (ret < 0)
401 return ret;
402
403 /* Nothing more to do for injected (scan mode/triggered) conversions */
404 if (adc->nconv > 1 || trig)
405 return 0;
406
407 /* Software start (single or continuous) regular conversion */
408 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
409 DFSDM_CR1_RSWSTART_MASK,
410 DFSDM_CR1_RSWSTART(1));
411}
412
413static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
414 unsigned int fl_id)
415{
416 /* Disable conversion */
417 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
418 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
419}
420
421static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
422 unsigned int fl_id,
423 struct iio_trigger *trig)
424{
425 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
426 struct regmap *regmap = adc->dfsdm->regmap;
427 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
428 int ret;
429
430 if (trig) {
431 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
432 if (ret < 0)
433 return ret;
434
435 /* set trigger source and polarity (default to rising edge) */
436 jextsel = ret;
437 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
438 }
439
440 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
441 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
442 DFSDM_CR1_JEXTSEL(jextsel) |
443 DFSDM_CR1_JEXTEN(jexten));
444 if (ret < 0)
445 return ret;
446
447 return 0;
448}
449
450static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
451 unsigned int fl_id,
452 struct iio_trigger *trig)
453{
454 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
455 struct regmap *regmap = adc->dfsdm->regmap;
456 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
457 struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
458 const struct iio_chan_spec *chan;
459 unsigned int bit;
460 int ret;
461
462 fl->fast = 0;
463
464 /*
465 * In continuous mode, use fast mode configuration,
466 * if it provides a better resolution.
467 */
468 if (adc->nconv == 1 && !trig &&
469 (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
470 if (fl->flo[1].res >= fl->flo[0].res) {
471 fl->fast = 1;
472 flo = &fl->flo[1];
473 }
474 }
475
476 if (!flo->res)
477 return -EINVAL;
478
479 for_each_set_bit(bit, &adc->smask,
480 sizeof(adc->smask) * BITS_PER_BYTE) {
481 chan = indio_dev->channels + bit;
482
483 ret = regmap_update_bits(regmap,
484 DFSDM_CHCFGR2(chan->channel),
485 DFSDM_CHCFGR2_DTRBS_MASK,
486 DFSDM_CHCFGR2_DTRBS(flo->rshift));
487 if (ret)
488 return ret;
489 }
490
491 return 0;
492}
493
494static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
495 unsigned int fl_id,
496 struct iio_trigger *trig)
497{
498 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
499 struct regmap *regmap = adc->dfsdm->regmap;
500 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
501 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
502 u32 cr1;
503 const struct iio_chan_spec *chan;
504 unsigned int bit, jchg = 0;
505 int ret;
506
507 /* Average integrator oversampling */
508 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
509 DFSDM_FCR_IOSR(flo->iosr - 1));
510 if (ret)
511 return ret;
512
513 /* Filter order and Oversampling */
514 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
515 DFSDM_FCR_FOSR(flo->fosr - 1));
516 if (ret)
517 return ret;
518
519 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
520 DFSDM_FCR_FORD(fl->ford));
521 if (ret)
522 return ret;
523
524 ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
525 if (ret)
526 return ret;
527
528 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
529 DFSDM_CR1_FAST_MASK,
530 DFSDM_CR1_FAST(fl->fast));
531 if (ret)
532 return ret;
533
534 /*
535 * DFSDM modes configuration W.R.T audio/iio type modes
536 * ----------------------------------------------------------------
537 * Modes | regular | regular | injected | injected |
538 * | | continuous | | + scan |
539 * --------------|---------|--------------|----------|------------|
540 * single conv | x | | | |
541 * (1 chan) | | | | |
542 * --------------|---------|--------------|----------|------------|
543 * 1 Audio chan | | sample freq | | |
544 * | | or sync_mode | | |
545 * --------------|---------|--------------|----------|------------|
546 * 1 IIO chan | | sample freq | trigger | |
547 * | | or sync_mode | | |
548 * --------------|---------|--------------|----------|------------|
549 * 2+ IIO chans | | | | trigger or |
550 * | | | | sync_mode |
551 * ----------------------------------------------------------------
552 */
553 if (adc->nconv == 1 && !trig) {
554 bit = __ffs(adc->smask);
555 chan = indio_dev->channels + bit;
556
557 /* Use regular conversion for single channel without trigger */
558 cr1 = DFSDM_CR1_RCH(chan->channel);
559
560 /* Continuous conversions triggered by SPI clk in buffer mode */
561 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
562 cr1 |= DFSDM_CR1_RCONT(1);
563
564 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
565 } else {
566 /* Use injected conversion for multiple channels */
567 for_each_set_bit(bit, &adc->smask,
568 sizeof(adc->smask) * BITS_PER_BYTE) {
569 chan = indio_dev->channels + bit;
570 jchg |= BIT(chan->channel);
571 }
572 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
573 if (ret < 0)
574 return ret;
575
576 /* Use scan mode for multiple channels */
577 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
578
579 /*
580 * Continuous conversions not supported in injected mode,
581 * either use:
582 * - conversions in sync with filter 0
583 * - triggered conversions
584 */
585 if (!fl->sync_mode && !trig)
586 return -EINVAL;
587 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
588 }
589
590 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
591 cr1);
592}
593
594static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
595 struct iio_dev *indio_dev,
596 struct iio_chan_spec *ch)
597{
598 struct stm32_dfsdm_channel *df_ch;
599 const char *of_str;
600 int chan_idx = ch->scan_index;
601 int ret, val;
602
603 ret = of_property_read_u32_index(indio_dev->dev.of_node,
604 "st,adc-channels", chan_idx,
605 &ch->channel);
606 if (ret < 0) {
607 dev_err(&indio_dev->dev,
608 " Error parsing 'st,adc-channels' for idx %d\n",
609 chan_idx);
610 return ret;
611 }
612 if (ch->channel >= dfsdm->num_chs) {
613 dev_err(&indio_dev->dev,
614 " Error bad channel number %d (max = %d)\n",
615 ch->channel, dfsdm->num_chs);
616 return -EINVAL;
617 }
618
619 ret = of_property_read_string_index(indio_dev->dev.of_node,
620 "st,adc-channel-names", chan_idx,
621 &ch->datasheet_name);
622 if (ret < 0) {
623 dev_err(&indio_dev->dev,
624 " Error parsing 'st,adc-channel-names' for idx %d\n",
625 chan_idx);
626 return ret;
627 }
628
629 df_ch = &dfsdm->ch_list[ch->channel];
630 df_ch->id = ch->channel;
631
632 ret = of_property_read_string_index(indio_dev->dev.of_node,
633 "st,adc-channel-types", chan_idx,
634 &of_str);
635 if (!ret) {
636 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
637 if (val < 0)
638 return val;
639 } else {
640 val = 0;
641 }
642 df_ch->type = val;
643
644 ret = of_property_read_string_index(indio_dev->dev.of_node,
645 "st,adc-channel-clk-src", chan_idx,
646 &of_str);
647 if (!ret) {
648 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
649 if (val < 0)
650 return val;
651 } else {
652 val = 0;
653 }
654 df_ch->src = val;
655
656 ret = of_property_read_u32_index(indio_dev->dev.of_node,
657 "st,adc-alt-channel", chan_idx,
658 &df_ch->alt_si);
659 if (ret < 0)
660 df_ch->alt_si = 0;
661
662 return 0;
663}
664
665static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
666 uintptr_t priv,
667 const struct iio_chan_spec *chan,
668 char *buf)
669{
670 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
671
672 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
673}
674
675static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
676 unsigned int sample_freq,
677 unsigned int spi_freq)
678{
679 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
680 unsigned int oversamp;
681 int ret;
682
683 oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
684 if (spi_freq % sample_freq)
685 dev_dbg(&indio_dev->dev,
686 "Rate not accurate. requested (%u), actual (%u)\n",
687 sample_freq, spi_freq / oversamp);
688
689 ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
690 if (ret < 0)
691 return ret;
692
693 adc->sample_freq = spi_freq / oversamp;
694 adc->oversamp = oversamp;
695
696 return 0;
697}
698
699static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
700 uintptr_t priv,
701 const struct iio_chan_spec *chan,
702 const char *buf, size_t len)
703{
704 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
705 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
706 unsigned int sample_freq = adc->sample_freq;
707 unsigned int spi_freq;
708 int ret;
709
710 dev_err(&indio_dev->dev, "enter %s\n", __func__);
711 /* If DFSDM is master on SPI, SPI freq can not be updated */
712 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
713 return -EPERM;
714
715 ret = kstrtoint(buf, 0, &spi_freq);
716 if (ret)
717 return ret;
718
719 if (!spi_freq)
720 return -EINVAL;
721
722 if (sample_freq) {
723 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
724 if (ret < 0)
725 return ret;
726 }
727 adc->spi_freq = spi_freq;
728
729 return len;
730}
731
732static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
733 struct iio_trigger *trig)
734{
735 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
736 struct regmap *regmap = adc->dfsdm->regmap;
737 int ret;
738
739 ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
740 if (ret < 0)
741 return ret;
742
743 ret = stm32_dfsdm_start_channel(indio_dev);
744 if (ret < 0)
745 return ret;
746
747 ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
748 if (ret < 0)
749 goto stop_channels;
750
751 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
752 if (ret < 0)
753 goto filter_unconfigure;
754
755 return 0;
756
757filter_unconfigure:
758 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
759 DFSDM_CR1_CFG_MASK, 0);
760stop_channels:
761 stm32_dfsdm_stop_channel(indio_dev);
762
763 return ret;
764}
765
766static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
767{
768 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
769 struct regmap *regmap = adc->dfsdm->regmap;
770
771 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
772
773 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
774 DFSDM_CR1_CFG_MASK, 0);
775
776 stm32_dfsdm_stop_channel(indio_dev);
777}
778
779static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
780 unsigned int val)
781{
782 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
783 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
784 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
785
786 /*
787 * DMA cyclic transfers are used, buffer is split into two periods.
788 * There should be :
789 * - always one buffer (period) DMA is working on
790 * - one buffer (period) driver pushed to ASoC side.
791 */
792 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
793 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
794
795 return 0;
796}
797
798static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
799{
800 struct dma_tx_state state;
801 enum dma_status status;
802
803 status = dmaengine_tx_status(adc->dma_chan,
804 adc->dma_chan->cookie,
805 &state);
806 if (status == DMA_IN_PROGRESS) {
807 /* Residue is size in bytes from end of buffer */
808 unsigned int i = adc->buf_sz - state.residue;
809 unsigned int size;
810
811 /* Return available bytes */
812 if (i >= adc->bufi)
813 size = i - adc->bufi;
814 else
815 size = adc->buf_sz + i - adc->bufi;
816
817 return size;
818 }
819
820 return 0;
821}
822
823static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
824 s32 *buffer)
825{
826 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
827 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
828 unsigned int i = adc->nconv;
829 s32 *ptr = buffer;
830
831 while (i--) {
832 /* Mask 8 LSB that contains the channel ID */
833 *ptr &= 0xFFFFFF00;
834 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
835 if (*ptr > flo->max)
836 *ptr -= 1;
837 /*
838 * Samples from filter are retrieved with 23 bits resolution
839 * or less. Shift left to align MSB on 24 bits.
840 */
841 *ptr <<= flo->lshift;
842
843 ptr++;
844 }
845}
846
847static void stm32_dfsdm_dma_buffer_done(void *data)
848{
849 struct iio_dev *indio_dev = data;
850 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
851 int available = stm32_dfsdm_adc_dma_residue(adc);
852 size_t old_pos;
853
854 /*
855 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
856 * offers only an interface to push data samples per samples.
857 * For this reason IIO buffer interface is not used and interface is
858 * bypassed using a private callback registered by ASoC.
859 * This should be a temporary solution waiting a cyclic DMA engine
860 * support in IIO.
861 */
862
863 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
864 adc->bufi, available);
865 old_pos = adc->bufi;
866
867 while (available >= indio_dev->scan_bytes) {
868 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
869
870 stm32_dfsdm_process_data(adc, buffer);
871
872 available -= indio_dev->scan_bytes;
873 adc->bufi += indio_dev->scan_bytes;
874 if (adc->bufi >= adc->buf_sz) {
875 if (adc->cb)
876 adc->cb(&adc->rx_buf[old_pos],
877 adc->buf_sz - old_pos, adc->cb_priv);
878 adc->bufi = 0;
879 old_pos = 0;
880 }
881 /*
882 * In DMA mode the trigger services of IIO are not used
883 * (e.g. no call to iio_trigger_poll).
884 * Calling irq handler associated to the hardware trigger is not
885 * relevant as the conversions have already been done. Data
886 * transfers are performed directly in DMA callback instead.
887 * This implementation avoids to call trigger irq handler that
888 * may sleep, in an atomic context (DMA irq handler context).
889 */
890 if (adc->dev_data->type == DFSDM_IIO)
891 iio_push_to_buffers(indio_dev, buffer);
892 }
893 if (adc->cb)
894 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
895 adc->cb_priv);
896}
897
898static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
899{
900 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
901 /*
902 * The DFSDM supports half-word transfers. However, for 16 bits record,
903 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
904 * shift is required.
905 */
906 struct dma_slave_config config = {
907 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
908 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
909 };
910 struct dma_async_tx_descriptor *desc;
911 dma_cookie_t cookie;
912 int ret;
913
914 if (!adc->dma_chan)
915 return -EINVAL;
916
917 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
918 adc->buf_sz, adc->buf_sz / 2);
919
920 if (adc->nconv == 1 && !indio_dev->trig)
921 config.src_addr += DFSDM_RDATAR(adc->fl_id);
922 else
923 config.src_addr += DFSDM_JDATAR(adc->fl_id);
924 ret = dmaengine_slave_config(adc->dma_chan, &config);
925 if (ret)
926 return ret;
927
928 /* Prepare a DMA cyclic transaction */
929 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
930 adc->dma_buf,
931 adc->buf_sz, adc->buf_sz / 2,
932 DMA_DEV_TO_MEM,
933 DMA_PREP_INTERRUPT);
934 if (!desc)
935 return -EBUSY;
936
937 desc->callback = stm32_dfsdm_dma_buffer_done;
938 desc->callback_param = indio_dev;
939
940 cookie = dmaengine_submit(desc);
941 ret = dma_submit_error(cookie);
942 if (ret)
943 goto err_stop_dma;
944
945 /* Issue pending DMA requests */
946 dma_async_issue_pending(adc->dma_chan);
947
948 if (adc->nconv == 1 && !indio_dev->trig) {
949 /* Enable regular DMA transfer*/
950 ret = regmap_update_bits(adc->dfsdm->regmap,
951 DFSDM_CR1(adc->fl_id),
952 DFSDM_CR1_RDMAEN_MASK,
953 DFSDM_CR1_RDMAEN_MASK);
954 } else {
955 /* Enable injected DMA transfer*/
956 ret = regmap_update_bits(adc->dfsdm->regmap,
957 DFSDM_CR1(adc->fl_id),
958 DFSDM_CR1_JDMAEN_MASK,
959 DFSDM_CR1_JDMAEN_MASK);
960 }
961
962 if (ret < 0)
963 goto err_stop_dma;
964
965 return 0;
966
967err_stop_dma:
968 dmaengine_terminate_all(adc->dma_chan);
969
970 return ret;
971}
972
973static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
974{
975 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
976
977 if (!adc->dma_chan)
978 return;
979
980 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
981 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
982 dmaengine_terminate_all(adc->dma_chan);
983}
984
985static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
986 const unsigned long *scan_mask)
987{
988 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
989
990 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
991 adc->smask = *scan_mask;
992
993 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
994
995 return 0;
996}
997
998static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
999{
1000 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1001 int ret;
1002
1003 /* Reset adc buffer index */
1004 adc->bufi = 0;
1005
1006 if (adc->hwc) {
1007 ret = iio_hw_consumer_enable(adc->hwc);
1008 if (ret < 0)
1009 return ret;
1010 }
1011
1012 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1013 if (ret < 0)
1014 goto err_stop_hwc;
1015
1016 ret = stm32_dfsdm_adc_dma_start(indio_dev);
1017 if (ret) {
1018 dev_err(&indio_dev->dev, "Can't start DMA\n");
1019 goto stop_dfsdm;
1020 }
1021
1022 ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
1023 if (ret) {
1024 dev_err(&indio_dev->dev, "Can't start conversion\n");
1025 goto err_stop_dma;
1026 }
1027
1028 return 0;
1029
1030err_stop_dma:
1031 stm32_dfsdm_adc_dma_stop(indio_dev);
1032stop_dfsdm:
1033 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1034err_stop_hwc:
1035 if (adc->hwc)
1036 iio_hw_consumer_disable(adc->hwc);
1037
1038 return ret;
1039}
1040
1041static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1042{
1043 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1044
1045 stm32_dfsdm_stop_conv(indio_dev);
1046
1047 stm32_dfsdm_adc_dma_stop(indio_dev);
1048
1049 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1050
1051 if (adc->hwc)
1052 iio_hw_consumer_disable(adc->hwc);
1053
1054 return 0;
1055}
1056
1057static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1058 .postenable = &stm32_dfsdm_postenable,
1059 .predisable = &stm32_dfsdm_predisable,
1060};
1061
1062/**
1063 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1064 * DMA transfer period is achieved.
1065 *
1066 * @iio_dev: Handle to IIO device.
1067 * @cb: Pointer to callback function:
1068 * - data: pointer to data buffer
1069 * - size: size in byte of the data buffer
1070 * - private: pointer to consumer private structure.
1071 * @private: Pointer to consumer private structure.
1072 */
1073int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1074 int (*cb)(const void *data, size_t size,
1075 void *private),
1076 void *private)
1077{
1078 struct stm32_dfsdm_adc *adc;
1079
1080 if (!iio_dev)
1081 return -EINVAL;
1082 adc = iio_priv(iio_dev);
1083
1084 adc->cb = cb;
1085 adc->cb_priv = private;
1086
1087 return 0;
1088}
1089EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1090
1091/**
1092 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1093 *
1094 * @iio_dev: Handle to IIO device.
1095 */
1096int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1097{
1098 struct stm32_dfsdm_adc *adc;
1099
1100 if (!iio_dev)
1101 return -EINVAL;
1102 adc = iio_priv(iio_dev);
1103
1104 adc->cb = NULL;
1105 adc->cb_priv = NULL;
1106
1107 return 0;
1108}
1109EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1110
1111static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1112 const struct iio_chan_spec *chan, int *res)
1113{
1114 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1115 long timeout;
1116 int ret;
1117
1118 reinit_completion(&adc->completion);
1119
1120 adc->buffer = res;
1121
1122 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1123 if (ret < 0)
1124 return ret;
1125
1126 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1127 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1128 if (ret < 0)
1129 goto stop_dfsdm;
1130
1131 adc->nconv = 1;
1132 adc->smask = BIT(chan->scan_index);
1133 ret = stm32_dfsdm_start_conv(indio_dev, NULL);
1134 if (ret < 0) {
1135 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1136 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1137 goto stop_dfsdm;
1138 }
1139
1140 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1141 DFSDM_TIMEOUT);
1142
1143 /* Mask IRQ for regular conversion achievement*/
1144 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1145 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1146
1147 if (timeout == 0)
1148 ret = -ETIMEDOUT;
1149 else if (timeout < 0)
1150 ret = timeout;
1151 else
1152 ret = IIO_VAL_INT;
1153
1154 stm32_dfsdm_stop_conv(indio_dev);
1155
1156 stm32_dfsdm_process_data(adc, res);
1157
1158stop_dfsdm:
1159 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1160
1161 return ret;
1162}
1163
1164static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1165 struct iio_chan_spec const *chan,
1166 int val, int val2, long mask)
1167{
1168 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1169 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1170 unsigned int spi_freq;
1171 int ret = -EINVAL;
1172
1173 switch (ch->src) {
1174 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1175 spi_freq = adc->dfsdm->spi_master_freq;
1176 break;
1177 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1178 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1179 spi_freq = adc->dfsdm->spi_master_freq / 2;
1180 break;
1181 default:
1182 spi_freq = adc->spi_freq;
1183 }
1184
1185 switch (mask) {
1186 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1187 ret = iio_device_claim_direct_mode(indio_dev);
1188 if (ret)
1189 return ret;
1190
1191 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1192 if (!ret) {
1193 dev_dbg(&indio_dev->dev,
1194 "Sampling rate changed from (%u) to (%u)\n",
1195 adc->sample_freq, spi_freq / val);
1196 adc->oversamp = val;
1197 adc->sample_freq = spi_freq / val;
1198 }
1199 iio_device_release_direct_mode(indio_dev);
1200 return ret;
1201
1202 case IIO_CHAN_INFO_SAMP_FREQ:
1203 if (!val)
1204 return -EINVAL;
1205
1206 ret = iio_device_claim_direct_mode(indio_dev);
1207 if (ret)
1208 return ret;
1209
1210 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1211 iio_device_release_direct_mode(indio_dev);
1212 return ret;
1213 }
1214
1215 return -EINVAL;
1216}
1217
1218static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1219 struct iio_chan_spec const *chan, int *val,
1220 int *val2, long mask)
1221{
1222 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1223 int ret;
1224
1225 switch (mask) {
1226 case IIO_CHAN_INFO_RAW:
1227 ret = iio_device_claim_direct_mode(indio_dev);
1228 if (ret)
1229 return ret;
1230 ret = iio_hw_consumer_enable(adc->hwc);
1231 if (ret < 0) {
1232 dev_err(&indio_dev->dev,
1233 "%s: IIO enable failed (channel %d)\n",
1234 __func__, chan->channel);
1235 iio_device_release_direct_mode(indio_dev);
1236 return ret;
1237 }
1238 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1239 iio_hw_consumer_disable(adc->hwc);
1240 if (ret < 0) {
1241 dev_err(&indio_dev->dev,
1242 "%s: Conversion failed (channel %d)\n",
1243 __func__, chan->channel);
1244 iio_device_release_direct_mode(indio_dev);
1245 return ret;
1246 }
1247 iio_device_release_direct_mode(indio_dev);
1248 return IIO_VAL_INT;
1249
1250 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1251 *val = adc->oversamp;
1252
1253 return IIO_VAL_INT;
1254
1255 case IIO_CHAN_INFO_SAMP_FREQ:
1256 *val = adc->sample_freq;
1257
1258 return IIO_VAL_INT;
1259 }
1260
1261 return -EINVAL;
1262}
1263
1264static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1265 struct iio_trigger *trig)
1266{
1267 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1268}
1269
1270static const struct iio_info stm32_dfsdm_info_audio = {
1271 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1272 .read_raw = stm32_dfsdm_read_raw,
1273 .write_raw = stm32_dfsdm_write_raw,
1274 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1275};
1276
1277static const struct iio_info stm32_dfsdm_info_adc = {
1278 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1279 .read_raw = stm32_dfsdm_read_raw,
1280 .write_raw = stm32_dfsdm_write_raw,
1281 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1282 .validate_trigger = stm32_dfsdm_validate_trigger,
1283};
1284
1285static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1286{
1287 struct iio_dev *indio_dev = arg;
1288 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1289 struct regmap *regmap = adc->dfsdm->regmap;
1290 unsigned int status, int_en;
1291
1292 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1293 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1294
1295 if (status & DFSDM_ISR_REOCF_MASK) {
1296 /* Read the data register clean the IRQ status */
1297 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1298 complete(&adc->completion);
1299 }
1300
1301 if (status & DFSDM_ISR_ROVRF_MASK) {
1302 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1303 dev_warn(&indio_dev->dev, "Overrun detected\n");
1304 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1305 DFSDM_ICR_CLRROVRF_MASK,
1306 DFSDM_ICR_CLRROVRF_MASK);
1307 }
1308
1309 return IRQ_HANDLED;
1310}
1311
1312/*
1313 * Define external info for SPI Frequency and audio sampling rate that can be
1314 * configured by ASoC driver through consumer.h API
1315 */
1316static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1317 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1318 {
1319 .name = "spi_clk_freq",
1320 .shared = IIO_SHARED_BY_TYPE,
1321 .read = dfsdm_adc_audio_get_spiclk,
1322 .write = dfsdm_adc_audio_set_spiclk,
1323 },
1324 {},
1325};
1326
1327static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1328{
1329 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1330
1331 if (adc->dma_chan) {
1332 dma_free_coherent(adc->dma_chan->device->dev,
1333 DFSDM_DMA_BUFFER_SIZE,
1334 adc->rx_buf, adc->dma_buf);
1335 dma_release_channel(adc->dma_chan);
1336 }
1337}
1338
1339static int stm32_dfsdm_dma_request(struct device *dev,
1340 struct iio_dev *indio_dev)
1341{
1342 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1343
1344 adc->dma_chan = dma_request_chan(dev, "rx");
1345 if (IS_ERR(adc->dma_chan)) {
1346 int ret = PTR_ERR(adc->dma_chan);
1347
1348 adc->dma_chan = NULL;
1349 return ret;
1350 }
1351
1352 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1353 DFSDM_DMA_BUFFER_SIZE,
1354 &adc->dma_buf, GFP_KERNEL);
1355 if (!adc->rx_buf) {
1356 dma_release_channel(adc->dma_chan);
1357 return -ENOMEM;
1358 }
1359
1360 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1361 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1362
1363 return 0;
1364}
1365
1366static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1367 struct iio_chan_spec *ch)
1368{
1369 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1370 int ret;
1371
1372 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1373 if (ret < 0)
1374 return ret;
1375
1376 ch->type = IIO_VOLTAGE;
1377 ch->indexed = 1;
1378
1379 /*
1380 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1381 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1382 */
1383 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1384 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1385 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1386
1387 if (adc->dev_data->type == DFSDM_AUDIO) {
1388 ch->ext_info = dfsdm_adc_audio_ext_info;
1389 } else {
1390 ch->scan_type.shift = 8;
1391 }
1392 ch->scan_type.sign = 's';
1393 ch->scan_type.realbits = 24;
1394 ch->scan_type.storagebits = 32;
1395
1396 return stm32_dfsdm_chan_configure(adc->dfsdm,
1397 &adc->dfsdm->ch_list[ch->channel]);
1398}
1399
1400static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1401{
1402 struct iio_chan_spec *ch;
1403 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1404 struct stm32_dfsdm_channel *d_ch;
1405 int ret;
1406
1407 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1408 if (!ch)
1409 return -ENOMEM;
1410
1411 ch->scan_index = 0;
1412
1413 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1414 if (ret < 0) {
1415 dev_err(&indio_dev->dev, "Channels init failed\n");
1416 return ret;
1417 }
1418 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1419
1420 d_ch = &adc->dfsdm->ch_list[ch->channel];
1421 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1422 adc->spi_freq = adc->dfsdm->spi_master_freq;
1423
1424 indio_dev->num_channels = 1;
1425 indio_dev->channels = ch;
1426
1427 return stm32_dfsdm_dma_request(dev, indio_dev);
1428}
1429
1430static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1431{
1432 struct iio_chan_spec *ch;
1433 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1434 int num_ch;
1435 int ret, chan_idx;
1436
1437 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1438 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1439 if (ret < 0)
1440 return ret;
1441
1442 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1443 "st,adc-channels");
1444 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1445 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1446 return num_ch < 0 ? num_ch : -EINVAL;
1447 }
1448
1449 /* Bind to SD modulator IIO device */
1450 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1451 if (IS_ERR(adc->hwc))
1452 return -EPROBE_DEFER;
1453
1454 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1455 GFP_KERNEL);
1456 if (!ch)
1457 return -ENOMEM;
1458
1459 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1460 ch[chan_idx].scan_index = chan_idx;
1461 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1462 if (ret < 0) {
1463 dev_err(&indio_dev->dev, "Channels init failed\n");
1464 return ret;
1465 }
1466 }
1467
1468 indio_dev->num_channels = num_ch;
1469 indio_dev->channels = ch;
1470
1471 init_completion(&adc->completion);
1472
1473 /* Optionally request DMA */
1474 ret = stm32_dfsdm_dma_request(dev, indio_dev);
1475 if (ret) {
1476 if (ret != -ENODEV) {
1477 if (ret != -EPROBE_DEFER)
1478 dev_err(dev,
1479 "DMA channel request failed with %d\n",
1480 ret);
1481 return ret;
1482 }
1483
1484 dev_dbg(dev, "No DMA support\n");
1485 return 0;
1486 }
1487
1488 ret = iio_triggered_buffer_setup(indio_dev,
1489 &iio_pollfunc_store_time, NULL,
1490 &stm32_dfsdm_buffer_setup_ops);
1491 if (ret) {
1492 stm32_dfsdm_dma_release(indio_dev);
1493 dev_err(&indio_dev->dev, "buffer setup failed\n");
1494 return ret;
1495 }
1496
1497 /* lptimer/timer hardware triggers */
1498 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1499
1500 return 0;
1501}
1502
1503static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1504 .type = DFSDM_IIO,
1505 .init = stm32_dfsdm_adc_init,
1506};
1507
1508static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1509 .type = DFSDM_AUDIO,
1510 .init = stm32_dfsdm_audio_init,
1511};
1512
1513static const struct of_device_id stm32_dfsdm_adc_match[] = {
1514 {
1515 .compatible = "st,stm32-dfsdm-adc",
1516 .data = &stm32h7_dfsdm_adc_data,
1517 },
1518 {
1519 .compatible = "st,stm32-dfsdm-dmic",
1520 .data = &stm32h7_dfsdm_audio_data,
1521 },
1522 {}
1523};
1524
1525static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1526{
1527 struct device *dev = &pdev->dev;
1528 struct stm32_dfsdm_adc *adc;
1529 struct device_node *np = dev->of_node;
1530 const struct stm32_dfsdm_dev_data *dev_data;
1531 struct iio_dev *iio;
1532 char *name;
1533 int ret, irq, val;
1534
1535 dev_data = of_device_get_match_data(dev);
1536 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1537 if (!iio) {
1538 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1539 return -ENOMEM;
1540 }
1541
1542 adc = iio_priv(iio);
1543 adc->dfsdm = dev_get_drvdata(dev->parent);
1544
1545 iio->dev.of_node = np;
1546 iio->modes = INDIO_DIRECT_MODE;
1547
1548 platform_set_drvdata(pdev, iio);
1549
1550 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1551 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1552 dev_err(dev, "Missing or bad reg property\n");
1553 return -EINVAL;
1554 }
1555
1556 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1557 if (!name)
1558 return -ENOMEM;
1559 if (dev_data->type == DFSDM_AUDIO) {
1560 iio->info = &stm32_dfsdm_info_audio;
1561 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1562 } else {
1563 iio->info = &stm32_dfsdm_info_adc;
1564 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1565 }
1566 iio->name = name;
1567
1568 /*
1569 * In a first step IRQs generated for channels are not treated.
1570 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1571 */
1572 irq = platform_get_irq(pdev, 0);
1573 if (irq < 0)
1574 return irq;
1575
1576 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1577 0, pdev->name, iio);
1578 if (ret < 0) {
1579 dev_err(dev, "Failed to request IRQ\n");
1580 return ret;
1581 }
1582
1583 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1584 if (ret < 0) {
1585 dev_err(dev, "Failed to set filter order\n");
1586 return ret;
1587 }
1588
1589 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1590
1591 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1592 if (!ret)
1593 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1594
1595 adc->dev_data = dev_data;
1596 ret = dev_data->init(dev, iio);
1597 if (ret < 0)
1598 return ret;
1599
1600 ret = iio_device_register(iio);
1601 if (ret < 0)
1602 goto err_cleanup;
1603
1604 if (dev_data->type == DFSDM_AUDIO) {
1605 ret = of_platform_populate(np, NULL, NULL, dev);
1606 if (ret < 0) {
1607 dev_err(dev, "Failed to find an audio DAI\n");
1608 goto err_unregister;
1609 }
1610 }
1611
1612 return 0;
1613
1614err_unregister:
1615 iio_device_unregister(iio);
1616err_cleanup:
1617 stm32_dfsdm_dma_release(iio);
1618
1619 return ret;
1620}
1621
1622static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1623{
1624 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1625 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1626
1627 if (adc->dev_data->type == DFSDM_AUDIO)
1628 of_platform_depopulate(&pdev->dev);
1629 iio_device_unregister(indio_dev);
1630 stm32_dfsdm_dma_release(indio_dev);
1631
1632 return 0;
1633}
1634
1635static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1636{
1637 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1638
1639 if (iio_buffer_enabled(indio_dev))
1640 stm32_dfsdm_predisable(indio_dev);
1641
1642 return 0;
1643}
1644
1645static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1646{
1647 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1648 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1649 const struct iio_chan_spec *chan;
1650 struct stm32_dfsdm_channel *ch;
1651 int i, ret;
1652
1653 /* restore channels configuration */
1654 for (i = 0; i < indio_dev->num_channels; i++) {
1655 chan = indio_dev->channels + i;
1656 ch = &adc->dfsdm->ch_list[chan->channel];
1657 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1658 if (ret)
1659 return ret;
1660 }
1661
1662 if (iio_buffer_enabled(indio_dev))
1663 stm32_dfsdm_postenable(indio_dev);
1664
1665 return 0;
1666}
1667
1668static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1669 stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1670
1671static struct platform_driver stm32_dfsdm_adc_driver = {
1672 .driver = {
1673 .name = "stm32-dfsdm-adc",
1674 .of_match_table = stm32_dfsdm_adc_match,
1675 .pm = &stm32_dfsdm_adc_pm_ops,
1676 },
1677 .probe = stm32_dfsdm_adc_probe,
1678 .remove = stm32_dfsdm_adc_remove,
1679};
1680module_platform_driver(stm32_dfsdm_adc_driver);
1681
1682MODULE_DESCRIPTION("STM32 sigma delta ADC");
1683MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1684MODULE_LICENSE("GPL v2");