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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12#ifndef _ASM_IO_H
13#define _ASM_IO_H
14
15#include <linux/compiler.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18
19#include <asm/addrspace.h>
20#include <asm/byteorder.h>
21#include <asm/cpu.h>
22#include <asm/cpu-features.h>
23#include <asm-generic/iomap.h>
24#include <asm/page.h>
25#include <asm/pgtable-bits.h>
26#include <asm/processor.h>
27#include <asm/string.h>
28
29#include <ioremap.h>
30#include <mangle-port.h>
31
32/*
33 * Slowdown I/O port space accesses for antique hardware.
34 */
35#undef CONF_SLOWDOWN_IO
36
37/*
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
41 * execute in place.
42 */
43# define __raw_ioswabb(a, x) (x)
44# define __raw_ioswabw(a, x) (x)
45# define __raw_ioswabl(a, x) (x)
46# define __raw_ioswabq(a, x) (x)
47# define ____raw_ioswabq(a, x) (x)
48
49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50
51#define IO_SPACE_LIMIT 0xffff
52
53/*
54 * On MIPS I/O ports are memory mapped, so we access them using normal
55 * load/store instructions. mips_io_port_base is the virtual address to
56 * which all ports are being mapped. For sake of efficiency some code
57 * assumes that this is an address that can be loaded with a single lui
58 * instruction, so the lower 16 bits must be zero. Should be true on
59 * on any sane architecture; generic code does not use this assumption.
60 */
61extern const unsigned long mips_io_port_base;
62
63/*
64 * Gcc will generate code to load the value of mips_io_port_base after each
65 * function call which may be fairly wasteful in some cases. So we don't
66 * play quite by the book. We tell gcc mips_io_port_base is a long variable
67 * which solves the code generation issue. Now we need to violate the
68 * aliasing rules a little to make initialization possible and finally we
69 * will need the barrier() to fight side effects of the aliasing chat.
70 * This trickery will eventually collapse under gcc's optimizer. Oh well.
71 */
72static inline void set_io_port_base(unsigned long base)
73{
74 * (unsigned long *) &mips_io_port_base = base;
75 barrier();
76}
77
78/*
79 * Thanks to James van Artsdalen for a better timing-fix than
80 * the two short jumps: using outb's to a nonexistent port seems
81 * to guarantee better timings even on fast machines.
82 *
83 * On the other hand, I'd like to be sure of a non-existent port:
84 * I feel a bit unsafe about using 0x80 (should be safe, though)
85 *
86 * Linus
87 *
88 */
89
90#define __SLOW_DOWN_IO \
91 __asm__ __volatile__( \
92 "sb\t$0,0x80(%0)" \
93 : : "r" (mips_io_port_base));
94
95#ifdef CONF_SLOWDOWN_IO
96#ifdef REALLY_SLOW_IO
97#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
98#else
99#define SLOW_DOWN_IO __SLOW_DOWN_IO
100#endif
101#else
102#define SLOW_DOWN_IO
103#endif
104
105/*
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
108 *
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
112 *
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
115 * this function
116 */
117static inline unsigned long virt_to_phys(volatile const void *address)
118{
119 return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
120}
121
122/*
123 * phys_to_virt - map physical address to virtual
124 * @address: address to remap
125 *
126 * The returned virtual address is a current CPU mapping for
127 * the memory address given. It is only valid to use this function on
128 * addresses that have a kernel mapping
129 *
130 * This function does not handle bus mappings for DMA transfers. In
131 * almost all conceivable cases a device driver should not be using
132 * this function
133 */
134static inline void * phys_to_virt(unsigned long address)
135{
136 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
137}
138
139/*
140 * ISA I/O bus memory addresses are 1:1 with the physical address.
141 */
142static inline unsigned long isa_virt_to_bus(volatile void * address)
143{
144 return (unsigned long)address - PAGE_OFFSET;
145}
146
147static inline void * isa_bus_to_virt(unsigned long address)
148{
149 return (void *)(address + PAGE_OFFSET);
150}
151
152#define isa_page_to_bus page_to_phys
153
154/*
155 * However PCI ones are not necessarily 1:1 and therefore these interfaces
156 * are forbidden in portable PCI drivers.
157 *
158 * Allow them for x86 for legacy drivers, though.
159 */
160#define virt_to_bus virt_to_phys
161#define bus_to_virt phys_to_virt
162
163/*
164 * Change "struct page" to physical address.
165 */
166#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
167
168extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
169extern void __iounmap(const volatile void __iomem *addr);
170
171static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
172 unsigned long flags)
173{
174 void __iomem *addr = plat_ioremap(offset, size, flags);
175
176 if (addr)
177 return addr;
178
179#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
180
181 if (cpu_has_64bit_addresses) {
182 u64 base = UNCAC_BASE;
183
184 /*
185 * R10000 supports a 2 bit uncached attribute therefore
186 * UNCAC_BASE may not equal IO_BASE.
187 */
188 if (flags == _CACHE_UNCACHED)
189 base = (u64) IO_BASE;
190 return (void __iomem *) (unsigned long) (base + offset);
191 } else if (__builtin_constant_p(offset) &&
192 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
193 phys_t phys_addr, last_addr;
194
195 phys_addr = fixup_bigphys_addr(offset, size);
196
197 /* Don't allow wraparound or zero size. */
198 last_addr = phys_addr + size - 1;
199 if (!size || last_addr < phys_addr)
200 return NULL;
201
202 /*
203 * Map uncached objects in the low 512MB of address
204 * space using KSEG1.
205 */
206 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
207 flags == _CACHE_UNCACHED)
208 return (void __iomem *)
209 (unsigned long)CKSEG1ADDR(phys_addr);
210 }
211
212 return __ioremap(offset, size, flags);
213
214#undef __IS_LOW512
215}
216
217/*
218 * ioremap - map bus memory into CPU space
219 * @offset: bus address of the memory
220 * @size: size of the resource to map
221 *
222 * ioremap performs a platform specific sequence of operations to
223 * make bus memory CPU accessible via the readb/readw/readl/writeb/
224 * writew/writel functions and the other mmio helpers. The returned
225 * address is not guaranteed to be usable directly as a virtual
226 * address.
227 */
228#define ioremap(offset, size) \
229 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
230
231/*
232 * ioremap_nocache - map bus memory into CPU space
233 * @offset: bus address of the memory
234 * @size: size of the resource to map
235 *
236 * ioremap_nocache performs a platform specific sequence of operations to
237 * make bus memory CPU accessible via the readb/readw/readl/writeb/
238 * writew/writel functions and the other mmio helpers. The returned
239 * address is not guaranteed to be usable directly as a virtual
240 * address.
241 *
242 * This version of ioremap ensures that the memory is marked uncachable
243 * on the CPU as well as honouring existing caching rules from things like
244 * the PCI bus. Note that there are other caches and buffers on many
245 * busses. In particular driver authors should read up on PCI writes
246 *
247 * It's useful if some control registers are in such an area and
248 * write combining or read caching is not desirable:
249 */
250#define ioremap_nocache(offset, size) \
251 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
252
253/*
254 * ioremap_cachable - map bus memory into CPU space
255 * @offset: bus address of the memory
256 * @size: size of the resource to map
257 *
258 * ioremap_nocache performs a platform specific sequence of operations to
259 * make bus memory CPU accessible via the readb/readw/readl/writeb/
260 * writew/writel functions and the other mmio helpers. The returned
261 * address is not guaranteed to be usable directly as a virtual
262 * address.
263 *
264 * This version of ioremap ensures that the memory is marked cachable by
265 * the CPU. Also enables full write-combining. Useful for some
266 * memory-like regions on I/O busses.
267 */
268#define ioremap_cachable(offset, size) \
269 __ioremap_mode((offset), (size), _page_cachable_default)
270
271/*
272 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
273 * requests a cachable mapping, ioremap_uncached_accelerated requests a
274 * mapping using the uncached accelerated mode which isn't supported on
275 * all processors.
276 */
277#define ioremap_cacheable_cow(offset, size) \
278 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
279#define ioremap_uncached_accelerated(offset, size) \
280 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
281
282static inline void iounmap(const volatile void __iomem *addr)
283{
284 if (plat_iounmap(addr))
285 return;
286
287#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
288
289 if (cpu_has_64bit_addresses ||
290 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
291 return;
292
293 __iounmap(addr);
294
295#undef __IS_KSEG1
296}
297
298#ifdef CONFIG_CPU_CAVIUM_OCTEON
299#define war_octeon_io_reorder_wmb() wmb()
300#else
301#define war_octeon_io_reorder_wmb() do { } while (0)
302#endif
303
304#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
305 \
306static inline void pfx##write##bwlq(type val, \
307 volatile void __iomem *mem) \
308{ \
309 volatile type *__mem; \
310 type __val; \
311 \
312 war_octeon_io_reorder_wmb(); \
313 \
314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
315 \
316 __val = pfx##ioswab##bwlq(__mem, val); \
317 \
318 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
319 *__mem = __val; \
320 else if (cpu_has_64bits) { \
321 unsigned long __flags; \
322 type __tmp; \
323 \
324 if (irq) \
325 local_irq_save(__flags); \
326 __asm__ __volatile__( \
327 ".set mips3" "\t\t# __writeq""\n\t" \
328 "dsll32 %L0, %L0, 0" "\n\t" \
329 "dsrl32 %L0, %L0, 0" "\n\t" \
330 "dsll32 %M0, %M0, 0" "\n\t" \
331 "or %L0, %L0, %M0" "\n\t" \
332 ".set push" "\n\t" \
333 ".set noreorder" "\n\t" \
334 ".set nomacro" "\n\t" \
335 "sd %L0, %2" "\n\t" \
336 ".set pop" "\n\t" \
337 ".set mips0" "\n" \
338 : "=r" (__tmp) \
339 : "0" (__val), "R" (*__mem)); \
340 if (irq) \
341 local_irq_restore(__flags); \
342 } else \
343 BUG(); \
344} \
345 \
346static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
347{ \
348 volatile type *__mem; \
349 type __val; \
350 \
351 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
352 \
353 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
354 __val = *__mem; \
355 else if (cpu_has_64bits) { \
356 unsigned long __flags; \
357 \
358 if (irq) \
359 local_irq_save(__flags); \
360 __asm__ __volatile__( \
361 ".set mips3" "\t\t# __readq" "\n\t" \
362 ".set push" "\n\t" \
363 ".set noreorder" "\n\t" \
364 ".set nomacro" "\n\t" \
365 "ld %L0, %1" "\n\t" \
366 ".set pop" "\n\t" \
367 "dsra32 %M0, %L0, 0" "\n\t" \
368 "sll %L0, %L0, 0" "\n\t" \
369 ".set mips0" "\n" \
370 : "=r" (__val) \
371 : "R" (*__mem)); \
372 if (irq) \
373 local_irq_restore(__flags); \
374 } else { \
375 __val = 0; \
376 BUG(); \
377 } \
378 \
379 return pfx##ioswab##bwlq(__mem, __val); \
380}
381
382#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
383 \
384static inline void pfx##out##bwlq##p(type val, unsigned long port) \
385{ \
386 volatile type *__addr; \
387 type __val; \
388 \
389 war_octeon_io_reorder_wmb(); \
390 \
391 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
392 \
393 __val = pfx##ioswab##bwlq(__addr, val); \
394 \
395 /* Really, we want this to be atomic */ \
396 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
397 \
398 *__addr = __val; \
399 slow; \
400} \
401 \
402static inline type pfx##in##bwlq##p(unsigned long port) \
403{ \
404 volatile type *__addr; \
405 type __val; \
406 \
407 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
408 \
409 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
410 \
411 __val = *__addr; \
412 slow; \
413 \
414 return pfx##ioswab##bwlq(__addr, __val); \
415}
416
417#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
418 \
419__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
420
421#define BUILDIO_MEM(bwlq, type) \
422 \
423__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
424__BUILD_MEMORY_PFX(, bwlq, type) \
425__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
426
427BUILDIO_MEM(b, u8)
428BUILDIO_MEM(w, u16)
429BUILDIO_MEM(l, u32)
430BUILDIO_MEM(q, u64)
431
432#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
433 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
434 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
435
436#define BUILDIO_IOPORT(bwlq, type) \
437 __BUILD_IOPORT_PFX(, bwlq, type) \
438 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
439
440BUILDIO_IOPORT(b, u8)
441BUILDIO_IOPORT(w, u16)
442BUILDIO_IOPORT(l, u32)
443#ifdef CONFIG_64BIT
444BUILDIO_IOPORT(q, u64)
445#endif
446
447#define __BUILDIO(bwlq, type) \
448 \
449__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
450
451__BUILDIO(q, u64)
452
453#define readb_relaxed readb
454#define readw_relaxed readw
455#define readl_relaxed readl
456#define readq_relaxed readq
457
458#define readb_be(addr) \
459 __raw_readb((__force unsigned *)(addr))
460#define readw_be(addr) \
461 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
462#define readl_be(addr) \
463 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
464#define readq_be(addr) \
465 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
466
467#define writeb_be(val, addr) \
468 __raw_writeb((val), (__force unsigned *)(addr))
469#define writew_be(val, addr) \
470 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
471#define writel_be(val, addr) \
472 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
473#define writeq_be(val, addr) \
474 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
475
476/*
477 * Some code tests for these symbols
478 */
479#define readq readq
480#define writeq writeq
481
482#define __BUILD_MEMORY_STRING(bwlq, type) \
483 \
484static inline void writes##bwlq(volatile void __iomem *mem, \
485 const void *addr, unsigned int count) \
486{ \
487 const volatile type *__addr = addr; \
488 \
489 while (count--) { \
490 __mem_write##bwlq(*__addr, mem); \
491 __addr++; \
492 } \
493} \
494 \
495static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
496 unsigned int count) \
497{ \
498 volatile type *__addr = addr; \
499 \
500 while (count--) { \
501 *__addr = __mem_read##bwlq(mem); \
502 __addr++; \
503 } \
504}
505
506#define __BUILD_IOPORT_STRING(bwlq, type) \
507 \
508static inline void outs##bwlq(unsigned long port, const void *addr, \
509 unsigned int count) \
510{ \
511 const volatile type *__addr = addr; \
512 \
513 while (count--) { \
514 __mem_out##bwlq(*__addr, port); \
515 __addr++; \
516 } \
517} \
518 \
519static inline void ins##bwlq(unsigned long port, void *addr, \
520 unsigned int count) \
521{ \
522 volatile type *__addr = addr; \
523 \
524 while (count--) { \
525 *__addr = __mem_in##bwlq(port); \
526 __addr++; \
527 } \
528}
529
530#define BUILDSTRING(bwlq, type) \
531 \
532__BUILD_MEMORY_STRING(bwlq, type) \
533__BUILD_IOPORT_STRING(bwlq, type)
534
535BUILDSTRING(b, u8)
536BUILDSTRING(w, u16)
537BUILDSTRING(l, u32)
538#ifdef CONFIG_64BIT
539BUILDSTRING(q, u64)
540#endif
541
542
543#ifdef CONFIG_CPU_CAVIUM_OCTEON
544#define mmiowb() wmb()
545#else
546/* Depends on MIPS II instruction set */
547#define mmiowb() asm volatile ("sync" ::: "memory")
548#endif
549
550static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
551{
552 memset((void __force *) addr, val, count);
553}
554static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
555{
556 memcpy(dst, (void __force *) src, count);
557}
558static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
559{
560 memcpy((void __force *) dst, src, count);
561}
562
563/*
564 * The caches on some architectures aren't dma-coherent and have need to
565 * handle this in software. There are three types of operations that
566 * can be applied to dma buffers.
567 *
568 * - dma_cache_wback_inv(start, size) makes caches and coherent by
569 * writing the content of the caches back to memory, if necessary.
570 * The function also invalidates the affected part of the caches as
571 * necessary before DMA transfers from outside to memory.
572 * - dma_cache_wback(start, size) makes caches and coherent by
573 * writing the content of the caches back to memory, if necessary.
574 * The function also invalidates the affected part of the caches as
575 * necessary before DMA transfers from outside to memory.
576 * - dma_cache_inv(start, size) invalidates the affected parts of the
577 * caches. Dirty lines of the caches may be written back or simply
578 * be discarded. This operation is necessary before dma operations
579 * to the memory.
580 *
581 * This API used to be exported; it now is for arch code internal use only.
582 */
583#ifdef CONFIG_DMA_NONCOHERENT
584
585extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
586extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
587extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
588
589#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
590#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
591#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
592
593#else /* Sane hardware */
594
595#define dma_cache_wback_inv(start,size) \
596 do { (void) (start); (void) (size); } while (0)
597#define dma_cache_wback(start,size) \
598 do { (void) (start); (void) (size); } while (0)
599#define dma_cache_inv(start,size) \
600 do { (void) (start); (void) (size); } while (0)
601
602#endif /* CONFIG_DMA_NONCOHERENT */
603
604/*
605 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
606 * Avoid interrupt mucking, just adjust the address for 4-byte access.
607 * Assume the addresses are 8-byte aligned.
608 */
609#ifdef __MIPSEB__
610#define __CSR_32_ADJUST 4
611#else
612#define __CSR_32_ADJUST 0
613#endif
614
615#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
616#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
617
618/*
619 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
620 * access
621 */
622#define xlate_dev_mem_ptr(p) __va(p)
623
624/*
625 * Convert a virtual cached pointer to an uncached pointer
626 */
627#define xlate_dev_kmem_ptr(p) p
628
629#endif /* _ASM_IO_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12#ifndef _ASM_IO_H
13#define _ASM_IO_H
14
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/irqflags.h>
18
19#include <asm/addrspace.h>
20#include <asm/barrier.h>
21#include <asm/bug.h>
22#include <asm/byteorder.h>
23#include <asm/cpu.h>
24#include <asm/cpu-features.h>
25#include <asm/page.h>
26#include <asm/pgtable-bits.h>
27#include <asm/string.h>
28#include <mangle-port.h>
29
30/*
31 * Raw operations are never swapped in software. OTOH values that raw
32 * operations are working on may or may not have been swapped by the bus
33 * hardware. An example use would be for flash memory that's used for
34 * execute in place.
35 */
36# define __raw_ioswabb(a, x) (x)
37# define __raw_ioswabw(a, x) (x)
38# define __raw_ioswabl(a, x) (x)
39# define __raw_ioswabq(a, x) (x)
40# define ____raw_ioswabq(a, x) (x)
41
42# define _ioswabb ioswabb
43# define _ioswabw ioswabw
44# define _ioswabl ioswabl
45# define _ioswabq ioswabq
46
47# define __relaxed_ioswabb ioswabb
48# define __relaxed_ioswabw ioswabw
49# define __relaxed_ioswabl ioswabl
50# define __relaxed_ioswabq ioswabq
51
52/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
53
54/*
55 * On MIPS I/O ports are memory mapped, so we access them using normal
56 * load/store instructions. mips_io_port_base is the virtual address to
57 * which all ports are being mapped. For sake of efficiency some code
58 * assumes that this is an address that can be loaded with a single lui
59 * instruction, so the lower 16 bits must be zero. Should be true on
60 * any sane architecture; generic code does not use this assumption.
61 */
62extern unsigned long mips_io_port_base;
63
64static inline void set_io_port_base(unsigned long base)
65{
66 mips_io_port_base = base;
67}
68
69/*
70 * Provide the necessary definitions for generic iomap. We make use of
71 * mips_io_port_base for iomap(), but we don't reserve any low addresses for
72 * use with I/O ports.
73 */
74
75#define HAVE_ARCH_PIO_SIZE
76#define PIO_OFFSET mips_io_port_base
77#define PIO_MASK IO_SPACE_LIMIT
78#define PIO_RESERVED 0x0UL
79
80/*
81 * Enforce in-order execution of data I/O. In the MIPS architecture
82 * these are equivalent to corresponding platform-specific memory
83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
84 * with sync additionally defined.
85 */
86#define iobarrier_rw() mb()
87#define iobarrier_r() rmb()
88#define iobarrier_w() wmb()
89#define iobarrier_sync() iob()
90
91/*
92 * virt_to_phys - map virtual addresses to physical
93 * @address: address to remap
94 *
95 * The returned physical address is the physical (CPU) mapping for
96 * the memory address given. It is only valid to use this function on
97 * addresses directly mapped or allocated via kmalloc.
98 *
99 * This function does not give bus mappings for DMA transfers. In
100 * almost all conceivable cases a device driver should not be using
101 * this function
102 */
103static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
104{
105 return __pa(address);
106}
107
108#ifdef CONFIG_DEBUG_VIRTUAL
109extern phys_addr_t __virt_to_phys(volatile const void *x);
110#else
111#define __virt_to_phys(x) __virt_to_phys_nodebug(x)
112#endif
113
114#define virt_to_phys virt_to_phys
115static inline phys_addr_t virt_to_phys(const volatile void *x)
116{
117 return __virt_to_phys(x);
118}
119
120/*
121 * ISA I/O bus memory addresses are 1:1 with the physical address.
122 */
123static inline unsigned long isa_virt_to_bus(volatile void *address)
124{
125 return virt_to_phys(address);
126}
127
128void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
129 unsigned long prot_val);
130void iounmap(const volatile void __iomem *addr);
131
132/*
133 * ioremap - map bus memory into CPU space
134 * @offset: bus address of the memory
135 * @size: size of the resource to map
136 *
137 * ioremap performs a platform specific sequence of operations to
138 * make bus memory CPU accessible via the readb/readw/readl/writeb/
139 * writew/writel functions and the other mmio helpers. The returned
140 * address is not guaranteed to be usable directly as a virtual
141 * address.
142 */
143#define ioremap(offset, size) \
144 ioremap_prot((offset), (size), _CACHE_UNCACHED)
145
146/*
147 * ioremap_cache - map bus memory into CPU space
148 * @offset: bus address of the memory
149 * @size: size of the resource to map
150 *
151 * ioremap_cache performs a platform specific sequence of operations to
152 * make bus memory CPU accessible via the readb/readw/readl/writeb/
153 * writew/writel functions and the other mmio helpers. The returned
154 * address is not guaranteed to be usable directly as a virtual
155 * address.
156 *
157 * This version of ioremap ensures that the memory is marked cacheable by
158 * the CPU. Also enables full write-combining. Useful for some
159 * memory-like regions on I/O busses.
160 */
161#define ioremap_cache(offset, size) \
162 ioremap_prot((offset), (size), _page_cachable_default)
163
164/*
165 * ioremap_wc - map bus memory into CPU space
166 * @offset: bus address of the memory
167 * @size: size of the resource to map
168 *
169 * ioremap_wc performs a platform specific sequence of operations to
170 * make bus memory CPU accessible via the readb/readw/readl/writeb/
171 * writew/writel functions and the other mmio helpers. The returned
172 * address is not guaranteed to be usable directly as a virtual
173 * address.
174 *
175 * This version of ioremap ensures that the memory is marked uncacheable
176 * but accelerated by means of write-combining feature. It is specifically
177 * useful for PCIe prefetchable windows, which may vastly improve a
178 * communications performance. If it was determined on boot stage, what
179 * CPU CCA doesn't support UCA, the method shall fall-back to the
180 * _CACHE_UNCACHED option (see cpu_probe() method).
181 */
182#define ioremap_wc(offset, size) \
183 ioremap_prot((offset), (size), boot_cpu_data.writecombine)
184
185#if defined(CONFIG_CPU_CAVIUM_OCTEON)
186#define war_io_reorder_wmb() wmb()
187#else
188#define war_io_reorder_wmb() barrier()
189#endif
190
191#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
192 \
193static inline void pfx##write##bwlq(type val, \
194 volatile void __iomem *mem) \
195{ \
196 volatile type *__mem; \
197 type __val; \
198 \
199 if (barrier) \
200 iobarrier_rw(); \
201 else \
202 war_io_reorder_wmb(); \
203 \
204 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
205 \
206 __val = pfx##ioswab##bwlq(__mem, val); \
207 \
208 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
209 *__mem = __val; \
210 else if (cpu_has_64bits) { \
211 unsigned long __flags; \
212 type __tmp; \
213 \
214 if (irq) \
215 local_irq_save(__flags); \
216 __asm__ __volatile__( \
217 ".set push" "\t\t# __writeq""\n\t" \
218 ".set arch=r4000" "\n\t" \
219 "dsll32 %L0, %L0, 0" "\n\t" \
220 "dsrl32 %L0, %L0, 0" "\n\t" \
221 "dsll32 %M0, %M0, 0" "\n\t" \
222 "or %L0, %L0, %M0" "\n\t" \
223 "sd %L0, %2" "\n\t" \
224 ".set pop" "\n" \
225 : "=r" (__tmp) \
226 : "0" (__val), "m" (*__mem)); \
227 if (irq) \
228 local_irq_restore(__flags); \
229 } else \
230 BUG(); \
231} \
232 \
233static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
234{ \
235 volatile type *__mem; \
236 type __val; \
237 \
238 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
239 \
240 if (barrier) \
241 iobarrier_rw(); \
242 \
243 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
244 __val = *__mem; \
245 else if (cpu_has_64bits) { \
246 unsigned long __flags; \
247 \
248 if (irq) \
249 local_irq_save(__flags); \
250 __asm__ __volatile__( \
251 ".set push" "\t\t# __readq" "\n\t" \
252 ".set arch=r4000" "\n\t" \
253 "ld %L0, %1" "\n\t" \
254 "dsra32 %M0, %L0, 0" "\n\t" \
255 "sll %L0, %L0, 0" "\n\t" \
256 ".set pop" "\n" \
257 : "=r" (__val) \
258 : "m" (*__mem)); \
259 if (irq) \
260 local_irq_restore(__flags); \
261 } else { \
262 __val = 0; \
263 BUG(); \
264 } \
265 \
266 /* prevent prefetching of coherent DMA data prematurely */ \
267 if (!relax) \
268 rmb(); \
269 return pfx##ioswab##bwlq(__mem, __val); \
270}
271
272#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax) \
273 \
274static inline void pfx##out##bwlq(type val, unsigned long port) \
275{ \
276 volatile type *__addr; \
277 type __val; \
278 \
279 if (barrier) \
280 iobarrier_rw(); \
281 else \
282 war_io_reorder_wmb(); \
283 \
284 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
285 \
286 __val = pfx##ioswab##bwlq(__addr, val); \
287 \
288 /* Really, we want this to be atomic */ \
289 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
290 \
291 *__addr = __val; \
292} \
293 \
294static inline type pfx##in##bwlq(unsigned long port) \
295{ \
296 volatile type *__addr; \
297 type __val; \
298 \
299 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
300 \
301 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
302 \
303 if (barrier) \
304 iobarrier_rw(); \
305 \
306 __val = *__addr; \
307 \
308 /* prevent prefetching of coherent DMA data prematurely */ \
309 if (!relax) \
310 rmb(); \
311 return pfx##ioswab##bwlq(__addr, __val); \
312}
313
314#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
315 \
316__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
317
318#define BUILDIO_MEM(bwlq, type) \
319 \
320__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
321__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
322__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
323__BUILD_MEMORY_PFX(, bwlq, type, 0)
324
325BUILDIO_MEM(b, u8)
326BUILDIO_MEM(w, u16)
327BUILDIO_MEM(l, u32)
328#ifdef CONFIG_64BIT
329BUILDIO_MEM(q, u64)
330#else
331__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
332__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
333#endif
334
335#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
336 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0)
337
338#define BUILDIO_IOPORT(bwlq, type) \
339 __BUILD_IOPORT_PFX(_, bwlq, type) \
340 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
341
342BUILDIO_IOPORT(b, u8)
343BUILDIO_IOPORT(w, u16)
344BUILDIO_IOPORT(l, u32)
345#ifdef CONFIG_64BIT
346BUILDIO_IOPORT(q, u64)
347#endif
348
349#define __BUILDIO(bwlq, type) \
350 \
351__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
352
353__BUILDIO(q, u64)
354
355#define readb_relaxed __relaxed_readb
356#define readw_relaxed __relaxed_readw
357#define readl_relaxed __relaxed_readl
358#ifdef CONFIG_64BIT
359#define readq_relaxed __relaxed_readq
360#endif
361
362#define writeb_relaxed __relaxed_writeb
363#define writew_relaxed __relaxed_writew
364#define writel_relaxed __relaxed_writel
365#ifdef CONFIG_64BIT
366#define writeq_relaxed __relaxed_writeq
367#endif
368
369#define readb_be(addr) \
370 __raw_readb((__force unsigned *)(addr))
371#define readw_be(addr) \
372 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
373#define readl_be(addr) \
374 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
375#define readq_be(addr) \
376 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
377
378#define writeb_be(val, addr) \
379 __raw_writeb((val), (__force unsigned *)(addr))
380#define writew_be(val, addr) \
381 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
382#define writel_be(val, addr) \
383 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
384#define writeq_be(val, addr) \
385 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
386
387#define __BUILD_MEMORY_STRING(bwlq, type) \
388 \
389static inline void writes##bwlq(volatile void __iomem *mem, \
390 const void *addr, unsigned int count) \
391{ \
392 const volatile type *__addr = addr; \
393 \
394 while (count--) { \
395 __mem_write##bwlq(*__addr, mem); \
396 __addr++; \
397 } \
398} \
399 \
400static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
401 unsigned int count) \
402{ \
403 volatile type *__addr = addr; \
404 \
405 while (count--) { \
406 *__addr = __mem_read##bwlq(mem); \
407 __addr++; \
408 } \
409}
410
411#define __BUILD_IOPORT_STRING(bwlq, type) \
412 \
413static inline void outs##bwlq(unsigned long port, const void *addr, \
414 unsigned int count) \
415{ \
416 const volatile type *__addr = addr; \
417 \
418 while (count--) { \
419 __mem_out##bwlq(*__addr, port); \
420 __addr++; \
421 } \
422} \
423 \
424static inline void ins##bwlq(unsigned long port, void *addr, \
425 unsigned int count) \
426{ \
427 volatile type *__addr = addr; \
428 \
429 while (count--) { \
430 *__addr = __mem_in##bwlq(port); \
431 __addr++; \
432 } \
433}
434
435#define BUILDSTRING(bwlq, type) \
436 \
437__BUILD_MEMORY_STRING(bwlq, type) \
438__BUILD_IOPORT_STRING(bwlq, type)
439
440BUILDSTRING(b, u8)
441BUILDSTRING(w, u16)
442BUILDSTRING(l, u32)
443#ifdef CONFIG_64BIT
444BUILDSTRING(q, u64)
445#endif
446
447
448/*
449 * The caches on some architectures aren't dma-coherent and have need to
450 * handle this in software. There are three types of operations that
451 * can be applied to dma buffers.
452 *
453 * - dma_cache_wback_inv(start, size) makes caches and coherent by
454 * writing the content of the caches back to memory, if necessary.
455 * The function also invalidates the affected part of the caches as
456 * necessary before DMA transfers from outside to memory.
457 * - dma_cache_wback(start, size) makes caches and coherent by
458 * writing the content of the caches back to memory, if necessary.
459 * The function also invalidates the affected part of the caches as
460 * necessary before DMA transfers from outside to memory.
461 * - dma_cache_inv(start, size) invalidates the affected parts of the
462 * caches. Dirty lines of the caches may be written back or simply
463 * be discarded. This operation is necessary before dma operations
464 * to the memory.
465 *
466 * This API used to be exported; it now is for arch code internal use only.
467 */
468#ifdef CONFIG_DMA_NONCOHERENT
469
470extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
471extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
472extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
473
474#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
475#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
476#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
477
478#else /* Sane hardware */
479
480#define dma_cache_wback_inv(start,size) \
481 do { (void) (start); (void) (size); } while (0)
482#define dma_cache_wback(start,size) \
483 do { (void) (start); (void) (size); } while (0)
484#define dma_cache_inv(start,size) \
485 do { (void) (start); (void) (size); } while (0)
486
487#endif /* CONFIG_DMA_NONCOHERENT */
488
489/*
490 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
491 * Avoid interrupt mucking, just adjust the address for 4-byte access.
492 * Assume the addresses are 8-byte aligned.
493 */
494#ifdef __MIPSEB__
495#define __CSR_32_ADJUST 4
496#else
497#define __CSR_32_ADJUST 0
498#endif
499
500#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
501#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
502
503#define __raw_readb __raw_readb
504#define __raw_readw __raw_readw
505#define __raw_readl __raw_readl
506#ifdef CONFIG_64BIT
507#define __raw_readq __raw_readq
508#endif
509#define __raw_writeb __raw_writeb
510#define __raw_writew __raw_writew
511#define __raw_writel __raw_writel
512#ifdef CONFIG_64BIT
513#define __raw_writeq __raw_writeq
514#endif
515
516#define readb readb
517#define readw readw
518#define readl readl
519#ifdef CONFIG_64BIT
520#define readq readq
521#endif
522#define writeb writeb
523#define writew writew
524#define writel writel
525#ifdef CONFIG_64BIT
526#define writeq writeq
527#endif
528
529#define readsb readsb
530#define readsw readsw
531#define readsl readsl
532#ifdef CONFIG_64BIT
533#define readsq readsq
534#endif
535#define writesb writesb
536#define writesw writesw
537#define writesl writesl
538#ifdef CONFIG_64BIT
539#define writesq writesq
540#endif
541
542#define _inb _inb
543#define _inw _inw
544#define _inl _inl
545#define insb insb
546#define insw insw
547#define insl insl
548
549#define _outb _outb
550#define _outw _outw
551#define _outl _outl
552#define outsb outsb
553#define outsw outsw
554#define outsl outsl
555
556void __ioread64_copy(void *to, const void __iomem *from, size_t count);
557
558#include <asm-generic/io.h>
559
560static inline void *isa_bus_to_virt(unsigned long address)
561{
562 return phys_to_virt(address);
563}
564
565#endif /* _ASM_IO_H */