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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12#ifndef _ASM_IO_H
13#define _ASM_IO_H
14
15#include <linux/compiler.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18
19#include <asm/addrspace.h>
20#include <asm/byteorder.h>
21#include <asm/cpu.h>
22#include <asm/cpu-features.h>
23#include <asm-generic/iomap.h>
24#include <asm/page.h>
25#include <asm/pgtable-bits.h>
26#include <asm/processor.h>
27#include <asm/string.h>
28
29#include <ioremap.h>
30#include <mangle-port.h>
31
32/*
33 * Slowdown I/O port space accesses for antique hardware.
34 */
35#undef CONF_SLOWDOWN_IO
36
37/*
38 * Raw operations are never swapped in software. OTOH values that raw
39 * operations are working on may or may not have been swapped by the bus
40 * hardware. An example use would be for flash memory that's used for
41 * execute in place.
42 */
43# define __raw_ioswabb(a, x) (x)
44# define __raw_ioswabw(a, x) (x)
45# define __raw_ioswabl(a, x) (x)
46# define __raw_ioswabq(a, x) (x)
47# define ____raw_ioswabq(a, x) (x)
48
49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50
51#define IO_SPACE_LIMIT 0xffff
52
53/*
54 * On MIPS I/O ports are memory mapped, so we access them using normal
55 * load/store instructions. mips_io_port_base is the virtual address to
56 * which all ports are being mapped. For sake of efficiency some code
57 * assumes that this is an address that can be loaded with a single lui
58 * instruction, so the lower 16 bits must be zero. Should be true on
59 * on any sane architecture; generic code does not use this assumption.
60 */
61extern const unsigned long mips_io_port_base;
62
63/*
64 * Gcc will generate code to load the value of mips_io_port_base after each
65 * function call which may be fairly wasteful in some cases. So we don't
66 * play quite by the book. We tell gcc mips_io_port_base is a long variable
67 * which solves the code generation issue. Now we need to violate the
68 * aliasing rules a little to make initialization possible and finally we
69 * will need the barrier() to fight side effects of the aliasing chat.
70 * This trickery will eventually collapse under gcc's optimizer. Oh well.
71 */
72static inline void set_io_port_base(unsigned long base)
73{
74 * (unsigned long *) &mips_io_port_base = base;
75 barrier();
76}
77
78/*
79 * Thanks to James van Artsdalen for a better timing-fix than
80 * the two short jumps: using outb's to a nonexistent port seems
81 * to guarantee better timings even on fast machines.
82 *
83 * On the other hand, I'd like to be sure of a non-existent port:
84 * I feel a bit unsafe about using 0x80 (should be safe, though)
85 *
86 * Linus
87 *
88 */
89
90#define __SLOW_DOWN_IO \
91 __asm__ __volatile__( \
92 "sb\t$0,0x80(%0)" \
93 : : "r" (mips_io_port_base));
94
95#ifdef CONF_SLOWDOWN_IO
96#ifdef REALLY_SLOW_IO
97#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
98#else
99#define SLOW_DOWN_IO __SLOW_DOWN_IO
100#endif
101#else
102#define SLOW_DOWN_IO
103#endif
104
105/*
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
108 *
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
112 *
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
115 * this function
116 */
117static inline unsigned long virt_to_phys(volatile const void *address)
118{
119 return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
120}
121
122/*
123 * phys_to_virt - map physical address to virtual
124 * @address: address to remap
125 *
126 * The returned virtual address is a current CPU mapping for
127 * the memory address given. It is only valid to use this function on
128 * addresses that have a kernel mapping
129 *
130 * This function does not handle bus mappings for DMA transfers. In
131 * almost all conceivable cases a device driver should not be using
132 * this function
133 */
134static inline void * phys_to_virt(unsigned long address)
135{
136 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
137}
138
139/*
140 * ISA I/O bus memory addresses are 1:1 with the physical address.
141 */
142static inline unsigned long isa_virt_to_bus(volatile void * address)
143{
144 return (unsigned long)address - PAGE_OFFSET;
145}
146
147static inline void * isa_bus_to_virt(unsigned long address)
148{
149 return (void *)(address + PAGE_OFFSET);
150}
151
152#define isa_page_to_bus page_to_phys
153
154/*
155 * However PCI ones are not necessarily 1:1 and therefore these interfaces
156 * are forbidden in portable PCI drivers.
157 *
158 * Allow them for x86 for legacy drivers, though.
159 */
160#define virt_to_bus virt_to_phys
161#define bus_to_virt phys_to_virt
162
163/*
164 * Change "struct page" to physical address.
165 */
166#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
167
168extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
169extern void __iounmap(const volatile void __iomem *addr);
170
171static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
172 unsigned long flags)
173{
174 void __iomem *addr = plat_ioremap(offset, size, flags);
175
176 if (addr)
177 return addr;
178
179#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
180
181 if (cpu_has_64bit_addresses) {
182 u64 base = UNCAC_BASE;
183
184 /*
185 * R10000 supports a 2 bit uncached attribute therefore
186 * UNCAC_BASE may not equal IO_BASE.
187 */
188 if (flags == _CACHE_UNCACHED)
189 base = (u64) IO_BASE;
190 return (void __iomem *) (unsigned long) (base + offset);
191 } else if (__builtin_constant_p(offset) &&
192 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
193 phys_t phys_addr, last_addr;
194
195 phys_addr = fixup_bigphys_addr(offset, size);
196
197 /* Don't allow wraparound or zero size. */
198 last_addr = phys_addr + size - 1;
199 if (!size || last_addr < phys_addr)
200 return NULL;
201
202 /*
203 * Map uncached objects in the low 512MB of address
204 * space using KSEG1.
205 */
206 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
207 flags == _CACHE_UNCACHED)
208 return (void __iomem *)
209 (unsigned long)CKSEG1ADDR(phys_addr);
210 }
211
212 return __ioremap(offset, size, flags);
213
214#undef __IS_LOW512
215}
216
217/*
218 * ioremap - map bus memory into CPU space
219 * @offset: bus address of the memory
220 * @size: size of the resource to map
221 *
222 * ioremap performs a platform specific sequence of operations to
223 * make bus memory CPU accessible via the readb/readw/readl/writeb/
224 * writew/writel functions and the other mmio helpers. The returned
225 * address is not guaranteed to be usable directly as a virtual
226 * address.
227 */
228#define ioremap(offset, size) \
229 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
230
231/*
232 * ioremap_nocache - map bus memory into CPU space
233 * @offset: bus address of the memory
234 * @size: size of the resource to map
235 *
236 * ioremap_nocache performs a platform specific sequence of operations to
237 * make bus memory CPU accessible via the readb/readw/readl/writeb/
238 * writew/writel functions and the other mmio helpers. The returned
239 * address is not guaranteed to be usable directly as a virtual
240 * address.
241 *
242 * This version of ioremap ensures that the memory is marked uncachable
243 * on the CPU as well as honouring existing caching rules from things like
244 * the PCI bus. Note that there are other caches and buffers on many
245 * busses. In particular driver authors should read up on PCI writes
246 *
247 * It's useful if some control registers are in such an area and
248 * write combining or read caching is not desirable:
249 */
250#define ioremap_nocache(offset, size) \
251 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
252
253/*
254 * ioremap_cachable - map bus memory into CPU space
255 * @offset: bus address of the memory
256 * @size: size of the resource to map
257 *
258 * ioremap_nocache performs a platform specific sequence of operations to
259 * make bus memory CPU accessible via the readb/readw/readl/writeb/
260 * writew/writel functions and the other mmio helpers. The returned
261 * address is not guaranteed to be usable directly as a virtual
262 * address.
263 *
264 * This version of ioremap ensures that the memory is marked cachable by
265 * the CPU. Also enables full write-combining. Useful for some
266 * memory-like regions on I/O busses.
267 */
268#define ioremap_cachable(offset, size) \
269 __ioremap_mode((offset), (size), _page_cachable_default)
270
271/*
272 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
273 * requests a cachable mapping, ioremap_uncached_accelerated requests a
274 * mapping using the uncached accelerated mode which isn't supported on
275 * all processors.
276 */
277#define ioremap_cacheable_cow(offset, size) \
278 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
279#define ioremap_uncached_accelerated(offset, size) \
280 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
281
282static inline void iounmap(const volatile void __iomem *addr)
283{
284 if (plat_iounmap(addr))
285 return;
286
287#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
288
289 if (cpu_has_64bit_addresses ||
290 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
291 return;
292
293 __iounmap(addr);
294
295#undef __IS_KSEG1
296}
297
298#ifdef CONFIG_CPU_CAVIUM_OCTEON
299#define war_octeon_io_reorder_wmb() wmb()
300#else
301#define war_octeon_io_reorder_wmb() do { } while (0)
302#endif
303
304#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
305 \
306static inline void pfx##write##bwlq(type val, \
307 volatile void __iomem *mem) \
308{ \
309 volatile type *__mem; \
310 type __val; \
311 \
312 war_octeon_io_reorder_wmb(); \
313 \
314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
315 \
316 __val = pfx##ioswab##bwlq(__mem, val); \
317 \
318 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
319 *__mem = __val; \
320 else if (cpu_has_64bits) { \
321 unsigned long __flags; \
322 type __tmp; \
323 \
324 if (irq) \
325 local_irq_save(__flags); \
326 __asm__ __volatile__( \
327 ".set mips3" "\t\t# __writeq""\n\t" \
328 "dsll32 %L0, %L0, 0" "\n\t" \
329 "dsrl32 %L0, %L0, 0" "\n\t" \
330 "dsll32 %M0, %M0, 0" "\n\t" \
331 "or %L0, %L0, %M0" "\n\t" \
332 ".set push" "\n\t" \
333 ".set noreorder" "\n\t" \
334 ".set nomacro" "\n\t" \
335 "sd %L0, %2" "\n\t" \
336 ".set pop" "\n\t" \
337 ".set mips0" "\n" \
338 : "=r" (__tmp) \
339 : "0" (__val), "R" (*__mem)); \
340 if (irq) \
341 local_irq_restore(__flags); \
342 } else \
343 BUG(); \
344} \
345 \
346static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
347{ \
348 volatile type *__mem; \
349 type __val; \
350 \
351 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
352 \
353 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
354 __val = *__mem; \
355 else if (cpu_has_64bits) { \
356 unsigned long __flags; \
357 \
358 if (irq) \
359 local_irq_save(__flags); \
360 __asm__ __volatile__( \
361 ".set mips3" "\t\t# __readq" "\n\t" \
362 ".set push" "\n\t" \
363 ".set noreorder" "\n\t" \
364 ".set nomacro" "\n\t" \
365 "ld %L0, %1" "\n\t" \
366 ".set pop" "\n\t" \
367 "dsra32 %M0, %L0, 0" "\n\t" \
368 "sll %L0, %L0, 0" "\n\t" \
369 ".set mips0" "\n" \
370 : "=r" (__val) \
371 : "R" (*__mem)); \
372 if (irq) \
373 local_irq_restore(__flags); \
374 } else { \
375 __val = 0; \
376 BUG(); \
377 } \
378 \
379 return pfx##ioswab##bwlq(__mem, __val); \
380}
381
382#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
383 \
384static inline void pfx##out##bwlq##p(type val, unsigned long port) \
385{ \
386 volatile type *__addr; \
387 type __val; \
388 \
389 war_octeon_io_reorder_wmb(); \
390 \
391 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
392 \
393 __val = pfx##ioswab##bwlq(__addr, val); \
394 \
395 /* Really, we want this to be atomic */ \
396 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
397 \
398 *__addr = __val; \
399 slow; \
400} \
401 \
402static inline type pfx##in##bwlq##p(unsigned long port) \
403{ \
404 volatile type *__addr; \
405 type __val; \
406 \
407 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
408 \
409 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
410 \
411 __val = *__addr; \
412 slow; \
413 \
414 return pfx##ioswab##bwlq(__addr, __val); \
415}
416
417#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
418 \
419__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
420
421#define BUILDIO_MEM(bwlq, type) \
422 \
423__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
424__BUILD_MEMORY_PFX(, bwlq, type) \
425__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
426
427BUILDIO_MEM(b, u8)
428BUILDIO_MEM(w, u16)
429BUILDIO_MEM(l, u32)
430BUILDIO_MEM(q, u64)
431
432#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
433 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
434 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
435
436#define BUILDIO_IOPORT(bwlq, type) \
437 __BUILD_IOPORT_PFX(, bwlq, type) \
438 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
439
440BUILDIO_IOPORT(b, u8)
441BUILDIO_IOPORT(w, u16)
442BUILDIO_IOPORT(l, u32)
443#ifdef CONFIG_64BIT
444BUILDIO_IOPORT(q, u64)
445#endif
446
447#define __BUILDIO(bwlq, type) \
448 \
449__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
450
451__BUILDIO(q, u64)
452
453#define readb_relaxed readb
454#define readw_relaxed readw
455#define readl_relaxed readl
456#define readq_relaxed readq
457
458#define readb_be(addr) \
459 __raw_readb((__force unsigned *)(addr))
460#define readw_be(addr) \
461 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
462#define readl_be(addr) \
463 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
464#define readq_be(addr) \
465 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
466
467#define writeb_be(val, addr) \
468 __raw_writeb((val), (__force unsigned *)(addr))
469#define writew_be(val, addr) \
470 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
471#define writel_be(val, addr) \
472 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
473#define writeq_be(val, addr) \
474 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
475
476/*
477 * Some code tests for these symbols
478 */
479#define readq readq
480#define writeq writeq
481
482#define __BUILD_MEMORY_STRING(bwlq, type) \
483 \
484static inline void writes##bwlq(volatile void __iomem *mem, \
485 const void *addr, unsigned int count) \
486{ \
487 const volatile type *__addr = addr; \
488 \
489 while (count--) { \
490 __mem_write##bwlq(*__addr, mem); \
491 __addr++; \
492 } \
493} \
494 \
495static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
496 unsigned int count) \
497{ \
498 volatile type *__addr = addr; \
499 \
500 while (count--) { \
501 *__addr = __mem_read##bwlq(mem); \
502 __addr++; \
503 } \
504}
505
506#define __BUILD_IOPORT_STRING(bwlq, type) \
507 \
508static inline void outs##bwlq(unsigned long port, const void *addr, \
509 unsigned int count) \
510{ \
511 const volatile type *__addr = addr; \
512 \
513 while (count--) { \
514 __mem_out##bwlq(*__addr, port); \
515 __addr++; \
516 } \
517} \
518 \
519static inline void ins##bwlq(unsigned long port, void *addr, \
520 unsigned int count) \
521{ \
522 volatile type *__addr = addr; \
523 \
524 while (count--) { \
525 *__addr = __mem_in##bwlq(port); \
526 __addr++; \
527 } \
528}
529
530#define BUILDSTRING(bwlq, type) \
531 \
532__BUILD_MEMORY_STRING(bwlq, type) \
533__BUILD_IOPORT_STRING(bwlq, type)
534
535BUILDSTRING(b, u8)
536BUILDSTRING(w, u16)
537BUILDSTRING(l, u32)
538#ifdef CONFIG_64BIT
539BUILDSTRING(q, u64)
540#endif
541
542
543#ifdef CONFIG_CPU_CAVIUM_OCTEON
544#define mmiowb() wmb()
545#else
546/* Depends on MIPS II instruction set */
547#define mmiowb() asm volatile ("sync" ::: "memory")
548#endif
549
550static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
551{
552 memset((void __force *) addr, val, count);
553}
554static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
555{
556 memcpy(dst, (void __force *) src, count);
557}
558static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
559{
560 memcpy((void __force *) dst, src, count);
561}
562
563/*
564 * The caches on some architectures aren't dma-coherent and have need to
565 * handle this in software. There are three types of operations that
566 * can be applied to dma buffers.
567 *
568 * - dma_cache_wback_inv(start, size) makes caches and coherent by
569 * writing the content of the caches back to memory, if necessary.
570 * The function also invalidates the affected part of the caches as
571 * necessary before DMA transfers from outside to memory.
572 * - dma_cache_wback(start, size) makes caches and coherent by
573 * writing the content of the caches back to memory, if necessary.
574 * The function also invalidates the affected part of the caches as
575 * necessary before DMA transfers from outside to memory.
576 * - dma_cache_inv(start, size) invalidates the affected parts of the
577 * caches. Dirty lines of the caches may be written back or simply
578 * be discarded. This operation is necessary before dma operations
579 * to the memory.
580 *
581 * This API used to be exported; it now is for arch code internal use only.
582 */
583#ifdef CONFIG_DMA_NONCOHERENT
584
585extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
586extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
587extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
588
589#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
590#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
591#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
592
593#else /* Sane hardware */
594
595#define dma_cache_wback_inv(start,size) \
596 do { (void) (start); (void) (size); } while (0)
597#define dma_cache_wback(start,size) \
598 do { (void) (start); (void) (size); } while (0)
599#define dma_cache_inv(start,size) \
600 do { (void) (start); (void) (size); } while (0)
601
602#endif /* CONFIG_DMA_NONCOHERENT */
603
604/*
605 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
606 * Avoid interrupt mucking, just adjust the address for 4-byte access.
607 * Assume the addresses are 8-byte aligned.
608 */
609#ifdef __MIPSEB__
610#define __CSR_32_ADJUST 4
611#else
612#define __CSR_32_ADJUST 0
613#endif
614
615#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
616#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
617
618/*
619 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
620 * access
621 */
622#define xlate_dev_mem_ptr(p) __va(p)
623
624/*
625 * Convert a virtual cached pointer to an uncached pointer
626 */
627#define xlate_dev_kmem_ptr(p) p
628
629#endif /* _ASM_IO_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12#ifndef _ASM_IO_H
13#define _ASM_IO_H
14
15#define ARCH_HAS_IOREMAP_WC
16
17#include <linux/compiler.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/irqflags.h>
21
22#include <asm/addrspace.h>
23#include <asm/barrier.h>
24#include <asm/bug.h>
25#include <asm/byteorder.h>
26#include <asm/cpu.h>
27#include <asm/cpu-features.h>
28#include <asm-generic/iomap.h>
29#include <asm/page.h>
30#include <asm/pgtable-bits.h>
31#include <asm/processor.h>
32#include <asm/string.h>
33#include <mangle-port.h>
34
35/*
36 * Raw operations are never swapped in software. OTOH values that raw
37 * operations are working on may or may not have been swapped by the bus
38 * hardware. An example use would be for flash memory that's used for
39 * execute in place.
40 */
41# define __raw_ioswabb(a, x) (x)
42# define __raw_ioswabw(a, x) (x)
43# define __raw_ioswabl(a, x) (x)
44# define __raw_ioswabq(a, x) (x)
45# define ____raw_ioswabq(a, x) (x)
46
47# define __relaxed_ioswabb ioswabb
48# define __relaxed_ioswabw ioswabw
49# define __relaxed_ioswabl ioswabl
50# define __relaxed_ioswabq ioswabq
51
52/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
53
54/*
55 * On MIPS I/O ports are memory mapped, so we access them using normal
56 * load/store instructions. mips_io_port_base is the virtual address to
57 * which all ports are being mapped. For sake of efficiency some code
58 * assumes that this is an address that can be loaded with a single lui
59 * instruction, so the lower 16 bits must be zero. Should be true on
60 * any sane architecture; generic code does not use this assumption.
61 */
62extern unsigned long mips_io_port_base;
63
64static inline void set_io_port_base(unsigned long base)
65{
66 mips_io_port_base = base;
67}
68
69/*
70 * Provide the necessary definitions for generic iomap. We make use of
71 * mips_io_port_base for iomap(), but we don't reserve any low addresses for
72 * use with I/O ports.
73 */
74
75#define HAVE_ARCH_PIO_SIZE
76#define PIO_OFFSET mips_io_port_base
77#define PIO_MASK IO_SPACE_LIMIT
78#define PIO_RESERVED 0x0UL
79
80/*
81 * Enforce in-order execution of data I/O. In the MIPS architecture
82 * these are equivalent to corresponding platform-specific memory
83 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
84 * with sync additionally defined.
85 */
86#define iobarrier_rw() mb()
87#define iobarrier_r() rmb()
88#define iobarrier_w() wmb()
89#define iobarrier_sync() iob()
90
91/*
92 * virt_to_phys - map virtual addresses to physical
93 * @address: address to remap
94 *
95 * The returned physical address is the physical (CPU) mapping for
96 * the memory address given. It is only valid to use this function on
97 * addresses directly mapped or allocated via kmalloc.
98 *
99 * This function does not give bus mappings for DMA transfers. In
100 * almost all conceivable cases a device driver should not be using
101 * this function
102 */
103static inline unsigned long virt_to_phys(volatile const void *address)
104{
105 return __pa(address);
106}
107
108/*
109 * phys_to_virt - map physical address to virtual
110 * @address: address to remap
111 *
112 * The returned virtual address is a current CPU mapping for
113 * the memory address given. It is only valid to use this function on
114 * addresses that have a kernel mapping
115 *
116 * This function does not handle bus mappings for DMA transfers. In
117 * almost all conceivable cases a device driver should not be using
118 * this function
119 */
120static inline void * phys_to_virt(unsigned long address)
121{
122 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
123}
124
125/*
126 * ISA I/O bus memory addresses are 1:1 with the physical address.
127 */
128static inline unsigned long isa_virt_to_bus(volatile void *address)
129{
130 return virt_to_phys(address);
131}
132
133static inline void *isa_bus_to_virt(unsigned long address)
134{
135 return phys_to_virt(address);
136}
137
138/*
139 * However PCI ones are not necessarily 1:1 and therefore these interfaces
140 * are forbidden in portable PCI drivers.
141 *
142 * Allow them for x86 for legacy drivers, though.
143 */
144#define virt_to_bus virt_to_phys
145#define bus_to_virt phys_to_virt
146
147/*
148 * Change "struct page" to physical address.
149 */
150#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
151
152void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
153 unsigned long prot_val);
154void iounmap(const volatile void __iomem *addr);
155
156/*
157 * ioremap - map bus memory into CPU space
158 * @offset: bus address of the memory
159 * @size: size of the resource to map
160 *
161 * ioremap performs a platform specific sequence of operations to
162 * make bus memory CPU accessible via the readb/readw/readl/writeb/
163 * writew/writel functions and the other mmio helpers. The returned
164 * address is not guaranteed to be usable directly as a virtual
165 * address.
166 */
167#define ioremap(offset, size) \
168 ioremap_prot((offset), (size), _CACHE_UNCACHED)
169#define ioremap_uc ioremap
170
171/*
172 * ioremap_cache - map bus memory into CPU space
173 * @offset: bus address of the memory
174 * @size: size of the resource to map
175 *
176 * ioremap_cache performs a platform specific sequence of operations to
177 * make bus memory CPU accessible via the readb/readw/readl/writeb/
178 * writew/writel functions and the other mmio helpers. The returned
179 * address is not guaranteed to be usable directly as a virtual
180 * address.
181 *
182 * This version of ioremap ensures that the memory is marked cachable by
183 * the CPU. Also enables full write-combining. Useful for some
184 * memory-like regions on I/O busses.
185 */
186#define ioremap_cache(offset, size) \
187 ioremap_prot((offset), (size), _page_cachable_default)
188
189/*
190 * ioremap_wc - map bus memory into CPU space
191 * @offset: bus address of the memory
192 * @size: size of the resource to map
193 *
194 * ioremap_wc performs a platform specific sequence of operations to
195 * make bus memory CPU accessible via the readb/readw/readl/writeb/
196 * writew/writel functions and the other mmio helpers. The returned
197 * address is not guaranteed to be usable directly as a virtual
198 * address.
199 *
200 * This version of ioremap ensures that the memory is marked uncachable
201 * but accelerated by means of write-combining feature. It is specifically
202 * useful for PCIe prefetchable windows, which may vastly improve a
203 * communications performance. If it was determined on boot stage, what
204 * CPU CCA doesn't support UCA, the method shall fall-back to the
205 * _CACHE_UNCACHED option (see cpu_probe() method).
206 */
207#define ioremap_wc(offset, size) \
208 ioremap_prot((offset), (size), boot_cpu_data.writecombine)
209
210#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
211#define war_io_reorder_wmb() wmb()
212#else
213#define war_io_reorder_wmb() barrier()
214#endif
215
216#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
217 \
218static inline void pfx##write##bwlq(type val, \
219 volatile void __iomem *mem) \
220{ \
221 volatile type *__mem; \
222 type __val; \
223 \
224 if (barrier) \
225 iobarrier_rw(); \
226 else \
227 war_io_reorder_wmb(); \
228 \
229 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
230 \
231 __val = pfx##ioswab##bwlq(__mem, val); \
232 \
233 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
234 *__mem = __val; \
235 else if (cpu_has_64bits) { \
236 unsigned long __flags; \
237 type __tmp; \
238 \
239 if (irq) \
240 local_irq_save(__flags); \
241 __asm__ __volatile__( \
242 ".set push" "\t\t# __writeq""\n\t" \
243 ".set arch=r4000" "\n\t" \
244 "dsll32 %L0, %L0, 0" "\n\t" \
245 "dsrl32 %L0, %L0, 0" "\n\t" \
246 "dsll32 %M0, %M0, 0" "\n\t" \
247 "or %L0, %L0, %M0" "\n\t" \
248 "sd %L0, %2" "\n\t" \
249 ".set pop" "\n" \
250 : "=r" (__tmp) \
251 : "0" (__val), "m" (*__mem)); \
252 if (irq) \
253 local_irq_restore(__flags); \
254 } else \
255 BUG(); \
256} \
257 \
258static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
259{ \
260 volatile type *__mem; \
261 type __val; \
262 \
263 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
264 \
265 if (barrier) \
266 iobarrier_rw(); \
267 \
268 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
269 __val = *__mem; \
270 else if (cpu_has_64bits) { \
271 unsigned long __flags; \
272 \
273 if (irq) \
274 local_irq_save(__flags); \
275 __asm__ __volatile__( \
276 ".set push" "\t\t# __readq" "\n\t" \
277 ".set arch=r4000" "\n\t" \
278 "ld %L0, %1" "\n\t" \
279 "dsra32 %M0, %L0, 0" "\n\t" \
280 "sll %L0, %L0, 0" "\n\t" \
281 ".set pop" "\n" \
282 : "=r" (__val) \
283 : "m" (*__mem)); \
284 if (irq) \
285 local_irq_restore(__flags); \
286 } else { \
287 __val = 0; \
288 BUG(); \
289 } \
290 \
291 /* prevent prefetching of coherent DMA data prematurely */ \
292 if (!relax) \
293 rmb(); \
294 return pfx##ioswab##bwlq(__mem, __val); \
295}
296
297#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
298 \
299static inline void pfx##out##bwlq##p(type val, unsigned long port) \
300{ \
301 volatile type *__addr; \
302 type __val; \
303 \
304 if (barrier) \
305 iobarrier_rw(); \
306 else \
307 war_io_reorder_wmb(); \
308 \
309 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
310 \
311 __val = pfx##ioswab##bwlq(__addr, val); \
312 \
313 /* Really, we want this to be atomic */ \
314 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
315 \
316 *__addr = __val; \
317} \
318 \
319static inline type pfx##in##bwlq##p(unsigned long port) \
320{ \
321 volatile type *__addr; \
322 type __val; \
323 \
324 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
325 \
326 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
327 \
328 if (barrier) \
329 iobarrier_rw(); \
330 \
331 __val = *__addr; \
332 \
333 /* prevent prefetching of coherent DMA data prematurely */ \
334 if (!relax) \
335 rmb(); \
336 return pfx##ioswab##bwlq(__addr, __val); \
337}
338
339#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
340 \
341__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
342
343#define BUILDIO_MEM(bwlq, type) \
344 \
345__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
346__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
347__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
348__BUILD_MEMORY_PFX(, bwlq, type, 0)
349
350BUILDIO_MEM(b, u8)
351BUILDIO_MEM(w, u16)
352BUILDIO_MEM(l, u32)
353#ifdef CONFIG_64BIT
354BUILDIO_MEM(q, u64)
355#else
356__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
357__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
358#endif
359
360#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
361 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
362 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
363
364#define BUILDIO_IOPORT(bwlq, type) \
365 __BUILD_IOPORT_PFX(, bwlq, type) \
366 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
367
368BUILDIO_IOPORT(b, u8)
369BUILDIO_IOPORT(w, u16)
370BUILDIO_IOPORT(l, u32)
371#ifdef CONFIG_64BIT
372BUILDIO_IOPORT(q, u64)
373#endif
374
375#define __BUILDIO(bwlq, type) \
376 \
377__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
378
379__BUILDIO(q, u64)
380
381#define readb_relaxed __relaxed_readb
382#define readw_relaxed __relaxed_readw
383#define readl_relaxed __relaxed_readl
384#ifdef CONFIG_64BIT
385#define readq_relaxed __relaxed_readq
386#endif
387
388#define writeb_relaxed __relaxed_writeb
389#define writew_relaxed __relaxed_writew
390#define writel_relaxed __relaxed_writel
391#ifdef CONFIG_64BIT
392#define writeq_relaxed __relaxed_writeq
393#endif
394
395#define readb_be(addr) \
396 __raw_readb((__force unsigned *)(addr))
397#define readw_be(addr) \
398 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
399#define readl_be(addr) \
400 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
401#define readq_be(addr) \
402 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
403
404#define writeb_be(val, addr) \
405 __raw_writeb((val), (__force unsigned *)(addr))
406#define writew_be(val, addr) \
407 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
408#define writel_be(val, addr) \
409 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
410#define writeq_be(val, addr) \
411 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
412
413/*
414 * Some code tests for these symbols
415 */
416#ifdef CONFIG_64BIT
417#define readq readq
418#define writeq writeq
419#endif
420
421#define __BUILD_MEMORY_STRING(bwlq, type) \
422 \
423static inline void writes##bwlq(volatile void __iomem *mem, \
424 const void *addr, unsigned int count) \
425{ \
426 const volatile type *__addr = addr; \
427 \
428 while (count--) { \
429 __mem_write##bwlq(*__addr, mem); \
430 __addr++; \
431 } \
432} \
433 \
434static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
435 unsigned int count) \
436{ \
437 volatile type *__addr = addr; \
438 \
439 while (count--) { \
440 *__addr = __mem_read##bwlq(mem); \
441 __addr++; \
442 } \
443}
444
445#define __BUILD_IOPORT_STRING(bwlq, type) \
446 \
447static inline void outs##bwlq(unsigned long port, const void *addr, \
448 unsigned int count) \
449{ \
450 const volatile type *__addr = addr; \
451 \
452 while (count--) { \
453 __mem_out##bwlq(*__addr, port); \
454 __addr++; \
455 } \
456} \
457 \
458static inline void ins##bwlq(unsigned long port, void *addr, \
459 unsigned int count) \
460{ \
461 volatile type *__addr = addr; \
462 \
463 while (count--) { \
464 *__addr = __mem_in##bwlq(port); \
465 __addr++; \
466 } \
467}
468
469#define BUILDSTRING(bwlq, type) \
470 \
471__BUILD_MEMORY_STRING(bwlq, type) \
472__BUILD_IOPORT_STRING(bwlq, type)
473
474BUILDSTRING(b, u8)
475BUILDSTRING(w, u16)
476BUILDSTRING(l, u32)
477#ifdef CONFIG_64BIT
478BUILDSTRING(q, u64)
479#endif
480
481static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
482{
483 memset((void __force *) addr, val, count);
484}
485static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
486{
487 memcpy(dst, (void __force *) src, count);
488}
489static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
490{
491 memcpy((void __force *) dst, src, count);
492}
493
494/*
495 * The caches on some architectures aren't dma-coherent and have need to
496 * handle this in software. There are three types of operations that
497 * can be applied to dma buffers.
498 *
499 * - dma_cache_wback_inv(start, size) makes caches and coherent by
500 * writing the content of the caches back to memory, if necessary.
501 * The function also invalidates the affected part of the caches as
502 * necessary before DMA transfers from outside to memory.
503 * - dma_cache_wback(start, size) makes caches and coherent by
504 * writing the content of the caches back to memory, if necessary.
505 * The function also invalidates the affected part of the caches as
506 * necessary before DMA transfers from outside to memory.
507 * - dma_cache_inv(start, size) invalidates the affected parts of the
508 * caches. Dirty lines of the caches may be written back or simply
509 * be discarded. This operation is necessary before dma operations
510 * to the memory.
511 *
512 * This API used to be exported; it now is for arch code internal use only.
513 */
514#ifdef CONFIG_DMA_NONCOHERENT
515
516extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
517extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
518extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
519
520#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
521#define dma_cache_wback(start, size) _dma_cache_wback(start, size)
522#define dma_cache_inv(start, size) _dma_cache_inv(start, size)
523
524#else /* Sane hardware */
525
526#define dma_cache_wback_inv(start,size) \
527 do { (void) (start); (void) (size); } while (0)
528#define dma_cache_wback(start,size) \
529 do { (void) (start); (void) (size); } while (0)
530#define dma_cache_inv(start,size) \
531 do { (void) (start); (void) (size); } while (0)
532
533#endif /* CONFIG_DMA_NONCOHERENT */
534
535/*
536 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
537 * Avoid interrupt mucking, just adjust the address for 4-byte access.
538 * Assume the addresses are 8-byte aligned.
539 */
540#ifdef __MIPSEB__
541#define __CSR_32_ADJUST 4
542#else
543#define __CSR_32_ADJUST 0
544#endif
545
546#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
547#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
548
549/*
550 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
551 * access
552 */
553#define xlate_dev_mem_ptr(p) __va(p)
554
555/*
556 * Convert a virtual cached pointer to an uncached pointer
557 */
558#define xlate_dev_kmem_ptr(p) p
559
560void __ioread64_copy(void *to, const void __iomem *from, size_t count);
561
562#endif /* _ASM_IO_H */