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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#ifndef __MSM_GPU_H__
8#define __MSM_GPU_H__
9
10#include <linux/adreno-smmu-priv.h>
11#include <linux/clk.h>
12#include <linux/devfreq.h>
13#include <linux/interconnect.h>
14#include <linux/pm_opp.h>
15#include <linux/regulator/consumer.h>
16
17#include "msm_drv.h"
18#include "msm_fence.h"
19#include "msm_ringbuffer.h"
20#include "msm_gem.h"
21
22struct msm_gem_submit;
23struct msm_gpu_perfcntr;
24struct msm_gpu_state;
25struct msm_file_private;
26
27struct msm_gpu_config {
28 const char *ioname;
29 unsigned int nr_rings;
30};
31
32/* So far, with hardware that I've seen to date, we can have:
33 * + zero, one, or two z180 2d cores
34 * + a3xx or a2xx 3d core, which share a common CP (the firmware
35 * for the CP seems to implement some different PM4 packet types
36 * but the basics of cmdstream submission are the same)
37 *
38 * Which means that the eventual complete "class" hierarchy, once
39 * support for all past and present hw is in place, becomes:
40 * + msm_gpu
41 * + adreno_gpu
42 * + a3xx_gpu
43 * + a2xx_gpu
44 * + z180_gpu
45 */
46struct msm_gpu_funcs {
47 int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
48 uint32_t param, uint64_t *value, uint32_t *len);
49 int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
50 uint32_t param, uint64_t value, uint32_t len);
51 int (*hw_init)(struct msm_gpu *gpu);
52
53 /**
54 * @ucode_load: Optional hook to upload fw to GEM objs
55 */
56 int (*ucode_load)(struct msm_gpu *gpu);
57
58 int (*pm_suspend)(struct msm_gpu *gpu);
59 int (*pm_resume)(struct msm_gpu *gpu);
60 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
62 irqreturn_t (*irq)(struct msm_gpu *irq);
63 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 void (*recover)(struct msm_gpu *gpu);
65 void (*destroy)(struct msm_gpu *gpu);
66#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
67 /* show GPU status in debugfs: */
68 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
69 struct drm_printer *p);
70 /* for generation specific debugfs: */
71 void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
72#endif
73 /* note: gpu_busy() can assume that we have been pm_resumed */
74 u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
75 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
76 int (*gpu_state_put)(struct msm_gpu_state *state);
77 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
78 /* note: gpu_set_freq() can assume that we have been pm_resumed */
79 void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
80 bool suspended);
81 struct msm_gem_address_space *(*create_address_space)
82 (struct msm_gpu *gpu, struct platform_device *pdev);
83 struct msm_gem_address_space *(*create_private_address_space)
84 (struct msm_gpu *gpu);
85 uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
86
87 /**
88 * progress: Has the GPU made progress?
89 *
90 * Return true if GPU position in cmdstream has advanced (or changed)
91 * since the last call. To avoid false negatives, this should account
92 * for cmdstream that is buffered in this FIFO upstream of the CP fw.
93 */
94 bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
95};
96
97/* Additional state for iommu faults: */
98struct msm_gpu_fault_info {
99 u64 ttbr0;
100 unsigned long iova;
101 int flags;
102 const char *type;
103 const char *block;
104};
105
106/**
107 * struct msm_gpu_devfreq - devfreq related state
108 */
109struct msm_gpu_devfreq {
110 /** devfreq: devfreq instance */
111 struct devfreq *devfreq;
112
113 /** lock: lock for "suspended", "busy_cycles", and "time" */
114 struct mutex lock;
115
116 /**
117 * idle_freq:
118 *
119 * Shadow frequency used while the GPU is idle. From the PoV of
120 * the devfreq governor, we are continuing to sample busyness and
121 * adjust frequency while the GPU is idle, but we use this shadow
122 * value as the GPU is actually clamped to minimum frequency while
123 * it is inactive.
124 */
125 unsigned long idle_freq;
126
127 /**
128 * boost_constraint:
129 *
130 * A PM QoS constraint to boost min freq for a period of time
131 * until the boost expires.
132 */
133 struct dev_pm_qos_request boost_freq;
134
135 /**
136 * busy_cycles: Last busy counter value, for calculating elapsed busy
137 * cycles since last sampling period.
138 */
139 u64 busy_cycles;
140
141 /** time: Time of last sampling period. */
142 ktime_t time;
143
144 /** idle_time: Time of last transition to idle: */
145 ktime_t idle_time;
146
147 /**
148 * idle_work:
149 *
150 * Used to delay clamping to idle freq on active->idle transition.
151 */
152 struct msm_hrtimer_work idle_work;
153
154 /**
155 * boost_work:
156 *
157 * Used to reset the boost_constraint after the boost period has
158 * elapsed
159 */
160 struct msm_hrtimer_work boost_work;
161
162 /** suspended: tracks if we're suspended */
163 bool suspended;
164};
165
166struct msm_gpu {
167 const char *name;
168 struct drm_device *dev;
169 struct platform_device *pdev;
170 const struct msm_gpu_funcs *funcs;
171
172 struct adreno_smmu_priv adreno_smmu;
173
174 /* performance counters (hw & sw): */
175 spinlock_t perf_lock;
176 bool perfcntr_active;
177 struct {
178 bool active;
179 ktime_t time;
180 } last_sample;
181 uint32_t totaltime, activetime; /* sw counters */
182 uint32_t last_cntrs[5]; /* hw counters */
183 const struct msm_gpu_perfcntr *perfcntrs;
184 uint32_t num_perfcntrs;
185
186 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS];
187 int nr_rings;
188
189 /**
190 * sysprof_active:
191 *
192 * The count of contexts that have enabled system profiling.
193 */
194 refcount_t sysprof_active;
195
196 /**
197 * lock:
198 *
199 * General lock for serializing all the gpu things.
200 *
201 * TODO move to per-ring locking where feasible (ie. submit/retire
202 * path, etc)
203 */
204 struct mutex lock;
205
206 /**
207 * active_submits:
208 *
209 * The number of submitted but not yet retired submits, used to
210 * determine transitions between active and idle.
211 *
212 * Protected by active_lock
213 */
214 int active_submits;
215
216 /** lock: protects active_submits and idle/active transitions */
217 struct mutex active_lock;
218
219 /* does gpu need hw_init? */
220 bool needs_hw_init;
221
222 /**
223 * global_faults: number of GPU hangs not attributed to a particular
224 * address space
225 */
226 int global_faults;
227
228 void __iomem *mmio;
229 int irq;
230
231 struct msm_gem_address_space *aspace;
232
233 /* Power Control: */
234 struct regulator *gpu_reg, *gpu_cx;
235 struct clk_bulk_data *grp_clks;
236 int nr_clocks;
237 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
238 uint32_t fast_rate;
239
240 /* Hang and Inactivity Detection:
241 */
242#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */
243
244#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */
245#define DRM_MSM_HANGCHECK_PROGRESS_RETRIES 3
246 struct timer_list hangcheck_timer;
247
248 /* Fault info for most recent iova fault: */
249 struct msm_gpu_fault_info fault_info;
250
251 /* work for handling GPU ioval faults: */
252 struct kthread_work fault_work;
253
254 /* work for handling GPU recovery: */
255 struct kthread_work recover_work;
256
257 /** retire_event: notified when submits are retired: */
258 wait_queue_head_t retire_event;
259
260 /* work for handling active-list retiring: */
261 struct kthread_work retire_work;
262
263 /* worker for retire/recover: */
264 struct kthread_worker *worker;
265
266 struct drm_gem_object *memptrs_bo;
267
268 struct msm_gpu_devfreq devfreq;
269
270 uint32_t suspend_count;
271
272 struct msm_gpu_state *crashstate;
273
274 /* True if the hardware supports expanded apriv (a650 and newer) */
275 bool hw_apriv;
276
277 /**
278 * @allow_relocs: allow relocs in SUBMIT ioctl
279 *
280 * Mesa won't use relocs for driver version 1.4.0 and later. This
281 * switch-over happened early enough in mesa a6xx bringup that we
282 * can disallow relocs for a6xx and newer.
283 */
284 bool allow_relocs;
285
286 struct thermal_cooling_device *cooling;
287};
288
289static inline struct msm_gpu *dev_to_gpu(struct device *dev)
290{
291 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
292
293 if (!adreno_smmu)
294 return NULL;
295
296 return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
297}
298
299/* It turns out that all targets use the same ringbuffer size */
300#define MSM_GPU_RINGBUFFER_SZ SZ_32K
301#define MSM_GPU_RINGBUFFER_BLKSIZE 32
302
303#define MSM_GPU_RB_CNTL_DEFAULT \
304 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
305 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
306
307static inline bool msm_gpu_active(struct msm_gpu *gpu)
308{
309 int i;
310
311 for (i = 0; i < gpu->nr_rings; i++) {
312 struct msm_ringbuffer *ring = gpu->rb[i];
313
314 if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))
315 return true;
316 }
317
318 return false;
319}
320
321/* Perf-Counters:
322 * The select_reg and select_val are just there for the benefit of the child
323 * class that actually enables the perf counter.. but msm_gpu base class
324 * will handle sampling/displaying the counters.
325 */
326
327struct msm_gpu_perfcntr {
328 uint32_t select_reg;
329 uint32_t sample_reg;
330 uint32_t select_val;
331 const char *name;
332};
333
334/*
335 * The number of priority levels provided by drm gpu scheduler. The
336 * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some
337 * cases, so we don't use it (no need for kernel generated jobs).
338 */
339#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_LOW - DRM_SCHED_PRIORITY_HIGH)
340
341/**
342 * struct msm_file_private - per-drm_file context
343 *
344 * @queuelock: synchronizes access to submitqueues list
345 * @submitqueues: list of &msm_gpu_submitqueue created by userspace
346 * @queueid: counter incremented each time a submitqueue is created,
347 * used to assign &msm_gpu_submitqueue.id
348 * @aspace: the per-process GPU address-space
349 * @ref: reference count
350 * @seqno: unique per process seqno
351 */
352struct msm_file_private {
353 rwlock_t queuelock;
354 struct list_head submitqueues;
355 int queueid;
356 struct msm_gem_address_space *aspace;
357 struct kref ref;
358 int seqno;
359
360 /**
361 * sysprof:
362 *
363 * The value of MSM_PARAM_SYSPROF set by userspace. This is
364 * intended to be used by system profiling tools like Mesa's
365 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
366 *
367 * Setting a value of 1 will preserve performance counters across
368 * context switches. Setting a value of 2 will in addition
369 * suppress suspend. (Performance counters lose state across
370 * power collapse, which is undesirable for profiling in some
371 * cases.)
372 *
373 * The value automatically reverts to zero when the drm device
374 * file is closed.
375 */
376 int sysprof;
377
378 /**
379 * comm: Overridden task comm, see MSM_PARAM_COMM
380 *
381 * Accessed under msm_gpu::lock
382 */
383 char *comm;
384
385 /**
386 * cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE
387 *
388 * Accessed under msm_gpu::lock
389 */
390 char *cmdline;
391
392 /**
393 * elapsed:
394 *
395 * The total (cumulative) elapsed time GPU was busy with rendering
396 * from this context in ns.
397 */
398 uint64_t elapsed_ns;
399
400 /**
401 * cycles:
402 *
403 * The total (cumulative) GPU cycles elapsed attributed to this
404 * context.
405 */
406 uint64_t cycles;
407
408 /**
409 * entities:
410 *
411 * Table of per-priority-level sched entities used by submitqueues
412 * associated with this &drm_file. Because some userspace apps
413 * make assumptions about rendering from multiple gl contexts
414 * (of the same priority) within the process happening in FIFO
415 * order without requiring any fencing beyond MakeCurrent(), we
416 * create at most one &drm_sched_entity per-process per-priority-
417 * level.
418 */
419 struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS];
420
421 /**
422 * ctx_mem:
423 *
424 * Total amount of memory of GEM buffers with handles attached for
425 * this context.
426 */
427 atomic64_t ctx_mem;
428};
429
430/**
431 * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
432 *
433 * @gpu: the gpu instance
434 * @prio: the userspace priority level
435 * @ring_nr: [out] the ringbuffer the userspace priority maps to
436 * @sched_prio: [out] the gpu scheduler priority level which the userspace
437 * priority maps to
438 *
439 * With drm/scheduler providing it's own level of prioritization, our total
440 * number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES).
441 * Each ring is associated with it's own scheduler instance. However, our
442 * UABI is that lower numerical values are higher priority. So mapping the
443 * single userspace priority level into ring_nr and sched_prio takes some
444 * care. The userspace provided priority (when a submitqueue is created)
445 * is mapped to ring nr and scheduler priority as such:
446 *
447 * ring_nr = userspace_prio / NR_SCHED_PRIORITIES
448 * sched_prio = NR_SCHED_PRIORITIES -
449 * (userspace_prio % NR_SCHED_PRIORITIES) - 1
450 *
451 * This allows generations without preemption (nr_rings==1) to have some
452 * amount of prioritization, and provides more priority levels for gens
453 * that do have preemption.
454 */
455static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,
456 unsigned *ring_nr, enum drm_sched_priority *sched_prio)
457{
458 unsigned rn, sp;
459
460 rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp);
461
462 /* invert sched priority to map to higher-numeric-is-higher-
463 * priority convention
464 */
465 sp = NR_SCHED_PRIORITIES - sp - 1;
466
467 if (rn >= gpu->nr_rings)
468 return -EINVAL;
469
470 *ring_nr = rn;
471 *sched_prio = sp;
472
473 return 0;
474}
475
476/**
477 * struct msm_gpu_submitqueues - Userspace created context.
478 *
479 * A submitqueue is associated with a gl context or vk queue (or equiv)
480 * in userspace.
481 *
482 * @id: userspace id for the submitqueue, unique within the drm_file
483 * @flags: userspace flags for the submitqueue, specified at creation
484 * (currently unusued)
485 * @ring_nr: the ringbuffer used by this submitqueue, which is determined
486 * by the submitqueue's priority
487 * @faults: the number of GPU hangs associated with this submitqueue
488 * @last_fence: the sequence number of the last allocated fence (for error
489 * checking)
490 * @ctx: the per-drm_file context associated with the submitqueue (ie.
491 * which set of pgtables do submits jobs associated with the
492 * submitqueue use)
493 * @node: node in the context's list of submitqueues
494 * @fence_idr: maps fence-id to dma_fence for userspace visible fence
495 * seqno, protected by submitqueue lock
496 * @idr_lock: for serializing access to fence_idr
497 * @lock: submitqueue lock for serializing submits on a queue
498 * @ref: reference count
499 * @entity: the submit job-queue
500 */
501struct msm_gpu_submitqueue {
502 int id;
503 u32 flags;
504 u32 ring_nr;
505 int faults;
506 uint32_t last_fence;
507 struct msm_file_private *ctx;
508 struct list_head node;
509 struct idr fence_idr;
510 struct spinlock idr_lock;
511 struct mutex lock;
512 struct kref ref;
513 struct drm_sched_entity *entity;
514};
515
516struct msm_gpu_state_bo {
517 u64 iova;
518 size_t size;
519 u32 flags;
520 void *data;
521 bool encoded;
522 char name[32];
523};
524
525struct msm_gpu_state {
526 struct kref ref;
527 struct timespec64 time;
528
529 struct {
530 u64 iova;
531 u32 fence;
532 u32 seqno;
533 u32 rptr;
534 u32 wptr;
535 void *data;
536 int data_size;
537 bool encoded;
538 } ring[MSM_GPU_MAX_RINGS];
539
540 int nr_registers;
541 u32 *registers;
542
543 u32 rbbm_status;
544
545 char *comm;
546 char *cmd;
547
548 struct msm_gpu_fault_info fault_info;
549
550 int nr_bos;
551 struct msm_gpu_state_bo *bos;
552};
553
554static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
555{
556 writel(data, gpu->mmio + (reg << 2));
557}
558
559static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
560{
561 return readl(gpu->mmio + (reg << 2));
562}
563
564static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
565{
566 msm_rmw(gpu->mmio + (reg << 2), mask, or);
567}
568
569static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
570{
571 u64 val;
572
573 /*
574 * Why not a readq here? Two reasons: 1) many of the LO registers are
575 * not quad word aligned and 2) the GPU hardware designers have a bit
576 * of a history of putting registers where they fit, especially in
577 * spins. The longer a GPU family goes the higher the chance that
578 * we'll get burned. We could do a series of validity checks if we
579 * wanted to, but really is a readq() that much better? Nah.
580 */
581
582 /*
583 * For some lo/hi registers (like perfcounters), the hi value is latched
584 * when the lo is read, so make sure to read the lo first to trigger
585 * that
586 */
587 val = (u64) readl(gpu->mmio + (reg << 2));
588 val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
589
590 return val;
591}
592
593static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
594{
595 /* Why not a writeq here? Read the screed above */
596 writel(lower_32_bits(val), gpu->mmio + (reg << 2));
597 writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
598}
599
600int msm_gpu_pm_suspend(struct msm_gpu *gpu);
601int msm_gpu_pm_resume(struct msm_gpu *gpu);
602
603void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
604 struct drm_printer *p);
605
606int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
607struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
608 u32 id);
609int msm_submitqueue_create(struct drm_device *drm,
610 struct msm_file_private *ctx,
611 u32 prio, u32 flags, u32 *id);
612int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
613 struct drm_msm_submitqueue_query *args);
614int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
615void msm_submitqueue_close(struct msm_file_private *ctx);
616
617void msm_submitqueue_destroy(struct kref *kref);
618
619int msm_file_private_set_sysprof(struct msm_file_private *ctx,
620 struct msm_gpu *gpu, int sysprof);
621void __msm_file_private_destroy(struct kref *kref);
622
623static inline void msm_file_private_put(struct msm_file_private *ctx)
624{
625 kref_put(&ctx->ref, __msm_file_private_destroy);
626}
627
628static inline struct msm_file_private *msm_file_private_get(
629 struct msm_file_private *ctx)
630{
631 kref_get(&ctx->ref);
632 return ctx;
633}
634
635void msm_devfreq_init(struct msm_gpu *gpu);
636void msm_devfreq_cleanup(struct msm_gpu *gpu);
637void msm_devfreq_resume(struct msm_gpu *gpu);
638void msm_devfreq_suspend(struct msm_gpu *gpu);
639void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
640void msm_devfreq_active(struct msm_gpu *gpu);
641void msm_devfreq_idle(struct msm_gpu *gpu);
642
643int msm_gpu_hw_init(struct msm_gpu *gpu);
644
645void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
646void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
647int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
648 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
649
650void msm_gpu_retire(struct msm_gpu *gpu);
651void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
652
653int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
654 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
655 const char *name, struct msm_gpu_config *config);
656
657struct msm_gem_address_space *
658msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
659
660void msm_gpu_cleanup(struct msm_gpu *gpu);
661
662struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
663void __init adreno_register(void);
664void __exit adreno_unregister(void);
665
666static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue)
667{
668 if (queue)
669 kref_put(&queue->ref, msm_submitqueue_destroy);
670}
671
672static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
673{
674 struct msm_gpu_state *state = NULL;
675
676 mutex_lock(&gpu->lock);
677
678 if (gpu->crashstate) {
679 kref_get(&gpu->crashstate->ref);
680 state = gpu->crashstate;
681 }
682
683 mutex_unlock(&gpu->lock);
684
685 return state;
686}
687
688static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
689{
690 mutex_lock(&gpu->lock);
691
692 if (gpu->crashstate) {
693 if (gpu->funcs->gpu_state_put(gpu->crashstate))
694 gpu->crashstate = NULL;
695 }
696
697 mutex_unlock(&gpu->lock);
698}
699
700/*
701 * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
702 * support expanded privileges
703 */
704#define check_apriv(gpu, flags) \
705 (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
706
707
708#endif /* __MSM_GPU_H__ */