Loading...
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
25
26struct stmpe_gpio {
27 struct gpio_chip chip;
28 struct stmpe *stmpe;
29 struct device *dev;
30 struct mutex irq_lock;
31
32 int irq_base;
33 unsigned norequest_mask;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct stmpe_gpio, chip);
43}
44
45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
48 struct stmpe *stmpe = stmpe_gpio->stmpe;
49 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = stmpe_reg_read(stmpe, reg);
54 if (ret < 0)
55 return ret;
56
57 return ret & mask;
58}
59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
63 struct stmpe *stmpe = stmpe_gpio->stmpe;
64 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8);
67
68 stmpe_reg_write(stmpe, reg, mask);
69}
70
71static int stmpe_gpio_direction_output(struct gpio_chip *chip,
72 unsigned offset, int val)
73{
74 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
75 struct stmpe *stmpe = stmpe_gpio->stmpe;
76 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
77 u8 mask = 1 << (offset % 8);
78
79 stmpe_gpio_set(chip, offset, val);
80
81 return stmpe_set_bits(stmpe, reg, mask, mask);
82}
83
84static int stmpe_gpio_direction_input(struct gpio_chip *chip,
85 unsigned offset)
86{
87 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
88 struct stmpe *stmpe = stmpe_gpio->stmpe;
89 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
90 u8 mask = 1 << (offset % 8);
91
92 return stmpe_set_bits(stmpe, reg, mask, 0);
93}
94
95static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96{
97 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98
99 return stmpe_gpio->irq_base + offset;
100}
101
102static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
103{
104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105 struct stmpe *stmpe = stmpe_gpio->stmpe;
106
107 if (stmpe_gpio->norequest_mask & (1 << offset))
108 return -EINVAL;
109
110 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
111}
112
113static struct gpio_chip template_chip = {
114 .label = "stmpe",
115 .owner = THIS_MODULE,
116 .direction_input = stmpe_gpio_direction_input,
117 .get = stmpe_gpio_get,
118 .direction_output = stmpe_gpio_direction_output,
119 .set = stmpe_gpio_set,
120 .to_irq = stmpe_gpio_to_irq,
121 .request = stmpe_gpio_request,
122 .can_sleep = 1,
123};
124
125static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
126{
127 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
128 int offset = d->irq - stmpe_gpio->irq_base;
129 int regoffset = offset / 8;
130 int mask = 1 << (offset % 8);
131
132 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
133 return -EINVAL;
134
135 if (type == IRQ_TYPE_EDGE_RISING)
136 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
137 else
138 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
139
140 if (type == IRQ_TYPE_EDGE_FALLING)
141 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
142 else
143 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
144
145 return 0;
146}
147
148static void stmpe_gpio_irq_lock(struct irq_data *d)
149{
150 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
151
152 mutex_lock(&stmpe_gpio->irq_lock);
153}
154
155static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
156{
157 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;
166
167 for (i = 0; i < CACHE_NR_REGS; i++) {
168 for (j = 0; j < num_banks; j++) {
169 u8 old = stmpe_gpio->oldregs[i][j];
170 u8 new = stmpe_gpio->regs[i][j];
171
172 if (new == old)
173 continue;
174
175 stmpe_gpio->oldregs[i][j] = new;
176 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
177 }
178 }
179
180 mutex_unlock(&stmpe_gpio->irq_lock);
181}
182
183static void stmpe_gpio_irq_mask(struct irq_data *d)
184{
185 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
186 int offset = d->irq - stmpe_gpio->irq_base;
187 int regoffset = offset / 8;
188 int mask = 1 << (offset % 8);
189
190 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
191}
192
193static void stmpe_gpio_irq_unmask(struct irq_data *d)
194{
195 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
196 int offset = d->irq - stmpe_gpio->irq_base;
197 int regoffset = offset / 8;
198 int mask = 1 << (offset % 8);
199
200 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
201}
202
203static struct irq_chip stmpe_gpio_irq_chip = {
204 .name = "stmpe-gpio",
205 .irq_bus_lock = stmpe_gpio_irq_lock,
206 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
207 .irq_mask = stmpe_gpio_irq_mask,
208 .irq_unmask = stmpe_gpio_irq_unmask,
209 .irq_set_type = stmpe_gpio_irq_set_type,
210};
211
212static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
213{
214 struct stmpe_gpio *stmpe_gpio = dev;
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 u8 status[num_banks];
219 int ret;
220 int i;
221
222 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
223 if (ret < 0)
224 return IRQ_NONE;
225
226 for (i = 0; i < num_banks; i++) {
227 int bank = num_banks - i - 1;
228 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
229 unsigned int stat = status[i];
230
231 stat &= enabled;
232 if (!stat)
233 continue;
234
235 while (stat) {
236 int bit = __ffs(stat);
237 int line = bank * 8 + bit;
238
239 handle_nested_irq(stmpe_gpio->irq_base + line);
240 stat &= ~(1 << bit);
241 }
242
243 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
244 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
245 status[i]);
246 }
247
248 return IRQ_HANDLED;
249}
250
251static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
252{
253 int base = stmpe_gpio->irq_base;
254 int irq;
255
256 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
257 irq_set_chip_data(irq, stmpe_gpio);
258 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
259 handle_simple_irq);
260 irq_set_nested_thread(irq, 1);
261#ifdef CONFIG_ARM
262 set_irq_flags(irq, IRQF_VALID);
263#else
264 irq_set_noprobe(irq);
265#endif
266 }
267
268 return 0;
269}
270
271static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
272{
273 int base = stmpe_gpio->irq_base;
274 int irq;
275
276 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
277#ifdef CONFIG_ARM
278 set_irq_flags(irq, 0);
279#endif
280 irq_set_chip_and_handler(irq, NULL, NULL);
281 irq_set_chip_data(irq, NULL);
282 }
283}
284
285static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
286{
287 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
288 struct stmpe_gpio_platform_data *pdata;
289 struct stmpe_gpio *stmpe_gpio;
290 int ret;
291 int irq;
292
293 pdata = stmpe->pdata->gpio;
294
295 irq = platform_get_irq(pdev, 0);
296 if (irq < 0)
297 return irq;
298
299 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
300 if (!stmpe_gpio)
301 return -ENOMEM;
302
303 mutex_init(&stmpe_gpio->irq_lock);
304
305 stmpe_gpio->dev = &pdev->dev;
306 stmpe_gpio->stmpe = stmpe;
307 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
308
309 stmpe_gpio->chip = template_chip;
310 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
311 stmpe_gpio->chip.dev = &pdev->dev;
312 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
313
314 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
315
316 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
317 if (ret)
318 goto out_free;
319
320 ret = stmpe_gpio_irq_init(stmpe_gpio);
321 if (ret)
322 goto out_disable;
323
324 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
325 "stmpe-gpio", stmpe_gpio);
326 if (ret) {
327 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
328 goto out_removeirq;
329 }
330
331 ret = gpiochip_add(&stmpe_gpio->chip);
332 if (ret) {
333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
334 goto out_freeirq;
335 }
336
337 if (pdata && pdata->setup)
338 pdata->setup(stmpe, stmpe_gpio->chip.base);
339
340 platform_set_drvdata(pdev, stmpe_gpio);
341
342 return 0;
343
344out_freeirq:
345 free_irq(irq, stmpe_gpio);
346out_removeirq:
347 stmpe_gpio_irq_remove(stmpe_gpio);
348out_disable:
349 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
350out_free:
351 kfree(stmpe_gpio);
352 return ret;
353}
354
355static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
356{
357 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
358 struct stmpe *stmpe = stmpe_gpio->stmpe;
359 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
360 int irq = platform_get_irq(pdev, 0);
361 int ret;
362
363 if (pdata && pdata->remove)
364 pdata->remove(stmpe, stmpe_gpio->chip.base);
365
366 ret = gpiochip_remove(&stmpe_gpio->chip);
367 if (ret < 0) {
368 dev_err(stmpe_gpio->dev,
369 "unable to remove gpiochip: %d\n", ret);
370 return ret;
371 }
372
373 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
374
375 free_irq(irq, stmpe_gpio);
376 stmpe_gpio_irq_remove(stmpe_gpio);
377 platform_set_drvdata(pdev, NULL);
378 kfree(stmpe_gpio);
379
380 return 0;
381}
382
383static struct platform_driver stmpe_gpio_driver = {
384 .driver.name = "stmpe-gpio",
385 .driver.owner = THIS_MODULE,
386 .probe = stmpe_gpio_probe,
387 .remove = __devexit_p(stmpe_gpio_remove),
388};
389
390static int __init stmpe_gpio_init(void)
391{
392 return platform_driver_register(&stmpe_gpio_driver);
393}
394subsys_initcall(stmpe_gpio_init);
395
396static void __exit stmpe_gpio_exit(void)
397{
398 platform_driver_unregister(&stmpe_gpio_driver);
399}
400module_exit(stmpe_gpio_exit);
401
402MODULE_LICENSE("GPL v2");
403MODULE_DESCRIPTION("STMPExxxx GPIO driver");
404MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/bitops.h>
9#include <linux/cleanup.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/stmpe.h>
14#include <linux/property.h>
15#include <linux/platform_device.h>
16#include <linux/seq_file.h>
17#include <linux/slab.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25enum { LSB, CSB, MSB };
26
27#define CACHE_NR_REGS 3
28/* No variant has more than 24 GPIOs */
29#define CACHE_NR_BANKS (24 / 8)
30
31struct stmpe_gpio {
32 struct gpio_chip chip;
33 struct stmpe *stmpe;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 if (ret & mask)
88 return GPIO_LINE_DIRECTION_OUT;
89
90 return GPIO_LINE_DIRECTION_IN;
91}
92
93static int stmpe_gpio_direction_output(struct gpio_chip *chip,
94 unsigned offset, int val)
95{
96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
99 u8 mask = BIT(offset % 8);
100
101 stmpe_gpio_set(chip, offset, val);
102
103 return stmpe_set_bits(stmpe, reg, mask, mask);
104}
105
106static int stmpe_gpio_direction_input(struct gpio_chip *chip,
107 unsigned offset)
108{
109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
110 struct stmpe *stmpe = stmpe_gpio->stmpe;
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
112 u8 mask = BIT(offset % 8);
113
114 return stmpe_set_bits(stmpe, reg, mask, 0);
115}
116
117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
118{
119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
120 struct stmpe *stmpe = stmpe_gpio->stmpe;
121
122 if (stmpe_gpio->norequest_mask & BIT(offset))
123 return -EINVAL;
124
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
126}
127
128static const struct gpio_chip template_chip = {
129 .label = "stmpe",
130 .owner = THIS_MODULE,
131 .get_direction = stmpe_gpio_get_direction,
132 .direction_input = stmpe_gpio_direction_input,
133 .get = stmpe_gpio_get,
134 .direction_output = stmpe_gpio_direction_output,
135 .set = stmpe_gpio_set,
136 .request = stmpe_gpio_request,
137 .can_sleep = true,
138};
139
140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141{
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
144 int offset = d->hwirq;
145 int regoffset = offset / 8;
146 int mask = BIT(offset % 8);
147
148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
149 return -EINVAL;
150
151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
153 stmpe_gpio->stmpe->partnum == STMPE1600)
154 return 0;
155
156 if (type & IRQ_TYPE_EDGE_RISING)
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
158 else
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
160
161 if (type & IRQ_TYPE_EDGE_FALLING)
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
163 else
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
165
166 return 0;
167}
168
169static void stmpe_gpio_irq_lock(struct irq_data *d)
170{
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
173
174 mutex_lock(&stmpe_gpio->irq_lock);
175}
176
177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
178{
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
181 struct stmpe *stmpe = stmpe_gpio->stmpe;
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
193 };
194 int ret, i, j;
195
196 /*
197 * STMPE1600: to be able to get IRQ from pins,
198 * a read must be done on GPMR register, or a write in
199 * GPSR or GPCR registers
200 */
201 if (stmpe->partnum == STMPE1600) {
202 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
203 if (ret < 0) {
204 dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
205 goto err;
206 }
207 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
208 if (ret < 0) {
209 dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
210 goto err;
211 }
212 }
213
214 for (i = 0; i < CACHE_NR_REGS; i++) {
215 /* STMPE801 and STMPE1600 don't have RE and FE registers */
216 if ((stmpe->partnum == STMPE801 ||
217 stmpe->partnum == STMPE1600) &&
218 (i != REG_IE))
219 continue;
220
221 for (j = 0; j < num_banks; j++) {
222 u8 old = stmpe_gpio->oldregs[i][j];
223 u8 new = stmpe_gpio->regs[i][j];
224
225 if (new == old)
226 continue;
227
228 stmpe_gpio->oldregs[i][j] = new;
229 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
230 }
231 }
232
233err:
234 mutex_unlock(&stmpe_gpio->irq_lock);
235}
236
237static void stmpe_gpio_irq_mask(struct irq_data *d)
238{
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
241 int offset = d->hwirq;
242 int regoffset = offset / 8;
243 int mask = BIT(offset % 8);
244
245 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
246 gpiochip_disable_irq(gc, offset);
247}
248
249static void stmpe_gpio_irq_unmask(struct irq_data *d)
250{
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
253 int offset = d->hwirq;
254 int regoffset = offset / 8;
255 int mask = BIT(offset % 8);
256
257 gpiochip_enable_irq(gc, offset);
258 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
259}
260
261static void stmpe_dbg_show_one(struct seq_file *s,
262 struct gpio_chip *gc,
263 unsigned offset, unsigned gpio)
264{
265 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
266 struct stmpe *stmpe = stmpe_gpio->stmpe;
267 bool val = !!stmpe_gpio_get(gc, offset);
268 u8 bank = offset / 8;
269 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
270 u8 mask = BIT(offset % 8);
271 int ret;
272 u8 dir;
273
274 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
275 if (IS_ERR(label))
276 return;
277
278 ret = stmpe_reg_read(stmpe, dir_reg);
279 if (ret < 0)
280 return;
281 dir = !!(ret & mask);
282
283 if (dir) {
284 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
285 gpio, label ?: "(none)",
286 val ? "hi" : "lo");
287 } else {
288 u8 edge_det_reg;
289 u8 rise_reg;
290 u8 fall_reg;
291 u8 irqen_reg;
292
293 static const char * const edge_det_values[] = {
294 "edge-inactive",
295 "edge-asserted",
296 "not-supported"
297 };
298 static const char * const rise_values[] = {
299 "no-rising-edge-detection",
300 "rising-edge-detection",
301 "not-supported"
302 };
303 static const char * const fall_values[] = {
304 "no-falling-edge-detection",
305 "falling-edge-detection",
306 "not-supported"
307 };
308 #define NOT_SUPPORTED_IDX 2
309 u8 edge_det = NOT_SUPPORTED_IDX;
310 u8 rise = NOT_SUPPORTED_IDX;
311 u8 fall = NOT_SUPPORTED_IDX;
312 bool irqen;
313
314 switch (stmpe->partnum) {
315 case STMPE610:
316 case STMPE811:
317 case STMPE1601:
318 case STMPE2401:
319 case STMPE2403:
320 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
321 ret = stmpe_reg_read(stmpe, edge_det_reg);
322 if (ret < 0)
323 return;
324 edge_det = !!(ret & mask);
325 fallthrough;
326 case STMPE1801:
327 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
328 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
329
330 ret = stmpe_reg_read(stmpe, rise_reg);
331 if (ret < 0)
332 return;
333 rise = !!(ret & mask);
334 ret = stmpe_reg_read(stmpe, fall_reg);
335 if (ret < 0)
336 return;
337 fall = !!(ret & mask);
338 fallthrough;
339 case STMPE801:
340 case STMPE1600:
341 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
342 break;
343
344 default:
345 return;
346 }
347
348 ret = stmpe_reg_read(stmpe, irqen_reg);
349 if (ret < 0)
350 return;
351 irqen = !!(ret & mask);
352
353 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
354 gpio, label ?: "(none)",
355 val ? "hi" : "lo",
356 edge_det_values[edge_det],
357 irqen ? "IRQ-enabled" : "IRQ-disabled",
358 rise_values[rise],
359 fall_values[fall]);
360 }
361}
362
363static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
364{
365 unsigned i;
366 unsigned gpio = gc->base;
367
368 for (i = 0; i < gc->ngpio; i++, gpio++) {
369 stmpe_dbg_show_one(s, gc, i, gpio);
370 seq_putc(s, '\n');
371 }
372}
373
374static const struct irq_chip stmpe_gpio_irq_chip = {
375 .name = "stmpe-gpio",
376 .irq_bus_lock = stmpe_gpio_irq_lock,
377 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
378 .irq_mask = stmpe_gpio_irq_mask,
379 .irq_unmask = stmpe_gpio_irq_unmask,
380 .irq_set_type = stmpe_gpio_irq_set_type,
381 .flags = IRQCHIP_IMMUTABLE,
382 GPIOCHIP_IRQ_RESOURCE_HELPERS,
383};
384
385#define MAX_GPIOS 24
386
387static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
388{
389 struct stmpe_gpio *stmpe_gpio = dev;
390 struct stmpe *stmpe = stmpe_gpio->stmpe;
391 u8 statmsbreg;
392 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
393 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
394 int ret;
395 int i;
396
397 /*
398 * the stmpe_block_read() call below, imposes to set statmsbreg
399 * with the register located at the lowest address. As STMPE1600
400 * variant is the only one which respect registers address's order
401 * (LSB regs located at lowest address than MSB ones) whereas all
402 * the others have a registers layout with MSB located before the
403 * LSB regs.
404 */
405 if (stmpe->partnum == STMPE1600)
406 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
407 else
408 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
409
410 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
411 if (ret < 0)
412 return IRQ_NONE;
413
414 for (i = 0; i < num_banks; i++) {
415 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
416 num_banks - i - 1;
417 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
418 unsigned int stat = status[i];
419
420 stat &= enabled;
421 if (!stat)
422 continue;
423
424 while (stat) {
425 int bit = __ffs(stat);
426 int line = bank * 8 + bit;
427 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
428 line);
429
430 handle_nested_irq(child_irq);
431 stat &= ~BIT(bit);
432 }
433
434 /*
435 * interrupt status register write has no effect on
436 * 801/1801/1600, bits are cleared when read.
437 * Edge detect register is not present on 801/1600/1801
438 */
439 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
440 stmpe->partnum != STMPE1801) {
441 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
442 stmpe_reg_write(stmpe,
443 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
444 status[i]);
445 }
446 }
447
448 return IRQ_HANDLED;
449}
450
451static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
452 unsigned long *valid_mask,
453 unsigned int ngpios)
454{
455 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
456 int i;
457
458 if (!stmpe_gpio->norequest_mask)
459 return;
460
461 /* Forbid unused lines to be mapped as IRQs */
462 for (i = 0; i < sizeof(u32); i++) {
463 if (stmpe_gpio->norequest_mask & BIT(i))
464 clear_bit(i, valid_mask);
465 }
466}
467
468static void stmpe_gpio_disable(void *stmpe)
469{
470 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
471}
472
473static int stmpe_gpio_probe(struct platform_device *pdev)
474{
475 struct device *dev = &pdev->dev;
476 struct stmpe *stmpe = dev_get_drvdata(dev->parent);
477 struct stmpe_gpio *stmpe_gpio;
478 int ret, irq;
479
480 if (stmpe->num_gpios > MAX_GPIOS) {
481 dev_err(dev, "Need to increase maximum GPIO number\n");
482 return -EINVAL;
483 }
484
485 stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
486 if (!stmpe_gpio)
487 return -ENOMEM;
488
489 mutex_init(&stmpe_gpio->irq_lock);
490
491 stmpe_gpio->stmpe = stmpe;
492 stmpe_gpio->chip = template_chip;
493 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
494 stmpe_gpio->chip.parent = dev;
495 stmpe_gpio->chip.base = -1;
496
497 if (IS_ENABLED(CONFIG_DEBUG_FS))
498 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
499
500 device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
501
502 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
503 if (ret)
504 return ret;
505
506 ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
507 if (ret)
508 return ret;
509
510 irq = platform_get_irq(pdev, 0);
511 if (irq > 0) {
512 struct gpio_irq_chip *girq;
513
514 ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
515 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
516 if (ret)
517 return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
518
519 girq = &stmpe_gpio->chip.irq;
520 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
521 /* This will let us handle the parent IRQ in the driver */
522 girq->parent_handler = NULL;
523 girq->num_parents = 0;
524 girq->parents = NULL;
525 girq->default_type = IRQ_TYPE_NONE;
526 girq->handler = handle_simple_irq;
527 girq->threaded = true;
528 girq->init_valid_mask = stmpe_init_irq_valid_mask;
529 }
530
531 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
532}
533
534static struct platform_driver stmpe_gpio_driver = {
535 .driver = {
536 .suppress_bind_attrs = true,
537 .name = "stmpe-gpio",
538 },
539 .probe = stmpe_gpio_probe,
540};
541
542static int __init stmpe_gpio_init(void)
543{
544 return platform_driver_register(&stmpe_gpio_driver);
545}
546subsys_initcall(stmpe_gpio_init);