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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
25
26struct stmpe_gpio {
27 struct gpio_chip chip;
28 struct stmpe *stmpe;
29 struct device *dev;
30 struct mutex irq_lock;
31
32 int irq_base;
33 unsigned norequest_mask;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct stmpe_gpio, chip);
43}
44
45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
48 struct stmpe *stmpe = stmpe_gpio->stmpe;
49 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = stmpe_reg_read(stmpe, reg);
54 if (ret < 0)
55 return ret;
56
57 return ret & mask;
58}
59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
63 struct stmpe *stmpe = stmpe_gpio->stmpe;
64 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8);
67
68 stmpe_reg_write(stmpe, reg, mask);
69}
70
71static int stmpe_gpio_direction_output(struct gpio_chip *chip,
72 unsigned offset, int val)
73{
74 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
75 struct stmpe *stmpe = stmpe_gpio->stmpe;
76 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
77 u8 mask = 1 << (offset % 8);
78
79 stmpe_gpio_set(chip, offset, val);
80
81 return stmpe_set_bits(stmpe, reg, mask, mask);
82}
83
84static int stmpe_gpio_direction_input(struct gpio_chip *chip,
85 unsigned offset)
86{
87 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
88 struct stmpe *stmpe = stmpe_gpio->stmpe;
89 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
90 u8 mask = 1 << (offset % 8);
91
92 return stmpe_set_bits(stmpe, reg, mask, 0);
93}
94
95static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96{
97 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98
99 return stmpe_gpio->irq_base + offset;
100}
101
102static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
103{
104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105 struct stmpe *stmpe = stmpe_gpio->stmpe;
106
107 if (stmpe_gpio->norequest_mask & (1 << offset))
108 return -EINVAL;
109
110 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
111}
112
113static struct gpio_chip template_chip = {
114 .label = "stmpe",
115 .owner = THIS_MODULE,
116 .direction_input = stmpe_gpio_direction_input,
117 .get = stmpe_gpio_get,
118 .direction_output = stmpe_gpio_direction_output,
119 .set = stmpe_gpio_set,
120 .to_irq = stmpe_gpio_to_irq,
121 .request = stmpe_gpio_request,
122 .can_sleep = 1,
123};
124
125static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
126{
127 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
128 int offset = d->irq - stmpe_gpio->irq_base;
129 int regoffset = offset / 8;
130 int mask = 1 << (offset % 8);
131
132 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
133 return -EINVAL;
134
135 if (type == IRQ_TYPE_EDGE_RISING)
136 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
137 else
138 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
139
140 if (type == IRQ_TYPE_EDGE_FALLING)
141 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
142 else
143 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
144
145 return 0;
146}
147
148static void stmpe_gpio_irq_lock(struct irq_data *d)
149{
150 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
151
152 mutex_lock(&stmpe_gpio->irq_lock);
153}
154
155static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
156{
157 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;
166
167 for (i = 0; i < CACHE_NR_REGS; i++) {
168 for (j = 0; j < num_banks; j++) {
169 u8 old = stmpe_gpio->oldregs[i][j];
170 u8 new = stmpe_gpio->regs[i][j];
171
172 if (new == old)
173 continue;
174
175 stmpe_gpio->oldregs[i][j] = new;
176 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
177 }
178 }
179
180 mutex_unlock(&stmpe_gpio->irq_lock);
181}
182
183static void stmpe_gpio_irq_mask(struct irq_data *d)
184{
185 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
186 int offset = d->irq - stmpe_gpio->irq_base;
187 int regoffset = offset / 8;
188 int mask = 1 << (offset % 8);
189
190 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
191}
192
193static void stmpe_gpio_irq_unmask(struct irq_data *d)
194{
195 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
196 int offset = d->irq - stmpe_gpio->irq_base;
197 int regoffset = offset / 8;
198 int mask = 1 << (offset % 8);
199
200 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
201}
202
203static struct irq_chip stmpe_gpio_irq_chip = {
204 .name = "stmpe-gpio",
205 .irq_bus_lock = stmpe_gpio_irq_lock,
206 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
207 .irq_mask = stmpe_gpio_irq_mask,
208 .irq_unmask = stmpe_gpio_irq_unmask,
209 .irq_set_type = stmpe_gpio_irq_set_type,
210};
211
212static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
213{
214 struct stmpe_gpio *stmpe_gpio = dev;
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 u8 status[num_banks];
219 int ret;
220 int i;
221
222 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
223 if (ret < 0)
224 return IRQ_NONE;
225
226 for (i = 0; i < num_banks; i++) {
227 int bank = num_banks - i - 1;
228 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
229 unsigned int stat = status[i];
230
231 stat &= enabled;
232 if (!stat)
233 continue;
234
235 while (stat) {
236 int bit = __ffs(stat);
237 int line = bank * 8 + bit;
238
239 handle_nested_irq(stmpe_gpio->irq_base + line);
240 stat &= ~(1 << bit);
241 }
242
243 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
244 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
245 status[i]);
246 }
247
248 return IRQ_HANDLED;
249}
250
251static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
252{
253 int base = stmpe_gpio->irq_base;
254 int irq;
255
256 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
257 irq_set_chip_data(irq, stmpe_gpio);
258 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
259 handle_simple_irq);
260 irq_set_nested_thread(irq, 1);
261#ifdef CONFIG_ARM
262 set_irq_flags(irq, IRQF_VALID);
263#else
264 irq_set_noprobe(irq);
265#endif
266 }
267
268 return 0;
269}
270
271static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
272{
273 int base = stmpe_gpio->irq_base;
274 int irq;
275
276 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
277#ifdef CONFIG_ARM
278 set_irq_flags(irq, 0);
279#endif
280 irq_set_chip_and_handler(irq, NULL, NULL);
281 irq_set_chip_data(irq, NULL);
282 }
283}
284
285static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
286{
287 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
288 struct stmpe_gpio_platform_data *pdata;
289 struct stmpe_gpio *stmpe_gpio;
290 int ret;
291 int irq;
292
293 pdata = stmpe->pdata->gpio;
294
295 irq = platform_get_irq(pdev, 0);
296 if (irq < 0)
297 return irq;
298
299 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
300 if (!stmpe_gpio)
301 return -ENOMEM;
302
303 mutex_init(&stmpe_gpio->irq_lock);
304
305 stmpe_gpio->dev = &pdev->dev;
306 stmpe_gpio->stmpe = stmpe;
307 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
308
309 stmpe_gpio->chip = template_chip;
310 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
311 stmpe_gpio->chip.dev = &pdev->dev;
312 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
313
314 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
315
316 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
317 if (ret)
318 goto out_free;
319
320 ret = stmpe_gpio_irq_init(stmpe_gpio);
321 if (ret)
322 goto out_disable;
323
324 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
325 "stmpe-gpio", stmpe_gpio);
326 if (ret) {
327 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
328 goto out_removeirq;
329 }
330
331 ret = gpiochip_add(&stmpe_gpio->chip);
332 if (ret) {
333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
334 goto out_freeirq;
335 }
336
337 if (pdata && pdata->setup)
338 pdata->setup(stmpe, stmpe_gpio->chip.base);
339
340 platform_set_drvdata(pdev, stmpe_gpio);
341
342 return 0;
343
344out_freeirq:
345 free_irq(irq, stmpe_gpio);
346out_removeirq:
347 stmpe_gpio_irq_remove(stmpe_gpio);
348out_disable:
349 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
350out_free:
351 kfree(stmpe_gpio);
352 return ret;
353}
354
355static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
356{
357 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
358 struct stmpe *stmpe = stmpe_gpio->stmpe;
359 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
360 int irq = platform_get_irq(pdev, 0);
361 int ret;
362
363 if (pdata && pdata->remove)
364 pdata->remove(stmpe, stmpe_gpio->chip.base);
365
366 ret = gpiochip_remove(&stmpe_gpio->chip);
367 if (ret < 0) {
368 dev_err(stmpe_gpio->dev,
369 "unable to remove gpiochip: %d\n", ret);
370 return ret;
371 }
372
373 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
374
375 free_irq(irq, stmpe_gpio);
376 stmpe_gpio_irq_remove(stmpe_gpio);
377 platform_set_drvdata(pdev, NULL);
378 kfree(stmpe_gpio);
379
380 return 0;
381}
382
383static struct platform_driver stmpe_gpio_driver = {
384 .driver.name = "stmpe-gpio",
385 .driver.owner = THIS_MODULE,
386 .probe = stmpe_gpio_probe,
387 .remove = __devexit_p(stmpe_gpio_remove),
388};
389
390static int __init stmpe_gpio_init(void)
391{
392 return platform_driver_register(&stmpe_gpio_driver);
393}
394subsys_initcall(stmpe_gpio_init);
395
396static void __exit stmpe_gpio_exit(void)
397{
398 platform_driver_unregister(&stmpe_gpio_driver);
399}
400module_exit(stmpe_gpio_exit);
401
402MODULE_LICENSE("GPL v2");
403MODULE_DESCRIPTION("STMPExxxx GPIO driver");
404MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/interrupt.h>
16#include <linux/of.h>
17#include <linux/mfd/stmpe.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25#define CACHE_NR_REGS 3
26#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
27
28struct stmpe_gpio {
29 struct gpio_chip chip;
30 struct stmpe *stmpe;
31 struct device *dev;
32 struct mutex irq_lock;
33 struct irq_domain *domain;
34
35 int irq_base;
36 unsigned norequest_mask;
37
38 /* Caches of interrupt control registers for bus_lock */
39 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
40 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
41};
42
43static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
44{
45 return container_of(chip, struct stmpe_gpio, chip);
46}
47
48static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
49{
50 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
51 struct stmpe *stmpe = stmpe_gpio->stmpe;
52 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
53 u8 mask = 1 << (offset % 8);
54 int ret;
55
56 ret = stmpe_reg_read(stmpe, reg);
57 if (ret < 0)
58 return ret;
59
60 return !!(ret & mask);
61}
62
63static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
64{
65 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
66 struct stmpe *stmpe = stmpe_gpio->stmpe;
67 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
68 u8 reg = stmpe->regs[which] - (offset / 8);
69 u8 mask = 1 << (offset % 8);
70
71 /*
72 * Some variants have single register for gpio set/clear functionality.
73 * For them we need to write 0 to clear and 1 to set.
74 */
75 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
76 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
77 else
78 stmpe_reg_write(stmpe, reg, mask);
79}
80
81static int stmpe_gpio_direction_output(struct gpio_chip *chip,
82 unsigned offset, int val)
83{
84 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
85 struct stmpe *stmpe = stmpe_gpio->stmpe;
86 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
87 u8 mask = 1 << (offset % 8);
88
89 stmpe_gpio_set(chip, offset, val);
90
91 return stmpe_set_bits(stmpe, reg, mask, mask);
92}
93
94static int stmpe_gpio_direction_input(struct gpio_chip *chip,
95 unsigned offset)
96{
97 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98 struct stmpe *stmpe = stmpe_gpio->stmpe;
99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
100 u8 mask = 1 << (offset % 8);
101
102 return stmpe_set_bits(stmpe, reg, mask, 0);
103}
104
105static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
106{
107 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
108
109 return irq_create_mapping(stmpe_gpio->domain, offset);
110}
111
112static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
113{
114 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
115 struct stmpe *stmpe = stmpe_gpio->stmpe;
116
117 if (stmpe_gpio->norequest_mask & (1 << offset))
118 return -EINVAL;
119
120 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
121}
122
123static struct gpio_chip template_chip = {
124 .label = "stmpe",
125 .owner = THIS_MODULE,
126 .direction_input = stmpe_gpio_direction_input,
127 .get = stmpe_gpio_get,
128 .direction_output = stmpe_gpio_direction_output,
129 .set = stmpe_gpio_set,
130 .to_irq = stmpe_gpio_to_irq,
131 .request = stmpe_gpio_request,
132 .can_sleep = true,
133};
134
135static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
136{
137 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
138 int offset = d->hwirq;
139 int regoffset = offset / 8;
140 int mask = 1 << (offset % 8);
141
142 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
143 return -EINVAL;
144
145 /* STMPE801 doesn't have RE and FE registers */
146 if (stmpe_gpio->stmpe->partnum == STMPE801)
147 return 0;
148
149 if (type == IRQ_TYPE_EDGE_RISING)
150 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
151 else
152 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
153
154 if (type == IRQ_TYPE_EDGE_FALLING)
155 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
156 else
157 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
158
159 return 0;
160}
161
162static void stmpe_gpio_irq_lock(struct irq_data *d)
163{
164 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
165
166 mutex_lock(&stmpe_gpio->irq_lock);
167}
168
169static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
170{
171 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
172 struct stmpe *stmpe = stmpe_gpio->stmpe;
173 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
174 static const u8 regmap[] = {
175 [REG_RE] = STMPE_IDX_GPRER_LSB,
176 [REG_FE] = STMPE_IDX_GPFER_LSB,
177 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
178 };
179 int i, j;
180
181 for (i = 0; i < CACHE_NR_REGS; i++) {
182 /* STMPE801 doesn't have RE and FE registers */
183 if ((stmpe->partnum == STMPE801) &&
184 (i != REG_IE))
185 continue;
186
187 for (j = 0; j < num_banks; j++) {
188 u8 old = stmpe_gpio->oldregs[i][j];
189 u8 new = stmpe_gpio->regs[i][j];
190
191 if (new == old)
192 continue;
193
194 stmpe_gpio->oldregs[i][j] = new;
195 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
196 }
197 }
198
199 mutex_unlock(&stmpe_gpio->irq_lock);
200}
201
202static void stmpe_gpio_irq_mask(struct irq_data *d)
203{
204 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
205 int offset = d->hwirq;
206 int regoffset = offset / 8;
207 int mask = 1 << (offset % 8);
208
209 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
210}
211
212static void stmpe_gpio_irq_unmask(struct irq_data *d)
213{
214 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
215 int offset = d->hwirq;
216 int regoffset = offset / 8;
217 int mask = 1 << (offset % 8);
218
219 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
220}
221
222static struct irq_chip stmpe_gpio_irq_chip = {
223 .name = "stmpe-gpio",
224 .irq_bus_lock = stmpe_gpio_irq_lock,
225 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
226 .irq_mask = stmpe_gpio_irq_mask,
227 .irq_unmask = stmpe_gpio_irq_unmask,
228 .irq_set_type = stmpe_gpio_irq_set_type,
229};
230
231static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
232{
233 struct stmpe_gpio *stmpe_gpio = dev;
234 struct stmpe *stmpe = stmpe_gpio->stmpe;
235 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
236 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
237 u8 status[num_banks];
238 int ret;
239 int i;
240
241 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
242 if (ret < 0)
243 return IRQ_NONE;
244
245 for (i = 0; i < num_banks; i++) {
246 int bank = num_banks - i - 1;
247 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
248 unsigned int stat = status[i];
249
250 stat &= enabled;
251 if (!stat)
252 continue;
253
254 while (stat) {
255 int bit = __ffs(stat);
256 int line = bank * 8 + bit;
257 int child_irq = irq_find_mapping(stmpe_gpio->domain,
258 line);
259
260 handle_nested_irq(child_irq);
261 stat &= ~(1 << bit);
262 }
263
264 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
265
266 /* Edge detect register is not present on 801 */
267 if (stmpe->partnum != STMPE801)
268 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
269 + i, status[i]);
270 }
271
272 return IRQ_HANDLED;
273}
274
275static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
276 irq_hw_number_t hwirq)
277{
278 struct stmpe_gpio *stmpe_gpio = d->host_data;
279
280 if (!stmpe_gpio)
281 return -EINVAL;
282
283 irq_set_chip_data(irq, stmpe_gpio);
284 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
285 handle_simple_irq);
286 irq_set_nested_thread(irq, 1);
287#ifdef CONFIG_ARM
288 set_irq_flags(irq, IRQF_VALID);
289#else
290 irq_set_noprobe(irq);
291#endif
292
293 return 0;
294}
295
296static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
297{
298#ifdef CONFIG_ARM
299 set_irq_flags(irq, 0);
300#endif
301 irq_set_chip_and_handler(irq, NULL, NULL);
302 irq_set_chip_data(irq, NULL);
303}
304
305static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
306 .unmap = stmpe_gpio_irq_unmap,
307 .map = stmpe_gpio_irq_map,
308 .xlate = irq_domain_xlate_twocell,
309};
310
311static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
312 struct device_node *np)
313{
314 int base = 0;
315
316 if (!np)
317 base = stmpe_gpio->irq_base;
318
319 stmpe_gpio->domain = irq_domain_add_simple(np,
320 stmpe_gpio->chip.ngpio, base,
321 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
322 if (!stmpe_gpio->domain) {
323 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
324 return -ENOSYS;
325 }
326
327 return 0;
328}
329
330static int stmpe_gpio_probe(struct platform_device *pdev)
331{
332 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
333 struct device_node *np = pdev->dev.of_node;
334 struct stmpe_gpio_platform_data *pdata;
335 struct stmpe_gpio *stmpe_gpio;
336 int ret;
337 int irq = 0;
338
339 pdata = stmpe->pdata->gpio;
340
341 irq = platform_get_irq(pdev, 0);
342
343 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
344 if (!stmpe_gpio)
345 return -ENOMEM;
346
347 mutex_init(&stmpe_gpio->irq_lock);
348
349 stmpe_gpio->dev = &pdev->dev;
350 stmpe_gpio->stmpe = stmpe;
351 stmpe_gpio->chip = template_chip;
352 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
353 stmpe_gpio->chip.dev = &pdev->dev;
354#ifdef CONFIG_OF
355 stmpe_gpio->chip.of_node = np;
356#endif
357 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
358
359 if (pdata)
360 stmpe_gpio->norequest_mask = pdata->norequest_mask;
361 else if (np)
362 of_property_read_u32(np, "st,norequest-mask",
363 &stmpe_gpio->norequest_mask);
364
365 if (irq >= 0)
366 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
367 else
368 dev_info(&pdev->dev,
369 "device configured in no-irq mode; "
370 "irqs are not available\n");
371
372 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
373 if (ret)
374 goto out_free;
375
376 if (irq >= 0) {
377 ret = stmpe_gpio_irq_init(stmpe_gpio, np);
378 if (ret)
379 goto out_disable;
380
381 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
382 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
383 if (ret) {
384 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
385 goto out_disable;
386 }
387 }
388
389 ret = gpiochip_add(&stmpe_gpio->chip);
390 if (ret) {
391 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
392 goto out_freeirq;
393 }
394
395 if (pdata && pdata->setup)
396 pdata->setup(stmpe, stmpe_gpio->chip.base);
397
398 platform_set_drvdata(pdev, stmpe_gpio);
399
400 return 0;
401
402out_freeirq:
403 if (irq >= 0)
404 free_irq(irq, stmpe_gpio);
405out_disable:
406 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
407out_free:
408 kfree(stmpe_gpio);
409 return ret;
410}
411
412static int stmpe_gpio_remove(struct platform_device *pdev)
413{
414 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
415 struct stmpe *stmpe = stmpe_gpio->stmpe;
416 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
417 int irq = platform_get_irq(pdev, 0);
418 int ret;
419
420 if (pdata && pdata->remove)
421 pdata->remove(stmpe, stmpe_gpio->chip.base);
422
423 ret = gpiochip_remove(&stmpe_gpio->chip);
424 if (ret < 0) {
425 dev_err(stmpe_gpio->dev,
426 "unable to remove gpiochip: %d\n", ret);
427 return ret;
428 }
429
430 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
431
432 if (irq >= 0)
433 free_irq(irq, stmpe_gpio);
434
435 kfree(stmpe_gpio);
436
437 return 0;
438}
439
440static struct platform_driver stmpe_gpio_driver = {
441 .driver.name = "stmpe-gpio",
442 .driver.owner = THIS_MODULE,
443 .probe = stmpe_gpio_probe,
444 .remove = stmpe_gpio_remove,
445};
446
447static int __init stmpe_gpio_init(void)
448{
449 return platform_driver_register(&stmpe_gpio_driver);
450}
451subsys_initcall(stmpe_gpio_init);
452
453static void __exit stmpe_gpio_exit(void)
454{
455 platform_driver_unregister(&stmpe_gpio_driver);
456}
457module_exit(stmpe_gpio_exit);
458
459MODULE_LICENSE("GPL v2");
460MODULE_DESCRIPTION("STMPExxxx GPIO driver");
461MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");