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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
25
26struct stmpe_gpio {
27 struct gpio_chip chip;
28 struct stmpe *stmpe;
29 struct device *dev;
30 struct mutex irq_lock;
31
32 int irq_base;
33 unsigned norequest_mask;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct stmpe_gpio, chip);
43}
44
45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
48 struct stmpe *stmpe = stmpe_gpio->stmpe;
49 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = stmpe_reg_read(stmpe, reg);
54 if (ret < 0)
55 return ret;
56
57 return ret & mask;
58}
59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
63 struct stmpe *stmpe = stmpe_gpio->stmpe;
64 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8);
67
68 stmpe_reg_write(stmpe, reg, mask);
69}
70
71static int stmpe_gpio_direction_output(struct gpio_chip *chip,
72 unsigned offset, int val)
73{
74 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
75 struct stmpe *stmpe = stmpe_gpio->stmpe;
76 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
77 u8 mask = 1 << (offset % 8);
78
79 stmpe_gpio_set(chip, offset, val);
80
81 return stmpe_set_bits(stmpe, reg, mask, mask);
82}
83
84static int stmpe_gpio_direction_input(struct gpio_chip *chip,
85 unsigned offset)
86{
87 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
88 struct stmpe *stmpe = stmpe_gpio->stmpe;
89 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
90 u8 mask = 1 << (offset % 8);
91
92 return stmpe_set_bits(stmpe, reg, mask, 0);
93}
94
95static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
96{
97 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98
99 return stmpe_gpio->irq_base + offset;
100}
101
102static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
103{
104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105 struct stmpe *stmpe = stmpe_gpio->stmpe;
106
107 if (stmpe_gpio->norequest_mask & (1 << offset))
108 return -EINVAL;
109
110 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
111}
112
113static struct gpio_chip template_chip = {
114 .label = "stmpe",
115 .owner = THIS_MODULE,
116 .direction_input = stmpe_gpio_direction_input,
117 .get = stmpe_gpio_get,
118 .direction_output = stmpe_gpio_direction_output,
119 .set = stmpe_gpio_set,
120 .to_irq = stmpe_gpio_to_irq,
121 .request = stmpe_gpio_request,
122 .can_sleep = 1,
123};
124
125static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
126{
127 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
128 int offset = d->irq - stmpe_gpio->irq_base;
129 int regoffset = offset / 8;
130 int mask = 1 << (offset % 8);
131
132 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
133 return -EINVAL;
134
135 if (type == IRQ_TYPE_EDGE_RISING)
136 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
137 else
138 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
139
140 if (type == IRQ_TYPE_EDGE_FALLING)
141 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
142 else
143 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
144
145 return 0;
146}
147
148static void stmpe_gpio_irq_lock(struct irq_data *d)
149{
150 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
151
152 mutex_lock(&stmpe_gpio->irq_lock);
153}
154
155static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
156{
157 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;
166
167 for (i = 0; i < CACHE_NR_REGS; i++) {
168 for (j = 0; j < num_banks; j++) {
169 u8 old = stmpe_gpio->oldregs[i][j];
170 u8 new = stmpe_gpio->regs[i][j];
171
172 if (new == old)
173 continue;
174
175 stmpe_gpio->oldregs[i][j] = new;
176 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
177 }
178 }
179
180 mutex_unlock(&stmpe_gpio->irq_lock);
181}
182
183static void stmpe_gpio_irq_mask(struct irq_data *d)
184{
185 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
186 int offset = d->irq - stmpe_gpio->irq_base;
187 int regoffset = offset / 8;
188 int mask = 1 << (offset % 8);
189
190 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
191}
192
193static void stmpe_gpio_irq_unmask(struct irq_data *d)
194{
195 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
196 int offset = d->irq - stmpe_gpio->irq_base;
197 int regoffset = offset / 8;
198 int mask = 1 << (offset % 8);
199
200 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
201}
202
203static struct irq_chip stmpe_gpio_irq_chip = {
204 .name = "stmpe-gpio",
205 .irq_bus_lock = stmpe_gpio_irq_lock,
206 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
207 .irq_mask = stmpe_gpio_irq_mask,
208 .irq_unmask = stmpe_gpio_irq_unmask,
209 .irq_set_type = stmpe_gpio_irq_set_type,
210};
211
212static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
213{
214 struct stmpe_gpio *stmpe_gpio = dev;
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 u8 status[num_banks];
219 int ret;
220 int i;
221
222 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
223 if (ret < 0)
224 return IRQ_NONE;
225
226 for (i = 0; i < num_banks; i++) {
227 int bank = num_banks - i - 1;
228 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
229 unsigned int stat = status[i];
230
231 stat &= enabled;
232 if (!stat)
233 continue;
234
235 while (stat) {
236 int bit = __ffs(stat);
237 int line = bank * 8 + bit;
238
239 handle_nested_irq(stmpe_gpio->irq_base + line);
240 stat &= ~(1 << bit);
241 }
242
243 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
244 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
245 status[i]);
246 }
247
248 return IRQ_HANDLED;
249}
250
251static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
252{
253 int base = stmpe_gpio->irq_base;
254 int irq;
255
256 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
257 irq_set_chip_data(irq, stmpe_gpio);
258 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
259 handle_simple_irq);
260 irq_set_nested_thread(irq, 1);
261#ifdef CONFIG_ARM
262 set_irq_flags(irq, IRQF_VALID);
263#else
264 irq_set_noprobe(irq);
265#endif
266 }
267
268 return 0;
269}
270
271static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
272{
273 int base = stmpe_gpio->irq_base;
274 int irq;
275
276 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
277#ifdef CONFIG_ARM
278 set_irq_flags(irq, 0);
279#endif
280 irq_set_chip_and_handler(irq, NULL, NULL);
281 irq_set_chip_data(irq, NULL);
282 }
283}
284
285static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
286{
287 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
288 struct stmpe_gpio_platform_data *pdata;
289 struct stmpe_gpio *stmpe_gpio;
290 int ret;
291 int irq;
292
293 pdata = stmpe->pdata->gpio;
294
295 irq = platform_get_irq(pdev, 0);
296 if (irq < 0)
297 return irq;
298
299 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
300 if (!stmpe_gpio)
301 return -ENOMEM;
302
303 mutex_init(&stmpe_gpio->irq_lock);
304
305 stmpe_gpio->dev = &pdev->dev;
306 stmpe_gpio->stmpe = stmpe;
307 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
308
309 stmpe_gpio->chip = template_chip;
310 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
311 stmpe_gpio->chip.dev = &pdev->dev;
312 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
313
314 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
315
316 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
317 if (ret)
318 goto out_free;
319
320 ret = stmpe_gpio_irq_init(stmpe_gpio);
321 if (ret)
322 goto out_disable;
323
324 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
325 "stmpe-gpio", stmpe_gpio);
326 if (ret) {
327 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
328 goto out_removeirq;
329 }
330
331 ret = gpiochip_add(&stmpe_gpio->chip);
332 if (ret) {
333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
334 goto out_freeirq;
335 }
336
337 if (pdata && pdata->setup)
338 pdata->setup(stmpe, stmpe_gpio->chip.base);
339
340 platform_set_drvdata(pdev, stmpe_gpio);
341
342 return 0;
343
344out_freeirq:
345 free_irq(irq, stmpe_gpio);
346out_removeirq:
347 stmpe_gpio_irq_remove(stmpe_gpio);
348out_disable:
349 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
350out_free:
351 kfree(stmpe_gpio);
352 return ret;
353}
354
355static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
356{
357 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
358 struct stmpe *stmpe = stmpe_gpio->stmpe;
359 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
360 int irq = platform_get_irq(pdev, 0);
361 int ret;
362
363 if (pdata && pdata->remove)
364 pdata->remove(stmpe, stmpe_gpio->chip.base);
365
366 ret = gpiochip_remove(&stmpe_gpio->chip);
367 if (ret < 0) {
368 dev_err(stmpe_gpio->dev,
369 "unable to remove gpiochip: %d\n", ret);
370 return ret;
371 }
372
373 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
374
375 free_irq(irq, stmpe_gpio);
376 stmpe_gpio_irq_remove(stmpe_gpio);
377 platform_set_drvdata(pdev, NULL);
378 kfree(stmpe_gpio);
379
380 return 0;
381}
382
383static struct platform_driver stmpe_gpio_driver = {
384 .driver.name = "stmpe-gpio",
385 .driver.owner = THIS_MODULE,
386 .probe = stmpe_gpio_probe,
387 .remove = __devexit_p(stmpe_gpio_remove),
388};
389
390static int __init stmpe_gpio_init(void)
391{
392 return platform_driver_register(&stmpe_gpio_driver);
393}
394subsys_initcall(stmpe_gpio_init);
395
396static void __exit stmpe_gpio_exit(void)
397{
398 platform_driver_unregister(&stmpe_gpio_driver);
399}
400module_exit(stmpe_gpio_exit);
401
402MODULE_LICENSE("GPL v2");
403MODULE_DESCRIPTION("STMPExxxx GPIO driver");
404MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/interrupt.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
25
26struct stmpe_gpio {
27 struct gpio_chip chip;
28 struct stmpe *stmpe;
29 struct device *dev;
30 struct mutex irq_lock;
31
32 int irq_base;
33 unsigned norequest_mask;
34
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct stmpe_gpio, chip);
43}
44
45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
46{
47 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
48 struct stmpe *stmpe = stmpe_gpio->stmpe;
49 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
50 u8 mask = 1 << (offset % 8);
51 int ret;
52
53 ret = stmpe_reg_read(stmpe, reg);
54 if (ret < 0)
55 return ret;
56
57 return !!(ret & mask);
58}
59
60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
61{
62 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
63 struct stmpe *stmpe = stmpe_gpio->stmpe;
64 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
65 u8 reg = stmpe->regs[which] - (offset / 8);
66 u8 mask = 1 << (offset % 8);
67
68 /*
69 * Some variants have single register for gpio set/clear functionality.
70 * For them we need to write 0 to clear and 1 to set.
71 */
72 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
73 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
74 else
75 stmpe_reg_write(stmpe, reg, mask);
76}
77
78static int stmpe_gpio_direction_output(struct gpio_chip *chip,
79 unsigned offset, int val)
80{
81 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
82 struct stmpe *stmpe = stmpe_gpio->stmpe;
83 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
84 u8 mask = 1 << (offset % 8);
85
86 stmpe_gpio_set(chip, offset, val);
87
88 return stmpe_set_bits(stmpe, reg, mask, mask);
89}
90
91static int stmpe_gpio_direction_input(struct gpio_chip *chip,
92 unsigned offset)
93{
94 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
95 struct stmpe *stmpe = stmpe_gpio->stmpe;
96 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
97 u8 mask = 1 << (offset % 8);
98
99 return stmpe_set_bits(stmpe, reg, mask, 0);
100}
101
102static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
103{
104 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105
106 return stmpe_gpio->irq_base + offset;
107}
108
109static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
110{
111 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
112 struct stmpe *stmpe = stmpe_gpio->stmpe;
113
114 if (stmpe_gpio->norequest_mask & (1 << offset))
115 return -EINVAL;
116
117 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
118}
119
120static struct gpio_chip template_chip = {
121 .label = "stmpe",
122 .owner = THIS_MODULE,
123 .direction_input = stmpe_gpio_direction_input,
124 .get = stmpe_gpio_get,
125 .direction_output = stmpe_gpio_direction_output,
126 .set = stmpe_gpio_set,
127 .to_irq = stmpe_gpio_to_irq,
128 .request = stmpe_gpio_request,
129 .can_sleep = 1,
130};
131
132static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
133{
134 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
135 int offset = d->irq - stmpe_gpio->irq_base;
136 int regoffset = offset / 8;
137 int mask = 1 << (offset % 8);
138
139 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
140 return -EINVAL;
141
142 /* STMPE801 doesn't have RE and FE registers */
143 if (stmpe_gpio->stmpe->partnum == STMPE801)
144 return 0;
145
146 if (type == IRQ_TYPE_EDGE_RISING)
147 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
148 else
149 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
150
151 if (type == IRQ_TYPE_EDGE_FALLING)
152 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
153 else
154 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
155
156 return 0;
157}
158
159static void stmpe_gpio_irq_lock(struct irq_data *d)
160{
161 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
162
163 mutex_lock(&stmpe_gpio->irq_lock);
164}
165
166static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
167{
168 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
169 struct stmpe *stmpe = stmpe_gpio->stmpe;
170 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
171 static const u8 regmap[] = {
172 [REG_RE] = STMPE_IDX_GPRER_LSB,
173 [REG_FE] = STMPE_IDX_GPFER_LSB,
174 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
175 };
176 int i, j;
177
178 for (i = 0; i < CACHE_NR_REGS; i++) {
179 /* STMPE801 doesn't have RE and FE registers */
180 if ((stmpe->partnum == STMPE801) &&
181 (i != REG_IE))
182 continue;
183
184 for (j = 0; j < num_banks; j++) {
185 u8 old = stmpe_gpio->oldregs[i][j];
186 u8 new = stmpe_gpio->regs[i][j];
187
188 if (new == old)
189 continue;
190
191 stmpe_gpio->oldregs[i][j] = new;
192 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
193 }
194 }
195
196 mutex_unlock(&stmpe_gpio->irq_lock);
197}
198
199static void stmpe_gpio_irq_mask(struct irq_data *d)
200{
201 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
202 int offset = d->irq - stmpe_gpio->irq_base;
203 int regoffset = offset / 8;
204 int mask = 1 << (offset % 8);
205
206 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
207}
208
209static void stmpe_gpio_irq_unmask(struct irq_data *d)
210{
211 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
212 int offset = d->irq - stmpe_gpio->irq_base;
213 int regoffset = offset / 8;
214 int mask = 1 << (offset % 8);
215
216 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
217}
218
219static struct irq_chip stmpe_gpio_irq_chip = {
220 .name = "stmpe-gpio",
221 .irq_bus_lock = stmpe_gpio_irq_lock,
222 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
223 .irq_mask = stmpe_gpio_irq_mask,
224 .irq_unmask = stmpe_gpio_irq_unmask,
225 .irq_set_type = stmpe_gpio_irq_set_type,
226};
227
228static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
229{
230 struct stmpe_gpio *stmpe_gpio = dev;
231 struct stmpe *stmpe = stmpe_gpio->stmpe;
232 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
233 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
234 u8 status[num_banks];
235 int ret;
236 int i;
237
238 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
239 if (ret < 0)
240 return IRQ_NONE;
241
242 for (i = 0; i < num_banks; i++) {
243 int bank = num_banks - i - 1;
244 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
245 unsigned int stat = status[i];
246
247 stat &= enabled;
248 if (!stat)
249 continue;
250
251 while (stat) {
252 int bit = __ffs(stat);
253 int line = bank * 8 + bit;
254
255 handle_nested_irq(stmpe_gpio->irq_base + line);
256 stat &= ~(1 << bit);
257 }
258
259 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
260
261 /* Edge detect register is not present on 801 */
262 if (stmpe->partnum != STMPE801)
263 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
264 + i, status[i]);
265 }
266
267 return IRQ_HANDLED;
268}
269
270static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
271{
272 int base = stmpe_gpio->irq_base;
273 int irq;
274
275 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
276 irq_set_chip_data(irq, stmpe_gpio);
277 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
278 handle_simple_irq);
279 irq_set_nested_thread(irq, 1);
280#ifdef CONFIG_ARM
281 set_irq_flags(irq, IRQF_VALID);
282#else
283 irq_set_noprobe(irq);
284#endif
285 }
286
287 return 0;
288}
289
290static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
291{
292 int base = stmpe_gpio->irq_base;
293 int irq;
294
295 for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
296#ifdef CONFIG_ARM
297 set_irq_flags(irq, 0);
298#endif
299 irq_set_chip_and_handler(irq, NULL, NULL);
300 irq_set_chip_data(irq, NULL);
301 }
302}
303
304static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
305{
306 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
307 struct stmpe_gpio_platform_data *pdata;
308 struct stmpe_gpio *stmpe_gpio;
309 int ret;
310 int irq = 0;
311
312 pdata = stmpe->pdata->gpio;
313
314 irq = platform_get_irq(pdev, 0);
315
316 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
317 if (!stmpe_gpio)
318 return -ENOMEM;
319
320 mutex_init(&stmpe_gpio->irq_lock);
321
322 stmpe_gpio->dev = &pdev->dev;
323 stmpe_gpio->stmpe = stmpe;
324 stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
325
326 stmpe_gpio->chip = template_chip;
327 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
328 stmpe_gpio->chip.dev = &pdev->dev;
329 stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
330
331 if (irq >= 0)
332 stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
333 else
334 dev_info(&pdev->dev,
335 "device configured in no-irq mode; "
336 "irqs are not available\n");
337
338 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
339 if (ret)
340 goto out_free;
341
342 if (irq >= 0) {
343 ret = stmpe_gpio_irq_init(stmpe_gpio);
344 if (ret)
345 goto out_disable;
346
347 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
348 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
349 if (ret) {
350 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
351 goto out_removeirq;
352 }
353 }
354
355 ret = gpiochip_add(&stmpe_gpio->chip);
356 if (ret) {
357 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
358 goto out_freeirq;
359 }
360
361 if (pdata && pdata->setup)
362 pdata->setup(stmpe, stmpe_gpio->chip.base);
363
364 platform_set_drvdata(pdev, stmpe_gpio);
365
366 return 0;
367
368out_freeirq:
369 if (irq >= 0)
370 free_irq(irq, stmpe_gpio);
371out_removeirq:
372 if (irq >= 0)
373 stmpe_gpio_irq_remove(stmpe_gpio);
374out_disable:
375 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
376out_free:
377 kfree(stmpe_gpio);
378 return ret;
379}
380
381static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
382{
383 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
384 struct stmpe *stmpe = stmpe_gpio->stmpe;
385 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
386 int irq = platform_get_irq(pdev, 0);
387 int ret;
388
389 if (pdata && pdata->remove)
390 pdata->remove(stmpe, stmpe_gpio->chip.base);
391
392 ret = gpiochip_remove(&stmpe_gpio->chip);
393 if (ret < 0) {
394 dev_err(stmpe_gpio->dev,
395 "unable to remove gpiochip: %d\n", ret);
396 return ret;
397 }
398
399 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
400
401 if (irq >= 0) {
402 free_irq(irq, stmpe_gpio);
403 stmpe_gpio_irq_remove(stmpe_gpio);
404 }
405 platform_set_drvdata(pdev, NULL);
406 kfree(stmpe_gpio);
407
408 return 0;
409}
410
411static struct platform_driver stmpe_gpio_driver = {
412 .driver.name = "stmpe-gpio",
413 .driver.owner = THIS_MODULE,
414 .probe = stmpe_gpio_probe,
415 .remove = __devexit_p(stmpe_gpio_remove),
416};
417
418static int __init stmpe_gpio_init(void)
419{
420 return platform_driver_register(&stmpe_gpio_driver);
421}
422subsys_initcall(stmpe_gpio_init);
423
424static void __exit stmpe_gpio_exit(void)
425{
426 platform_driver_unregister(&stmpe_gpio_driver);
427}
428module_exit(stmpe_gpio_exit);
429
430MODULE_LICENSE("GPL v2");
431MODULE_DESCRIPTION("STMPExxxx GPIO driver");
432MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");