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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 */
5
6/**
7 * DOC: VC4 DSI0/DSI1 module
8 *
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
11 * controller.
12 *
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
15 *
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
18 * hopefully present.
19 */
20
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23#include <linux/completion.h>
24#include <linux/component.h>
25#include <linux/dma-mapping.h>
26#include <linux/dmaengine.h>
27#include <linux/i2c.h>
28#include <linux/io.h>
29#include <linux/of_address.h>
30#include <linux/of_platform.h>
31#include <linux/pm_runtime.h>
32
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_simple_kms_helper.h>
41
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45#define DSI_CMD_FIFO_DEPTH 16
46#define DSI_PIX_FIFO_DEPTH 256
47#define DSI_PIX_FIFO_WIDTH 4
48
49#define DSI0_CTRL 0x00
50
51/* Command packet control. */
52#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
53#define DSI1_TXPKT1C 0x04
54# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
55# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
56# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
57# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
58
59# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
60# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
61/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
63/* Primary display where cmdfifo provides part of the payload and
64 * pixelvalve the rest.
65 */
66# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
67/* Secondary display where cmdfifo provides part of the payload and
68 * pixfifo the rest.
69 */
70# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
71
72# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
73# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
74
75# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
76# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
77/* Command only. Uses TXPKT1H and DISPLAY_NO */
78# define DSI_TXPKT1C_CMD_CTRL_TX 0
79/* Command with BTA for either ack or read data. */
80# define DSI_TXPKT1C_CMD_CTRL_RX 1
81/* Trigger according to TRIG_CMD */
82# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
83/* BTA alone for getting error status after a command, or a TE trigger
84 * without a previous command.
85 */
86# define DSI_TXPKT1C_CMD_CTRL_BTA 3
87
88# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91# define DSI_TXPKT1C_CMD_EN BIT(0)
92
93/* Command packet header. */
94#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
95#define DSI1_TXPKT1H 0x08
96# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
97# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
98# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
99# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
100# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
101# define DSI_TXPKT1H_BC_DT_SHIFT 0
102
103#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
104#define DSI1_RXPKT1H 0x14
105# define DSI_RXPKT1H_CRC_ERR BIT(31)
106# define DSI_RXPKT1H_DET_ERR BIT(30)
107# define DSI_RXPKT1H_ECC_ERR BIT(29)
108# define DSI_RXPKT1H_COR_ERR BIT(28)
109# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
111/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
113# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
114/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
116# define DSI_RXPKT1H_SHORT_1_SHIFT 16
117# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
118# define DSI_RXPKT1H_SHORT_0_SHIFT 8
119# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
120# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
121
122#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
123#define DSI1_RXPKT2H 0x18
124# define DSI_RXPKT1H_DET_ERR BIT(30)
125# define DSI_RXPKT1H_ECC_ERR BIT(29)
126# define DSI_RXPKT1H_COR_ERR BIT(28)
127# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
128# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
129# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
130# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
131# define DSI_RXPKT1H_DT_SHIFT 0
132
133#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
134#define DSI1_TXPKT_CMD_FIFO 0x1c
135
136#define DSI0_DISP0_CTRL 0x18
137# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
138# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
139# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
140# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
141# define DSI_DISP0_LP_STOP_DISABLE 0
142# define DSI_DISP0_LP_STOP_PERLINE 1
143# define DSI_DISP0_LP_STOP_PERFRAME 2
144
145/* Transmit RGB pixels and null packets only during HACTIVE, instead
146 * of going to LP-STOP.
147 */
148# define DSI_DISP_HACTIVE_NULL BIT(10)
149/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150# define DSI_DISP_VBLP_CTRL BIT(9)
151/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152# define DSI_DISP_HFP_CTRL BIT(8)
153/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154# define DSI_DISP_HBP_CTRL BIT(7)
155# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
156# define DSI_DISP0_CHANNEL_SHIFT 5
157/* Enables end events for HSYNC/VSYNC, not just start events. */
158# define DSI_DISP0_ST_END BIT(4)
159# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
160# define DSI_DISP0_PFORMAT_SHIFT 2
161# define DSI_PFORMAT_RGB565 0
162# define DSI_PFORMAT_RGB666_PACKED 1
163# define DSI_PFORMAT_RGB666 2
164# define DSI_PFORMAT_RGB888 3
165/* Default is VIDEO mode. */
166# define DSI_DISP0_COMMAND_MODE BIT(1)
167# define DSI_DISP0_ENABLE BIT(0)
168
169#define DSI0_DISP1_CTRL 0x1c
170#define DSI1_DISP1_CTRL 0x2c
171/* Format of the data written to TXPKT_PIX_FIFO. */
172# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
173# define DSI_DISP1_PFORMAT_SHIFT 1
174# define DSI_DISP1_PFORMAT_16BIT 0
175# define DSI_DISP1_PFORMAT_24BIT 1
176# define DSI_DISP1_PFORMAT_32BIT_LE 2
177# define DSI_DISP1_PFORMAT_32BIT_BE 3
178
179/* DISP1 is always command mode. */
180# define DSI_DISP1_ENABLE BIT(0)
181
182#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
183
184#define DSI0_INT_STAT 0x24
185#define DSI0_INT_EN 0x28
186# define DSI1_INT_PHY_D3_ULPS BIT(30)
187# define DSI1_INT_PHY_D3_STOP BIT(29)
188# define DSI1_INT_PHY_D2_ULPS BIT(28)
189# define DSI1_INT_PHY_D2_STOP BIT(27)
190# define DSI1_INT_PHY_D1_ULPS BIT(26)
191# define DSI1_INT_PHY_D1_STOP BIT(25)
192# define DSI1_INT_PHY_D0_ULPS BIT(24)
193# define DSI1_INT_PHY_D0_STOP BIT(23)
194# define DSI1_INT_FIFO_ERR BIT(22)
195# define DSI1_INT_PHY_DIR_RTF BIT(21)
196# define DSI1_INT_PHY_RXLPDT BIT(20)
197# define DSI1_INT_PHY_RXTRIG BIT(19)
198# define DSI1_INT_PHY_D0_LPDT BIT(18)
199# define DSI1_INT_PHY_DIR_FTR BIT(17)
200
201/* Signaled when the clock lane enters the given state. */
202# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
203# define DSI1_INT_PHY_CLOCK_HS BIT(15)
204# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
205
206/* Signaled on timeouts */
207# define DSI1_INT_PR_TO BIT(13)
208# define DSI1_INT_TA_TO BIT(12)
209# define DSI1_INT_LPRX_TO BIT(11)
210# define DSI1_INT_HSTX_TO BIT(10)
211
212/* Contention on a line when trying to drive the line low */
213# define DSI1_INT_ERR_CONT_LP1 BIT(9)
214# define DSI1_INT_ERR_CONT_LP0 BIT(8)
215
216/* Control error: incorrect line state sequence on data lane 0. */
217# define DSI1_INT_ERR_CONTROL BIT(7)
218/* LPDT synchronization error (bits received not a multiple of 8. */
219
220# define DSI1_INT_ERR_SYNC_ESC BIT(6)
221/* Signaled after receiving an error packet from the display in
222 * response to a read.
223 */
224# define DSI1_INT_RXPKT2 BIT(5)
225/* Signaled after receiving a packet. The header and optional short
226 * response will be in RXPKT1H, and a long response will be in the
227 * RXPKT_FIFO.
228 */
229# define DSI1_INT_RXPKT1 BIT(4)
230# define DSI1_INT_TXPKT2_DONE BIT(3)
231# define DSI1_INT_TXPKT2_END BIT(2)
232/* Signaled after all repeats of TXPKT1 are transferred. */
233# define DSI1_INT_TXPKT1_DONE BIT(1)
234/* Signaled after each TXPKT1 repeat is scheduled. */
235# define DSI1_INT_TXPKT1_END BIT(0)
236
237#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
238 DSI1_INT_ERR_CONTROL | \
239 DSI1_INT_ERR_CONT_LP0 | \
240 DSI1_INT_ERR_CONT_LP1 | \
241 DSI1_INT_HSTX_TO | \
242 DSI1_INT_LPRX_TO | \
243 DSI1_INT_TA_TO | \
244 DSI1_INT_PR_TO)
245
246#define DSI0_STAT 0x2c
247#define DSI0_HSTX_TO_CNT 0x30
248#define DSI0_LPRX_TO_CNT 0x34
249#define DSI0_TA_TO_CNT 0x38
250#define DSI0_PR_TO_CNT 0x3c
251#define DSI0_PHYC 0x40
252# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
253# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
254# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
255# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
256# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
257# define DSI1_PHYC_CLANE_ULPS BIT(17)
258# define DSI1_PHYC_CLANE_ENABLE BIT(16)
259# define DSI_PHYC_DLANE3_ULPS BIT(13)
260# define DSI_PHYC_DLANE3_ENABLE BIT(12)
261# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
262# define DSI0_PHYC_CLANE_ULPS BIT(9)
263# define DSI_PHYC_DLANE2_ULPS BIT(9)
264# define DSI0_PHYC_CLANE_ENABLE BIT(8)
265# define DSI_PHYC_DLANE2_ENABLE BIT(8)
266# define DSI_PHYC_DLANE1_ULPS BIT(5)
267# define DSI_PHYC_DLANE1_ENABLE BIT(4)
268# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
269# define DSI_PHYC_DLANE0_ULPS BIT(1)
270# define DSI_PHYC_DLANE0_ENABLE BIT(0)
271
272#define DSI0_HS_CLT0 0x44
273#define DSI0_HS_CLT1 0x48
274#define DSI0_HS_CLT2 0x4c
275#define DSI0_HS_DLT3 0x50
276#define DSI0_HS_DLT4 0x54
277#define DSI0_HS_DLT5 0x58
278#define DSI0_HS_DLT6 0x5c
279#define DSI0_HS_DLT7 0x60
280
281#define DSI0_PHY_AFEC0 0x64
282# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
283# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
284# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
285# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
286# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
287# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
288# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
289# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
290# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
291# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
292# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
293# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
294# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
295# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
296# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
297# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
298# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
299# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
300# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
301# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
302# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
303# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
304# define DSI1_PHY_AFEC0_RESET BIT(13)
305# define DSI1_PHY_AFEC0_PD BIT(12)
306# define DSI0_PHY_AFEC0_RESET BIT(11)
307# define DSI1_PHY_AFEC0_PD_BG BIT(11)
308# define DSI0_PHY_AFEC0_PD BIT(10)
309# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
310# define DSI0_PHY_AFEC0_PD_BG BIT(9)
311# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
312# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
313# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
314# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
315# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
316# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
317# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
318
319#define DSI0_PHY_AFEC1 0x68
320# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
321# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
322# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
323# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
324# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
325# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
326
327#define DSI0_TST_SEL 0x6c
328#define DSI0_TST_MON 0x70
329#define DSI0_ID 0x74
330# define DSI_ID_VALUE 0x00647369
331
332#define DSI1_CTRL 0x00
333# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
334# define DSI_CTRL_HS_CLKC_SHIFT 14
335# define DSI_CTRL_HS_CLKC_BYTE 0
336# define DSI_CTRL_HS_CLKC_DDR2 1
337# define DSI_CTRL_HS_CLKC_DDR 2
338
339# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
340# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
341# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
342# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
343# define DSI_CTRL_CAL_BYTE BIT(9)
344# define DSI_CTRL_INV_BYTE BIT(8)
345# define DSI_CTRL_CLR_LDF BIT(7)
346# define DSI0_CTRL_CLR_PBCF BIT(6)
347# define DSI1_CTRL_CLR_RXF BIT(6)
348# define DSI0_CTRL_CLR_CPBCF BIT(5)
349# define DSI1_CTRL_CLR_PDF BIT(5)
350# define DSI0_CTRL_CLR_PDF BIT(4)
351# define DSI1_CTRL_CLR_CDF BIT(4)
352# define DSI0_CTRL_CLR_CDF BIT(3)
353# define DSI0_CTRL_CTRL2 BIT(2)
354# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
355# define DSI0_CTRL_CTRL1 BIT(1)
356# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
357# define DSI0_CTRL_CTRL0 BIT(0)
358# define DSI1_CTRL_EN BIT(0)
359# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
360 DSI0_CTRL_CLR_PBCF | \
361 DSI0_CTRL_CLR_CPBCF | \
362 DSI0_CTRL_CLR_PDF | \
363 DSI0_CTRL_CLR_CDF)
364# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
365 DSI1_CTRL_CLR_RXF | \
366 DSI1_CTRL_CLR_PDF | \
367 DSI1_CTRL_CLR_CDF)
368
369#define DSI1_TXPKT2C 0x0c
370#define DSI1_TXPKT2H 0x10
371#define DSI1_TXPKT_PIX_FIFO 0x20
372#define DSI1_RXPKT_FIFO 0x24
373#define DSI1_DISP0_CTRL 0x28
374#define DSI1_INT_STAT 0x30
375#define DSI1_INT_EN 0x34
376/* State reporting bits. These mostly behave like INT_STAT, where
377 * writing a 1 clears the bit.
378 */
379#define DSI1_STAT 0x38
380# define DSI1_STAT_PHY_D3_ULPS BIT(31)
381# define DSI1_STAT_PHY_D3_STOP BIT(30)
382# define DSI1_STAT_PHY_D2_ULPS BIT(29)
383# define DSI1_STAT_PHY_D2_STOP BIT(28)
384# define DSI1_STAT_PHY_D1_ULPS BIT(27)
385# define DSI1_STAT_PHY_D1_STOP BIT(26)
386# define DSI1_STAT_PHY_D0_ULPS BIT(25)
387# define DSI1_STAT_PHY_D0_STOP BIT(24)
388# define DSI1_STAT_FIFO_ERR BIT(23)
389# define DSI1_STAT_PHY_RXLPDT BIT(22)
390# define DSI1_STAT_PHY_RXTRIG BIT(21)
391# define DSI1_STAT_PHY_D0_LPDT BIT(20)
392/* Set when in forward direction */
393# define DSI1_STAT_PHY_DIR BIT(19)
394# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
395# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
396# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
397# define DSI1_STAT_PR_TO BIT(15)
398# define DSI1_STAT_TA_TO BIT(14)
399# define DSI1_STAT_LPRX_TO BIT(13)
400# define DSI1_STAT_HSTX_TO BIT(12)
401# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
402# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
403# define DSI1_STAT_ERR_CONTROL BIT(9)
404# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
405# define DSI1_STAT_RXPKT2 BIT(7)
406# define DSI1_STAT_RXPKT1 BIT(6)
407# define DSI1_STAT_TXPKT2_BUSY BIT(5)
408# define DSI1_STAT_TXPKT2_DONE BIT(4)
409# define DSI1_STAT_TXPKT2_END BIT(3)
410# define DSI1_STAT_TXPKT1_BUSY BIT(2)
411# define DSI1_STAT_TXPKT1_DONE BIT(1)
412# define DSI1_STAT_TXPKT1_END BIT(0)
413
414#define DSI1_HSTX_TO_CNT 0x3c
415#define DSI1_LPRX_TO_CNT 0x40
416#define DSI1_TA_TO_CNT 0x44
417#define DSI1_PR_TO_CNT 0x48
418#define DSI1_PHYC 0x4c
419
420#define DSI1_HS_CLT0 0x50
421# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
422# define DSI_HS_CLT0_CZERO_SHIFT 18
423# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
424# define DSI_HS_CLT0_CPRE_SHIFT 9
425# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
426# define DSI_HS_CLT0_CPREP_SHIFT 0
427
428#define DSI1_HS_CLT1 0x54
429# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
430# define DSI_HS_CLT1_CTRAIL_SHIFT 9
431# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
432# define DSI_HS_CLT1_CPOST_SHIFT 0
433
434#define DSI1_HS_CLT2 0x58
435# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
436# define DSI_HS_CLT2_WUP_SHIFT 0
437
438#define DSI1_HS_DLT3 0x5c
439# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
440# define DSI_HS_DLT3_EXIT_SHIFT 18
441# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
442# define DSI_HS_DLT3_ZERO_SHIFT 9
443# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
444# define DSI_HS_DLT3_PRE_SHIFT 0
445
446#define DSI1_HS_DLT4 0x60
447# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
448# define DSI_HS_DLT4_ANLAT_SHIFT 18
449# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
450# define DSI_HS_DLT4_TRAIL_SHIFT 9
451# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
452# define DSI_HS_DLT4_LPX_SHIFT 0
453
454#define DSI1_HS_DLT5 0x64
455# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
456# define DSI_HS_DLT5_INIT_SHIFT 0
457
458#define DSI1_HS_DLT6 0x68
459# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
460# define DSI_HS_DLT6_TA_GET_SHIFT 24
461# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
462# define DSI_HS_DLT6_TA_SURE_SHIFT 16
463# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
464# define DSI_HS_DLT6_TA_GO_SHIFT 8
465# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
466# define DSI_HS_DLT6_LP_LPX_SHIFT 0
467
468#define DSI1_HS_DLT7 0x6c
469# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
470# define DSI_HS_DLT7_LP_WUP_SHIFT 0
471
472#define DSI1_PHY_AFEC0 0x70
473
474#define DSI1_PHY_AFEC1 0x74
475# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
476# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
477# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
478# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
479# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
480# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
481# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
482# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
483# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
484# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
485
486#define DSI1_TST_SEL 0x78
487#define DSI1_TST_MON 0x7c
488#define DSI1_PHY_TST1 0x80
489#define DSI1_PHY_TST2 0x84
490#define DSI1_PHY_FIFO_STAT 0x88
491/* Actually, all registers in the range that aren't otherwise claimed
492 * will return the ID.
493 */
494#define DSI1_ID 0x8c
495
496/* General DSI hardware state. */
497struct vc4_dsi {
498 struct platform_device *pdev;
499
500 struct mipi_dsi_host dsi_host;
501 struct drm_encoder *encoder;
502 struct drm_bridge *bridge;
503 struct list_head bridge_chain;
504
505 void __iomem *regs;
506
507 struct dma_chan *reg_dma_chan;
508 dma_addr_t reg_dma_paddr;
509 u32 *reg_dma_mem;
510 dma_addr_t reg_paddr;
511
512 /* Whether we're on bcm2835's DSI0 or DSI1. */
513 int port;
514
515 /* DSI channel for the panel we're connected to. */
516 u32 channel;
517 u32 lanes;
518 u32 format;
519 u32 divider;
520 u32 mode_flags;
521
522 /* Input clock from CPRMAN to the digital PHY, for the DSI
523 * escape clock.
524 */
525 struct clk *escape_clock;
526
527 /* Input clock to the analog PHY, used to generate the DSI bit
528 * clock.
529 */
530 struct clk *pll_phy_clock;
531
532 /* HS Clocks generated within the DSI analog PHY. */
533 struct clk_fixed_factor phy_clocks[3];
534
535 struct clk_hw_onecell_data *clk_onecell;
536
537 /* Pixel clock output to the pixelvalve, generated from the HS
538 * clock.
539 */
540 struct clk *pixel_clock;
541
542 struct completion xfer_completion;
543 int xfer_result;
544
545 struct debugfs_regset32 regset;
546};
547
548#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
549
550static inline void
551dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
552{
553 struct dma_chan *chan = dsi->reg_dma_chan;
554 struct dma_async_tx_descriptor *tx;
555 dma_cookie_t cookie;
556 int ret;
557
558 /* DSI0 should be able to write normally. */
559 if (!chan) {
560 writel(val, dsi->regs + offset);
561 return;
562 }
563
564 *dsi->reg_dma_mem = val;
565
566 tx = chan->device->device_prep_dma_memcpy(chan,
567 dsi->reg_paddr + offset,
568 dsi->reg_dma_paddr,
569 4, 0);
570 if (!tx) {
571 DRM_ERROR("Failed to set up DMA register write\n");
572 return;
573 }
574
575 cookie = tx->tx_submit(tx);
576 ret = dma_submit_error(cookie);
577 if (ret) {
578 DRM_ERROR("Failed to submit DMA: %d\n", ret);
579 return;
580 }
581 ret = dma_sync_wait(chan, cookie);
582 if (ret)
583 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
584}
585
586#define DSI_READ(offset) readl(dsi->regs + (offset))
587#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
588#define DSI_PORT_READ(offset) \
589 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
590#define DSI_PORT_WRITE(offset, val) \
591 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
592#define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
593
594/* VC4 DSI encoder KMS struct */
595struct vc4_dsi_encoder {
596 struct vc4_encoder base;
597 struct vc4_dsi *dsi;
598};
599
600static inline struct vc4_dsi_encoder *
601to_vc4_dsi_encoder(struct drm_encoder *encoder)
602{
603 return container_of(encoder, struct vc4_dsi_encoder, base.base);
604}
605
606static const struct debugfs_reg32 dsi0_regs[] = {
607 VC4_REG32(DSI0_CTRL),
608 VC4_REG32(DSI0_STAT),
609 VC4_REG32(DSI0_HSTX_TO_CNT),
610 VC4_REG32(DSI0_LPRX_TO_CNT),
611 VC4_REG32(DSI0_TA_TO_CNT),
612 VC4_REG32(DSI0_PR_TO_CNT),
613 VC4_REG32(DSI0_DISP0_CTRL),
614 VC4_REG32(DSI0_DISP1_CTRL),
615 VC4_REG32(DSI0_INT_STAT),
616 VC4_REG32(DSI0_INT_EN),
617 VC4_REG32(DSI0_PHYC),
618 VC4_REG32(DSI0_HS_CLT0),
619 VC4_REG32(DSI0_HS_CLT1),
620 VC4_REG32(DSI0_HS_CLT2),
621 VC4_REG32(DSI0_HS_DLT3),
622 VC4_REG32(DSI0_HS_DLT4),
623 VC4_REG32(DSI0_HS_DLT5),
624 VC4_REG32(DSI0_HS_DLT6),
625 VC4_REG32(DSI0_HS_DLT7),
626 VC4_REG32(DSI0_PHY_AFEC0),
627 VC4_REG32(DSI0_PHY_AFEC1),
628 VC4_REG32(DSI0_ID),
629};
630
631static const struct debugfs_reg32 dsi1_regs[] = {
632 VC4_REG32(DSI1_CTRL),
633 VC4_REG32(DSI1_STAT),
634 VC4_REG32(DSI1_HSTX_TO_CNT),
635 VC4_REG32(DSI1_LPRX_TO_CNT),
636 VC4_REG32(DSI1_TA_TO_CNT),
637 VC4_REG32(DSI1_PR_TO_CNT),
638 VC4_REG32(DSI1_DISP0_CTRL),
639 VC4_REG32(DSI1_DISP1_CTRL),
640 VC4_REG32(DSI1_INT_STAT),
641 VC4_REG32(DSI1_INT_EN),
642 VC4_REG32(DSI1_PHYC),
643 VC4_REG32(DSI1_HS_CLT0),
644 VC4_REG32(DSI1_HS_CLT1),
645 VC4_REG32(DSI1_HS_CLT2),
646 VC4_REG32(DSI1_HS_DLT3),
647 VC4_REG32(DSI1_HS_DLT4),
648 VC4_REG32(DSI1_HS_DLT5),
649 VC4_REG32(DSI1_HS_DLT6),
650 VC4_REG32(DSI1_HS_DLT7),
651 VC4_REG32(DSI1_PHY_AFEC0),
652 VC4_REG32(DSI1_PHY_AFEC1),
653 VC4_REG32(DSI1_ID),
654};
655
656static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
657{
658 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
659
660 if (latch)
661 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
662 else
663 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
664
665 DSI_PORT_WRITE(PHY_AFEC0, afec0);
666}
667
668/* Enters or exits Ultra Low Power State. */
669static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
670{
671 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
672 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
673 DSI_PHYC_DLANE0_ULPS |
674 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
675 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
676 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
677 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
678 DSI1_STAT_PHY_D0_ULPS |
679 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
680 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
681 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
682 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
683 DSI1_STAT_PHY_D0_STOP |
684 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
685 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
686 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
687 int ret;
688 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
689 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
690
691 if (ulps == ulps_currently_enabled)
692 return;
693
694 DSI_PORT_WRITE(STAT, stat_ulps);
695 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
696 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
697 if (ret) {
698 dev_warn(&dsi->pdev->dev,
699 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
700 DSI_PORT_READ(STAT));
701 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
702 vc4_dsi_latch_ulps(dsi, false);
703 return;
704 }
705
706 /* The DSI module can't be disabled while the module is
707 * generating ULPS state. So, to be able to disable the
708 * module, we have the AFE latch the ULPS state and continue
709 * on to having the module enter STOP.
710 */
711 vc4_dsi_latch_ulps(dsi, ulps);
712
713 DSI_PORT_WRITE(STAT, stat_stop);
714 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
715 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
716 if (ret) {
717 dev_warn(&dsi->pdev->dev,
718 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
719 DSI_PORT_READ(STAT));
720 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
721 return;
722 }
723}
724
725static u32
726dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
727{
728 /* The HS timings have to be rounded up to a multiple of 8
729 * because we're using the byte clock.
730 */
731 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
732}
733
734/* ESC always runs at 100Mhz. */
735#define ESC_TIME_NS 10
736
737static u32
738dsi_esc_timing(u32 ns)
739{
740 return DIV_ROUND_UP(ns, ESC_TIME_NS);
741}
742
743static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
744{
745 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
746 struct vc4_dsi *dsi = vc4_encoder->dsi;
747 struct device *dev = &dsi->pdev->dev;
748 struct drm_bridge *iter;
749
750 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
751 if (iter->funcs->disable)
752 iter->funcs->disable(iter);
753 }
754
755 vc4_dsi_ulps(dsi, true);
756
757 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) {
758 if (iter->funcs->post_disable)
759 iter->funcs->post_disable(iter);
760 }
761
762 clk_disable_unprepare(dsi->pll_phy_clock);
763 clk_disable_unprepare(dsi->escape_clock);
764 clk_disable_unprepare(dsi->pixel_clock);
765
766 pm_runtime_put(dev);
767}
768
769/* Extends the mode's blank intervals to handle BCM2835's integer-only
770 * DSI PLL divider.
771 *
772 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
773 * driver since most peripherals are hanging off of the PLLD_PER
774 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
775 * the pixel clock), only has an integer divider off of DSI.
776 *
777 * To get our panel mode to refresh at the expected 60Hz, we need to
778 * extend the horizontal blank time. This means we drive a
779 * higher-than-expected clock rate to the panel, but that's what the
780 * firmware does too.
781 */
782static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
783 const struct drm_display_mode *mode,
784 struct drm_display_mode *adjusted_mode)
785{
786 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
787 struct vc4_dsi *dsi = vc4_encoder->dsi;
788 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
789 unsigned long parent_rate = clk_get_rate(phy_parent);
790 unsigned long pixel_clock_hz = mode->clock * 1000;
791 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
792 int divider;
793
794 /* Find what divider gets us a faster clock than the requested
795 * pixel clock.
796 */
797 for (divider = 1; divider < 8; divider++) {
798 if (parent_rate / divider < pll_clock) {
799 divider--;
800 break;
801 }
802 }
803
804 /* Now that we've picked a PLL divider, calculate back to its
805 * pixel clock.
806 */
807 pll_clock = parent_rate / divider;
808 pixel_clock_hz = pll_clock / dsi->divider;
809
810 adjusted_mode->clock = pixel_clock_hz / 1000;
811
812 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
813 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
814 mode->clock;
815 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
816 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
817
818 return true;
819}
820
821static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
822{
823 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
824 struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
825 struct vc4_dsi *dsi = vc4_encoder->dsi;
826 struct device *dev = &dsi->pdev->dev;
827 bool debug_dump_regs = false;
828 struct drm_bridge *iter;
829 unsigned long hs_clock;
830 u32 ui_ns;
831 /* Minimum LP state duration in escape clock cycles. */
832 u32 lpx = dsi_esc_timing(60);
833 unsigned long pixel_clock_hz = mode->clock * 1000;
834 unsigned long dsip_clock;
835 unsigned long phy_clock;
836 int ret;
837
838 ret = pm_runtime_get_sync(dev);
839 if (ret) {
840 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port);
841 return;
842 }
843
844 if (debug_dump_regs) {
845 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
846 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
847 drm_print_regset32(&p, &dsi->regset);
848 }
849
850 /* Round up the clk_set_rate() request slightly, since
851 * PLLD_DSI1 is an integer divider and its rate selection will
852 * never round up.
853 */
854 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
855 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
856 if (ret) {
857 dev_err(&dsi->pdev->dev,
858 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
859 }
860
861 /* Reset the DSI and all its fifos. */
862 DSI_PORT_WRITE(CTRL,
863 DSI_CTRL_SOFT_RESET_CFG |
864 DSI_PORT_BIT(CTRL_RESET_FIFOS));
865
866 DSI_PORT_WRITE(CTRL,
867 DSI_CTRL_HSDT_EOT_DISABLE |
868 DSI_CTRL_RX_LPDT_EOT_DISABLE);
869
870 /* Clear all stat bits so we see what has happened during enable. */
871 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
872
873 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
874 if (dsi->port == 0) {
875 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
876 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
877
878 if (dsi->lanes < 2)
879 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
880
881 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
882 afec0 |= DSI0_PHY_AFEC0_RESET;
883
884 DSI_PORT_WRITE(PHY_AFEC0, afec0);
885
886 DSI_PORT_WRITE(PHY_AFEC1,
887 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
888 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
889 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
890 } else {
891 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
892 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
893 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
894 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
895 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
896 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
897 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
898
899 if (dsi->lanes < 4)
900 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
901 if (dsi->lanes < 3)
902 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
903 if (dsi->lanes < 2)
904 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
905
906 afec0 |= DSI1_PHY_AFEC0_RESET;
907
908 DSI_PORT_WRITE(PHY_AFEC0, afec0);
909
910 DSI_PORT_WRITE(PHY_AFEC1, 0);
911
912 /* AFEC reset hold time */
913 mdelay(1);
914 }
915
916 ret = clk_prepare_enable(dsi->escape_clock);
917 if (ret) {
918 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
919 return;
920 }
921
922 ret = clk_prepare_enable(dsi->pll_phy_clock);
923 if (ret) {
924 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
925 return;
926 }
927
928 hs_clock = clk_get_rate(dsi->pll_phy_clock);
929
930 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
931 * not the pixel clock rate. DSIxP take from the APHY's byte,
932 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
933 * that rate. Separately, a value derived from PIX_CLK_DIV
934 * and HS_CLKC is fed into the PV to divide down to the actual
935 * pixel clock for pushing pixels into DSI.
936 */
937 dsip_clock = phy_clock / 8;
938 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
939 if (ret) {
940 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
941 dsip_clock, ret);
942 }
943
944 ret = clk_prepare_enable(dsi->pixel_clock);
945 if (ret) {
946 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
947 return;
948 }
949
950 /* How many ns one DSI unit interval is. Note that the clock
951 * is DDR, so there's an extra divide by 2.
952 */
953 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
954
955 DSI_PORT_WRITE(HS_CLT0,
956 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
957 DSI_HS_CLT0_CZERO) |
958 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
959 DSI_HS_CLT0_CPRE) |
960 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
961 DSI_HS_CLT0_CPREP));
962
963 DSI_PORT_WRITE(HS_CLT1,
964 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
965 DSI_HS_CLT1_CTRAIL) |
966 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
967 DSI_HS_CLT1_CPOST));
968
969 DSI_PORT_WRITE(HS_CLT2,
970 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
971 DSI_HS_CLT2_WUP));
972
973 DSI_PORT_WRITE(HS_DLT3,
974 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
975 DSI_HS_DLT3_EXIT) |
976 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
977 DSI_HS_DLT3_ZERO) |
978 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
979 DSI_HS_DLT3_PRE));
980
981 DSI_PORT_WRITE(HS_DLT4,
982 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
983 DSI_HS_DLT4_LPX) |
984 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
985 dsi_hs_timing(ui_ns, 60, 4)),
986 DSI_HS_DLT4_TRAIL) |
987 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
988
989 /* T_INIT is how long STOP is driven after power-up to
990 * indicate to the slave (also coming out of power-up) that
991 * master init is complete, and should be greater than the
992 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
993 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
994 * T_INIT,SLAVE, while allowing protocols on top of it to give
995 * greater minimums. The vc4 firmware uses an extremely
996 * conservative 5ms, and we maintain that here.
997 */
998 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
999 5 * 1000 * 1000, 0),
1000 DSI_HS_DLT5_INIT));
1001
1002 DSI_PORT_WRITE(HS_DLT6,
1003 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1004 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1005 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1006 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1007
1008 DSI_PORT_WRITE(HS_DLT7,
1009 VC4_SET_FIELD(dsi_esc_timing(1000000),
1010 DSI_HS_DLT7_LP_WUP));
1011
1012 DSI_PORT_WRITE(PHYC,
1013 DSI_PHYC_DLANE0_ENABLE |
1014 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1015 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1016 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1017 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1018 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1019 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1020 (dsi->port == 0 ?
1021 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1022 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1023
1024 DSI_PORT_WRITE(CTRL,
1025 DSI_PORT_READ(CTRL) |
1026 DSI_CTRL_CAL_BYTE);
1027
1028 /* HS timeout in HS clock cycles: disabled. */
1029 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1030 /* LP receive timeout in HS clocks. */
1031 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1032 /* Bus turnaround timeout */
1033 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1034 /* Display reset sequence timeout */
1035 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1036
1037 /* Set up DISP1 for transferring long command payloads through
1038 * the pixfifo.
1039 */
1040 DSI_PORT_WRITE(DISP1_CTRL,
1041 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1042 DSI_DISP1_PFORMAT) |
1043 DSI_DISP1_ENABLE);
1044
1045 /* Ungate the block. */
1046 if (dsi->port == 0)
1047 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1048 else
1049 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1050
1051 /* Bring AFE out of reset. */
1052 if (dsi->port == 0) {
1053 } else {
1054 DSI_PORT_WRITE(PHY_AFEC0,
1055 DSI_PORT_READ(PHY_AFEC0) &
1056 ~DSI1_PHY_AFEC0_RESET);
1057 }
1058
1059 vc4_dsi_ulps(dsi, false);
1060
1061 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1062 if (iter->funcs->pre_enable)
1063 iter->funcs->pre_enable(iter);
1064 }
1065
1066 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1067 DSI_PORT_WRITE(DISP0_CTRL,
1068 VC4_SET_FIELD(dsi->divider,
1069 DSI_DISP0_PIX_CLK_DIV) |
1070 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1071 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1072 DSI_DISP0_LP_STOP_CTRL) |
1073 DSI_DISP0_ST_END |
1074 DSI_DISP0_ENABLE);
1075 } else {
1076 DSI_PORT_WRITE(DISP0_CTRL,
1077 DSI_DISP0_COMMAND_MODE |
1078 DSI_DISP0_ENABLE);
1079 }
1080
1081 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1082 if (iter->funcs->enable)
1083 iter->funcs->enable(iter);
1084 }
1085
1086 if (debug_dump_regs) {
1087 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1088 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1089 drm_print_regset32(&p, &dsi->regset);
1090 }
1091}
1092
1093static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1094 const struct mipi_dsi_msg *msg)
1095{
1096 struct vc4_dsi *dsi = host_to_dsi(host);
1097 struct mipi_dsi_packet packet;
1098 u32 pkth = 0, pktc = 0;
1099 int i, ret;
1100 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1101 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1102
1103 mipi_dsi_create_packet(&packet, msg);
1104
1105 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1106 pkth |= VC4_SET_FIELD(packet.header[1] |
1107 (packet.header[2] << 8),
1108 DSI_TXPKT1H_BC_PARAM);
1109 if (is_long) {
1110 /* Divide data across the various FIFOs we have available.
1111 * The command FIFO takes byte-oriented data, but is of
1112 * limited size. The pixel FIFO (never actually used for
1113 * pixel data in reality) is word oriented, and substantially
1114 * larger. So, we use the pixel FIFO for most of the data,
1115 * sending the residual bytes in the command FIFO at the start.
1116 *
1117 * With this arrangement, the command FIFO will never get full.
1118 */
1119 if (packet.payload_length <= 16) {
1120 cmd_fifo_len = packet.payload_length;
1121 pix_fifo_len = 0;
1122 } else {
1123 cmd_fifo_len = (packet.payload_length %
1124 DSI_PIX_FIFO_WIDTH);
1125 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1126 DSI_PIX_FIFO_WIDTH);
1127 }
1128
1129 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1130
1131 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1132 }
1133
1134 if (msg->rx_len) {
1135 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1136 DSI_TXPKT1C_CMD_CTRL);
1137 } else {
1138 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1139 DSI_TXPKT1C_CMD_CTRL);
1140 }
1141
1142 for (i = 0; i < cmd_fifo_len; i++)
1143 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1144 for (i = 0; i < pix_fifo_len; i++) {
1145 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1146
1147 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1148 pix[0] |
1149 pix[1] << 8 |
1150 pix[2] << 16 |
1151 pix[3] << 24);
1152 }
1153
1154 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1155 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1156 if (is_long)
1157 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1158
1159 /* Send one copy of the packet. Larger repeats are used for pixel
1160 * data in command mode.
1161 */
1162 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1163
1164 pktc |= DSI_TXPKT1C_CMD_EN;
1165 if (pix_fifo_len) {
1166 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1167 DSI_TXPKT1C_DISPLAY_NO);
1168 } else {
1169 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1170 DSI_TXPKT1C_DISPLAY_NO);
1171 }
1172
1173 /* Enable the appropriate interrupt for the transfer completion. */
1174 dsi->xfer_result = 0;
1175 reinit_completion(&dsi->xfer_completion);
1176 DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1177 if (msg->rx_len) {
1178 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1179 DSI1_INT_PHY_DIR_RTF));
1180 } else {
1181 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1182 DSI1_INT_TXPKT1_DONE));
1183 }
1184
1185 /* Send the packet. */
1186 DSI_PORT_WRITE(TXPKT1H, pkth);
1187 DSI_PORT_WRITE(TXPKT1C, pktc);
1188
1189 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1190 msecs_to_jiffies(1000))) {
1191 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1192 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1193 DSI_PORT_READ(INT_STAT));
1194 ret = -ETIMEDOUT;
1195 } else {
1196 ret = dsi->xfer_result;
1197 }
1198
1199 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1200
1201 if (ret)
1202 goto reset_fifo_and_return;
1203
1204 if (ret == 0 && msg->rx_len) {
1205 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1206 u8 *msg_rx = msg->rx_buf;
1207
1208 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1209 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1210 DSI_RXPKT1H_BC_PARAM);
1211
1212 if (rxlen != msg->rx_len) {
1213 DRM_ERROR("DSI returned %db, expecting %db\n",
1214 rxlen, (int)msg->rx_len);
1215 ret = -ENXIO;
1216 goto reset_fifo_and_return;
1217 }
1218
1219 for (i = 0; i < msg->rx_len; i++)
1220 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1221 } else {
1222 /* FINISHME: Handle AWER */
1223
1224 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1225 DSI_RXPKT1H_SHORT_0);
1226 if (msg->rx_len > 1) {
1227 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1228 DSI_RXPKT1H_SHORT_1);
1229 }
1230 }
1231 }
1232
1233 return ret;
1234
1235reset_fifo_and_return:
1236 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1237
1238 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1239 udelay(1);
1240 DSI_PORT_WRITE(CTRL,
1241 DSI_PORT_READ(CTRL) |
1242 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1243
1244 DSI_PORT_WRITE(TXPKT1C, 0);
1245 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1246 return ret;
1247}
1248
1249static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1250 struct mipi_dsi_device *device)
1251{
1252 struct vc4_dsi *dsi = host_to_dsi(host);
1253
1254 dsi->lanes = device->lanes;
1255 dsi->channel = device->channel;
1256 dsi->mode_flags = device->mode_flags;
1257
1258 switch (device->format) {
1259 case MIPI_DSI_FMT_RGB888:
1260 dsi->format = DSI_PFORMAT_RGB888;
1261 dsi->divider = 24 / dsi->lanes;
1262 break;
1263 case MIPI_DSI_FMT_RGB666:
1264 dsi->format = DSI_PFORMAT_RGB666;
1265 dsi->divider = 24 / dsi->lanes;
1266 break;
1267 case MIPI_DSI_FMT_RGB666_PACKED:
1268 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1269 dsi->divider = 18 / dsi->lanes;
1270 break;
1271 case MIPI_DSI_FMT_RGB565:
1272 dsi->format = DSI_PFORMAT_RGB565;
1273 dsi->divider = 16 / dsi->lanes;
1274 break;
1275 default:
1276 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1277 dsi->format);
1278 return 0;
1279 }
1280
1281 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1282 dev_err(&dsi->pdev->dev,
1283 "Only VIDEO mode panels supported currently.\n");
1284 return 0;
1285 }
1286
1287 return 0;
1288}
1289
1290static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1291 struct mipi_dsi_device *device)
1292{
1293 return 0;
1294}
1295
1296static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1297 .attach = vc4_dsi_host_attach,
1298 .detach = vc4_dsi_host_detach,
1299 .transfer = vc4_dsi_host_transfer,
1300};
1301
1302static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1303 .disable = vc4_dsi_encoder_disable,
1304 .enable = vc4_dsi_encoder_enable,
1305 .mode_fixup = vc4_dsi_encoder_mode_fixup,
1306};
1307
1308static const struct of_device_id vc4_dsi_dt_match[] = {
1309 { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1310 {}
1311};
1312
1313static void dsi_handle_error(struct vc4_dsi *dsi,
1314 irqreturn_t *ret, u32 stat, u32 bit,
1315 const char *type)
1316{
1317 if (!(stat & bit))
1318 return;
1319
1320 DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1321 *ret = IRQ_HANDLED;
1322}
1323
1324/*
1325 * Initial handler for port 1 where we need the reg_dma workaround.
1326 * The register DMA writes sleep, so we can't do it in the top half.
1327 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1328 * parent interrupt contrller until our interrupt thread is done.
1329 */
1330static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1331{
1332 struct vc4_dsi *dsi = data;
1333 u32 stat = DSI_PORT_READ(INT_STAT);
1334
1335 if (!stat)
1336 return IRQ_NONE;
1337
1338 return IRQ_WAKE_THREAD;
1339}
1340
1341/*
1342 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1343 * 1 where we need the reg_dma workaround.
1344 */
1345static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1346{
1347 struct vc4_dsi *dsi = data;
1348 u32 stat = DSI_PORT_READ(INT_STAT);
1349 irqreturn_t ret = IRQ_NONE;
1350
1351 DSI_PORT_WRITE(INT_STAT, stat);
1352
1353 dsi_handle_error(dsi, &ret, stat,
1354 DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1355 dsi_handle_error(dsi, &ret, stat,
1356 DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1357 dsi_handle_error(dsi, &ret, stat,
1358 DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1359 dsi_handle_error(dsi, &ret, stat,
1360 DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1361 dsi_handle_error(dsi, &ret, stat,
1362 DSI1_INT_HSTX_TO, "HSTX timeout");
1363 dsi_handle_error(dsi, &ret, stat,
1364 DSI1_INT_LPRX_TO, "LPRX timeout");
1365 dsi_handle_error(dsi, &ret, stat,
1366 DSI1_INT_TA_TO, "turnaround timeout");
1367 dsi_handle_error(dsi, &ret, stat,
1368 DSI1_INT_PR_TO, "peripheral reset timeout");
1369
1370 if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1371 complete(&dsi->xfer_completion);
1372 ret = IRQ_HANDLED;
1373 } else if (stat & DSI1_INT_HSTX_TO) {
1374 complete(&dsi->xfer_completion);
1375 dsi->xfer_result = -ETIMEDOUT;
1376 ret = IRQ_HANDLED;
1377 }
1378
1379 return ret;
1380}
1381
1382/**
1383 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1384 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1385 * @dsi: DSI encoder
1386 */
1387static int
1388vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1389{
1390 struct device *dev = &dsi->pdev->dev;
1391 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1392 static const struct {
1393 const char *dsi0_name, *dsi1_name;
1394 int div;
1395 } phy_clocks[] = {
1396 { "dsi0_byte", "dsi1_byte", 8 },
1397 { "dsi0_ddr2", "dsi1_ddr2", 4 },
1398 { "dsi0_ddr", "dsi1_ddr", 2 },
1399 };
1400 int i;
1401
1402 dsi->clk_onecell = devm_kzalloc(dev,
1403 sizeof(*dsi->clk_onecell) +
1404 ARRAY_SIZE(phy_clocks) *
1405 sizeof(struct clk_hw *),
1406 GFP_KERNEL);
1407 if (!dsi->clk_onecell)
1408 return -ENOMEM;
1409 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1410
1411 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1412 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1413 struct clk_init_data init;
1414 int ret;
1415
1416 /* We just use core fixed factor clock ops for the PHY
1417 * clocks. The clocks are actually gated by the
1418 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1419 * setting if we use the DDR/DDR2 clocks. However,
1420 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1421 * setting both our parent DSI PLL's rate and this
1422 * clock's rate, so it knows if DDR/DDR2 are going to
1423 * be used and could enable the gates itself.
1424 */
1425 fix->mult = 1;
1426 fix->div = phy_clocks[i].div;
1427 fix->hw.init = &init;
1428
1429 memset(&init, 0, sizeof(init));
1430 init.parent_names = &parent_name;
1431 init.num_parents = 1;
1432 if (dsi->port == 1)
1433 init.name = phy_clocks[i].dsi1_name;
1434 else
1435 init.name = phy_clocks[i].dsi0_name;
1436 init.ops = &clk_fixed_factor_ops;
1437
1438 ret = devm_clk_hw_register(dev, &fix->hw);
1439 if (ret)
1440 return ret;
1441
1442 dsi->clk_onecell->hws[i] = &fix->hw;
1443 }
1444
1445 return of_clk_add_hw_provider(dev->of_node,
1446 of_clk_hw_onecell_get,
1447 dsi->clk_onecell);
1448}
1449
1450static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1451{
1452 struct platform_device *pdev = to_platform_device(dev);
1453 struct drm_device *drm = dev_get_drvdata(master);
1454 struct vc4_dev *vc4 = to_vc4_dev(drm);
1455 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1456 struct vc4_dsi_encoder *vc4_dsi_encoder;
1457 struct drm_panel *panel;
1458 const struct of_device_id *match;
1459 dma_cap_mask_t dma_mask;
1460 int ret;
1461
1462 match = of_match_device(vc4_dsi_dt_match, dev);
1463 if (!match)
1464 return -ENODEV;
1465
1466 dsi->port = (uintptr_t)match->data;
1467
1468 vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1469 GFP_KERNEL);
1470 if (!vc4_dsi_encoder)
1471 return -ENOMEM;
1472
1473 INIT_LIST_HEAD(&dsi->bridge_chain);
1474 vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1475 vc4_dsi_encoder->dsi = dsi;
1476 dsi->encoder = &vc4_dsi_encoder->base.base;
1477
1478 dsi->regs = vc4_ioremap_regs(pdev, 0);
1479 if (IS_ERR(dsi->regs))
1480 return PTR_ERR(dsi->regs);
1481
1482 dsi->regset.base = dsi->regs;
1483 if (dsi->port == 0) {
1484 dsi->regset.regs = dsi0_regs;
1485 dsi->regset.nregs = ARRAY_SIZE(dsi0_regs);
1486 } else {
1487 dsi->regset.regs = dsi1_regs;
1488 dsi->regset.nregs = ARRAY_SIZE(dsi1_regs);
1489 }
1490
1491 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1492 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1493 DSI_PORT_READ(ID), DSI_ID_VALUE);
1494 return -ENODEV;
1495 }
1496
1497 /* DSI1 has a broken AXI slave that doesn't respond to writes
1498 * from the ARM. It does handle writes from the DMA engine,
1499 * so set up a channel for talking to it.
1500 */
1501 if (dsi->port == 1) {
1502 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1503 &dsi->reg_dma_paddr,
1504 GFP_KERNEL);
1505 if (!dsi->reg_dma_mem) {
1506 DRM_ERROR("Failed to get DMA memory\n");
1507 return -ENOMEM;
1508 }
1509
1510 dma_cap_zero(dma_mask);
1511 dma_cap_set(DMA_MEMCPY, dma_mask);
1512 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1513 if (IS_ERR(dsi->reg_dma_chan)) {
1514 ret = PTR_ERR(dsi->reg_dma_chan);
1515 if (ret != -EPROBE_DEFER)
1516 DRM_ERROR("Failed to get DMA channel: %d\n",
1517 ret);
1518 return ret;
1519 }
1520
1521 /* Get the physical address of the device's registers. The
1522 * struct resource for the regs gives us the bus address
1523 * instead.
1524 */
1525 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1526 0, NULL, NULL));
1527 }
1528
1529 init_completion(&dsi->xfer_completion);
1530 /* At startup enable error-reporting interrupts and nothing else. */
1531 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1532 /* Clear any existing interrupt state. */
1533 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1534
1535 if (dsi->reg_dma_mem)
1536 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1537 vc4_dsi_irq_defer_to_thread_handler,
1538 vc4_dsi_irq_handler,
1539 IRQF_ONESHOT,
1540 "vc4 dsi", dsi);
1541 else
1542 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1543 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1544 if (ret) {
1545 if (ret != -EPROBE_DEFER)
1546 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1547 return ret;
1548 }
1549
1550 dsi->escape_clock = devm_clk_get(dev, "escape");
1551 if (IS_ERR(dsi->escape_clock)) {
1552 ret = PTR_ERR(dsi->escape_clock);
1553 if (ret != -EPROBE_DEFER)
1554 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1555 return ret;
1556 }
1557
1558 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1559 if (IS_ERR(dsi->pll_phy_clock)) {
1560 ret = PTR_ERR(dsi->pll_phy_clock);
1561 if (ret != -EPROBE_DEFER)
1562 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1563 return ret;
1564 }
1565
1566 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1567 if (IS_ERR(dsi->pixel_clock)) {
1568 ret = PTR_ERR(dsi->pixel_clock);
1569 if (ret != -EPROBE_DEFER)
1570 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1571 return ret;
1572 }
1573
1574 ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1575 &panel, &dsi->bridge);
1576 if (ret) {
1577 /* If the bridge or panel pointed by dev->of_node is not
1578 * enabled, just return 0 here so that we don't prevent the DRM
1579 * dev from being registered. Of course that means the DSI
1580 * encoder won't be exposed, but that's not a problem since
1581 * nothing is connected to it.
1582 */
1583 if (ret == -ENODEV)
1584 return 0;
1585
1586 return ret;
1587 }
1588
1589 if (panel) {
1590 dsi->bridge = devm_drm_panel_bridge_add_typed(dev, panel,
1591 DRM_MODE_CONNECTOR_DSI);
1592 if (IS_ERR(dsi->bridge))
1593 return PTR_ERR(dsi->bridge);
1594 }
1595
1596 /* The esc clock rate is supposed to always be 100Mhz. */
1597 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1598 if (ret) {
1599 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1600 return ret;
1601 }
1602
1603 ret = vc4_dsi_init_phy_clocks(dsi);
1604 if (ret)
1605 return ret;
1606
1607 if (dsi->port == 1)
1608 vc4->dsi1 = dsi;
1609
1610 drm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI);
1611 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1612
1613 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL, 0);
1614 if (ret) {
1615 dev_err(dev, "bridge attach failed: %d\n", ret);
1616 return ret;
1617 }
1618 /* Disable the atomic helper calls into the bridge. We
1619 * manually call the bridge pre_enable / enable / etc. calls
1620 * from our driver, since we need to sequence them within the
1621 * encoder's enable/disable paths.
1622 */
1623 list_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain);
1624
1625 if (dsi->port == 0)
1626 vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset);
1627 else
1628 vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset);
1629
1630 pm_runtime_enable(dev);
1631
1632 return 0;
1633}
1634
1635static void vc4_dsi_unbind(struct device *dev, struct device *master,
1636 void *data)
1637{
1638 struct drm_device *drm = dev_get_drvdata(master);
1639 struct vc4_dev *vc4 = to_vc4_dev(drm);
1640 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1641
1642 if (dsi->bridge)
1643 pm_runtime_disable(dev);
1644
1645 /*
1646 * Restore the bridge_chain so the bridge detach procedure can happen
1647 * normally.
1648 */
1649 list_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain);
1650 drm_encoder_cleanup(dsi->encoder);
1651
1652 if (dsi->port == 1)
1653 vc4->dsi1 = NULL;
1654}
1655
1656static const struct component_ops vc4_dsi_ops = {
1657 .bind = vc4_dsi_bind,
1658 .unbind = vc4_dsi_unbind,
1659};
1660
1661static int vc4_dsi_dev_probe(struct platform_device *pdev)
1662{
1663 struct device *dev = &pdev->dev;
1664 struct vc4_dsi *dsi;
1665 int ret;
1666
1667 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1668 if (!dsi)
1669 return -ENOMEM;
1670 dev_set_drvdata(dev, dsi);
1671
1672 dsi->pdev = pdev;
1673
1674 /* Note, the initialization sequence for DSI and panels is
1675 * tricky. The component bind above won't get past its
1676 * -EPROBE_DEFER until the panel/bridge probes. The
1677 * panel/bridge will return -EPROBE_DEFER until it has a
1678 * mipi_dsi_host to register its device to. So, we register
1679 * the host during pdev probe time, so vc4 as a whole can then
1680 * -EPROBE_DEFER its component bind process until the panel
1681 * successfully attaches.
1682 */
1683 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1684 dsi->dsi_host.dev = dev;
1685 mipi_dsi_host_register(&dsi->dsi_host);
1686
1687 ret = component_add(&pdev->dev, &vc4_dsi_ops);
1688 if (ret) {
1689 mipi_dsi_host_unregister(&dsi->dsi_host);
1690 return ret;
1691 }
1692
1693 return 0;
1694}
1695
1696static int vc4_dsi_dev_remove(struct platform_device *pdev)
1697{
1698 struct device *dev = &pdev->dev;
1699 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1700
1701 component_del(&pdev->dev, &vc4_dsi_ops);
1702 mipi_dsi_host_unregister(&dsi->dsi_host);
1703
1704 return 0;
1705}
1706
1707struct platform_driver vc4_dsi_driver = {
1708 .probe = vc4_dsi_dev_probe,
1709 .remove = vc4_dsi_dev_remove,
1710 .driver = {
1711 .name = "vc4_dsi",
1712 .of_match_table = vc4_dsi_dt_match,
1713 },
1714};