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1/*
2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
3 *
4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
5 *
6 * Adapted from mac_scsinew.c:
7 */
8/*
9 * Generic Macintosh NCR5380 driver
10 *
11 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
12 *
13 * derived in part from:
14 */
15/*
16 * Generic Generic NCR5380 driver
17 *
18 * Copyright 1995, Russell King
19 *
20 * ALPHA RELEASE 1.
21 *
22 * For more information, please consult
23 *
24 * NCR 5380 Family
25 * SCSI Protocol Controller
26 * Databook
27 *
28 * NCR Microelectronics
29 * 1635 Aeroplaza Drive
30 * Colorado Springs, CO 80916
31 * 1+ (719) 578-3400
32 * 1+ (800) 334-5454
33 */
34
35
36/*
37 * This is from mac_scsi.h, but hey, maybe this is useful for Sun3 too! :)
38 *
39 * Options :
40 *
41 * PARITY - enable parity checking. Not supported.
42 *
43 * SCSI2 - enable support for SCSI-II tagged queueing. Untested.
44 *
45 * USLEEP - enable support for devices that don't disconnect. Untested.
46 */
47
48/*
49 * $Log: sun3_NCR5380.c,v $
50 */
51
52#define AUTOSENSE
53
54#include <linux/types.h>
55#include <linux/stddef.h>
56#include <linux/ctype.h>
57#include <linux/delay.h>
58
59#include <linux/module.h>
60#include <linux/signal.h>
61#include <linux/ioport.h>
62#include <linux/init.h>
63#include <linux/blkdev.h>
64
65#include <asm/io.h>
66#include <asm/system.h>
67
68#include <asm/sun3ints.h>
69#include <asm/dvma.h>
70#include <asm/idprom.h>
71#include <asm/machines.h>
72
73#define NDEBUG 0
74
75#define NDEBUG_ABORT 0x00100000
76#define NDEBUG_TAGS 0x00200000
77#define NDEBUG_MERGING 0x00400000
78
79/* dma on! */
80#define REAL_DMA
81
82#include "scsi.h"
83#include "initio.h"
84#include <scsi/scsi_host.h>
85#include "sun3_scsi.h"
86
87static void NCR5380_print(struct Scsi_Host *instance);
88
89/* #define OLDDMA */
90
91#define USE_WRAPPER
92/*#define RESET_BOOT */
93#define DRIVER_SETUP
94
95/*
96 * BUG can be used to trigger a strange code-size related hang on 2.1 kernels
97 */
98#ifdef BUG
99#undef RESET_BOOT
100#undef DRIVER_SETUP
101#endif
102
103/* #define SUPPORT_TAGS */
104
105#define ENABLE_IRQ() enable_irq( IRQ_SUN3_SCSI );
106
107
108static irqreturn_t scsi_sun3_intr(int irq, void *dummy);
109static inline unsigned char sun3scsi_read(int reg);
110static inline void sun3scsi_write(int reg, int value);
111
112static int setup_can_queue = -1;
113module_param(setup_can_queue, int, 0);
114static int setup_cmd_per_lun = -1;
115module_param(setup_cmd_per_lun, int, 0);
116static int setup_sg_tablesize = -1;
117module_param(setup_sg_tablesize, int, 0);
118#ifdef SUPPORT_TAGS
119static int setup_use_tagged_queuing = -1;
120module_param(setup_use_tagged_queuing, int, 0);
121#endif
122static int setup_hostid = -1;
123module_param(setup_hostid, int, 0);
124
125static struct scsi_cmnd *sun3_dma_setup_done = NULL;
126
127#define AFTER_RESET_DELAY (HZ/2)
128
129/* ms to wait after hitting dma regs */
130#define SUN3_DMA_DELAY 10
131
132/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
133#define SUN3_DVMA_BUFSIZE 0xe000
134
135/* minimum number of bytes to do dma on */
136#define SUN3_DMA_MINSIZE 128
137
138static volatile unsigned char *sun3_scsi_regp;
139static volatile struct sun3_dma_regs *dregs;
140#ifdef OLDDMA
141static unsigned char *dmabuf = NULL; /* dma memory buffer */
142#endif
143static struct sun3_udc_regs *udc_regs = NULL;
144static unsigned char *sun3_dma_orig_addr = NULL;
145static unsigned long sun3_dma_orig_count = 0;
146static int sun3_dma_active = 0;
147static unsigned long last_residual = 0;
148
149/*
150 * NCR 5380 register access functions
151 */
152
153static inline unsigned char sun3scsi_read(int reg)
154{
155 return( sun3_scsi_regp[reg] );
156}
157
158static inline void sun3scsi_write(int reg, int value)
159{
160 sun3_scsi_regp[reg] = value;
161}
162
163/* dma controller register access functions */
164
165static inline unsigned short sun3_udc_read(unsigned char reg)
166{
167 unsigned short ret;
168
169 dregs->udc_addr = UDC_CSR;
170 udelay(SUN3_DMA_DELAY);
171 ret = dregs->udc_data;
172 udelay(SUN3_DMA_DELAY);
173
174 return ret;
175}
176
177static inline void sun3_udc_write(unsigned short val, unsigned char reg)
178{
179 dregs->udc_addr = reg;
180 udelay(SUN3_DMA_DELAY);
181 dregs->udc_data = val;
182 udelay(SUN3_DMA_DELAY);
183}
184
185/*
186 * XXX: status debug
187 */
188static struct Scsi_Host *default_instance;
189
190/*
191 * Function : int sun3scsi_detect(struct scsi_host_template * tpnt)
192 *
193 * Purpose : initializes mac NCR5380 driver based on the
194 * command line / compile time port and irq definitions.
195 *
196 * Inputs : tpnt - template for this SCSI adapter.
197 *
198 * Returns : 1 if a host adapter was found, 0 if not.
199 *
200 */
201
202int __init sun3scsi_detect(struct scsi_host_template * tpnt)
203{
204 unsigned long ioaddr;
205 static int called = 0;
206 struct Scsi_Host *instance;
207
208 /* check that this machine has an onboard 5380 */
209 switch(idprom->id_machtype) {
210 case SM_SUN3|SM_3_50:
211 case SM_SUN3|SM_3_60:
212 break;
213
214 default:
215 return 0;
216 }
217
218 if(called)
219 return 0;
220
221 tpnt->proc_name = "Sun3 5380 SCSI";
222
223 /* setup variables */
224 tpnt->can_queue =
225 (setup_can_queue > 0) ? setup_can_queue : CAN_QUEUE;
226 tpnt->cmd_per_lun =
227 (setup_cmd_per_lun > 0) ? setup_cmd_per_lun : CMD_PER_LUN;
228 tpnt->sg_tablesize =
229 (setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_TABLESIZE;
230
231 if (setup_hostid >= 0)
232 tpnt->this_id = setup_hostid;
233 else {
234 /* use 7 as default */
235 tpnt->this_id = 7;
236 }
237
238 ioaddr = (unsigned long)ioremap(IOBASE_SUN3_SCSI, PAGE_SIZE);
239 sun3_scsi_regp = (unsigned char *)ioaddr;
240
241 dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);
242
243 if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)))
244 == NULL) {
245 printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
246 return 0;
247 }
248#ifdef OLDDMA
249 if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) {
250 printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
251 return 0;
252 }
253#endif
254#ifdef SUPPORT_TAGS
255 if (setup_use_tagged_queuing < 0)
256 setup_use_tagged_queuing = USE_TAGGED_QUEUING;
257#endif
258
259 instance = scsi_register (tpnt, sizeof(struct NCR5380_hostdata));
260 if(instance == NULL)
261 return 0;
262
263 default_instance = instance;
264
265 instance->io_port = (unsigned long) ioaddr;
266 instance->irq = IRQ_SUN3_SCSI;
267
268 NCR5380_init(instance, 0);
269
270 instance->n_io_port = 32;
271
272 ((struct NCR5380_hostdata *)instance->hostdata)->ctrl = 0;
273
274 if (request_irq(instance->irq, scsi_sun3_intr,
275 0, "Sun3SCSI-5380", instance)) {
276#ifndef REAL_DMA
277 printk("scsi%d: IRQ%d not free, interrupts disabled\n",
278 instance->host_no, instance->irq);
279 instance->irq = SCSI_IRQ_NONE;
280#else
281 printk("scsi%d: IRQ%d not free, bailing out\n",
282 instance->host_no, instance->irq);
283 return 0;
284#endif
285 }
286
287 printk("scsi%d: Sun3 5380 at port %lX irq", instance->host_no, instance->io_port);
288 if (instance->irq == SCSI_IRQ_NONE)
289 printk ("s disabled");
290 else
291 printk (" %d", instance->irq);
292 printk(" options CAN_QUEUE=%d CMD_PER_LUN=%d release=%d",
293 instance->can_queue, instance->cmd_per_lun,
294 SUN3SCSI_PUBLIC_RELEASE);
295 printk("\nscsi%d:", instance->host_no);
296 NCR5380_print_options(instance);
297 printk("\n");
298
299 dregs->csr = 0;
300 udelay(SUN3_DMA_DELAY);
301 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
302 udelay(SUN3_DMA_DELAY);
303 dregs->fifo_count = 0;
304
305 called = 1;
306
307#ifdef RESET_BOOT
308 sun3_scsi_reset_boot(instance);
309#endif
310
311 return 1;
312}
313
314int sun3scsi_release (struct Scsi_Host *shpnt)
315{
316 if (shpnt->irq != SCSI_IRQ_NONE)
317 free_irq(shpnt->irq, shpnt);
318
319 iounmap((void *)sun3_scsi_regp);
320
321 NCR5380_exit(shpnt);
322 return 0;
323}
324
325#ifdef RESET_BOOT
326/*
327 * Our 'bus reset on boot' function
328 */
329
330static void sun3_scsi_reset_boot(struct Scsi_Host *instance)
331{
332 unsigned long end;
333
334 NCR5380_local_declare();
335 NCR5380_setup(instance);
336
337 /*
338 * Do a SCSI reset to clean up the bus during initialization. No
339 * messing with the queues, interrupts, or locks necessary here.
340 */
341
342 printk( "Sun3 SCSI: resetting the SCSI bus..." );
343
344 /* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */
345// sun3_disable_irq( IRQ_SUN3_SCSI );
346
347 /* get in phase */
348 NCR5380_write( TARGET_COMMAND_REG,
349 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
350
351 /* assert RST */
352 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
353
354 /* The min. reset hold time is 25us, so 40us should be enough */
355 udelay( 50 );
356
357 /* reset RST and interrupt */
358 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
359 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
360
361 for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
362 barrier();
363
364 /* switch on SCSI IRQ again */
365// sun3_enable_irq( IRQ_SUN3_SCSI );
366
367 printk( " done\n" );
368}
369#endif
370
371const char * sun3scsi_info (struct Scsi_Host *spnt) {
372 return "";
373}
374
375// safe bits for the CSR
376#define CSR_GOOD 0x060f
377
378static irqreturn_t scsi_sun3_intr(int irq, void *dummy)
379{
380 unsigned short csr = dregs->csr;
381 int handled = 0;
382
383 if(csr & ~CSR_GOOD) {
384 if(csr & CSR_DMA_BUSERR) {
385 printk("scsi%d: bus error in dma\n", default_instance->host_no);
386 }
387
388 if(csr & CSR_DMA_CONFLICT) {
389 printk("scsi%d: dma conflict\n", default_instance->host_no);
390 }
391 handled = 1;
392 }
393
394 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
395 NCR5380_intr(irq, dummy);
396 handled = 1;
397 }
398
399 return IRQ_RETVAL(handled);
400}
401
402/*
403 * Debug stuff - to be called on NMI, or sysrq key. Use at your own risk;
404 * reentering NCR5380_print_status seems to have ugly side effects
405 */
406
407/* this doesn't seem to get used at all -- sam */
408#if 0
409void sun3_sun3_debug (void)
410{
411 unsigned long flags;
412 NCR5380_local_declare();
413
414 if (default_instance) {
415 local_irq_save(flags);
416 NCR5380_print_status(default_instance);
417 local_irq_restore(flags);
418 }
419}
420#endif
421
422
423/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
424static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag)
425{
426#ifdef OLDDMA
427 if(write_flag)
428 memcpy(dmabuf, data, count);
429 else {
430 sun3_dma_orig_addr = data;
431 sun3_dma_orig_count = count;
432 }
433#else
434 void *addr;
435
436 if(sun3_dma_orig_addr != NULL)
437 dvma_unmap(sun3_dma_orig_addr);
438
439// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf);
440 addr = (void *)dvma_map((unsigned long) data, count);
441
442 sun3_dma_orig_addr = addr;
443 sun3_dma_orig_count = count;
444#endif
445 dregs->fifo_count = 0;
446 sun3_udc_write(UDC_RESET, UDC_CSR);
447
448 /* reset fifo */
449 dregs->csr &= ~CSR_FIFO;
450 dregs->csr |= CSR_FIFO;
451
452 /* set direction */
453 if(write_flag)
454 dregs->csr |= CSR_SEND;
455 else
456 dregs->csr &= ~CSR_SEND;
457
458 /* byte count for fifo */
459 dregs->fifo_count = count;
460
461 sun3_udc_write(UDC_RESET, UDC_CSR);
462
463 /* reset fifo */
464 dregs->csr &= ~CSR_FIFO;
465 dregs->csr |= CSR_FIFO;
466
467 if(dregs->fifo_count != count) {
468 printk("scsi%d: fifo_mismatch %04x not %04x\n",
469 default_instance->host_no, dregs->fifo_count,
470 (unsigned int) count);
471 NCR5380_print(default_instance);
472 }
473
474 /* setup udc */
475#ifdef OLDDMA
476 udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8);
477 udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff);
478#else
479 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
480 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
481#endif
482 udc_regs->count = count/2; /* count in words */
483 udc_regs->mode_hi = UDC_MODE_HIWORD;
484 if(write_flag) {
485 if(count & 1)
486 udc_regs->count++;
487 udc_regs->mode_lo = UDC_MODE_LSEND;
488 udc_regs->rsel = UDC_RSEL_SEND;
489 } else {
490 udc_regs->mode_lo = UDC_MODE_LRECV;
491 udc_regs->rsel = UDC_RSEL_RECV;
492 }
493
494 /* announce location of regs block */
495 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
496 UDC_CHN_HI);
497
498 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
499
500 /* set dma master on */
501 sun3_udc_write(0xd, UDC_MODE);
502
503 /* interrupt enable */
504 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
505
506 return count;
507
508}
509
510static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance)
511{
512 unsigned short resid;
513
514 dregs->udc_addr = 0x32;
515 udelay(SUN3_DMA_DELAY);
516 resid = dregs->udc_data;
517 udelay(SUN3_DMA_DELAY);
518 resid *= 2;
519
520 return (unsigned long) resid;
521}
522
523static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
524{
525 return last_residual;
526}
527
528static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted,
529 struct scsi_cmnd *cmd,
530 int write_flag)
531{
532 if (cmd->request->cmd_type == REQ_TYPE_FS)
533 return wanted;
534 else
535 return 0;
536}
537
538static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
539{
540
541 sun3_udc_write(UDC_CHN_START, UDC_CSR);
542
543 return 0;
544}
545
546/* clean up after our dma is done */
547static int sun3scsi_dma_finish(int write_flag)
548{
549 unsigned short count;
550 unsigned short fifo;
551 int ret = 0;
552
553 sun3_dma_active = 0;
554#if 1
555 // check to empty the fifo on a read
556 if(!write_flag) {
557 int tmo = 20000; /* .2 sec */
558
559 while(1) {
560 if(dregs->csr & CSR_FIFO_EMPTY)
561 break;
562
563 if(--tmo <= 0) {
564 printk("sun3scsi: fifo failed to empty!\n");
565 return 1;
566 }
567 udelay(10);
568 }
569 }
570
571#endif
572
573 count = sun3scsi_dma_count(default_instance);
574#ifdef OLDDMA
575
576 /* if we've finished a read, copy out the data we read */
577 if(sun3_dma_orig_addr) {
578 /* check for residual bytes after dma end */
579 if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
580 (BASR_PHASE_MATCH | BASR_ACK))) {
581 printk("scsi%d: sun3_scsi_finish: read overrun baby... ", default_instance->host_no);
582 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
583 ret = count;
584 }
585
586 /* copy in what we dma'd no matter what */
587 memcpy(sun3_dma_orig_addr, dmabuf, sun3_dma_orig_count);
588 sun3_dma_orig_addr = NULL;
589
590 }
591#else
592
593 fifo = dregs->fifo_count;
594 last_residual = fifo;
595
596 /* empty bytes from the fifo which didn't make it */
597 if((!write_flag) && (count - fifo) == 2) {
598 unsigned short data;
599 unsigned char *vaddr;
600
601 data = dregs->fifo_data;
602 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
603
604 vaddr += (sun3_dma_orig_count - fifo);
605
606 vaddr[-2] = (data & 0xff00) >> 8;
607 vaddr[-1] = (data & 0xff);
608 }
609
610 dvma_unmap(sun3_dma_orig_addr);
611 sun3_dma_orig_addr = NULL;
612#endif
613 sun3_udc_write(UDC_RESET, UDC_CSR);
614 dregs->fifo_count = 0;
615 dregs->csr &= ~CSR_SEND;
616
617 /* reset fifo */
618 dregs->csr &= ~CSR_FIFO;
619 dregs->csr |= CSR_FIFO;
620
621 sun3_dma_setup_done = NULL;
622
623 return ret;
624
625}
626
627#include "sun3_NCR5380.c"
628
629static struct scsi_host_template driver_template = {
630 .name = SUN3_SCSI_NAME,
631 .detect = sun3scsi_detect,
632 .release = sun3scsi_release,
633 .info = sun3scsi_info,
634 .queuecommand = sun3scsi_queue_command,
635 .eh_abort_handler = sun3scsi_abort,
636 .eh_bus_reset_handler = sun3scsi_bus_reset,
637 .can_queue = CAN_QUEUE,
638 .this_id = 7,
639 .sg_tablesize = SG_TABLESIZE,
640 .cmd_per_lun = CMD_PER_LUN,
641 .use_clustering = DISABLE_CLUSTERING
642};
643
644
645#include "scsi_module.c"
646
647MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
4 *
5 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
6 *
7 * VME support added by Sam Creasey
8 *
9 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
10 *
11 * Adapted from mac_scsinew.c:
12 */
13/*
14 * Generic Macintosh NCR5380 driver
15 *
16 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
17 *
18 * derived in part from:
19 */
20/*
21 * Generic Generic NCR5380 driver
22 *
23 * Copyright 1995, Russell King
24 */
25
26#include <linux/types.h>
27#include <linux/delay.h>
28#include <linux/module.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/platform_device.h>
33
34#include <asm/io.h>
35#include <asm/dvma.h>
36
37#include <scsi/scsi_host.h>
38
39/* minimum number of bytes to do dma on */
40#define DMA_MIN_SIZE 129
41
42/* Definitions for the core NCR5380 driver. */
43
44#define NCR5380_implementation_fields /* none */
45
46#define NCR5380_read(reg) in_8(hostdata->io + (reg))
47#define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
48
49#define NCR5380_queue_command sun3scsi_queue_command
50#define NCR5380_host_reset sun3scsi_host_reset
51#define NCR5380_abort sun3scsi_abort
52#define NCR5380_info sun3scsi_info
53
54#define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
55#define NCR5380_dma_recv_setup sun3scsi_dma_count
56#define NCR5380_dma_send_setup sun3scsi_dma_count
57#define NCR5380_dma_residual sun3scsi_dma_residual
58
59#include "NCR5380.h"
60
61/* dma regs start at regbase + 8, directly after the NCR regs */
62struct sun3_dma_regs {
63 unsigned short dma_addr_hi; /* vme only */
64 unsigned short dma_addr_lo; /* vme only */
65 unsigned short dma_count_hi; /* vme only */
66 unsigned short dma_count_lo; /* vme only */
67 unsigned short udc_data; /* udc dma data reg (obio only) */
68 unsigned short udc_addr; /* uda dma addr reg (obio only) */
69 unsigned short fifo_data; /* fifo data reg,
70 * holds extra byte on odd dma reads
71 */
72 unsigned short fifo_count;
73 unsigned short csr; /* control/status reg */
74 unsigned short bpack_hi; /* vme only */
75 unsigned short bpack_lo; /* vme only */
76 unsigned short ivect; /* vme only */
77 unsigned short fifo_count_hi; /* vme only */
78};
79
80/* ucd chip specific regs - live in dvma space */
81struct sun3_udc_regs {
82 unsigned short rsel; /* select regs to load */
83 unsigned short addr_hi; /* high word of addr */
84 unsigned short addr_lo; /* low word */
85 unsigned short count; /* words to be xfer'd */
86 unsigned short mode_hi; /* high word of channel mode */
87 unsigned short mode_lo; /* low word of channel mode */
88};
89
90/* addresses of the udc registers */
91#define UDC_MODE 0x38
92#define UDC_CSR 0x2e /* command/status */
93#define UDC_CHN_HI 0x26 /* chain high word */
94#define UDC_CHN_LO 0x22 /* chain lo word */
95#define UDC_CURA_HI 0x1a /* cur reg A high */
96#define UDC_CURA_LO 0x0a /* cur reg A low */
97#define UDC_CURB_HI 0x12 /* cur reg B high */
98#define UDC_CURB_LO 0x02 /* cur reg B low */
99#define UDC_MODE_HI 0x56 /* mode reg high */
100#define UDC_MODE_LO 0x52 /* mode reg low */
101#define UDC_COUNT 0x32 /* words to xfer */
102
103/* some udc commands */
104#define UDC_RESET 0
105#define UDC_CHN_START 0xa0 /* start chain */
106#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
107
108/* udc mode words */
109#define UDC_MODE_HIWORD 0x40
110#define UDC_MODE_LSEND 0xc2
111#define UDC_MODE_LRECV 0xd2
112
113/* udc reg selections */
114#define UDC_RSEL_SEND 0x282
115#define UDC_RSEL_RECV 0x182
116
117/* bits in csr reg */
118#define CSR_DMA_ACTIVE 0x8000
119#define CSR_DMA_CONFLICT 0x4000
120#define CSR_DMA_BUSERR 0x2000
121
122#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
123#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
124#define CSR_DMA_INT 0x100 /* dma interrupt pending */
125
126#define CSR_LEFT 0xc0
127#define CSR_LEFT_3 0xc0
128#define CSR_LEFT_2 0x80
129#define CSR_LEFT_1 0x40
130#define CSR_PACK_ENABLE 0x20
131
132#define CSR_DMA_ENABLE 0x10
133
134#define CSR_SEND 0x8 /* 1 = send 0 = recv */
135#define CSR_FIFO 0x2 /* reset fifo */
136#define CSR_INTR 0x4 /* interrupt enable */
137#define CSR_SCSI 0x1
138
139#define VME_DATA24 0x3d00
140
141extern int sun3_map_test(unsigned long, char *);
142
143static int setup_can_queue = -1;
144module_param(setup_can_queue, int, 0);
145static int setup_cmd_per_lun = -1;
146module_param(setup_cmd_per_lun, int, 0);
147static int setup_sg_tablesize = -1;
148module_param(setup_sg_tablesize, int, 0);
149static int setup_hostid = -1;
150module_param(setup_hostid, int, 0);
151
152/* ms to wait after hitting dma regs */
153#define SUN3_DMA_DELAY 10
154
155/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
156#define SUN3_DVMA_BUFSIZE 0xe000
157
158static struct scsi_cmnd *sun3_dma_setup_done;
159static volatile struct sun3_dma_regs *dregs;
160static struct sun3_udc_regs *udc_regs;
161static unsigned char *sun3_dma_orig_addr;
162static unsigned long sun3_dma_orig_count;
163static int sun3_dma_active;
164static unsigned long last_residual;
165
166#ifndef SUN3_SCSI_VME
167/* dma controller register access functions */
168
169static inline unsigned short sun3_udc_read(unsigned char reg)
170{
171 unsigned short ret;
172
173 dregs->udc_addr = UDC_CSR;
174 udelay(SUN3_DMA_DELAY);
175 ret = dregs->udc_data;
176 udelay(SUN3_DMA_DELAY);
177
178 return ret;
179}
180
181static inline void sun3_udc_write(unsigned short val, unsigned char reg)
182{
183 dregs->udc_addr = reg;
184 udelay(SUN3_DMA_DELAY);
185 dregs->udc_data = val;
186 udelay(SUN3_DMA_DELAY);
187}
188#endif
189
190// safe bits for the CSR
191#define CSR_GOOD 0x060f
192
193static irqreturn_t scsi_sun3_intr(int irq, void *dev)
194{
195 struct Scsi_Host *instance = dev;
196 unsigned short csr = dregs->csr;
197 int handled = 0;
198
199#ifdef SUN3_SCSI_VME
200 dregs->csr &= ~CSR_DMA_ENABLE;
201#endif
202
203 if(csr & ~CSR_GOOD) {
204 if (csr & CSR_DMA_BUSERR)
205 shost_printk(KERN_ERR, instance, "bus error in DMA\n");
206 if (csr & CSR_DMA_CONFLICT)
207 shost_printk(KERN_ERR, instance, "DMA conflict\n");
208 handled = 1;
209 }
210
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
212 NCR5380_intr(irq, dev);
213 handled = 1;
214 }
215
216 return IRQ_RETVAL(handled);
217}
218
219/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
220static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
221 unsigned char *data, int count, int write_flag)
222{
223 void *addr;
224
225 if(sun3_dma_orig_addr != NULL)
226 dvma_unmap(sun3_dma_orig_addr);
227
228#ifdef SUN3_SCSI_VME
229 addr = (void *)dvma_map_vme((unsigned long) data, count);
230#else
231 addr = (void *)dvma_map((unsigned long) data, count);
232#endif
233
234 sun3_dma_orig_addr = addr;
235 sun3_dma_orig_count = count;
236
237#ifndef SUN3_SCSI_VME
238 dregs->fifo_count = 0;
239 sun3_udc_write(UDC_RESET, UDC_CSR);
240
241 /* reset fifo */
242 dregs->csr &= ~CSR_FIFO;
243 dregs->csr |= CSR_FIFO;
244#endif
245
246 /* set direction */
247 if(write_flag)
248 dregs->csr |= CSR_SEND;
249 else
250 dregs->csr &= ~CSR_SEND;
251
252#ifdef SUN3_SCSI_VME
253 dregs->csr |= CSR_PACK_ENABLE;
254
255 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
256 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
257
258 dregs->dma_count_hi = 0;
259 dregs->dma_count_lo = 0;
260 dregs->fifo_count_hi = 0;
261 dregs->fifo_count = 0;
262#else
263 /* byte count for fifo */
264 dregs->fifo_count = count;
265
266 sun3_udc_write(UDC_RESET, UDC_CSR);
267
268 /* reset fifo */
269 dregs->csr &= ~CSR_FIFO;
270 dregs->csr |= CSR_FIFO;
271
272 if(dregs->fifo_count != count) {
273 shost_printk(KERN_ERR, hostdata->host,
274 "FIFO mismatch %04x not %04x\n",
275 dregs->fifo_count, (unsigned int) count);
276 NCR5380_dprint(NDEBUG_DMA, hostdata->host);
277 }
278
279 /* setup udc */
280 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
281 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
282 udc_regs->count = count/2; /* count in words */
283 udc_regs->mode_hi = UDC_MODE_HIWORD;
284 if(write_flag) {
285 if(count & 1)
286 udc_regs->count++;
287 udc_regs->mode_lo = UDC_MODE_LSEND;
288 udc_regs->rsel = UDC_RSEL_SEND;
289 } else {
290 udc_regs->mode_lo = UDC_MODE_LRECV;
291 udc_regs->rsel = UDC_RSEL_RECV;
292 }
293
294 /* announce location of regs block */
295 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
296 UDC_CHN_HI);
297
298 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
299
300 /* set dma master on */
301 sun3_udc_write(0xd, UDC_MODE);
302
303 /* interrupt enable */
304 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
305#endif
306
307 return count;
308
309}
310
311static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
312 unsigned char *data, int count)
313{
314 return count;
315}
316
317static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
318 unsigned char *data, int count)
319{
320 return sun3scsi_dma_setup(hostdata, data, count, 0);
321}
322
323static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
324 unsigned char *data, int count)
325{
326 return sun3scsi_dma_setup(hostdata, data, count, 1);
327}
328
329static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
330{
331 return last_residual;
332}
333
334static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
335 struct scsi_cmnd *cmd)
336{
337 int wanted_len = cmd->SCp.this_residual;
338
339 if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
340 return 0;
341
342 return wanted_len;
343}
344
345static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
346{
347#ifdef SUN3_SCSI_VME
348 unsigned short csr;
349
350 csr = dregs->csr;
351
352 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
353 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
354
355 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
356 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
357
358/* if(!(csr & CSR_DMA_ENABLE))
359 * dregs->csr |= CSR_DMA_ENABLE;
360 */
361#else
362 sun3_udc_write(UDC_CHN_START, UDC_CSR);
363#endif
364
365 return 0;
366}
367
368/* clean up after our dma is done */
369static int sun3scsi_dma_finish(int write_flag)
370{
371 unsigned short __maybe_unused count;
372 unsigned short fifo;
373 int ret = 0;
374
375 sun3_dma_active = 0;
376
377#ifdef SUN3_SCSI_VME
378 dregs->csr &= ~CSR_DMA_ENABLE;
379
380 fifo = dregs->fifo_count;
381 if (write_flag) {
382 if ((fifo > 0) && (fifo < sun3_dma_orig_count))
383 fifo++;
384 }
385
386 last_residual = fifo;
387 /* empty bytes from the fifo which didn't make it */
388 if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
389 unsigned char *vaddr;
390
391 vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
392
393 vaddr += (sun3_dma_orig_count - fifo);
394 vaddr--;
395
396 switch (dregs->csr & CSR_LEFT) {
397 case CSR_LEFT_3:
398 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
399 vaddr--;
400 fallthrough;
401
402 case CSR_LEFT_2:
403 *vaddr = (dregs->bpack_hi & 0x00ff);
404 vaddr--;
405 fallthrough;
406
407 case CSR_LEFT_1:
408 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
409 break;
410 }
411 }
412#else
413 // check to empty the fifo on a read
414 if(!write_flag) {
415 int tmo = 20000; /* .2 sec */
416
417 while(1) {
418 if(dregs->csr & CSR_FIFO_EMPTY)
419 break;
420
421 if(--tmo <= 0) {
422 printk("sun3scsi: fifo failed to empty!\n");
423 return 1;
424 }
425 udelay(10);
426 }
427 }
428
429 dregs->udc_addr = 0x32;
430 udelay(SUN3_DMA_DELAY);
431 count = 2 * dregs->udc_data;
432 udelay(SUN3_DMA_DELAY);
433
434 fifo = dregs->fifo_count;
435 last_residual = fifo;
436
437 /* empty bytes from the fifo which didn't make it */
438 if((!write_flag) && (count - fifo) == 2) {
439 unsigned short data;
440 unsigned char *vaddr;
441
442 data = dregs->fifo_data;
443 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
444
445 vaddr += (sun3_dma_orig_count - fifo);
446
447 vaddr[-2] = (data & 0xff00) >> 8;
448 vaddr[-1] = (data & 0xff);
449 }
450#endif
451
452 dvma_unmap(sun3_dma_orig_addr);
453 sun3_dma_orig_addr = NULL;
454
455#ifdef SUN3_SCSI_VME
456 dregs->dma_addr_hi = 0;
457 dregs->dma_addr_lo = 0;
458 dregs->dma_count_hi = 0;
459 dregs->dma_count_lo = 0;
460
461 dregs->fifo_count = 0;
462 dregs->fifo_count_hi = 0;
463
464 dregs->csr &= ~CSR_SEND;
465/* dregs->csr |= CSR_DMA_ENABLE; */
466#else
467 sun3_udc_write(UDC_RESET, UDC_CSR);
468 dregs->fifo_count = 0;
469 dregs->csr &= ~CSR_SEND;
470
471 /* reset fifo */
472 dregs->csr &= ~CSR_FIFO;
473 dregs->csr |= CSR_FIFO;
474#endif
475
476 sun3_dma_setup_done = NULL;
477
478 return ret;
479
480}
481
482#include "NCR5380.c"
483
484#ifdef SUN3_SCSI_VME
485#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
486#define DRV_MODULE_NAME "sun3_scsi_vme"
487#else
488#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
489#define DRV_MODULE_NAME "sun3_scsi"
490#endif
491
492#define PFX DRV_MODULE_NAME ": "
493
494static struct scsi_host_template sun3_scsi_template = {
495 .module = THIS_MODULE,
496 .proc_name = DRV_MODULE_NAME,
497 .name = SUN3_SCSI_NAME,
498 .info = sun3scsi_info,
499 .queuecommand = sun3scsi_queue_command,
500 .eh_abort_handler = sun3scsi_abort,
501 .eh_host_reset_handler = sun3scsi_host_reset,
502 .can_queue = 16,
503 .this_id = 7,
504 .sg_tablesize = 1,
505 .cmd_per_lun = 2,
506 .dma_boundary = PAGE_SIZE - 1,
507 .cmd_size = NCR5380_CMD_SIZE,
508};
509
510static int __init sun3_scsi_probe(struct platform_device *pdev)
511{
512 struct Scsi_Host *instance;
513 struct NCR5380_hostdata *hostdata;
514 int error;
515 struct resource *irq, *mem;
516 void __iomem *ioaddr;
517 int host_flags = 0;
518#ifdef SUN3_SCSI_VME
519 int i;
520#endif
521
522 if (setup_can_queue > 0)
523 sun3_scsi_template.can_queue = setup_can_queue;
524 if (setup_cmd_per_lun > 0)
525 sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
526 if (setup_sg_tablesize > 0)
527 sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
528 if (setup_hostid >= 0)
529 sun3_scsi_template.this_id = setup_hostid & 7;
530
531#ifdef SUN3_SCSI_VME
532 ioaddr = NULL;
533 for (i = 0; i < 2; i++) {
534 unsigned char x;
535
536 irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
537 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
538 if (!irq || !mem)
539 break;
540
541 ioaddr = sun3_ioremap(mem->start, resource_size(mem),
542 SUN3_PAGE_TYPE_VME16);
543 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
544
545 if (sun3_map_test((unsigned long)dregs, &x)) {
546 unsigned short oldcsr;
547
548 oldcsr = dregs->csr;
549 dregs->csr = 0;
550 udelay(SUN3_DMA_DELAY);
551 if (dregs->csr == 0x1400)
552 break;
553
554 dregs->csr = oldcsr;
555 }
556
557 iounmap(ioaddr);
558 ioaddr = NULL;
559 }
560 if (!ioaddr)
561 return -ENODEV;
562#else
563 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
564 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
565 if (!irq || !mem)
566 return -ENODEV;
567
568 ioaddr = ioremap(mem->start, resource_size(mem));
569 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
570
571 udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
572 if (!udc_regs) {
573 pr_err(PFX "couldn't allocate DVMA memory!\n");
574 iounmap(ioaddr);
575 return -ENOMEM;
576 }
577#endif
578
579 instance = scsi_host_alloc(&sun3_scsi_template,
580 sizeof(struct NCR5380_hostdata));
581 if (!instance) {
582 error = -ENOMEM;
583 goto fail_alloc;
584 }
585
586 instance->irq = irq->start;
587
588 hostdata = shost_priv(instance);
589 hostdata->base = mem->start;
590 hostdata->io = ioaddr;
591
592 error = NCR5380_init(instance, host_flags);
593 if (error)
594 goto fail_init;
595
596 error = request_irq(instance->irq, scsi_sun3_intr, 0,
597 "NCR5380", instance);
598 if (error) {
599 pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
600 instance->host_no, instance->irq);
601 goto fail_irq;
602 }
603
604 dregs->csr = 0;
605 udelay(SUN3_DMA_DELAY);
606 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
607 udelay(SUN3_DMA_DELAY);
608 dregs->fifo_count = 0;
609#ifdef SUN3_SCSI_VME
610 dregs->fifo_count_hi = 0;
611 dregs->dma_addr_hi = 0;
612 dregs->dma_addr_lo = 0;
613 dregs->dma_count_hi = 0;
614 dregs->dma_count_lo = 0;
615
616 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
617#endif
618
619 NCR5380_maybe_reset_bus(instance);
620
621 error = scsi_add_host(instance, NULL);
622 if (error)
623 goto fail_host;
624
625 platform_set_drvdata(pdev, instance);
626
627 scsi_scan_host(instance);
628 return 0;
629
630fail_host:
631 free_irq(instance->irq, instance);
632fail_irq:
633 NCR5380_exit(instance);
634fail_init:
635 scsi_host_put(instance);
636fail_alloc:
637 if (udc_regs)
638 dvma_free(udc_regs);
639 iounmap(ioaddr);
640 return error;
641}
642
643static int __exit sun3_scsi_remove(struct platform_device *pdev)
644{
645 struct Scsi_Host *instance = platform_get_drvdata(pdev);
646 struct NCR5380_hostdata *hostdata = shost_priv(instance);
647 void __iomem *ioaddr = hostdata->io;
648
649 scsi_remove_host(instance);
650 free_irq(instance->irq, instance);
651 NCR5380_exit(instance);
652 scsi_host_put(instance);
653 if (udc_regs)
654 dvma_free(udc_regs);
655 iounmap(ioaddr);
656 return 0;
657}
658
659static struct platform_driver sun3_scsi_driver = {
660 .remove = __exit_p(sun3_scsi_remove),
661 .driver = {
662 .name = DRV_MODULE_NAME,
663 },
664};
665
666module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
667
668MODULE_ALIAS("platform:" DRV_MODULE_NAME);
669MODULE_LICENSE("GPL");