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1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2008,2010 Intel Corporation
5 */
6
7#include <linux/intel-iommu.h>
8#include <linux/dma-resv.h>
9#include <linux/sync_file.h>
10#include <linux/uaccess.h>
11
12#include <drm/drm_syncobj.h>
13
14#include "display/intel_frontbuffer.h"
15
16#include "gem/i915_gem_ioctls.h"
17#include "gt/intel_context.h"
18#include "gt/intel_gt.h"
19#include "gt/intel_gt_buffer_pool.h"
20#include "gt/intel_gt_pm.h"
21#include "gt/intel_ring.h"
22
23#include "i915_drv.h"
24#include "i915_gem_clflush.h"
25#include "i915_gem_context.h"
26#include "i915_gem_ioctls.h"
27#include "i915_sw_fence_work.h"
28#include "i915_trace.h"
29
30struct eb_vma {
31 struct i915_vma *vma;
32 unsigned int flags;
33
34 /** This vma's place in the execbuf reservation list */
35 struct drm_i915_gem_exec_object2 *exec;
36 struct list_head bind_link;
37 struct list_head reloc_link;
38
39 struct hlist_node node;
40 u32 handle;
41};
42
43struct eb_vma_array {
44 struct kref kref;
45 struct eb_vma vma[];
46};
47
48enum {
49 FORCE_CPU_RELOC = 1,
50 FORCE_GTT_RELOC,
51 FORCE_GPU_RELOC,
52#define DBG_FORCE_RELOC 0 /* choose one of the above! */
53};
54
55#define __EXEC_OBJECT_HAS_PIN BIT(31)
56#define __EXEC_OBJECT_HAS_FENCE BIT(30)
57#define __EXEC_OBJECT_NEEDS_MAP BIT(29)
58#define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
59#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
60
61#define __EXEC_HAS_RELOC BIT(31)
62#define __EXEC_INTERNAL_FLAGS (~0u << 31)
63#define UPDATE PIN_OFFSET_FIXED
64
65#define BATCH_OFFSET_BIAS (256*1024)
66
67#define __I915_EXEC_ILLEGAL_FLAGS \
68 (__I915_EXEC_UNKNOWN_FLAGS | \
69 I915_EXEC_CONSTANTS_MASK | \
70 I915_EXEC_RESOURCE_STREAMER)
71
72/* Catch emission of unexpected errors for CI! */
73#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
74#undef EINVAL
75#define EINVAL ({ \
76 DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
77 22; \
78})
79#endif
80
81/**
82 * DOC: User command execution
83 *
84 * Userspace submits commands to be executed on the GPU as an instruction
85 * stream within a GEM object we call a batchbuffer. This instructions may
86 * refer to other GEM objects containing auxiliary state such as kernels,
87 * samplers, render targets and even secondary batchbuffers. Userspace does
88 * not know where in the GPU memory these objects reside and so before the
89 * batchbuffer is passed to the GPU for execution, those addresses in the
90 * batchbuffer and auxiliary objects are updated. This is known as relocation,
91 * or patching. To try and avoid having to relocate each object on the next
92 * execution, userspace is told the location of those objects in this pass,
93 * but this remains just a hint as the kernel may choose a new location for
94 * any object in the future.
95 *
96 * At the level of talking to the hardware, submitting a batchbuffer for the
97 * GPU to execute is to add content to a buffer from which the HW
98 * command streamer is reading.
99 *
100 * 1. Add a command to load the HW context. For Logical Ring Contexts, i.e.
101 * Execlists, this command is not placed on the same buffer as the
102 * remaining items.
103 *
104 * 2. Add a command to invalidate caches to the buffer.
105 *
106 * 3. Add a batchbuffer start command to the buffer; the start command is
107 * essentially a token together with the GPU address of the batchbuffer
108 * to be executed.
109 *
110 * 4. Add a pipeline flush to the buffer.
111 *
112 * 5. Add a memory write command to the buffer to record when the GPU
113 * is done executing the batchbuffer. The memory write writes the
114 * global sequence number of the request, ``i915_request::global_seqno``;
115 * the i915 driver uses the current value in the register to determine
116 * if the GPU has completed the batchbuffer.
117 *
118 * 6. Add a user interrupt command to the buffer. This command instructs
119 * the GPU to issue an interrupt when the command, pipeline flush and
120 * memory write are completed.
121 *
122 * 7. Inform the hardware of the additional commands added to the buffer
123 * (by updating the tail pointer).
124 *
125 * Processing an execbuf ioctl is conceptually split up into a few phases.
126 *
127 * 1. Validation - Ensure all the pointers, handles and flags are valid.
128 * 2. Reservation - Assign GPU address space for every object
129 * 3. Relocation - Update any addresses to point to the final locations
130 * 4. Serialisation - Order the request with respect to its dependencies
131 * 5. Construction - Construct a request to execute the batchbuffer
132 * 6. Submission (at some point in the future execution)
133 *
134 * Reserving resources for the execbuf is the most complicated phase. We
135 * neither want to have to migrate the object in the address space, nor do
136 * we want to have to update any relocations pointing to this object. Ideally,
137 * we want to leave the object where it is and for all the existing relocations
138 * to match. If the object is given a new address, or if userspace thinks the
139 * object is elsewhere, we have to parse all the relocation entries and update
140 * the addresses. Userspace can set the I915_EXEC_NORELOC flag to hint that
141 * all the target addresses in all of its objects match the value in the
142 * relocation entries and that they all match the presumed offsets given by the
143 * list of execbuffer objects. Using this knowledge, we know that if we haven't
144 * moved any buffers, all the relocation entries are valid and we can skip
145 * the update. (If userspace is wrong, the likely outcome is an impromptu GPU
146 * hang.) The requirement for using I915_EXEC_NO_RELOC are:
147 *
148 * The addresses written in the objects must match the corresponding
149 * reloc.presumed_offset which in turn must match the corresponding
150 * execobject.offset.
151 *
152 * Any render targets written to in the batch must be flagged with
153 * EXEC_OBJECT_WRITE.
154 *
155 * To avoid stalling, execobject.offset should match the current
156 * address of that object within the active context.
157 *
158 * The reservation is done is multiple phases. First we try and keep any
159 * object already bound in its current location - so as long as meets the
160 * constraints imposed by the new execbuffer. Any object left unbound after the
161 * first pass is then fitted into any available idle space. If an object does
162 * not fit, all objects are removed from the reservation and the process rerun
163 * after sorting the objects into a priority order (more difficult to fit
164 * objects are tried first). Failing that, the entire VM is cleared and we try
165 * to fit the execbuf once last time before concluding that it simply will not
166 * fit.
167 *
168 * A small complication to all of this is that we allow userspace not only to
169 * specify an alignment and a size for the object in the address space, but
170 * we also allow userspace to specify the exact offset. This objects are
171 * simpler to place (the location is known a priori) all we have to do is make
172 * sure the space is available.
173 *
174 * Once all the objects are in place, patching up the buried pointers to point
175 * to the final locations is a fairly simple job of walking over the relocation
176 * entry arrays, looking up the right address and rewriting the value into
177 * the object. Simple! ... The relocation entries are stored in user memory
178 * and so to access them we have to copy them into a local buffer. That copy
179 * has to avoid taking any pagefaults as they may lead back to a GEM object
180 * requiring the struct_mutex (i.e. recursive deadlock). So once again we split
181 * the relocation into multiple passes. First we try to do everything within an
182 * atomic context (avoid the pagefaults) which requires that we never wait. If
183 * we detect that we may wait, or if we need to fault, then we have to fallback
184 * to a slower path. The slowpath has to drop the mutex. (Can you hear alarm
185 * bells yet?) Dropping the mutex means that we lose all the state we have
186 * built up so far for the execbuf and we must reset any global data. However,
187 * we do leave the objects pinned in their final locations - which is a
188 * potential issue for concurrent execbufs. Once we have left the mutex, we can
189 * allocate and copy all the relocation entries into a large array at our
190 * leisure, reacquire the mutex, reclaim all the objects and other state and
191 * then proceed to update any incorrect addresses with the objects.
192 *
193 * As we process the relocation entries, we maintain a record of whether the
194 * object is being written to. Using NORELOC, we expect userspace to provide
195 * this information instead. We also check whether we can skip the relocation
196 * by comparing the expected value inside the relocation entry with the target's
197 * final address. If they differ, we have to map the current object and rewrite
198 * the 4 or 8 byte pointer within.
199 *
200 * Serialising an execbuf is quite simple according to the rules of the GEM
201 * ABI. Execution within each context is ordered by the order of submission.
202 * Writes to any GEM object are in order of submission and are exclusive. Reads
203 * from a GEM object are unordered with respect to other reads, but ordered by
204 * writes. A write submitted after a read cannot occur before the read, and
205 * similarly any read submitted after a write cannot occur before the write.
206 * Writes are ordered between engines such that only one write occurs at any
207 * time (completing any reads beforehand) - using semaphores where available
208 * and CPU serialisation otherwise. Other GEM access obey the same rules, any
209 * write (either via mmaps using set-domain, or via pwrite) must flush all GPU
210 * reads before starting, and any read (either using set-domain or pread) must
211 * flush all GPU writes before starting. (Note we only employ a barrier before,
212 * we currently rely on userspace not concurrently starting a new execution
213 * whilst reading or writing to an object. This may be an advantage or not
214 * depending on how much you trust userspace not to shoot themselves in the
215 * foot.) Serialisation may just result in the request being inserted into
216 * a DAG awaiting its turn, but most simple is to wait on the CPU until
217 * all dependencies are resolved.
218 *
219 * After all of that, is just a matter of closing the request and handing it to
220 * the hardware (well, leaving it in a queue to be executed). However, we also
221 * offer the ability for batchbuffers to be run with elevated privileges so
222 * that they access otherwise hidden registers. (Used to adjust L3 cache etc.)
223 * Before any batch is given extra privileges we first must check that it
224 * contains no nefarious instructions, we check that each instruction is from
225 * our whitelist and all registers are also from an allowed list. We first
226 * copy the user's batchbuffer to a shadow (so that the user doesn't have
227 * access to it, either by the CPU or GPU as we scan it) and then parse each
228 * instruction. If everything is ok, we set a flag telling the hardware to run
229 * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
230 */
231
232struct i915_execbuffer {
233 struct drm_i915_private *i915; /** i915 backpointer */
234 struct drm_file *file; /** per-file lookup tables and limits */
235 struct drm_i915_gem_execbuffer2 *args; /** ioctl parameters */
236 struct drm_i915_gem_exec_object2 *exec; /** ioctl execobj[] */
237 struct eb_vma *vma;
238
239 struct intel_engine_cs *engine; /** engine to queue the request to */
240 struct intel_context *context; /* logical state for the request */
241 struct i915_gem_context *gem_context; /** caller's context */
242
243 struct i915_request *request; /** our request to build */
244 struct eb_vma *batch; /** identity of the batch obj/vma */
245 struct i915_vma *trampoline; /** trampoline used for chaining */
246
247 /** actual size of execobj[] as we may extend it for the cmdparser */
248 unsigned int buffer_count;
249
250 /** list of vma not yet bound during reservation phase */
251 struct list_head unbound;
252
253 /** list of vma that have execobj.relocation_count */
254 struct list_head relocs;
255
256 /**
257 * Track the most recently used object for relocations, as we
258 * frequently have to perform multiple relocations within the same
259 * obj/page
260 */
261 struct reloc_cache {
262 struct drm_mm_node node; /** temporary GTT binding */
263 unsigned long vaddr; /** Current kmap address */
264 unsigned long page; /** Currently mapped page index */
265 unsigned int gen; /** Cached value of INTEL_GEN */
266 bool use_64bit_reloc : 1;
267 bool has_llc : 1;
268 bool has_fence : 1;
269 bool needs_unfenced : 1;
270
271 struct i915_vma *target;
272 struct i915_request *rq;
273 struct i915_vma *rq_vma;
274 u32 *rq_cmd;
275 unsigned int rq_size;
276 } reloc_cache;
277
278 u64 invalid_flags; /** Set of execobj.flags that are invalid */
279 u32 context_flags; /** Set of execobj.flags to insert from the ctx */
280
281 u32 batch_start_offset; /** Location within object of batch */
282 u32 batch_len; /** Length of batch within object */
283 u32 batch_flags; /** Flags composed for emit_bb_start() */
284
285 /**
286 * Indicate either the size of the hastable used to resolve
287 * relocation handles, or if negative that we are using a direct
288 * index into the execobj[].
289 */
290 int lut_size;
291 struct hlist_head *buckets; /** ht for relocation handles */
292 struct eb_vma_array *array;
293};
294
295static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
296{
297 return intel_engine_requires_cmd_parser(eb->engine) ||
298 (intel_engine_using_cmd_parser(eb->engine) &&
299 eb->args->batch_len);
300}
301
302static struct eb_vma_array *eb_vma_array_create(unsigned int count)
303{
304 struct eb_vma_array *arr;
305
306 arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN);
307 if (!arr)
308 return NULL;
309
310 kref_init(&arr->kref);
311 arr->vma[0].vma = NULL;
312
313 return arr;
314}
315
316static inline void eb_unreserve_vma(struct eb_vma *ev)
317{
318 struct i915_vma *vma = ev->vma;
319
320 if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
321 __i915_vma_unpin_fence(vma);
322
323 if (ev->flags & __EXEC_OBJECT_HAS_PIN)
324 __i915_vma_unpin(vma);
325
326 ev->flags &= ~(__EXEC_OBJECT_HAS_PIN |
327 __EXEC_OBJECT_HAS_FENCE);
328}
329
330static void eb_vma_array_destroy(struct kref *kref)
331{
332 struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref);
333 struct eb_vma *ev = arr->vma;
334
335 while (ev->vma) {
336 eb_unreserve_vma(ev);
337 i915_vma_put(ev->vma);
338 ev++;
339 }
340
341 kvfree(arr);
342}
343
344static void eb_vma_array_put(struct eb_vma_array *arr)
345{
346 kref_put(&arr->kref, eb_vma_array_destroy);
347}
348
349static int eb_create(struct i915_execbuffer *eb)
350{
351 /* Allocate an extra slot for use by the command parser + sentinel */
352 eb->array = eb_vma_array_create(eb->buffer_count + 2);
353 if (!eb->array)
354 return -ENOMEM;
355
356 eb->vma = eb->array->vma;
357
358 if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
359 unsigned int size = 1 + ilog2(eb->buffer_count);
360
361 /*
362 * Without a 1:1 association between relocation handles and
363 * the execobject[] index, we instead create a hashtable.
364 * We size it dynamically based on available memory, starting
365 * first with 1:1 assocative hash and scaling back until
366 * the allocation succeeds.
367 *
368 * Later on we use a positive lut_size to indicate we are
369 * using this hashtable, and a negative value to indicate a
370 * direct lookup.
371 */
372 do {
373 gfp_t flags;
374
375 /* While we can still reduce the allocation size, don't
376 * raise a warning and allow the allocation to fail.
377 * On the last pass though, we want to try as hard
378 * as possible to perform the allocation and warn
379 * if it fails.
380 */
381 flags = GFP_KERNEL;
382 if (size > 1)
383 flags |= __GFP_NORETRY | __GFP_NOWARN;
384
385 eb->buckets = kzalloc(sizeof(struct hlist_head) << size,
386 flags);
387 if (eb->buckets)
388 break;
389 } while (--size);
390
391 if (unlikely(!size)) {
392 eb_vma_array_put(eb->array);
393 return -ENOMEM;
394 }
395
396 eb->lut_size = size;
397 } else {
398 eb->lut_size = -eb->buffer_count;
399 }
400
401 return 0;
402}
403
404static bool
405eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
406 const struct i915_vma *vma,
407 unsigned int flags)
408{
409 if (vma->node.size < entry->pad_to_size)
410 return true;
411
412 if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment))
413 return true;
414
415 if (flags & EXEC_OBJECT_PINNED &&
416 vma->node.start != entry->offset)
417 return true;
418
419 if (flags & __EXEC_OBJECT_NEEDS_BIAS &&
420 vma->node.start < BATCH_OFFSET_BIAS)
421 return true;
422
423 if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) &&
424 (vma->node.start + vma->node.size - 1) >> 32)
425 return true;
426
427 if (flags & __EXEC_OBJECT_NEEDS_MAP &&
428 !i915_vma_is_map_and_fenceable(vma))
429 return true;
430
431 return false;
432}
433
434static u64 eb_pin_flags(const struct drm_i915_gem_exec_object2 *entry,
435 unsigned int exec_flags)
436{
437 u64 pin_flags = 0;
438
439 if (exec_flags & EXEC_OBJECT_NEEDS_GTT)
440 pin_flags |= PIN_GLOBAL;
441
442 /*
443 * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
444 * limit address to the first 4GBs for unflagged objects.
445 */
446 if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
447 pin_flags |= PIN_ZONE_4G;
448
449 if (exec_flags & __EXEC_OBJECT_NEEDS_MAP)
450 pin_flags |= PIN_MAPPABLE;
451
452 if (exec_flags & EXEC_OBJECT_PINNED)
453 pin_flags |= entry->offset | PIN_OFFSET_FIXED;
454 else if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS)
455 pin_flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
456
457 return pin_flags;
458}
459
460static inline bool
461eb_pin_vma(struct i915_execbuffer *eb,
462 const struct drm_i915_gem_exec_object2 *entry,
463 struct eb_vma *ev)
464{
465 struct i915_vma *vma = ev->vma;
466 u64 pin_flags;
467
468 if (vma->node.size)
469 pin_flags = vma->node.start;
470 else
471 pin_flags = entry->offset & PIN_OFFSET_MASK;
472
473 pin_flags |= PIN_USER | PIN_NOEVICT | PIN_OFFSET_FIXED;
474 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_GTT))
475 pin_flags |= PIN_GLOBAL;
476
477 /* Attempt to reuse the current location if available */
478 if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) {
479 if (entry->flags & EXEC_OBJECT_PINNED)
480 return false;
481
482 /* Failing that pick any _free_ space if suitable */
483 if (unlikely(i915_vma_pin(vma,
484 entry->pad_to_size,
485 entry->alignment,
486 eb_pin_flags(entry, ev->flags) |
487 PIN_USER | PIN_NOEVICT)))
488 return false;
489 }
490
491 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
492 if (unlikely(i915_vma_pin_fence(vma))) {
493 i915_vma_unpin(vma);
494 return false;
495 }
496
497 if (vma->fence)
498 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
499 }
500
501 ev->flags |= __EXEC_OBJECT_HAS_PIN;
502 return !eb_vma_misplaced(entry, vma, ev->flags);
503}
504
505static int
506eb_validate_vma(struct i915_execbuffer *eb,
507 struct drm_i915_gem_exec_object2 *entry,
508 struct i915_vma *vma)
509{
510 if (unlikely(entry->flags & eb->invalid_flags))
511 return -EINVAL;
512
513 if (unlikely(entry->alignment &&
514 !is_power_of_2_u64(entry->alignment)))
515 return -EINVAL;
516
517 /*
518 * Offset can be used as input (EXEC_OBJECT_PINNED), reject
519 * any non-page-aligned or non-canonical addresses.
520 */
521 if (unlikely(entry->flags & EXEC_OBJECT_PINNED &&
522 entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
523 return -EINVAL;
524
525 /* pad_to_size was once a reserved field, so sanitize it */
526 if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
527 if (unlikely(offset_in_page(entry->pad_to_size)))
528 return -EINVAL;
529 } else {
530 entry->pad_to_size = 0;
531 }
532 /*
533 * From drm_mm perspective address space is continuous,
534 * so from this point we're always using non-canonical
535 * form internally.
536 */
537 entry->offset = gen8_noncanonical_addr(entry->offset);
538
539 if (!eb->reloc_cache.has_fence) {
540 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
541 } else {
542 if ((entry->flags & EXEC_OBJECT_NEEDS_FENCE ||
543 eb->reloc_cache.needs_unfenced) &&
544 i915_gem_object_is_tiled(vma->obj))
545 entry->flags |= EXEC_OBJECT_NEEDS_GTT | __EXEC_OBJECT_NEEDS_MAP;
546 }
547
548 if (!(entry->flags & EXEC_OBJECT_PINNED))
549 entry->flags |= eb->context_flags;
550
551 return 0;
552}
553
554static void
555eb_add_vma(struct i915_execbuffer *eb,
556 unsigned int i, unsigned batch_idx,
557 struct i915_vma *vma)
558{
559 struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
560 struct eb_vma *ev = &eb->vma[i];
561
562 GEM_BUG_ON(i915_vma_is_closed(vma));
563
564 ev->vma = vma;
565 ev->exec = entry;
566 ev->flags = entry->flags;
567
568 if (eb->lut_size > 0) {
569 ev->handle = entry->handle;
570 hlist_add_head(&ev->node,
571 &eb->buckets[hash_32(entry->handle,
572 eb->lut_size)]);
573 }
574
575 if (entry->relocation_count)
576 list_add_tail(&ev->reloc_link, &eb->relocs);
577
578 /*
579 * SNA is doing fancy tricks with compressing batch buffers, which leads
580 * to negative relocation deltas. Usually that works out ok since the
581 * relocate address is still positive, except when the batch is placed
582 * very low in the GTT. Ensure this doesn't happen.
583 *
584 * Note that actual hangs have only been observed on gen7, but for
585 * paranoia do it everywhere.
586 */
587 if (i == batch_idx) {
588 if (entry->relocation_count &&
589 !(ev->flags & EXEC_OBJECT_PINNED))
590 ev->flags |= __EXEC_OBJECT_NEEDS_BIAS;
591 if (eb->reloc_cache.has_fence)
592 ev->flags |= EXEC_OBJECT_NEEDS_FENCE;
593
594 eb->batch = ev;
595 }
596
597 if (eb_pin_vma(eb, entry, ev)) {
598 if (entry->offset != vma->node.start) {
599 entry->offset = vma->node.start | UPDATE;
600 eb->args->flags |= __EXEC_HAS_RELOC;
601 }
602 } else {
603 eb_unreserve_vma(ev);
604 list_add_tail(&ev->bind_link, &eb->unbound);
605 }
606}
607
608static inline int use_cpu_reloc(const struct reloc_cache *cache,
609 const struct drm_i915_gem_object *obj)
610{
611 if (!i915_gem_object_has_struct_page(obj))
612 return false;
613
614 if (DBG_FORCE_RELOC == FORCE_CPU_RELOC)
615 return true;
616
617 if (DBG_FORCE_RELOC == FORCE_GTT_RELOC)
618 return false;
619
620 return (cache->has_llc ||
621 obj->cache_dirty ||
622 obj->cache_level != I915_CACHE_NONE);
623}
624
625static int eb_reserve_vma(const struct i915_execbuffer *eb,
626 struct eb_vma *ev,
627 u64 pin_flags)
628{
629 struct drm_i915_gem_exec_object2 *entry = ev->exec;
630 struct i915_vma *vma = ev->vma;
631 int err;
632
633 if (drm_mm_node_allocated(&vma->node) &&
634 eb_vma_misplaced(entry, vma, ev->flags)) {
635 err = i915_vma_unbind(vma);
636 if (err)
637 return err;
638 }
639
640 err = i915_vma_pin(vma,
641 entry->pad_to_size, entry->alignment,
642 eb_pin_flags(entry, ev->flags) | pin_flags);
643 if (err)
644 return err;
645
646 if (entry->offset != vma->node.start) {
647 entry->offset = vma->node.start | UPDATE;
648 eb->args->flags |= __EXEC_HAS_RELOC;
649 }
650
651 if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) {
652 err = i915_vma_pin_fence(vma);
653 if (unlikely(err)) {
654 i915_vma_unpin(vma);
655 return err;
656 }
657
658 if (vma->fence)
659 ev->flags |= __EXEC_OBJECT_HAS_FENCE;
660 }
661
662 ev->flags |= __EXEC_OBJECT_HAS_PIN;
663 GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags));
664
665 return 0;
666}
667
668static int eb_reserve(struct i915_execbuffer *eb)
669{
670 const unsigned int count = eb->buffer_count;
671 unsigned int pin_flags = PIN_USER | PIN_NONBLOCK;
672 struct list_head last;
673 struct eb_vma *ev;
674 unsigned int i, pass;
675 int err = 0;
676
677 /*
678 * Attempt to pin all of the buffers into the GTT.
679 * This is done in 3 phases:
680 *
681 * 1a. Unbind all objects that do not match the GTT constraints for
682 * the execbuffer (fenceable, mappable, alignment etc).
683 * 1b. Increment pin count for already bound objects.
684 * 2. Bind new objects.
685 * 3. Decrement pin count.
686 *
687 * This avoid unnecessary unbinding of later objects in order to make
688 * room for the earlier objects *unless* we need to defragment.
689 */
690
691 if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex))
692 return -EINTR;
693
694 pass = 0;
695 do {
696 list_for_each_entry(ev, &eb->unbound, bind_link) {
697 err = eb_reserve_vma(eb, ev, pin_flags);
698 if (err)
699 break;
700 }
701 if (!(err == -ENOSPC || err == -EAGAIN))
702 break;
703
704 /* Resort *all* the objects into priority order */
705 INIT_LIST_HEAD(&eb->unbound);
706 INIT_LIST_HEAD(&last);
707 for (i = 0; i < count; i++) {
708 unsigned int flags;
709
710 ev = &eb->vma[i];
711 flags = ev->flags;
712 if (flags & EXEC_OBJECT_PINNED &&
713 flags & __EXEC_OBJECT_HAS_PIN)
714 continue;
715
716 eb_unreserve_vma(ev);
717
718 if (flags & EXEC_OBJECT_PINNED)
719 /* Pinned must have their slot */
720 list_add(&ev->bind_link, &eb->unbound);
721 else if (flags & __EXEC_OBJECT_NEEDS_MAP)
722 /* Map require the lowest 256MiB (aperture) */
723 list_add_tail(&ev->bind_link, &eb->unbound);
724 else if (!(flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS))
725 /* Prioritise 4GiB region for restricted bo */
726 list_add(&ev->bind_link, &last);
727 else
728 list_add_tail(&ev->bind_link, &last);
729 }
730 list_splice_tail(&last, &eb->unbound);
731
732 if (err == -EAGAIN) {
733 mutex_unlock(&eb->i915->drm.struct_mutex);
734 flush_workqueue(eb->i915->mm.userptr_wq);
735 mutex_lock(&eb->i915->drm.struct_mutex);
736 continue;
737 }
738
739 switch (pass++) {
740 case 0:
741 break;
742
743 case 1:
744 /* Too fragmented, unbind everything and retry */
745 mutex_lock(&eb->context->vm->mutex);
746 err = i915_gem_evict_vm(eb->context->vm);
747 mutex_unlock(&eb->context->vm->mutex);
748 if (err)
749 goto unlock;
750 break;
751
752 default:
753 err = -ENOSPC;
754 goto unlock;
755 }
756
757 pin_flags = PIN_USER;
758 } while (1);
759
760unlock:
761 mutex_unlock(&eb->i915->drm.struct_mutex);
762 return err;
763}
764
765static unsigned int eb_batch_index(const struct i915_execbuffer *eb)
766{
767 if (eb->args->flags & I915_EXEC_BATCH_FIRST)
768 return 0;
769 else
770 return eb->buffer_count - 1;
771}
772
773static int eb_select_context(struct i915_execbuffer *eb)
774{
775 struct i915_gem_context *ctx;
776
777 ctx = i915_gem_context_lookup(eb->file->driver_priv, eb->args->rsvd1);
778 if (unlikely(!ctx))
779 return -ENOENT;
780
781 eb->gem_context = ctx;
782 if (rcu_access_pointer(ctx->vm))
783 eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
784
785 eb->context_flags = 0;
786 if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
787 eb->context_flags |= __EXEC_OBJECT_NEEDS_BIAS;
788
789 return 0;
790}
791
792static int __eb_add_lut(struct i915_execbuffer *eb,
793 u32 handle, struct i915_vma *vma)
794{
795 struct i915_gem_context *ctx = eb->gem_context;
796 struct i915_lut_handle *lut;
797 int err;
798
799 lut = i915_lut_handle_alloc();
800 if (unlikely(!lut))
801 return -ENOMEM;
802
803 i915_vma_get(vma);
804 if (!atomic_fetch_inc(&vma->open_count))
805 i915_vma_reopen(vma);
806 lut->handle = handle;
807 lut->ctx = ctx;
808
809 /* Check that the context hasn't been closed in the meantime */
810 err = -EINTR;
811 if (!mutex_lock_interruptible(&ctx->lut_mutex)) {
812 struct i915_address_space *vm = rcu_access_pointer(ctx->vm);
813
814 if (unlikely(vm && vma->vm != vm))
815 err = -EAGAIN; /* user racing with ctx set-vm */
816 else if (likely(!i915_gem_context_is_closed(ctx)))
817 err = radix_tree_insert(&ctx->handles_vma, handle, vma);
818 else
819 err = -ENOENT;
820 if (err == 0) { /* And nor has this handle */
821 struct drm_i915_gem_object *obj = vma->obj;
822
823 spin_lock(&obj->lut_lock);
824 if (idr_find(&eb->file->object_idr, handle) == obj) {
825 list_add(&lut->obj_link, &obj->lut_list);
826 } else {
827 radix_tree_delete(&ctx->handles_vma, handle);
828 err = -ENOENT;
829 }
830 spin_unlock(&obj->lut_lock);
831 }
832 mutex_unlock(&ctx->lut_mutex);
833 }
834 if (unlikely(err))
835 goto err;
836
837 return 0;
838
839err:
840 i915_vma_close(vma);
841 i915_vma_put(vma);
842 i915_lut_handle_free(lut);
843 return err;
844}
845
846static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
847{
848 struct i915_address_space *vm = eb->context->vm;
849
850 do {
851 struct drm_i915_gem_object *obj;
852 struct i915_vma *vma;
853 int err;
854
855 rcu_read_lock();
856 vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
857 if (likely(vma && vma->vm == vm))
858 vma = i915_vma_tryget(vma);
859 rcu_read_unlock();
860 if (likely(vma))
861 return vma;
862
863 obj = i915_gem_object_lookup(eb->file, handle);
864 if (unlikely(!obj))
865 return ERR_PTR(-ENOENT);
866
867 vma = i915_vma_instance(obj, vm, NULL);
868 if (IS_ERR(vma)) {
869 i915_gem_object_put(obj);
870 return vma;
871 }
872
873 err = __eb_add_lut(eb, handle, vma);
874 if (likely(!err))
875 return vma;
876
877 i915_gem_object_put(obj);
878 if (err != -EEXIST)
879 return ERR_PTR(err);
880 } while (1);
881}
882
883static int eb_lookup_vmas(struct i915_execbuffer *eb)
884{
885 unsigned int batch = eb_batch_index(eb);
886 unsigned int i;
887 int err = 0;
888
889 INIT_LIST_HEAD(&eb->relocs);
890 INIT_LIST_HEAD(&eb->unbound);
891
892 for (i = 0; i < eb->buffer_count; i++) {
893 struct i915_vma *vma;
894
895 vma = eb_lookup_vma(eb, eb->exec[i].handle);
896 if (IS_ERR(vma)) {
897 err = PTR_ERR(vma);
898 break;
899 }
900
901 err = eb_validate_vma(eb, &eb->exec[i], vma);
902 if (unlikely(err)) {
903 i915_vma_put(vma);
904 break;
905 }
906
907 eb_add_vma(eb, i, batch, vma);
908 }
909
910 eb->vma[i].vma = NULL;
911 return err;
912}
913
914static struct eb_vma *
915eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle)
916{
917 if (eb->lut_size < 0) {
918 if (handle >= -eb->lut_size)
919 return NULL;
920 return &eb->vma[handle];
921 } else {
922 struct hlist_head *head;
923 struct eb_vma *ev;
924
925 head = &eb->buckets[hash_32(handle, eb->lut_size)];
926 hlist_for_each_entry(ev, head, node) {
927 if (ev->handle == handle)
928 return ev;
929 }
930 return NULL;
931 }
932}
933
934static void eb_destroy(const struct i915_execbuffer *eb)
935{
936 GEM_BUG_ON(eb->reloc_cache.rq);
937
938 if (eb->array)
939 eb_vma_array_put(eb->array);
940
941 if (eb->lut_size > 0)
942 kfree(eb->buckets);
943}
944
945static inline u64
946relocation_target(const struct drm_i915_gem_relocation_entry *reloc,
947 const struct i915_vma *target)
948{
949 return gen8_canonical_addr((int)reloc->delta + target->node.start);
950}
951
952static void reloc_cache_init(struct reloc_cache *cache,
953 struct drm_i915_private *i915)
954{
955 cache->page = -1;
956 cache->vaddr = 0;
957 /* Must be a variable in the struct to allow GCC to unroll. */
958 cache->gen = INTEL_GEN(i915);
959 cache->has_llc = HAS_LLC(i915);
960 cache->use_64bit_reloc = HAS_64BIT_RELOC(i915);
961 cache->has_fence = cache->gen < 4;
962 cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment;
963 cache->node.flags = 0;
964 cache->rq = NULL;
965 cache->target = NULL;
966}
967
968static inline void *unmask_page(unsigned long p)
969{
970 return (void *)(uintptr_t)(p & PAGE_MASK);
971}
972
973static inline unsigned int unmask_flags(unsigned long p)
974{
975 return p & ~PAGE_MASK;
976}
977
978#define KMAP 0x4 /* after CLFLUSH_FLAGS */
979
980static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache)
981{
982 struct drm_i915_private *i915 =
983 container_of(cache, struct i915_execbuffer, reloc_cache)->i915;
984 return &i915->ggtt;
985}
986
987#define RELOC_TAIL 4
988
989static int reloc_gpu_chain(struct reloc_cache *cache)
990{
991 struct intel_gt_buffer_pool_node *pool;
992 struct i915_request *rq = cache->rq;
993 struct i915_vma *batch;
994 u32 *cmd;
995 int err;
996
997 pool = intel_gt_get_buffer_pool(rq->engine->gt, PAGE_SIZE);
998 if (IS_ERR(pool))
999 return PTR_ERR(pool);
1000
1001 batch = i915_vma_instance(pool->obj, rq->context->vm, NULL);
1002 if (IS_ERR(batch)) {
1003 err = PTR_ERR(batch);
1004 goto out_pool;
1005 }
1006
1007 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1008 if (err)
1009 goto out_pool;
1010
1011 GEM_BUG_ON(cache->rq_size + RELOC_TAIL > PAGE_SIZE / sizeof(u32));
1012 cmd = cache->rq_cmd + cache->rq_size;
1013 *cmd++ = MI_ARB_CHECK;
1014 if (cache->gen >= 8)
1015 *cmd++ = MI_BATCH_BUFFER_START_GEN8;
1016 else if (cache->gen >= 6)
1017 *cmd++ = MI_BATCH_BUFFER_START;
1018 else
1019 *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1020 *cmd++ = lower_32_bits(batch->node.start);
1021 *cmd++ = upper_32_bits(batch->node.start); /* Always 0 for gen<8 */
1022 i915_gem_object_flush_map(cache->rq_vma->obj);
1023 i915_gem_object_unpin_map(cache->rq_vma->obj);
1024 cache->rq_vma = NULL;
1025
1026 err = intel_gt_buffer_pool_mark_active(pool, rq);
1027 if (err == 0) {
1028 i915_vma_lock(batch);
1029 err = i915_request_await_object(rq, batch->obj, false);
1030 if (err == 0)
1031 err = i915_vma_move_to_active(batch, rq, 0);
1032 i915_vma_unlock(batch);
1033 }
1034 i915_vma_unpin(batch);
1035 if (err)
1036 goto out_pool;
1037
1038 cmd = i915_gem_object_pin_map(batch->obj,
1039 cache->has_llc ?
1040 I915_MAP_FORCE_WB :
1041 I915_MAP_FORCE_WC);
1042 if (IS_ERR(cmd)) {
1043 err = PTR_ERR(cmd);
1044 goto out_pool;
1045 }
1046
1047 /* Return with batch mapping (cmd) still pinned */
1048 cache->rq_cmd = cmd;
1049 cache->rq_size = 0;
1050 cache->rq_vma = batch;
1051
1052out_pool:
1053 intel_gt_buffer_pool_put(pool);
1054 return err;
1055}
1056
1057static unsigned int reloc_bb_flags(const struct reloc_cache *cache)
1058{
1059 return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE;
1060}
1061
1062static int reloc_gpu_flush(struct reloc_cache *cache)
1063{
1064 struct i915_request *rq;
1065 int err;
1066
1067 rq = fetch_and_zero(&cache->rq);
1068 if (!rq)
1069 return 0;
1070
1071 if (cache->rq_vma) {
1072 struct drm_i915_gem_object *obj = cache->rq_vma->obj;
1073
1074 GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));
1075 cache->rq_cmd[cache->rq_size++] = MI_BATCH_BUFFER_END;
1076
1077 __i915_gem_object_flush_map(obj,
1078 0, sizeof(u32) * cache->rq_size);
1079 i915_gem_object_unpin_map(obj);
1080 }
1081
1082 err = 0;
1083 if (rq->engine->emit_init_breadcrumb)
1084 err = rq->engine->emit_init_breadcrumb(rq);
1085 if (!err)
1086 err = rq->engine->emit_bb_start(rq,
1087 rq->batch->node.start,
1088 PAGE_SIZE,
1089 reloc_bb_flags(cache));
1090 if (err)
1091 i915_request_set_error_once(rq, err);
1092
1093 intel_gt_chipset_flush(rq->engine->gt);
1094 i915_request_add(rq);
1095
1096 return err;
1097}
1098
1099static void reloc_cache_reset(struct reloc_cache *cache)
1100{
1101 void *vaddr;
1102
1103 if (!cache->vaddr)
1104 return;
1105
1106 vaddr = unmask_page(cache->vaddr);
1107 if (cache->vaddr & KMAP) {
1108 if (cache->vaddr & CLFLUSH_AFTER)
1109 mb();
1110
1111 kunmap_atomic(vaddr);
1112 i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm);
1113 } else {
1114 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1115
1116 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1117 io_mapping_unmap_atomic((void __iomem *)vaddr);
1118
1119 if (drm_mm_node_allocated(&cache->node)) {
1120 ggtt->vm.clear_range(&ggtt->vm,
1121 cache->node.start,
1122 cache->node.size);
1123 mutex_lock(&ggtt->vm.mutex);
1124 drm_mm_remove_node(&cache->node);
1125 mutex_unlock(&ggtt->vm.mutex);
1126 } else {
1127 i915_vma_unpin((struct i915_vma *)cache->node.mm);
1128 }
1129 }
1130
1131 cache->vaddr = 0;
1132 cache->page = -1;
1133}
1134
1135static void *reloc_kmap(struct drm_i915_gem_object *obj,
1136 struct reloc_cache *cache,
1137 unsigned long page)
1138{
1139 void *vaddr;
1140
1141 if (cache->vaddr) {
1142 kunmap_atomic(unmask_page(cache->vaddr));
1143 } else {
1144 unsigned int flushes;
1145 int err;
1146
1147 err = i915_gem_object_prepare_write(obj, &flushes);
1148 if (err)
1149 return ERR_PTR(err);
1150
1151 BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
1152 BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
1153
1154 cache->vaddr = flushes | KMAP;
1155 cache->node.mm = (void *)obj;
1156 if (flushes)
1157 mb();
1158 }
1159
1160 vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page));
1161 cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr;
1162 cache->page = page;
1163
1164 return vaddr;
1165}
1166
1167static void *reloc_iomap(struct drm_i915_gem_object *obj,
1168 struct reloc_cache *cache,
1169 unsigned long page)
1170{
1171 struct i915_ggtt *ggtt = cache_to_ggtt(cache);
1172 unsigned long offset;
1173 void *vaddr;
1174
1175 if (cache->vaddr) {
1176 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
1177 io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
1178 } else {
1179 struct i915_vma *vma;
1180 int err;
1181
1182 if (i915_gem_object_is_tiled(obj))
1183 return ERR_PTR(-EINVAL);
1184
1185 if (use_cpu_reloc(cache, obj))
1186 return NULL;
1187
1188 i915_gem_object_lock(obj);
1189 err = i915_gem_object_set_to_gtt_domain(obj, true);
1190 i915_gem_object_unlock(obj);
1191 if (err)
1192 return ERR_PTR(err);
1193
1194 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1195 PIN_MAPPABLE |
1196 PIN_NONBLOCK /* NOWARN */ |
1197 PIN_NOEVICT);
1198 if (IS_ERR(vma)) {
1199 memset(&cache->node, 0, sizeof(cache->node));
1200 mutex_lock(&ggtt->vm.mutex);
1201 err = drm_mm_insert_node_in_range
1202 (&ggtt->vm.mm, &cache->node,
1203 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
1204 0, ggtt->mappable_end,
1205 DRM_MM_INSERT_LOW);
1206 mutex_unlock(&ggtt->vm.mutex);
1207 if (err) /* no inactive aperture space, use cpu reloc */
1208 return NULL;
1209 } else {
1210 cache->node.start = vma->node.start;
1211 cache->node.mm = (void *)vma;
1212 }
1213 }
1214
1215 offset = cache->node.start;
1216 if (drm_mm_node_allocated(&cache->node)) {
1217 ggtt->vm.insert_page(&ggtt->vm,
1218 i915_gem_object_get_dma_address(obj, page),
1219 offset, I915_CACHE_NONE, 0);
1220 } else {
1221 offset += page << PAGE_SHIFT;
1222 }
1223
1224 vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap,
1225 offset);
1226 cache->page = page;
1227 cache->vaddr = (unsigned long)vaddr;
1228
1229 return vaddr;
1230}
1231
1232static void *reloc_vaddr(struct drm_i915_gem_object *obj,
1233 struct reloc_cache *cache,
1234 unsigned long page)
1235{
1236 void *vaddr;
1237
1238 if (cache->page == page) {
1239 vaddr = unmask_page(cache->vaddr);
1240 } else {
1241 vaddr = NULL;
1242 if ((cache->vaddr & KMAP) == 0)
1243 vaddr = reloc_iomap(obj, cache, page);
1244 if (!vaddr)
1245 vaddr = reloc_kmap(obj, cache, page);
1246 }
1247
1248 return vaddr;
1249}
1250
1251static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
1252{
1253 if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
1254 if (flushes & CLFLUSH_BEFORE) {
1255 clflushopt(addr);
1256 mb();
1257 }
1258
1259 *addr = value;
1260
1261 /*
1262 * Writes to the same cacheline are serialised by the CPU
1263 * (including clflush). On the write path, we only require
1264 * that it hits memory in an orderly fashion and place
1265 * mb barriers at the start and end of the relocation phase
1266 * to ensure ordering of clflush wrt to the system.
1267 */
1268 if (flushes & CLFLUSH_AFTER)
1269 clflushopt(addr);
1270 } else
1271 *addr = value;
1272}
1273
1274static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
1275{
1276 struct drm_i915_gem_object *obj = vma->obj;
1277 int err;
1278
1279 i915_vma_lock(vma);
1280
1281 if (obj->cache_dirty & ~obj->cache_coherent)
1282 i915_gem_clflush_object(obj, 0);
1283 obj->write_domain = 0;
1284
1285 err = i915_request_await_object(rq, vma->obj, true);
1286 if (err == 0)
1287 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
1288
1289 i915_vma_unlock(vma);
1290
1291 return err;
1292}
1293
1294static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
1295 struct intel_engine_cs *engine,
1296 unsigned int len)
1297{
1298 struct reloc_cache *cache = &eb->reloc_cache;
1299 struct intel_gt_buffer_pool_node *pool;
1300 struct i915_request *rq;
1301 struct i915_vma *batch;
1302 u32 *cmd;
1303 int err;
1304
1305 pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE);
1306 if (IS_ERR(pool))
1307 return PTR_ERR(pool);
1308
1309 cmd = i915_gem_object_pin_map(pool->obj,
1310 cache->has_llc ?
1311 I915_MAP_FORCE_WB :
1312 I915_MAP_FORCE_WC);
1313 if (IS_ERR(cmd)) {
1314 err = PTR_ERR(cmd);
1315 goto out_pool;
1316 }
1317
1318 batch = i915_vma_instance(pool->obj, eb->context->vm, NULL);
1319 if (IS_ERR(batch)) {
1320 err = PTR_ERR(batch);
1321 goto err_unmap;
1322 }
1323
1324 err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
1325 if (err)
1326 goto err_unmap;
1327
1328 if (engine == eb->context->engine) {
1329 rq = i915_request_create(eb->context);
1330 } else {
1331 struct intel_context *ce;
1332
1333 ce = intel_context_create(engine);
1334 if (IS_ERR(ce)) {
1335 err = PTR_ERR(ce);
1336 goto err_unpin;
1337 }
1338
1339 i915_vm_put(ce->vm);
1340 ce->vm = i915_vm_get(eb->context->vm);
1341
1342 rq = intel_context_create_request(ce);
1343 intel_context_put(ce);
1344 }
1345 if (IS_ERR(rq)) {
1346 err = PTR_ERR(rq);
1347 goto err_unpin;
1348 }
1349
1350 err = intel_gt_buffer_pool_mark_active(pool, rq);
1351 if (err)
1352 goto err_request;
1353
1354 i915_vma_lock(batch);
1355 err = i915_request_await_object(rq, batch->obj, false);
1356 if (err == 0)
1357 err = i915_vma_move_to_active(batch, rq, 0);
1358 i915_vma_unlock(batch);
1359 if (err)
1360 goto skip_request;
1361
1362 rq->batch = batch;
1363 i915_vma_unpin(batch);
1364
1365 cache->rq = rq;
1366 cache->rq_cmd = cmd;
1367 cache->rq_size = 0;
1368 cache->rq_vma = batch;
1369
1370 /* Return with batch mapping (cmd) still pinned */
1371 goto out_pool;
1372
1373skip_request:
1374 i915_request_set_error_once(rq, err);
1375err_request:
1376 i915_request_add(rq);
1377err_unpin:
1378 i915_vma_unpin(batch);
1379err_unmap:
1380 i915_gem_object_unpin_map(pool->obj);
1381out_pool:
1382 intel_gt_buffer_pool_put(pool);
1383 return err;
1384}
1385
1386static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
1387{
1388 return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
1389}
1390
1391static u32 *reloc_gpu(struct i915_execbuffer *eb,
1392 struct i915_vma *vma,
1393 unsigned int len)
1394{
1395 struct reloc_cache *cache = &eb->reloc_cache;
1396 u32 *cmd;
1397 int err;
1398
1399 if (unlikely(!cache->rq)) {
1400 struct intel_engine_cs *engine = eb->engine;
1401
1402 if (!reloc_can_use_engine(engine)) {
1403 engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0];
1404 if (!engine)
1405 return ERR_PTR(-ENODEV);
1406 }
1407
1408 err = __reloc_gpu_alloc(eb, engine, len);
1409 if (unlikely(err))
1410 return ERR_PTR(err);
1411 }
1412
1413 if (vma != cache->target) {
1414 err = reloc_move_to_gpu(cache->rq, vma);
1415 if (unlikely(err)) {
1416 i915_request_set_error_once(cache->rq, err);
1417 return ERR_PTR(err);
1418 }
1419
1420 cache->target = vma;
1421 }
1422
1423 if (unlikely(cache->rq_size + len >
1424 PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) {
1425 err = reloc_gpu_chain(cache);
1426 if (unlikely(err)) {
1427 i915_request_set_error_once(cache->rq, err);
1428 return ERR_PTR(err);
1429 }
1430 }
1431
1432 GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32));
1433 cmd = cache->rq_cmd + cache->rq_size;
1434 cache->rq_size += len;
1435
1436 return cmd;
1437}
1438
1439static inline bool use_reloc_gpu(struct i915_vma *vma)
1440{
1441 if (DBG_FORCE_RELOC == FORCE_GPU_RELOC)
1442 return true;
1443
1444 if (DBG_FORCE_RELOC)
1445 return false;
1446
1447 return !dma_resv_test_signaled_rcu(vma->resv, true);
1448}
1449
1450static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset)
1451{
1452 struct page *page;
1453 unsigned long addr;
1454
1455 GEM_BUG_ON(vma->pages != vma->obj->mm.pages);
1456
1457 page = i915_gem_object_get_page(vma->obj, offset >> PAGE_SHIFT);
1458 addr = PFN_PHYS(page_to_pfn(page));
1459 GEM_BUG_ON(overflows_type(addr, u32)); /* expected dma32 */
1460
1461 return addr + offset_in_page(offset);
1462}
1463
1464static bool __reloc_entry_gpu(struct i915_execbuffer *eb,
1465 struct i915_vma *vma,
1466 u64 offset,
1467 u64 target_addr)
1468{
1469 const unsigned int gen = eb->reloc_cache.gen;
1470 unsigned int len;
1471 u32 *batch;
1472 u64 addr;
1473
1474 if (gen >= 8)
1475 len = offset & 7 ? 8 : 5;
1476 else if (gen >= 4)
1477 len = 4;
1478 else
1479 len = 3;
1480
1481 batch = reloc_gpu(eb, vma, len);
1482 if (IS_ERR(batch))
1483 return false;
1484
1485 addr = gen8_canonical_addr(vma->node.start + offset);
1486 if (gen >= 8) {
1487 if (offset & 7) {
1488 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1489 *batch++ = lower_32_bits(addr);
1490 *batch++ = upper_32_bits(addr);
1491 *batch++ = lower_32_bits(target_addr);
1492
1493 addr = gen8_canonical_addr(addr + 4);
1494
1495 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1496 *batch++ = lower_32_bits(addr);
1497 *batch++ = upper_32_bits(addr);
1498 *batch++ = upper_32_bits(target_addr);
1499 } else {
1500 *batch++ = (MI_STORE_DWORD_IMM_GEN4 | (1 << 21)) + 1;
1501 *batch++ = lower_32_bits(addr);
1502 *batch++ = upper_32_bits(addr);
1503 *batch++ = lower_32_bits(target_addr);
1504 *batch++ = upper_32_bits(target_addr);
1505 }
1506 } else if (gen >= 6) {
1507 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1508 *batch++ = 0;
1509 *batch++ = addr;
1510 *batch++ = target_addr;
1511 } else if (IS_I965G(eb->i915)) {
1512 *batch++ = MI_STORE_DWORD_IMM_GEN4;
1513 *batch++ = 0;
1514 *batch++ = vma_phys_addr(vma, offset);
1515 *batch++ = target_addr;
1516 } else if (gen >= 4) {
1517 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1518 *batch++ = 0;
1519 *batch++ = addr;
1520 *batch++ = target_addr;
1521 } else if (gen >= 3 &&
1522 !(IS_I915G(eb->i915) || IS_I915GM(eb->i915))) {
1523 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1524 *batch++ = addr;
1525 *batch++ = target_addr;
1526 } else {
1527 *batch++ = MI_STORE_DWORD_IMM;
1528 *batch++ = vma_phys_addr(vma, offset);
1529 *batch++ = target_addr;
1530 }
1531
1532 return true;
1533}
1534
1535static bool reloc_entry_gpu(struct i915_execbuffer *eb,
1536 struct i915_vma *vma,
1537 u64 offset,
1538 u64 target_addr)
1539{
1540 if (eb->reloc_cache.vaddr)
1541 return false;
1542
1543 if (!use_reloc_gpu(vma))
1544 return false;
1545
1546 return __reloc_entry_gpu(eb, vma, offset, target_addr);
1547}
1548
1549static u64
1550relocate_entry(struct i915_vma *vma,
1551 const struct drm_i915_gem_relocation_entry *reloc,
1552 struct i915_execbuffer *eb,
1553 const struct i915_vma *target)
1554{
1555 u64 target_addr = relocation_target(reloc, target);
1556 u64 offset = reloc->offset;
1557
1558 if (!reloc_entry_gpu(eb, vma, offset, target_addr)) {
1559 bool wide = eb->reloc_cache.use_64bit_reloc;
1560 void *vaddr;
1561
1562repeat:
1563 vaddr = reloc_vaddr(vma->obj,
1564 &eb->reloc_cache,
1565 offset >> PAGE_SHIFT);
1566 if (IS_ERR(vaddr))
1567 return PTR_ERR(vaddr);
1568
1569 GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32)));
1570 clflush_write32(vaddr + offset_in_page(offset),
1571 lower_32_bits(target_addr),
1572 eb->reloc_cache.vaddr);
1573
1574 if (wide) {
1575 offset += sizeof(u32);
1576 target_addr >>= 32;
1577 wide = false;
1578 goto repeat;
1579 }
1580 }
1581
1582 return target->node.start | UPDATE;
1583}
1584
1585static u64
1586eb_relocate_entry(struct i915_execbuffer *eb,
1587 struct eb_vma *ev,
1588 const struct drm_i915_gem_relocation_entry *reloc)
1589{
1590 struct drm_i915_private *i915 = eb->i915;
1591 struct eb_vma *target;
1592 int err;
1593
1594 /* we've already hold a reference to all valid objects */
1595 target = eb_get_vma(eb, reloc->target_handle);
1596 if (unlikely(!target))
1597 return -ENOENT;
1598
1599 /* Validate that the target is in a valid r/w GPU domain */
1600 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
1601 drm_dbg(&i915->drm, "reloc with multiple write domains: "
1602 "target %d offset %d "
1603 "read %08x write %08x",
1604 reloc->target_handle,
1605 (int) reloc->offset,
1606 reloc->read_domains,
1607 reloc->write_domain);
1608 return -EINVAL;
1609 }
1610 if (unlikely((reloc->write_domain | reloc->read_domains)
1611 & ~I915_GEM_GPU_DOMAINS)) {
1612 drm_dbg(&i915->drm, "reloc with read/write non-GPU domains: "
1613 "target %d offset %d "
1614 "read %08x write %08x",
1615 reloc->target_handle,
1616 (int) reloc->offset,
1617 reloc->read_domains,
1618 reloc->write_domain);
1619 return -EINVAL;
1620 }
1621
1622 if (reloc->write_domain) {
1623 target->flags |= EXEC_OBJECT_WRITE;
1624
1625 /*
1626 * Sandybridge PPGTT errata: We need a global gtt mapping
1627 * for MI and pipe_control writes because the gpu doesn't
1628 * properly redirect them through the ppgtt for non_secure
1629 * batchbuffers.
1630 */
1631 if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
1632 IS_GEN(eb->i915, 6)) {
1633 err = i915_vma_bind(target->vma,
1634 target->vma->obj->cache_level,
1635 PIN_GLOBAL, NULL);
1636 if (err)
1637 return err;
1638 }
1639 }
1640
1641 /*
1642 * If the relocation already has the right value in it, no
1643 * more work needs to be done.
1644 */
1645 if (!DBG_FORCE_RELOC &&
1646 gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset)
1647 return 0;
1648
1649 /* Check that the relocation address is valid... */
1650 if (unlikely(reloc->offset >
1651 ev->vma->size - (eb->reloc_cache.use_64bit_reloc ? 8 : 4))) {
1652 drm_dbg(&i915->drm, "Relocation beyond object bounds: "
1653 "target %d offset %d size %d.\n",
1654 reloc->target_handle,
1655 (int)reloc->offset,
1656 (int)ev->vma->size);
1657 return -EINVAL;
1658 }
1659 if (unlikely(reloc->offset & 3)) {
1660 drm_dbg(&i915->drm, "Relocation not 4-byte aligned: "
1661 "target %d offset %d.\n",
1662 reloc->target_handle,
1663 (int)reloc->offset);
1664 return -EINVAL;
1665 }
1666
1667 /*
1668 * If we write into the object, we need to force the synchronisation
1669 * barrier, either with an asynchronous clflush or if we executed the
1670 * patching using the GPU (though that should be serialised by the
1671 * timeline). To be completely sure, and since we are required to
1672 * do relocations we are already stalling, disable the user's opt
1673 * out of our synchronisation.
1674 */
1675 ev->flags &= ~EXEC_OBJECT_ASYNC;
1676
1677 /* and update the user's relocation entry */
1678 return relocate_entry(ev->vma, reloc, eb, target->vma);
1679}
1680
1681static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev)
1682{
1683#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
1684 struct drm_i915_gem_relocation_entry stack[N_RELOC(512)];
1685 const struct drm_i915_gem_exec_object2 *entry = ev->exec;
1686 struct drm_i915_gem_relocation_entry __user *urelocs =
1687 u64_to_user_ptr(entry->relocs_ptr);
1688 unsigned long remain = entry->relocation_count;
1689
1690 if (unlikely(remain > N_RELOC(ULONG_MAX)))
1691 return -EINVAL;
1692
1693 /*
1694 * We must check that the entire relocation array is safe
1695 * to read. However, if the array is not writable the user loses
1696 * the updated relocation values.
1697 */
1698 if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs))))
1699 return -EFAULT;
1700
1701 do {
1702 struct drm_i915_gem_relocation_entry *r = stack;
1703 unsigned int count =
1704 min_t(unsigned long, remain, ARRAY_SIZE(stack));
1705 unsigned int copied;
1706
1707 /*
1708 * This is the fast path and we cannot handle a pagefault
1709 * whilst holding the struct mutex lest the user pass in the
1710 * relocations contained within a mmaped bo. For in such a case
1711 * we, the page fault handler would call i915_gem_fault() and
1712 * we would try to acquire the struct mutex again. Obviously
1713 * this is bad and so lockdep complains vehemently.
1714 */
1715 copied = __copy_from_user(r, urelocs, count * sizeof(r[0]));
1716 if (unlikely(copied)) {
1717 remain = -EFAULT;
1718 goto out;
1719 }
1720
1721 remain -= count;
1722 do {
1723 u64 offset = eb_relocate_entry(eb, ev, r);
1724
1725 if (likely(offset == 0)) {
1726 } else if ((s64)offset < 0) {
1727 remain = (int)offset;
1728 goto out;
1729 } else {
1730 /*
1731 * Note that reporting an error now
1732 * leaves everything in an inconsistent
1733 * state as we have *already* changed
1734 * the relocation value inside the
1735 * object. As we have not changed the
1736 * reloc.presumed_offset or will not
1737 * change the execobject.offset, on the
1738 * call we may not rewrite the value
1739 * inside the object, leaving it
1740 * dangling and causing a GPU hang. Unless
1741 * userspace dynamically rebuilds the
1742 * relocations on each execbuf rather than
1743 * presume a static tree.
1744 *
1745 * We did previously check if the relocations
1746 * were writable (access_ok), an error now
1747 * would be a strange race with mprotect,
1748 * having already demonstrated that we
1749 * can read from this userspace address.
1750 */
1751 offset = gen8_canonical_addr(offset & ~UPDATE);
1752 __put_user(offset,
1753 &urelocs[r - stack].presumed_offset);
1754 }
1755 } while (r++, --count);
1756 urelocs += ARRAY_SIZE(stack);
1757 } while (remain);
1758out:
1759 reloc_cache_reset(&eb->reloc_cache);
1760 return remain;
1761}
1762
1763static int eb_relocate(struct i915_execbuffer *eb)
1764{
1765 int err;
1766
1767 err = eb_lookup_vmas(eb);
1768 if (err)
1769 return err;
1770
1771 if (!list_empty(&eb->unbound)) {
1772 err = eb_reserve(eb);
1773 if (err)
1774 return err;
1775 }
1776
1777 /* The objects are in their final locations, apply the relocations. */
1778 if (eb->args->flags & __EXEC_HAS_RELOC) {
1779 struct eb_vma *ev;
1780 int flush;
1781
1782 list_for_each_entry(ev, &eb->relocs, reloc_link) {
1783 err = eb_relocate_vma(eb, ev);
1784 if (err)
1785 break;
1786 }
1787
1788 flush = reloc_gpu_flush(&eb->reloc_cache);
1789 if (!err)
1790 err = flush;
1791 }
1792
1793 return err;
1794}
1795
1796static int eb_move_to_gpu(struct i915_execbuffer *eb)
1797{
1798 const unsigned int count = eb->buffer_count;
1799 struct ww_acquire_ctx acquire;
1800 unsigned int i;
1801 int err = 0;
1802
1803 ww_acquire_init(&acquire, &reservation_ww_class);
1804
1805 for (i = 0; i < count; i++) {
1806 struct eb_vma *ev = &eb->vma[i];
1807 struct i915_vma *vma = ev->vma;
1808
1809 err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire);
1810 if (err == -EDEADLK) {
1811 GEM_BUG_ON(i == 0);
1812 do {
1813 int j = i - 1;
1814
1815 ww_mutex_unlock(&eb->vma[j].vma->resv->lock);
1816
1817 swap(eb->vma[i], eb->vma[j]);
1818 } while (--i);
1819
1820 err = ww_mutex_lock_slow_interruptible(&vma->resv->lock,
1821 &acquire);
1822 }
1823 if (err)
1824 break;
1825 }
1826 ww_acquire_done(&acquire);
1827
1828 while (i--) {
1829 struct eb_vma *ev = &eb->vma[i];
1830 struct i915_vma *vma = ev->vma;
1831 unsigned int flags = ev->flags;
1832 struct drm_i915_gem_object *obj = vma->obj;
1833
1834 assert_vma_held(vma);
1835
1836 if (flags & EXEC_OBJECT_CAPTURE) {
1837 struct i915_capture_list *capture;
1838
1839 capture = kmalloc(sizeof(*capture), GFP_KERNEL);
1840 if (capture) {
1841 capture->next = eb->request->capture_list;
1842 capture->vma = vma;
1843 eb->request->capture_list = capture;
1844 }
1845 }
1846
1847 /*
1848 * If the GPU is not _reading_ through the CPU cache, we need
1849 * to make sure that any writes (both previous GPU writes from
1850 * before a change in snooping levels and normal CPU writes)
1851 * caught in that cache are flushed to main memory.
1852 *
1853 * We want to say
1854 * obj->cache_dirty &&
1855 * !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
1856 * but gcc's optimiser doesn't handle that as well and emits
1857 * two jumps instead of one. Maybe one day...
1858 */
1859 if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
1860 if (i915_gem_clflush_object(obj, 0))
1861 flags &= ~EXEC_OBJECT_ASYNC;
1862 }
1863
1864 if (err == 0 && !(flags & EXEC_OBJECT_ASYNC)) {
1865 err = i915_request_await_object
1866 (eb->request, obj, flags & EXEC_OBJECT_WRITE);
1867 }
1868
1869 if (err == 0)
1870 err = i915_vma_move_to_active(vma, eb->request, flags);
1871
1872 i915_vma_unlock(vma);
1873 eb_unreserve_vma(ev);
1874 }
1875 ww_acquire_fini(&acquire);
1876
1877 eb_vma_array_put(fetch_and_zero(&eb->array));
1878
1879 if (unlikely(err))
1880 goto err_skip;
1881
1882 /* Unconditionally flush any chipset caches (for streaming writes). */
1883 intel_gt_chipset_flush(eb->engine->gt);
1884 return 0;
1885
1886err_skip:
1887 i915_request_set_error_once(eb->request, err);
1888 return err;
1889}
1890
1891static int i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
1892{
1893 if (exec->flags & __I915_EXEC_ILLEGAL_FLAGS)
1894 return -EINVAL;
1895
1896 /* Kernel clipping was a DRI1 misfeature */
1897 if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
1898 if (exec->num_cliprects || exec->cliprects_ptr)
1899 return -EINVAL;
1900 }
1901
1902 if (exec->DR4 == 0xffffffff) {
1903 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
1904 exec->DR4 = 0;
1905 }
1906 if (exec->DR1 || exec->DR4)
1907 return -EINVAL;
1908
1909 if ((exec->batch_start_offset | exec->batch_len) & 0x7)
1910 return -EINVAL;
1911
1912 return 0;
1913}
1914
1915static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
1916{
1917 u32 *cs;
1918 int i;
1919
1920 if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
1921 drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
1922 return -EINVAL;
1923 }
1924
1925 cs = intel_ring_begin(rq, 4 * 2 + 2);
1926 if (IS_ERR(cs))
1927 return PTR_ERR(cs);
1928
1929 *cs++ = MI_LOAD_REGISTER_IMM(4);
1930 for (i = 0; i < 4; i++) {
1931 *cs++ = i915_mmio_reg_offset(GEN7_SO_WRITE_OFFSET(i));
1932 *cs++ = 0;
1933 }
1934 *cs++ = MI_NOOP;
1935 intel_ring_advance(rq, cs);
1936
1937 return 0;
1938}
1939
1940static struct i915_vma *
1941shadow_batch_pin(struct drm_i915_gem_object *obj,
1942 struct i915_address_space *vm,
1943 unsigned int flags)
1944{
1945 struct i915_vma *vma;
1946 int err;
1947
1948 vma = i915_vma_instance(obj, vm, NULL);
1949 if (IS_ERR(vma))
1950 return vma;
1951
1952 err = i915_vma_pin(vma, 0, 0, flags);
1953 if (err)
1954 return ERR_PTR(err);
1955
1956 return vma;
1957}
1958
1959struct eb_parse_work {
1960 struct dma_fence_work base;
1961 struct intel_engine_cs *engine;
1962 struct i915_vma *batch;
1963 struct i915_vma *shadow;
1964 struct i915_vma *trampoline;
1965 unsigned int batch_offset;
1966 unsigned int batch_length;
1967};
1968
1969static int __eb_parse(struct dma_fence_work *work)
1970{
1971 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
1972
1973 return intel_engine_cmd_parser(pw->engine,
1974 pw->batch,
1975 pw->batch_offset,
1976 pw->batch_length,
1977 pw->shadow,
1978 pw->trampoline);
1979}
1980
1981static void __eb_parse_release(struct dma_fence_work *work)
1982{
1983 struct eb_parse_work *pw = container_of(work, typeof(*pw), base);
1984
1985 if (pw->trampoline)
1986 i915_active_release(&pw->trampoline->active);
1987 i915_active_release(&pw->shadow->active);
1988 i915_active_release(&pw->batch->active);
1989}
1990
1991static const struct dma_fence_work_ops eb_parse_ops = {
1992 .name = "eb_parse",
1993 .work = __eb_parse,
1994 .release = __eb_parse_release,
1995};
1996
1997static inline int
1998__parser_mark_active(struct i915_vma *vma,
1999 struct intel_timeline *tl,
2000 struct dma_fence *fence)
2001{
2002 struct intel_gt_buffer_pool_node *node = vma->private;
2003
2004 return i915_active_ref(&node->active, tl, fence);
2005}
2006
2007static int
2008parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl)
2009{
2010 int err;
2011
2012 mutex_lock(&tl->mutex);
2013
2014 err = __parser_mark_active(pw->shadow, tl, &pw->base.dma);
2015 if (err)
2016 goto unlock;
2017
2018 if (pw->trampoline) {
2019 err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma);
2020 if (err)
2021 goto unlock;
2022 }
2023
2024unlock:
2025 mutex_unlock(&tl->mutex);
2026 return err;
2027}
2028
2029static int eb_parse_pipeline(struct i915_execbuffer *eb,
2030 struct i915_vma *shadow,
2031 struct i915_vma *trampoline)
2032{
2033 struct eb_parse_work *pw;
2034 int err;
2035
2036 pw = kzalloc(sizeof(*pw), GFP_KERNEL);
2037 if (!pw)
2038 return -ENOMEM;
2039
2040 err = i915_active_acquire(&eb->batch->vma->active);
2041 if (err)
2042 goto err_free;
2043
2044 err = i915_active_acquire(&shadow->active);
2045 if (err)
2046 goto err_batch;
2047
2048 if (trampoline) {
2049 err = i915_active_acquire(&trampoline->active);
2050 if (err)
2051 goto err_shadow;
2052 }
2053
2054 dma_fence_work_init(&pw->base, &eb_parse_ops);
2055
2056 pw->engine = eb->engine;
2057 pw->batch = eb->batch->vma;
2058 pw->batch_offset = eb->batch_start_offset;
2059 pw->batch_length = eb->batch_len;
2060 pw->shadow = shadow;
2061 pw->trampoline = trampoline;
2062
2063 /* Mark active refs early for this worker, in case we get interrupted */
2064 err = parser_mark_active(pw, eb->context->timeline);
2065 if (err)
2066 goto err_commit;
2067
2068 err = dma_resv_lock_interruptible(pw->batch->resv, NULL);
2069 if (err)
2070 goto err_commit;
2071
2072 err = dma_resv_reserve_shared(pw->batch->resv, 1);
2073 if (err)
2074 goto err_commit_unlock;
2075
2076 /* Wait for all writes (and relocs) into the batch to complete */
2077 err = i915_sw_fence_await_reservation(&pw->base.chain,
2078 pw->batch->resv, NULL, false,
2079 0, I915_FENCE_GFP);
2080 if (err < 0)
2081 goto err_commit_unlock;
2082
2083 /* Keep the batch alive and unwritten as we parse */
2084 dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma);
2085
2086 dma_resv_unlock(pw->batch->resv);
2087
2088 /* Force execution to wait for completion of the parser */
2089 dma_resv_lock(shadow->resv, NULL);
2090 dma_resv_add_excl_fence(shadow->resv, &pw->base.dma);
2091 dma_resv_unlock(shadow->resv);
2092
2093 dma_fence_work_commit_imm(&pw->base);
2094 return 0;
2095
2096err_commit_unlock:
2097 dma_resv_unlock(pw->batch->resv);
2098err_commit:
2099 i915_sw_fence_set_error_once(&pw->base.chain, err);
2100 dma_fence_work_commit_imm(&pw->base);
2101 return err;
2102
2103err_shadow:
2104 i915_active_release(&shadow->active);
2105err_batch:
2106 i915_active_release(&eb->batch->vma->active);
2107err_free:
2108 kfree(pw);
2109 return err;
2110}
2111
2112static int eb_parse(struct i915_execbuffer *eb)
2113{
2114 struct drm_i915_private *i915 = eb->i915;
2115 struct intel_gt_buffer_pool_node *pool;
2116 struct i915_vma *shadow, *trampoline;
2117 unsigned int len;
2118 int err;
2119
2120 if (!eb_use_cmdparser(eb))
2121 return 0;
2122
2123 len = eb->batch_len;
2124 if (!CMDPARSER_USES_GGTT(eb->i915)) {
2125 /*
2126 * ppGTT backed shadow buffers must be mapped RO, to prevent
2127 * post-scan tampering
2128 */
2129 if (!eb->context->vm->has_read_only) {
2130 drm_dbg(&i915->drm,
2131 "Cannot prevent post-scan tampering without RO capable vm\n");
2132 return -EINVAL;
2133 }
2134 } else {
2135 len += I915_CMD_PARSER_TRAMPOLINE_SIZE;
2136 }
2137
2138 pool = intel_gt_get_buffer_pool(eb->engine->gt, len);
2139 if (IS_ERR(pool))
2140 return PTR_ERR(pool);
2141
2142 shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER);
2143 if (IS_ERR(shadow)) {
2144 err = PTR_ERR(shadow);
2145 goto err;
2146 }
2147 i915_gem_object_set_readonly(shadow->obj);
2148 shadow->private = pool;
2149
2150 trampoline = NULL;
2151 if (CMDPARSER_USES_GGTT(eb->i915)) {
2152 trampoline = shadow;
2153
2154 shadow = shadow_batch_pin(pool->obj,
2155 &eb->engine->gt->ggtt->vm,
2156 PIN_GLOBAL);
2157 if (IS_ERR(shadow)) {
2158 err = PTR_ERR(shadow);
2159 shadow = trampoline;
2160 goto err_shadow;
2161 }
2162 shadow->private = pool;
2163
2164 eb->batch_flags |= I915_DISPATCH_SECURE;
2165 }
2166
2167 err = eb_parse_pipeline(eb, shadow, trampoline);
2168 if (err)
2169 goto err_trampoline;
2170
2171 eb->vma[eb->buffer_count].vma = i915_vma_get(shadow);
2172 eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN;
2173 eb->batch = &eb->vma[eb->buffer_count++];
2174 eb->vma[eb->buffer_count].vma = NULL;
2175
2176 eb->trampoline = trampoline;
2177 eb->batch_start_offset = 0;
2178
2179 return 0;
2180
2181err_trampoline:
2182 if (trampoline)
2183 i915_vma_unpin(trampoline);
2184err_shadow:
2185 i915_vma_unpin(shadow);
2186err:
2187 intel_gt_buffer_pool_put(pool);
2188 return err;
2189}
2190
2191static void
2192add_to_client(struct i915_request *rq, struct drm_file *file)
2193{
2194 struct drm_i915_file_private *file_priv = file->driver_priv;
2195
2196 rq->file_priv = file_priv;
2197
2198 spin_lock(&file_priv->mm.lock);
2199 list_add_tail(&rq->client_link, &file_priv->mm.request_list);
2200 spin_unlock(&file_priv->mm.lock);
2201}
2202
2203static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch)
2204{
2205 int err;
2206
2207 err = eb_move_to_gpu(eb);
2208 if (err)
2209 return err;
2210
2211 if (eb->args->flags & I915_EXEC_GEN7_SOL_RESET) {
2212 err = i915_reset_gen7_sol_offsets(eb->request);
2213 if (err)
2214 return err;
2215 }
2216
2217 /*
2218 * After we completed waiting for other engines (using HW semaphores)
2219 * then we can signal that this request/batch is ready to run. This
2220 * allows us to determine if the batch is still waiting on the GPU
2221 * or actually running by checking the breadcrumb.
2222 */
2223 if (eb->engine->emit_init_breadcrumb) {
2224 err = eb->engine->emit_init_breadcrumb(eb->request);
2225 if (err)
2226 return err;
2227 }
2228
2229 err = eb->engine->emit_bb_start(eb->request,
2230 batch->node.start +
2231 eb->batch_start_offset,
2232 eb->batch_len,
2233 eb->batch_flags);
2234 if (err)
2235 return err;
2236
2237 if (eb->trampoline) {
2238 GEM_BUG_ON(eb->batch_start_offset);
2239 err = eb->engine->emit_bb_start(eb->request,
2240 eb->trampoline->node.start +
2241 eb->batch_len,
2242 0, 0);
2243 if (err)
2244 return err;
2245 }
2246
2247 if (intel_context_nopreempt(eb->context))
2248 __set_bit(I915_FENCE_FLAG_NOPREEMPT, &eb->request->fence.flags);
2249
2250 return 0;
2251}
2252
2253static int num_vcs_engines(const struct drm_i915_private *i915)
2254{
2255 return hweight64(VDBOX_MASK(&i915->gt));
2256}
2257
2258/*
2259 * Find one BSD ring to dispatch the corresponding BSD command.
2260 * The engine index is returned.
2261 */
2262static unsigned int
2263gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv,
2264 struct drm_file *file)
2265{
2266 struct drm_i915_file_private *file_priv = file->driver_priv;
2267
2268 /* Check whether the file_priv has already selected one ring. */
2269 if ((int)file_priv->bsd_engine < 0)
2270 file_priv->bsd_engine =
2271 get_random_int() % num_vcs_engines(dev_priv);
2272
2273 return file_priv->bsd_engine;
2274}
2275
2276static const enum intel_engine_id user_ring_map[] = {
2277 [I915_EXEC_DEFAULT] = RCS0,
2278 [I915_EXEC_RENDER] = RCS0,
2279 [I915_EXEC_BLT] = BCS0,
2280 [I915_EXEC_BSD] = VCS0,
2281 [I915_EXEC_VEBOX] = VECS0
2282};
2283
2284static struct i915_request *eb_throttle(struct intel_context *ce)
2285{
2286 struct intel_ring *ring = ce->ring;
2287 struct intel_timeline *tl = ce->timeline;
2288 struct i915_request *rq;
2289
2290 /*
2291 * Completely unscientific finger-in-the-air estimates for suitable
2292 * maximum user request size (to avoid blocking) and then backoff.
2293 */
2294 if (intel_ring_update_space(ring) >= PAGE_SIZE)
2295 return NULL;
2296
2297 /*
2298 * Find a request that after waiting upon, there will be at least half
2299 * the ring available. The hysteresis allows us to compete for the
2300 * shared ring and should mean that we sleep less often prior to
2301 * claiming our resources, but not so long that the ring completely
2302 * drains before we can submit our next request.
2303 */
2304 list_for_each_entry(rq, &tl->requests, link) {
2305 if (rq->ring != ring)
2306 continue;
2307
2308 if (__intel_ring_space(rq->postfix,
2309 ring->emit, ring->size) > ring->size / 2)
2310 break;
2311 }
2312 if (&rq->link == &tl->requests)
2313 return NULL; /* weird, we will check again later for real */
2314
2315 return i915_request_get(rq);
2316}
2317
2318static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce)
2319{
2320 struct intel_timeline *tl;
2321 struct i915_request *rq;
2322 int err;
2323
2324 /*
2325 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2326 * EIO if the GPU is already wedged.
2327 */
2328 err = intel_gt_terminally_wedged(ce->engine->gt);
2329 if (err)
2330 return err;
2331
2332 if (unlikely(intel_context_is_banned(ce)))
2333 return -EIO;
2334
2335 /*
2336 * Pinning the contexts may generate requests in order to acquire
2337 * GGTT space, so do this first before we reserve a seqno for
2338 * ourselves.
2339 */
2340 err = intel_context_pin(ce);
2341 if (err)
2342 return err;
2343
2344 /*
2345 * Take a local wakeref for preparing to dispatch the execbuf as
2346 * we expect to access the hardware fairly frequently in the
2347 * process, and require the engine to be kept awake between accesses.
2348 * Upon dispatch, we acquire another prolonged wakeref that we hold
2349 * until the timeline is idle, which in turn releases the wakeref
2350 * taken on the engine, and the parent device.
2351 */
2352 tl = intel_context_timeline_lock(ce);
2353 if (IS_ERR(tl)) {
2354 err = PTR_ERR(tl);
2355 goto err_unpin;
2356 }
2357
2358 intel_context_enter(ce);
2359 rq = eb_throttle(ce);
2360
2361 intel_context_timeline_unlock(tl);
2362
2363 if (rq) {
2364 bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
2365 long timeout;
2366
2367 timeout = MAX_SCHEDULE_TIMEOUT;
2368 if (nonblock)
2369 timeout = 0;
2370
2371 timeout = i915_request_wait(rq,
2372 I915_WAIT_INTERRUPTIBLE,
2373 timeout);
2374 i915_request_put(rq);
2375
2376 if (timeout < 0) {
2377 err = nonblock ? -EWOULDBLOCK : timeout;
2378 goto err_exit;
2379 }
2380 }
2381
2382 eb->engine = ce->engine;
2383 eb->context = ce;
2384 return 0;
2385
2386err_exit:
2387 mutex_lock(&tl->mutex);
2388 intel_context_exit(ce);
2389 intel_context_timeline_unlock(tl);
2390err_unpin:
2391 intel_context_unpin(ce);
2392 return err;
2393}
2394
2395static void eb_unpin_engine(struct i915_execbuffer *eb)
2396{
2397 struct intel_context *ce = eb->context;
2398 struct intel_timeline *tl = ce->timeline;
2399
2400 mutex_lock(&tl->mutex);
2401 intel_context_exit(ce);
2402 mutex_unlock(&tl->mutex);
2403
2404 intel_context_unpin(ce);
2405}
2406
2407static unsigned int
2408eb_select_legacy_ring(struct i915_execbuffer *eb,
2409 struct drm_file *file,
2410 struct drm_i915_gem_execbuffer2 *args)
2411{
2412 struct drm_i915_private *i915 = eb->i915;
2413 unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
2414
2415 if (user_ring_id != I915_EXEC_BSD &&
2416 (args->flags & I915_EXEC_BSD_MASK)) {
2417 drm_dbg(&i915->drm,
2418 "execbuf with non bsd ring but with invalid "
2419 "bsd dispatch flags: %d\n", (int)(args->flags));
2420 return -1;
2421 }
2422
2423 if (user_ring_id == I915_EXEC_BSD && num_vcs_engines(i915) > 1) {
2424 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
2425
2426 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
2427 bsd_idx = gen8_dispatch_bsd_engine(i915, file);
2428 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
2429 bsd_idx <= I915_EXEC_BSD_RING2) {
2430 bsd_idx >>= I915_EXEC_BSD_SHIFT;
2431 bsd_idx--;
2432 } else {
2433 drm_dbg(&i915->drm,
2434 "execbuf with unknown bsd ring: %u\n",
2435 bsd_idx);
2436 return -1;
2437 }
2438
2439 return _VCS(bsd_idx);
2440 }
2441
2442 if (user_ring_id >= ARRAY_SIZE(user_ring_map)) {
2443 drm_dbg(&i915->drm, "execbuf with unknown ring: %u\n",
2444 user_ring_id);
2445 return -1;
2446 }
2447
2448 return user_ring_map[user_ring_id];
2449}
2450
2451static int
2452eb_pin_engine(struct i915_execbuffer *eb,
2453 struct drm_file *file,
2454 struct drm_i915_gem_execbuffer2 *args)
2455{
2456 struct intel_context *ce;
2457 unsigned int idx;
2458 int err;
2459
2460 if (i915_gem_context_user_engines(eb->gem_context))
2461 idx = args->flags & I915_EXEC_RING_MASK;
2462 else
2463 idx = eb_select_legacy_ring(eb, file, args);
2464
2465 ce = i915_gem_context_get_engine(eb->gem_context, idx);
2466 if (IS_ERR(ce))
2467 return PTR_ERR(ce);
2468
2469 err = __eb_pin_engine(eb, ce);
2470 intel_context_put(ce);
2471
2472 return err;
2473}
2474
2475static void
2476__free_fence_array(struct drm_syncobj **fences, unsigned int n)
2477{
2478 while (n--)
2479 drm_syncobj_put(ptr_mask_bits(fences[n], 2));
2480 kvfree(fences);
2481}
2482
2483static struct drm_syncobj **
2484get_fence_array(struct drm_i915_gem_execbuffer2 *args,
2485 struct drm_file *file)
2486{
2487 const unsigned long nfences = args->num_cliprects;
2488 struct drm_i915_gem_exec_fence __user *user;
2489 struct drm_syncobj **fences;
2490 unsigned long n;
2491 int err;
2492
2493 if (!(args->flags & I915_EXEC_FENCE_ARRAY))
2494 return NULL;
2495
2496 /* Check multiplication overflow for access_ok() and kvmalloc_array() */
2497 BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
2498 if (nfences > min_t(unsigned long,
2499 ULONG_MAX / sizeof(*user),
2500 SIZE_MAX / sizeof(*fences)))
2501 return ERR_PTR(-EINVAL);
2502
2503 user = u64_to_user_ptr(args->cliprects_ptr);
2504 if (!access_ok(user, nfences * sizeof(*user)))
2505 return ERR_PTR(-EFAULT);
2506
2507 fences = kvmalloc_array(nfences, sizeof(*fences),
2508 __GFP_NOWARN | GFP_KERNEL);
2509 if (!fences)
2510 return ERR_PTR(-ENOMEM);
2511
2512 for (n = 0; n < nfences; n++) {
2513 struct drm_i915_gem_exec_fence fence;
2514 struct drm_syncobj *syncobj;
2515
2516 if (__copy_from_user(&fence, user++, sizeof(fence))) {
2517 err = -EFAULT;
2518 goto err;
2519 }
2520
2521 if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
2522 err = -EINVAL;
2523 goto err;
2524 }
2525
2526 syncobj = drm_syncobj_find(file, fence.handle);
2527 if (!syncobj) {
2528 DRM_DEBUG("Invalid syncobj handle provided\n");
2529 err = -ENOENT;
2530 goto err;
2531 }
2532
2533 BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
2534 ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
2535
2536 fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
2537 }
2538
2539 return fences;
2540
2541err:
2542 __free_fence_array(fences, n);
2543 return ERR_PTR(err);
2544}
2545
2546static void
2547put_fence_array(struct drm_i915_gem_execbuffer2 *args,
2548 struct drm_syncobj **fences)
2549{
2550 if (fences)
2551 __free_fence_array(fences, args->num_cliprects);
2552}
2553
2554static int
2555await_fence_array(struct i915_execbuffer *eb,
2556 struct drm_syncobj **fences)
2557{
2558 const unsigned int nfences = eb->args->num_cliprects;
2559 unsigned int n;
2560 int err;
2561
2562 for (n = 0; n < nfences; n++) {
2563 struct drm_syncobj *syncobj;
2564 struct dma_fence *fence;
2565 unsigned int flags;
2566
2567 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2568 if (!(flags & I915_EXEC_FENCE_WAIT))
2569 continue;
2570
2571 fence = drm_syncobj_fence_get(syncobj);
2572 if (!fence)
2573 return -EINVAL;
2574
2575 err = i915_request_await_dma_fence(eb->request, fence);
2576 dma_fence_put(fence);
2577 if (err < 0)
2578 return err;
2579 }
2580
2581 return 0;
2582}
2583
2584static void
2585signal_fence_array(struct i915_execbuffer *eb,
2586 struct drm_syncobj **fences)
2587{
2588 const unsigned int nfences = eb->args->num_cliprects;
2589 struct dma_fence * const fence = &eb->request->fence;
2590 unsigned int n;
2591
2592 for (n = 0; n < nfences; n++) {
2593 struct drm_syncobj *syncobj;
2594 unsigned int flags;
2595
2596 syncobj = ptr_unpack_bits(fences[n], &flags, 2);
2597 if (!(flags & I915_EXEC_FENCE_SIGNAL))
2598 continue;
2599
2600 drm_syncobj_replace_fence(syncobj, fence);
2601 }
2602}
2603
2604static void retire_requests(struct intel_timeline *tl, struct i915_request *end)
2605{
2606 struct i915_request *rq, *rn;
2607
2608 list_for_each_entry_safe(rq, rn, &tl->requests, link)
2609 if (rq == end || !i915_request_retire(rq))
2610 break;
2611}
2612
2613static void eb_request_add(struct i915_execbuffer *eb)
2614{
2615 struct i915_request *rq = eb->request;
2616 struct intel_timeline * const tl = i915_request_timeline(rq);
2617 struct i915_sched_attr attr = {};
2618 struct i915_request *prev;
2619
2620 lockdep_assert_held(&tl->mutex);
2621 lockdep_unpin_lock(&tl->mutex, rq->cookie);
2622
2623 trace_i915_request_add(rq);
2624
2625 prev = __i915_request_commit(rq);
2626
2627 /* Check that the context wasn't destroyed before submission */
2628 if (likely(!intel_context_is_closed(eb->context))) {
2629 attr = eb->gem_context->sched;
2630 } else {
2631 /* Serialise with context_close via the add_to_timeline */
2632 i915_request_set_error_once(rq, -ENOENT);
2633 __i915_request_skip(rq);
2634 }
2635
2636 __i915_request_queue(rq, &attr);
2637
2638 /* Try to clean up the client's timeline after submitting the request */
2639 if (prev)
2640 retire_requests(tl, prev);
2641
2642 mutex_unlock(&tl->mutex);
2643}
2644
2645static int
2646i915_gem_do_execbuffer(struct drm_device *dev,
2647 struct drm_file *file,
2648 struct drm_i915_gem_execbuffer2 *args,
2649 struct drm_i915_gem_exec_object2 *exec,
2650 struct drm_syncobj **fences)
2651{
2652 struct drm_i915_private *i915 = to_i915(dev);
2653 struct i915_execbuffer eb;
2654 struct dma_fence *in_fence = NULL;
2655 struct sync_file *out_fence = NULL;
2656 struct i915_vma *batch;
2657 int out_fence_fd = -1;
2658 int err;
2659
2660 BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
2661 BUILD_BUG_ON(__EXEC_OBJECT_INTERNAL_FLAGS &
2662 ~__EXEC_OBJECT_UNKNOWN_FLAGS);
2663
2664 eb.i915 = i915;
2665 eb.file = file;
2666 eb.args = args;
2667 if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC))
2668 args->flags |= __EXEC_HAS_RELOC;
2669
2670 eb.exec = exec;
2671
2672 eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
2673 reloc_cache_init(&eb.reloc_cache, eb.i915);
2674
2675 eb.buffer_count = args->buffer_count;
2676 eb.batch_start_offset = args->batch_start_offset;
2677 eb.batch_len = args->batch_len;
2678 eb.trampoline = NULL;
2679
2680 eb.batch_flags = 0;
2681 if (args->flags & I915_EXEC_SECURE) {
2682 if (INTEL_GEN(i915) >= 11)
2683 return -ENODEV;
2684
2685 /* Return -EPERM to trigger fallback code on old binaries. */
2686 if (!HAS_SECURE_BATCHES(i915))
2687 return -EPERM;
2688
2689 if (!drm_is_current_master(file) || !capable(CAP_SYS_ADMIN))
2690 return -EPERM;
2691
2692 eb.batch_flags |= I915_DISPATCH_SECURE;
2693 }
2694 if (args->flags & I915_EXEC_IS_PINNED)
2695 eb.batch_flags |= I915_DISPATCH_PINNED;
2696
2697#define IN_FENCES (I915_EXEC_FENCE_IN | I915_EXEC_FENCE_SUBMIT)
2698 if (args->flags & IN_FENCES) {
2699 if ((args->flags & IN_FENCES) == IN_FENCES)
2700 return -EINVAL;
2701
2702 in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
2703 if (!in_fence)
2704 return -EINVAL;
2705 }
2706#undef IN_FENCES
2707
2708 if (args->flags & I915_EXEC_FENCE_OUT) {
2709 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
2710 if (out_fence_fd < 0) {
2711 err = out_fence_fd;
2712 goto err_in_fence;
2713 }
2714 }
2715
2716 err = eb_create(&eb);
2717 if (err)
2718 goto err_out_fence;
2719
2720 GEM_BUG_ON(!eb.lut_size);
2721
2722 err = eb_select_context(&eb);
2723 if (unlikely(err))
2724 goto err_destroy;
2725
2726 err = eb_pin_engine(&eb, file, args);
2727 if (unlikely(err))
2728 goto err_context;
2729
2730 err = eb_relocate(&eb);
2731 if (err) {
2732 /*
2733 * If the user expects the execobject.offset and
2734 * reloc.presumed_offset to be an exact match,
2735 * as for using NO_RELOC, then we cannot update
2736 * the execobject.offset until we have completed
2737 * relocation.
2738 */
2739 args->flags &= ~__EXEC_HAS_RELOC;
2740 goto err_vma;
2741 }
2742
2743 if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) {
2744 drm_dbg(&i915->drm,
2745 "Attempting to use self-modifying batch buffer\n");
2746 err = -EINVAL;
2747 goto err_vma;
2748 }
2749
2750 if (range_overflows_t(u64,
2751 eb.batch_start_offset, eb.batch_len,
2752 eb.batch->vma->size)) {
2753 drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
2754 err = -EINVAL;
2755 goto err_vma;
2756 }
2757
2758 if (eb.batch_len == 0)
2759 eb.batch_len = eb.batch->vma->size - eb.batch_start_offset;
2760
2761 err = eb_parse(&eb);
2762 if (err)
2763 goto err_vma;
2764
2765 /*
2766 * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
2767 * batch" bit. Hence we need to pin secure batches into the global gtt.
2768 * hsw should have this fixed, but bdw mucks it up again. */
2769 batch = eb.batch->vma;
2770 if (eb.batch_flags & I915_DISPATCH_SECURE) {
2771 struct i915_vma *vma;
2772
2773 /*
2774 * So on first glance it looks freaky that we pin the batch here
2775 * outside of the reservation loop. But:
2776 * - The batch is already pinned into the relevant ppgtt, so we
2777 * already have the backing storage fully allocated.
2778 * - No other BO uses the global gtt (well contexts, but meh),
2779 * so we don't really have issues with multiple objects not
2780 * fitting due to fragmentation.
2781 * So this is actually safe.
2782 */
2783 vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0);
2784 if (IS_ERR(vma)) {
2785 err = PTR_ERR(vma);
2786 goto err_parse;
2787 }
2788
2789 batch = vma;
2790 }
2791
2792 /* All GPU relocation batches must be submitted prior to the user rq */
2793 GEM_BUG_ON(eb.reloc_cache.rq);
2794
2795 /* Allocate a request for this batch buffer nice and early. */
2796 eb.request = i915_request_create(eb.context);
2797 if (IS_ERR(eb.request)) {
2798 err = PTR_ERR(eb.request);
2799 goto err_batch_unpin;
2800 }
2801
2802 if (in_fence) {
2803 if (args->flags & I915_EXEC_FENCE_SUBMIT)
2804 err = i915_request_await_execution(eb.request,
2805 in_fence,
2806 eb.engine->bond_execute);
2807 else
2808 err = i915_request_await_dma_fence(eb.request,
2809 in_fence);
2810 if (err < 0)
2811 goto err_request;
2812 }
2813
2814 if (fences) {
2815 err = await_fence_array(&eb, fences);
2816 if (err)
2817 goto err_request;
2818 }
2819
2820 if (out_fence_fd != -1) {
2821 out_fence = sync_file_create(&eb.request->fence);
2822 if (!out_fence) {
2823 err = -ENOMEM;
2824 goto err_request;
2825 }
2826 }
2827
2828 /*
2829 * Whilst this request exists, batch_obj will be on the
2830 * active_list, and so will hold the active reference. Only when this
2831 * request is retired will the the batch_obj be moved onto the
2832 * inactive_list and lose its active reference. Hence we do not need
2833 * to explicitly hold another reference here.
2834 */
2835 eb.request->batch = batch;
2836 if (batch->private)
2837 intel_gt_buffer_pool_mark_active(batch->private, eb.request);
2838
2839 trace_i915_request_queue(eb.request, eb.batch_flags);
2840 err = eb_submit(&eb, batch);
2841err_request:
2842 add_to_client(eb.request, file);
2843 i915_request_get(eb.request);
2844 eb_request_add(&eb);
2845
2846 if (fences)
2847 signal_fence_array(&eb, fences);
2848
2849 if (out_fence) {
2850 if (err == 0) {
2851 fd_install(out_fence_fd, out_fence->file);
2852 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
2853 args->rsvd2 |= (u64)out_fence_fd << 32;
2854 out_fence_fd = -1;
2855 } else {
2856 fput(out_fence->file);
2857 }
2858 }
2859 i915_request_put(eb.request);
2860
2861err_batch_unpin:
2862 if (eb.batch_flags & I915_DISPATCH_SECURE)
2863 i915_vma_unpin(batch);
2864err_parse:
2865 if (batch->private)
2866 intel_gt_buffer_pool_put(batch->private);
2867err_vma:
2868 if (eb.trampoline)
2869 i915_vma_unpin(eb.trampoline);
2870 eb_unpin_engine(&eb);
2871err_context:
2872 i915_gem_context_put(eb.gem_context);
2873err_destroy:
2874 eb_destroy(&eb);
2875err_out_fence:
2876 if (out_fence_fd != -1)
2877 put_unused_fd(out_fence_fd);
2878err_in_fence:
2879 dma_fence_put(in_fence);
2880 return err;
2881}
2882
2883static size_t eb_element_size(void)
2884{
2885 return sizeof(struct drm_i915_gem_exec_object2);
2886}
2887
2888static bool check_buffer_count(size_t count)
2889{
2890 const size_t sz = eb_element_size();
2891
2892 /*
2893 * When using LUT_HANDLE, we impose a limit of INT_MAX for the lookup
2894 * array size (see eb_create()). Otherwise, we can accept an array as
2895 * large as can be addressed (though use large arrays at your peril)!
2896 */
2897
2898 return !(count < 1 || count > INT_MAX || count > SIZE_MAX / sz - 1);
2899}
2900
2901/*
2902 * Legacy execbuffer just creates an exec2 list from the original exec object
2903 * list array and passes it to the real function.
2904 */
2905int
2906i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2907 struct drm_file *file)
2908{
2909 struct drm_i915_private *i915 = to_i915(dev);
2910 struct drm_i915_gem_execbuffer *args = data;
2911 struct drm_i915_gem_execbuffer2 exec2;
2912 struct drm_i915_gem_exec_object *exec_list = NULL;
2913 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
2914 const size_t count = args->buffer_count;
2915 unsigned int i;
2916 int err;
2917
2918 if (!check_buffer_count(count)) {
2919 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
2920 return -EINVAL;
2921 }
2922
2923 exec2.buffers_ptr = args->buffers_ptr;
2924 exec2.buffer_count = args->buffer_count;
2925 exec2.batch_start_offset = args->batch_start_offset;
2926 exec2.batch_len = args->batch_len;
2927 exec2.DR1 = args->DR1;
2928 exec2.DR4 = args->DR4;
2929 exec2.num_cliprects = args->num_cliprects;
2930 exec2.cliprects_ptr = args->cliprects_ptr;
2931 exec2.flags = I915_EXEC_RENDER;
2932 i915_execbuffer2_set_context_id(exec2, 0);
2933
2934 err = i915_gem_check_execbuffer(&exec2);
2935 if (err)
2936 return err;
2937
2938 /* Copy in the exec list from userland */
2939 exec_list = kvmalloc_array(count, sizeof(*exec_list),
2940 __GFP_NOWARN | GFP_KERNEL);
2941 exec2_list = kvmalloc_array(count, eb_element_size(),
2942 __GFP_NOWARN | GFP_KERNEL);
2943 if (exec_list == NULL || exec2_list == NULL) {
2944 drm_dbg(&i915->drm,
2945 "Failed to allocate exec list for %d buffers\n",
2946 args->buffer_count);
2947 kvfree(exec_list);
2948 kvfree(exec2_list);
2949 return -ENOMEM;
2950 }
2951 err = copy_from_user(exec_list,
2952 u64_to_user_ptr(args->buffers_ptr),
2953 sizeof(*exec_list) * count);
2954 if (err) {
2955 drm_dbg(&i915->drm, "copy %d exec entries failed %d\n",
2956 args->buffer_count, err);
2957 kvfree(exec_list);
2958 kvfree(exec2_list);
2959 return -EFAULT;
2960 }
2961
2962 for (i = 0; i < args->buffer_count; i++) {
2963 exec2_list[i].handle = exec_list[i].handle;
2964 exec2_list[i].relocation_count = exec_list[i].relocation_count;
2965 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
2966 exec2_list[i].alignment = exec_list[i].alignment;
2967 exec2_list[i].offset = exec_list[i].offset;
2968 if (INTEL_GEN(to_i915(dev)) < 4)
2969 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
2970 else
2971 exec2_list[i].flags = 0;
2972 }
2973
2974 err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
2975 if (exec2.flags & __EXEC_HAS_RELOC) {
2976 struct drm_i915_gem_exec_object __user *user_exec_list =
2977 u64_to_user_ptr(args->buffers_ptr);
2978
2979 /* Copy the new buffer offsets back to the user's exec list. */
2980 for (i = 0; i < args->buffer_count; i++) {
2981 if (!(exec2_list[i].offset & UPDATE))
2982 continue;
2983
2984 exec2_list[i].offset =
2985 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
2986 exec2_list[i].offset &= PIN_OFFSET_MASK;
2987 if (__copy_to_user(&user_exec_list[i].offset,
2988 &exec2_list[i].offset,
2989 sizeof(user_exec_list[i].offset)))
2990 break;
2991 }
2992 }
2993
2994 kvfree(exec_list);
2995 kvfree(exec2_list);
2996 return err;
2997}
2998
2999int
3000i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
3001 struct drm_file *file)
3002{
3003 struct drm_i915_private *i915 = to_i915(dev);
3004 struct drm_i915_gem_execbuffer2 *args = data;
3005 struct drm_i915_gem_exec_object2 *exec2_list;
3006 struct drm_syncobj **fences = NULL;
3007 const size_t count = args->buffer_count;
3008 int err;
3009
3010 if (!check_buffer_count(count)) {
3011 drm_dbg(&i915->drm, "execbuf2 with %zd buffers\n", count);
3012 return -EINVAL;
3013 }
3014
3015 err = i915_gem_check_execbuffer(args);
3016 if (err)
3017 return err;
3018
3019 exec2_list = kvmalloc_array(count, eb_element_size(),
3020 __GFP_NOWARN | GFP_KERNEL);
3021 if (exec2_list == NULL) {
3022 drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n",
3023 count);
3024 return -ENOMEM;
3025 }
3026 if (copy_from_user(exec2_list,
3027 u64_to_user_ptr(args->buffers_ptr),
3028 sizeof(*exec2_list) * count)) {
3029 drm_dbg(&i915->drm, "copy %zd exec entries failed\n", count);
3030 kvfree(exec2_list);
3031 return -EFAULT;
3032 }
3033
3034 if (args->flags & I915_EXEC_FENCE_ARRAY) {
3035 fences = get_fence_array(args, file);
3036 if (IS_ERR(fences)) {
3037 kvfree(exec2_list);
3038 return PTR_ERR(fences);
3039 }
3040 }
3041
3042 err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
3043
3044 /*
3045 * Now that we have begun execution of the batchbuffer, we ignore
3046 * any new error after this point. Also given that we have already
3047 * updated the associated relocations, we try to write out the current
3048 * object locations irrespective of any error.
3049 */
3050 if (args->flags & __EXEC_HAS_RELOC) {
3051 struct drm_i915_gem_exec_object2 __user *user_exec_list =
3052 u64_to_user_ptr(args->buffers_ptr);
3053 unsigned int i;
3054
3055 /* Copy the new buffer offsets back to the user's exec list. */
3056 /*
3057 * Note: count * sizeof(*user_exec_list) does not overflow,
3058 * because we checked 'count' in check_buffer_count().
3059 *
3060 * And this range already got effectively checked earlier
3061 * when we did the "copy_from_user()" above.
3062 */
3063 if (!user_write_access_begin(user_exec_list,
3064 count * sizeof(*user_exec_list)))
3065 goto end;
3066
3067 for (i = 0; i < args->buffer_count; i++) {
3068 if (!(exec2_list[i].offset & UPDATE))
3069 continue;
3070
3071 exec2_list[i].offset =
3072 gen8_canonical_addr(exec2_list[i].offset & PIN_OFFSET_MASK);
3073 unsafe_put_user(exec2_list[i].offset,
3074 &user_exec_list[i].offset,
3075 end_user);
3076 }
3077end_user:
3078 user_write_access_end();
3079end:;
3080 }
3081
3082 args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
3083 put_fence_array(args, fences);
3084 kvfree(exec2_list);
3085 return err;
3086}
3087
3088#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3089#include "selftests/i915_gem_execbuffer.c"
3090#endif