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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28#include "gt/intel_engine.h"
29
30#include "i915_drv.h"
31#include "i915_memcpy.h"
32
33/**
34 * DOC: batch buffer command parser
35 *
36 * Motivation:
37 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
38 * require userspace code to submit batches containing commands such as
39 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
40 * generations of the hardware will noop these commands in "unsecure" batches
41 * (which includes all userspace batches submitted via i915) even though the
42 * commands may be safe and represent the intended programming model of the
43 * device.
44 *
45 * The software command parser is similar in operation to the command parsing
46 * done in hardware for unsecure batches. However, the software parser allows
47 * some operations that would be noop'd by hardware, if the parser determines
48 * the operation is safe, and submits the batch as "secure" to prevent hardware
49 * parsing.
50 *
51 * Threats:
52 * At a high level, the hardware (and software) checks attempt to prevent
53 * granting userspace undue privileges. There are three categories of privilege.
54 *
55 * First, commands which are explicitly defined as privileged or which should
56 * only be used by the kernel driver. The parser rejects such commands
57 *
58 * Second, commands which access registers. To support correct/enhanced
59 * userspace functionality, particularly certain OpenGL extensions, the parser
60 * provides a whitelist of registers which userspace may safely access
61 *
62 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
63 * The parser always rejects such commands.
64 *
65 * The majority of the problematic commands fall in the MI_* range, with only a
66 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
67 *
68 * Implementation:
69 * Each engine maintains tables of commands and registers which the parser
70 * uses in scanning batch buffers submitted to that engine.
71 *
72 * Since the set of commands that the parser must check for is significantly
73 * smaller than the number of commands supported, the parser tables contain only
74 * those commands required by the parser. This generally works because command
75 * opcode ranges have standard command length encodings. So for commands that
76 * the parser does not need to check, it can easily skip them. This is
77 * implemented via a per-engine length decoding vfunc.
78 *
79 * Unfortunately, there are a number of commands that do not follow the standard
80 * length encoding for their opcode range, primarily amongst the MI_* commands.
81 * To handle this, the parser provides a way to define explicit "skip" entries
82 * in the per-engine command tables.
83 *
84 * Other command table entries map fairly directly to high level categories
85 * mentioned above: rejected, register whitelist. The parser implements a number
86 * of checks, including the privileged memory checks, via a general bitmasking
87 * mechanism.
88 */
89
90/*
91 * A command that requires special handling by the command parser.
92 */
93struct drm_i915_cmd_descriptor {
94 /*
95 * Flags describing how the command parser processes the command.
96 *
97 * CMD_DESC_FIXED: The command has a fixed length if this is set,
98 * a length mask if not set
99 * CMD_DESC_SKIP: The command is allowed but does not follow the
100 * standard length encoding for the opcode range in
101 * which it falls
102 * CMD_DESC_REJECT: The command is never allowed
103 * CMD_DESC_REGISTER: The command should be checked against the
104 * register whitelist for the appropriate ring
105 */
106 u32 flags;
107#define CMD_DESC_FIXED (1<<0)
108#define CMD_DESC_SKIP (1<<1)
109#define CMD_DESC_REJECT (1<<2)
110#define CMD_DESC_REGISTER (1<<3)
111#define CMD_DESC_BITMASK (1<<4)
112
113 /*
114 * The command's unique identification bits and the bitmask to get them.
115 * This isn't strictly the opcode field as defined in the spec and may
116 * also include type, subtype, and/or subop fields.
117 */
118 struct {
119 u32 value;
120 u32 mask;
121 } cmd;
122
123 /*
124 * The command's length. The command is either fixed length (i.e. does
125 * not include a length field) or has a length field mask. The flag
126 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
127 * a length mask. All command entries in a command table must include
128 * length information.
129 */
130 union {
131 u32 fixed;
132 u32 mask;
133 } length;
134
135 /*
136 * Describes where to find a register address in the command to check
137 * against the ring's register whitelist. Only valid if flags has the
138 * CMD_DESC_REGISTER bit set.
139 *
140 * A non-zero step value implies that the command may access multiple
141 * registers in sequence (e.g. LRI), in that case step gives the
142 * distance in dwords between individual offset fields.
143 */
144 struct {
145 u32 offset;
146 u32 mask;
147 u32 step;
148 } reg;
149
150#define MAX_CMD_DESC_BITMASKS 3
151 /*
152 * Describes command checks where a particular dword is masked and
153 * compared against an expected value. If the command does not match
154 * the expected value, the parser rejects it. Only valid if flags has
155 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
156 * are valid.
157 *
158 * If the check specifies a non-zero condition_mask then the parser
159 * only performs the check when the bits specified by condition_mask
160 * are non-zero.
161 */
162 struct {
163 u32 offset;
164 u32 mask;
165 u32 expected;
166 u32 condition_offset;
167 u32 condition_mask;
168 } bits[MAX_CMD_DESC_BITMASKS];
169};
170
171/*
172 * A table of commands requiring special handling by the command parser.
173 *
174 * Each engine has an array of tables. Each table consists of an array of
175 * command descriptors, which must be sorted with command opcodes in
176 * ascending order.
177 */
178struct drm_i915_cmd_table {
179 const struct drm_i915_cmd_descriptor *table;
180 int count;
181};
182
183#define STD_MI_OPCODE_SHIFT (32 - 9)
184#define STD_3D_OPCODE_SHIFT (32 - 16)
185#define STD_2D_OPCODE_SHIFT (32 - 10)
186#define STD_MFX_OPCODE_SHIFT (32 - 16)
187#define MIN_OPCODE_SHIFT 16
188
189#define CMD(op, opm, f, lm, fl, ...) \
190 { \
191 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
192 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \
193 .length = { (lm) }, \
194 __VA_ARGS__ \
195 }
196
197/* Convenience macros to compress the tables */
198#define SMI STD_MI_OPCODE_SHIFT
199#define S3D STD_3D_OPCODE_SHIFT
200#define S2D STD_2D_OPCODE_SHIFT
201#define SMFX STD_MFX_OPCODE_SHIFT
202#define F true
203#define S CMD_DESC_SKIP
204#define R CMD_DESC_REJECT
205#define W CMD_DESC_REGISTER
206#define B CMD_DESC_BITMASK
207
208/* Command Mask Fixed Len Action
209 ---------------------------------------------------------- */
210static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
211 CMD( MI_NOOP, SMI, F, 1, S ),
212 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
213 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
214 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
215 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
216 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
217 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
218 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
219 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
220 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
221 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
222 .reg = { .offset = 1, .mask = 0x007FFFFC },
223 .bits = {{
224 .offset = 0,
225 .mask = MI_GLOBAL_GTT,
226 .expected = 0,
227 }}, ),
228 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
229 .reg = { .offset = 1, .mask = 0x007FFFFC },
230 .bits = {{
231 .offset = 0,
232 .mask = MI_GLOBAL_GTT,
233 .expected = 0,
234 }}, ),
235 /*
236 * MI_BATCH_BUFFER_START requires some special handling. It's not
237 * really a 'skip' action but it doesn't seem like it's worth adding
238 * a new action. See i915_parse_cmds().
239 */
240 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
241};
242
243static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
244 CMD( MI_FLUSH, SMI, F, 1, S ),
245 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
246 CMD( MI_PREDICATE, SMI, F, 1, S ),
247 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
248 CMD( MI_SET_APPID, SMI, F, 1, S ),
249 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
250 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
251 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
252 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
253 .bits = {{
254 .offset = 0,
255 .mask = MI_GLOBAL_GTT,
256 .expected = 0,
257 }}, ),
258 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
259 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
260 .bits = {{
261 .offset = 0,
262 .mask = MI_GLOBAL_GTT,
263 .expected = 0,
264 }}, ),
265 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
266 .bits = {{
267 .offset = 1,
268 .mask = MI_REPORT_PERF_COUNT_GGTT,
269 .expected = 0,
270 }}, ),
271 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
272 .bits = {{
273 .offset = 0,
274 .mask = MI_GLOBAL_GTT,
275 .expected = 0,
276 }}, ),
277 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
278 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
279 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
280 .bits = {{
281 .offset = 2,
282 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
283 .expected = 0,
284 }}, ),
285 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
286 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
287 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
288 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
289 .bits = {{
290 .offset = 1,
291 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
292 .expected = 0,
293 },
294 {
295 .offset = 1,
296 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
297 PIPE_CONTROL_STORE_DATA_INDEX),
298 .expected = 0,
299 .condition_offset = 1,
300 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
301 }}, ),
302};
303
304static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
305 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
306 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
307 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
308 CMD( MI_SET_APPID, SMI, F, 1, S ),
309 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
310 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
311 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
312 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
313 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
314 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
315 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
316 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
317 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
318 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
319
320 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
321 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
322 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
323 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
324 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
325};
326
327static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
328 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
329 CMD( MI_SET_APPID, SMI, F, 1, S ),
330 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
331 .bits = {{
332 .offset = 0,
333 .mask = MI_GLOBAL_GTT,
334 .expected = 0,
335 }}, ),
336 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
337 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
338 .bits = {{
339 .offset = 0,
340 .mask = MI_FLUSH_DW_NOTIFY,
341 .expected = 0,
342 },
343 {
344 .offset = 1,
345 .mask = MI_FLUSH_DW_USE_GTT,
346 .expected = 0,
347 .condition_offset = 0,
348 .condition_mask = MI_FLUSH_DW_OP_MASK,
349 },
350 {
351 .offset = 0,
352 .mask = MI_FLUSH_DW_STORE_INDEX,
353 .expected = 0,
354 .condition_offset = 0,
355 .condition_mask = MI_FLUSH_DW_OP_MASK,
356 }}, ),
357 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
358 .bits = {{
359 .offset = 0,
360 .mask = MI_GLOBAL_GTT,
361 .expected = 0,
362 }}, ),
363 /*
364 * MFX_WAIT doesn't fit the way we handle length for most commands.
365 * It has a length field but it uses a non-standard length bias.
366 * It is always 1 dword though, so just treat it as fixed length.
367 */
368 CMD( MFX_WAIT, SMFX, F, 1, S ),
369};
370
371static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
372 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
373 CMD( MI_SET_APPID, SMI, F, 1, S ),
374 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
375 .bits = {{
376 .offset = 0,
377 .mask = MI_GLOBAL_GTT,
378 .expected = 0,
379 }}, ),
380 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
381 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
382 .bits = {{
383 .offset = 0,
384 .mask = MI_FLUSH_DW_NOTIFY,
385 .expected = 0,
386 },
387 {
388 .offset = 1,
389 .mask = MI_FLUSH_DW_USE_GTT,
390 .expected = 0,
391 .condition_offset = 0,
392 .condition_mask = MI_FLUSH_DW_OP_MASK,
393 },
394 {
395 .offset = 0,
396 .mask = MI_FLUSH_DW_STORE_INDEX,
397 .expected = 0,
398 .condition_offset = 0,
399 .condition_mask = MI_FLUSH_DW_OP_MASK,
400 }}, ),
401 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
402 .bits = {{
403 .offset = 0,
404 .mask = MI_GLOBAL_GTT,
405 .expected = 0,
406 }}, ),
407};
408
409static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
410 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
411 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
412 .bits = {{
413 .offset = 0,
414 .mask = MI_GLOBAL_GTT,
415 .expected = 0,
416 }}, ),
417 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
418 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
419 .bits = {{
420 .offset = 0,
421 .mask = MI_FLUSH_DW_NOTIFY,
422 .expected = 0,
423 },
424 {
425 .offset = 1,
426 .mask = MI_FLUSH_DW_USE_GTT,
427 .expected = 0,
428 .condition_offset = 0,
429 .condition_mask = MI_FLUSH_DW_OP_MASK,
430 },
431 {
432 .offset = 0,
433 .mask = MI_FLUSH_DW_STORE_INDEX,
434 .expected = 0,
435 .condition_offset = 0,
436 .condition_mask = MI_FLUSH_DW_OP_MASK,
437 }}, ),
438 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
439 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
440};
441
442static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
443 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
444 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
445};
446
447/*
448 * For Gen9 we can still rely on the h/w to enforce cmd security, and only
449 * need to re-enforce the register access checks. We therefore only need to
450 * teach the cmdparser how to find the end of each command, and identify
451 * register accesses. The table doesn't need to reject any commands, and so
452 * the only commands listed here are:
453 * 1) Those that touch registers
454 * 2) Those that do not have the default 8-bit length
455 *
456 * Note that the default MI length mask chosen for this table is 0xFF, not
457 * the 0x3F used on older devices. This is because the vast majority of MI
458 * cmds on Gen9 use a standard 8-bit Length field.
459 * All the Gen9 blitter instructions are standard 0xFF length mask, and
460 * none allow access to non-general registers, so in fact no BLT cmds are
461 * included in the table at all.
462 *
463 */
464static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = {
465 CMD( MI_NOOP, SMI, F, 1, S ),
466 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
467 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
468 CMD( MI_FLUSH, SMI, F, 1, S ),
469 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
470 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
471 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
472 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
473 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),
474 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),
475 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
476 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
477 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
478 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),
479 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,
480 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
481 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
482 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,
483 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
484 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
485 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
486
487 /*
488 * We allow BB_START but apply further checks. We just sanitize the
489 * basic fields here.
490 */
491#define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
492#define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1)
493 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,
494 .bits = {{
495 .offset = 0,
496 .mask = MI_BB_START_OPERAND_MASK,
497 .expected = MI_BB_START_OPERAND_EXPECT,
498 }}, ),
499};
500
501static const struct drm_i915_cmd_descriptor noop_desc =
502 CMD(MI_NOOP, SMI, F, 1, S);
503
504#undef CMD
505#undef SMI
506#undef S3D
507#undef S2D
508#undef SMFX
509#undef F
510#undef S
511#undef R
512#undef W
513#undef B
514
515static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
516 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
517 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
518};
519
520static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
521 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
522 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
523 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
524};
525
526static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
527 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
528 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
529};
530
531static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
532 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
533 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
534};
535
536static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
537 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
538 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
539};
540
541static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
542 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
543 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
544 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
545};
546
547static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = {
548 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) },
549};
550
551
552/*
553 * Register whitelists, sorted by increasing register offset.
554 */
555
556/*
557 * An individual whitelist entry granting access to register addr. If
558 * mask is non-zero the argument of immediate register writes will be
559 * AND-ed with mask, and the command will be rejected if the result
560 * doesn't match value.
561 *
562 * Registers with non-zero mask are only allowed to be written using
563 * LRI.
564 */
565struct drm_i915_reg_descriptor {
566 i915_reg_t addr;
567 u32 mask;
568 u32 value;
569};
570
571/* Convenience macro for adding 32-bit registers. */
572#define REG32(_reg, ...) \
573 { .addr = (_reg), __VA_ARGS__ }
574
575/*
576 * Convenience macro for adding 64-bit registers.
577 *
578 * Some registers that userspace accesses are 64 bits. The register
579 * access commands only allow 32-bit accesses. Hence, we have to include
580 * entries for both halves of the 64-bit registers.
581 */
582#define REG64(_reg) \
583 { .addr = _reg }, \
584 { .addr = _reg ## _UDW }
585
586#define REG64_IDX(_reg, idx) \
587 { .addr = _reg(idx) }, \
588 { .addr = _reg ## _UDW(idx) }
589
590static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
591 REG64(GPGPU_THREADS_DISPATCHED),
592 REG64(HS_INVOCATION_COUNT),
593 REG64(DS_INVOCATION_COUNT),
594 REG64(IA_VERTICES_COUNT),
595 REG64(IA_PRIMITIVES_COUNT),
596 REG64(VS_INVOCATION_COUNT),
597 REG64(GS_INVOCATION_COUNT),
598 REG64(GS_PRIMITIVES_COUNT),
599 REG64(CL_INVOCATION_COUNT),
600 REG64(CL_PRIMITIVES_COUNT),
601 REG64(PS_INVOCATION_COUNT),
602 REG64(PS_DEPTH_COUNT),
603 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
604 REG64(MI_PREDICATE_SRC0),
605 REG64(MI_PREDICATE_SRC1),
606 REG32(GEN7_3DPRIM_END_OFFSET),
607 REG32(GEN7_3DPRIM_START_VERTEX),
608 REG32(GEN7_3DPRIM_VERTEX_COUNT),
609 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
610 REG32(GEN7_3DPRIM_START_INSTANCE),
611 REG32(GEN7_3DPRIM_BASE_VERTEX),
612 REG32(GEN7_GPGPU_DISPATCHDIMX),
613 REG32(GEN7_GPGPU_DISPATCHDIMY),
614 REG32(GEN7_GPGPU_DISPATCHDIMZ),
615 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
616 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
617 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
618 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
619 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
620 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
621 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
622 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
623 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
624 REG32(GEN7_SO_WRITE_OFFSET(0)),
625 REG32(GEN7_SO_WRITE_OFFSET(1)),
626 REG32(GEN7_SO_WRITE_OFFSET(2)),
627 REG32(GEN7_SO_WRITE_OFFSET(3)),
628 REG32(GEN7_L3SQCREG1),
629 REG32(GEN7_L3CNTLREG2),
630 REG32(GEN7_L3CNTLREG3),
631 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
632};
633
634static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
635 REG64_IDX(HSW_CS_GPR, 0),
636 REG64_IDX(HSW_CS_GPR, 1),
637 REG64_IDX(HSW_CS_GPR, 2),
638 REG64_IDX(HSW_CS_GPR, 3),
639 REG64_IDX(HSW_CS_GPR, 4),
640 REG64_IDX(HSW_CS_GPR, 5),
641 REG64_IDX(HSW_CS_GPR, 6),
642 REG64_IDX(HSW_CS_GPR, 7),
643 REG64_IDX(HSW_CS_GPR, 8),
644 REG64_IDX(HSW_CS_GPR, 9),
645 REG64_IDX(HSW_CS_GPR, 10),
646 REG64_IDX(HSW_CS_GPR, 11),
647 REG64_IDX(HSW_CS_GPR, 12),
648 REG64_IDX(HSW_CS_GPR, 13),
649 REG64_IDX(HSW_CS_GPR, 14),
650 REG64_IDX(HSW_CS_GPR, 15),
651 REG32(HSW_SCRATCH1,
652 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
653 .value = 0),
654 REG32(HSW_ROW_CHICKEN3,
655 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
656 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
657 .value = 0),
658};
659
660static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
661 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
662 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
663 REG32(BCS_SWCTRL),
664 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
665};
666
667static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
668 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
669 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
670 REG32(BCS_SWCTRL),
671 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
672 REG64_IDX(BCS_GPR, 0),
673 REG64_IDX(BCS_GPR, 1),
674 REG64_IDX(BCS_GPR, 2),
675 REG64_IDX(BCS_GPR, 3),
676 REG64_IDX(BCS_GPR, 4),
677 REG64_IDX(BCS_GPR, 5),
678 REG64_IDX(BCS_GPR, 6),
679 REG64_IDX(BCS_GPR, 7),
680 REG64_IDX(BCS_GPR, 8),
681 REG64_IDX(BCS_GPR, 9),
682 REG64_IDX(BCS_GPR, 10),
683 REG64_IDX(BCS_GPR, 11),
684 REG64_IDX(BCS_GPR, 12),
685 REG64_IDX(BCS_GPR, 13),
686 REG64_IDX(BCS_GPR, 14),
687 REG64_IDX(BCS_GPR, 15),
688};
689
690#undef REG64
691#undef REG32
692
693struct drm_i915_reg_table {
694 const struct drm_i915_reg_descriptor *regs;
695 int num_regs;
696};
697
698static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
699 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
700};
701
702static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
703 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
704};
705
706static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
707 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
708 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) },
709};
710
711static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
712 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
713};
714
715static const struct drm_i915_reg_table gen9_blt_reg_tables[] = {
716 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) },
717};
718
719static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
720{
721 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
722 u32 subclient =
723 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
724
725 if (client == INSTR_MI_CLIENT)
726 return 0x3F;
727 else if (client == INSTR_RC_CLIENT) {
728 if (subclient == INSTR_MEDIA_SUBCLIENT)
729 return 0xFFFF;
730 else
731 return 0xFF;
732 }
733
734 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
735 return 0;
736}
737
738static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
739{
740 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
741 u32 subclient =
742 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
743 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
744
745 if (client == INSTR_MI_CLIENT)
746 return 0x3F;
747 else if (client == INSTR_RC_CLIENT) {
748 if (subclient == INSTR_MEDIA_SUBCLIENT) {
749 if (op == 6)
750 return 0xFFFF;
751 else
752 return 0xFFF;
753 } else
754 return 0xFF;
755 }
756
757 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
758 return 0;
759}
760
761static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
762{
763 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
764
765 if (client == INSTR_MI_CLIENT)
766 return 0x3F;
767 else if (client == INSTR_BC_CLIENT)
768 return 0xFF;
769
770 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
771 return 0;
772}
773
774static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)
775{
776 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
777
778 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT)
779 return 0xFF;
780
781 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
782 return 0;
783}
784
785static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
786 const struct drm_i915_cmd_table *cmd_tables,
787 int cmd_table_count)
788{
789 int i;
790 bool ret = true;
791
792 if (!cmd_tables || cmd_table_count == 0)
793 return true;
794
795 for (i = 0; i < cmd_table_count; i++) {
796 const struct drm_i915_cmd_table *table = &cmd_tables[i];
797 u32 previous = 0;
798 int j;
799
800 for (j = 0; j < table->count; j++) {
801 const struct drm_i915_cmd_descriptor *desc =
802 &table->table[j];
803 u32 curr = desc->cmd.value & desc->cmd.mask;
804
805 if (curr < previous) {
806 DRM_ERROR("CMD: %s [%d] command table not sorted: "
807 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
808 engine->name, engine->id,
809 i, j, curr, previous);
810 ret = false;
811 }
812
813 previous = curr;
814 }
815 }
816
817 return ret;
818}
819
820static bool check_sorted(const struct intel_engine_cs *engine,
821 const struct drm_i915_reg_descriptor *reg_table,
822 int reg_count)
823{
824 int i;
825 u32 previous = 0;
826 bool ret = true;
827
828 for (i = 0; i < reg_count; i++) {
829 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
830
831 if (curr < previous) {
832 DRM_ERROR("CMD: %s [%d] register table not sorted: "
833 "entry=%d reg=0x%08X prev=0x%08X\n",
834 engine->name, engine->id,
835 i, curr, previous);
836 ret = false;
837 }
838
839 previous = curr;
840 }
841
842 return ret;
843}
844
845static bool validate_regs_sorted(struct intel_engine_cs *engine)
846{
847 int i;
848 const struct drm_i915_reg_table *table;
849
850 for (i = 0; i < engine->reg_table_count; i++) {
851 table = &engine->reg_tables[i];
852 if (!check_sorted(engine, table->regs, table->num_regs))
853 return false;
854 }
855
856 return true;
857}
858
859struct cmd_node {
860 const struct drm_i915_cmd_descriptor *desc;
861 struct hlist_node node;
862};
863
864/*
865 * Different command ranges have different numbers of bits for the opcode. For
866 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
867 * problem is that, for example, MI commands use bits 22:16 for other fields
868 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
869 * we mask a command from a batch it could hash to the wrong bucket due to
870 * non-opcode bits being set. But if we don't include those bits, some 3D
871 * commands may hash to the same bucket due to not including opcode bits that
872 * make the command unique. For now, we will risk hashing to the same bucket.
873 */
874static inline u32 cmd_header_key(u32 x)
875{
876 switch (x >> INSTR_CLIENT_SHIFT) {
877 default:
878 case INSTR_MI_CLIENT:
879 return x >> STD_MI_OPCODE_SHIFT;
880 case INSTR_RC_CLIENT:
881 return x >> STD_3D_OPCODE_SHIFT;
882 case INSTR_BC_CLIENT:
883 return x >> STD_2D_OPCODE_SHIFT;
884 }
885}
886
887static int init_hash_table(struct intel_engine_cs *engine,
888 const struct drm_i915_cmd_table *cmd_tables,
889 int cmd_table_count)
890{
891 int i, j;
892
893 hash_init(engine->cmd_hash);
894
895 for (i = 0; i < cmd_table_count; i++) {
896 const struct drm_i915_cmd_table *table = &cmd_tables[i];
897
898 for (j = 0; j < table->count; j++) {
899 const struct drm_i915_cmd_descriptor *desc =
900 &table->table[j];
901 struct cmd_node *desc_node =
902 kmalloc(sizeof(*desc_node), GFP_KERNEL);
903
904 if (!desc_node)
905 return -ENOMEM;
906
907 desc_node->desc = desc;
908 hash_add(engine->cmd_hash, &desc_node->node,
909 cmd_header_key(desc->cmd.value));
910 }
911 }
912
913 return 0;
914}
915
916static void fini_hash_table(struct intel_engine_cs *engine)
917{
918 struct hlist_node *tmp;
919 struct cmd_node *desc_node;
920 int i;
921
922 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
923 hash_del(&desc_node->node);
924 kfree(desc_node);
925 }
926}
927
928/**
929 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
930 * @engine: the engine to initialize
931 *
932 * Optionally initializes fields related to batch buffer command parsing in the
933 * struct intel_engine_cs based on whether the platform requires software
934 * command parsing.
935 */
936void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
937{
938 const struct drm_i915_cmd_table *cmd_tables;
939 int cmd_table_count;
940 int ret;
941
942 if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&
943 engine->class == COPY_ENGINE_CLASS))
944 return;
945
946 switch (engine->class) {
947 case RENDER_CLASS:
948 if (IS_HASWELL(engine->i915)) {
949 cmd_tables = hsw_render_ring_cmd_table;
950 cmd_table_count =
951 ARRAY_SIZE(hsw_render_ring_cmd_table);
952 } else {
953 cmd_tables = gen7_render_cmd_table;
954 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
955 }
956
957 if (IS_HASWELL(engine->i915)) {
958 engine->reg_tables = hsw_render_reg_tables;
959 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
960 } else {
961 engine->reg_tables = ivb_render_reg_tables;
962 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
963 }
964 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
965 break;
966 case VIDEO_DECODE_CLASS:
967 cmd_tables = gen7_video_cmd_table;
968 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
969 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
970 break;
971 case COPY_ENGINE_CLASS:
972 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
973 if (IS_GEN(engine->i915, 9)) {
974 cmd_tables = gen9_blt_cmd_table;
975 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
976 engine->get_cmd_length_mask =
977 gen9_blt_get_cmd_length_mask;
978
979 /* BCS Engine unsafe without parser */
980 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
981 } else if (IS_HASWELL(engine->i915)) {
982 cmd_tables = hsw_blt_ring_cmd_table;
983 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
984 } else {
985 cmd_tables = gen7_blt_cmd_table;
986 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
987 }
988
989 if (IS_GEN(engine->i915, 9)) {
990 engine->reg_tables = gen9_blt_reg_tables;
991 engine->reg_table_count =
992 ARRAY_SIZE(gen9_blt_reg_tables);
993 } else if (IS_HASWELL(engine->i915)) {
994 engine->reg_tables = hsw_blt_reg_tables;
995 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
996 } else {
997 engine->reg_tables = ivb_blt_reg_tables;
998 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
999 }
1000 break;
1001 case VIDEO_ENHANCEMENT_CLASS:
1002 cmd_tables = hsw_vebox_cmd_table;
1003 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
1004 /* VECS can use the same length_mask function as VCS */
1005 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
1006 break;
1007 default:
1008 MISSING_CASE(engine->class);
1009 return;
1010 }
1011
1012 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
1013 DRM_ERROR("%s: command descriptions are not sorted\n",
1014 engine->name);
1015 return;
1016 }
1017 if (!validate_regs_sorted(engine)) {
1018 DRM_ERROR("%s: registers are not sorted\n", engine->name);
1019 return;
1020 }
1021
1022 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
1023 if (ret) {
1024 DRM_ERROR("%s: initialised failed!\n", engine->name);
1025 fini_hash_table(engine);
1026 return;
1027 }
1028
1029 engine->flags |= I915_ENGINE_USING_CMD_PARSER;
1030}
1031
1032/**
1033 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1034 * @engine: the engine to clean up
1035 *
1036 * Releases any resources related to command parsing that may have been
1037 * initialized for the specified engine.
1038 */
1039void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
1040{
1041 if (!intel_engine_using_cmd_parser(engine))
1042 return;
1043
1044 fini_hash_table(engine);
1045}
1046
1047static const struct drm_i915_cmd_descriptor*
1048find_cmd_in_table(struct intel_engine_cs *engine,
1049 u32 cmd_header)
1050{
1051 struct cmd_node *desc_node;
1052
1053 hash_for_each_possible(engine->cmd_hash, desc_node, node,
1054 cmd_header_key(cmd_header)) {
1055 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
1056 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1057 return desc;
1058 }
1059
1060 return NULL;
1061}
1062
1063/*
1064 * Returns a pointer to a descriptor for the command specified by cmd_header.
1065 *
1066 * The caller must supply space for a default descriptor via the default_desc
1067 * parameter. If no descriptor for the specified command exists in the engine's
1068 * command parser tables, this function fills in default_desc based on the
1069 * engine's default length encoding and returns default_desc.
1070 */
1071static const struct drm_i915_cmd_descriptor*
1072find_cmd(struct intel_engine_cs *engine,
1073 u32 cmd_header,
1074 const struct drm_i915_cmd_descriptor *desc,
1075 struct drm_i915_cmd_descriptor *default_desc)
1076{
1077 u32 mask;
1078
1079 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1080 return desc;
1081
1082 desc = find_cmd_in_table(engine, cmd_header);
1083 if (desc)
1084 return desc;
1085
1086 mask = engine->get_cmd_length_mask(cmd_header);
1087 if (!mask)
1088 return NULL;
1089
1090 default_desc->cmd.value = cmd_header;
1091 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1092 default_desc->length.mask = mask;
1093 default_desc->flags = CMD_DESC_SKIP;
1094 return default_desc;
1095}
1096
1097static const struct drm_i915_reg_descriptor *
1098__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1099{
1100 int start = 0, end = count;
1101 while (start < end) {
1102 int mid = start + (end - start) / 2;
1103 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1104 if (ret < 0)
1105 end = mid;
1106 else if (ret > 0)
1107 start = mid + 1;
1108 else
1109 return &table[mid];
1110 }
1111 return NULL;
1112}
1113
1114static const struct drm_i915_reg_descriptor *
1115find_reg(const struct intel_engine_cs *engine, u32 addr)
1116{
1117 const struct drm_i915_reg_table *table = engine->reg_tables;
1118 const struct drm_i915_reg_descriptor *reg = NULL;
1119 int count = engine->reg_table_count;
1120
1121 for (; !reg && (count > 0); ++table, --count)
1122 reg = __find_reg(table->regs, table->num_regs, addr);
1123
1124 return reg;
1125}
1126
1127/* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1128static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1129 struct drm_i915_gem_object *src_obj,
1130 u32 batch_start_offset,
1131 u32 batch_len,
1132 bool *needs_clflush_after)
1133{
1134 unsigned int src_needs_clflush;
1135 unsigned int dst_needs_clflush;
1136 void *dst, *src;
1137 int ret;
1138
1139 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush);
1140 if (ret)
1141 return ERR_PTR(ret);
1142
1143 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);
1144 i915_gem_object_finish_access(dst_obj);
1145 if (IS_ERR(dst))
1146 return dst;
1147
1148 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush);
1149 if (ret) {
1150 i915_gem_object_unpin_map(dst_obj);
1151 return ERR_PTR(ret);
1152 }
1153
1154 src = ERR_PTR(-ENODEV);
1155 if (src_needs_clflush &&
1156 i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {
1157 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1158 if (!IS_ERR(src)) {
1159 i915_memcpy_from_wc(dst,
1160 src + batch_start_offset,
1161 ALIGN(batch_len, 16));
1162 i915_gem_object_unpin_map(src_obj);
1163 }
1164 }
1165 if (IS_ERR(src)) {
1166 void *ptr;
1167 int offset, n;
1168
1169 offset = offset_in_page(batch_start_offset);
1170
1171 /* We can avoid clflushing partial cachelines before the write
1172 * if we only every write full cache-lines. Since we know that
1173 * both the source and destination are in multiples of
1174 * PAGE_SIZE, we can simply round up to the next cacheline.
1175 * We don't care about copying too much here as we only
1176 * validate up to the end of the batch.
1177 */
1178 if (dst_needs_clflush & CLFLUSH_BEFORE)
1179 batch_len = roundup(batch_len,
1180 boot_cpu_data.x86_clflush_size);
1181
1182 ptr = dst;
1183 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) {
1184 int len = min_t(int, batch_len, PAGE_SIZE - offset);
1185
1186 src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1187 if (src_needs_clflush)
1188 drm_clflush_virt_range(src + offset, len);
1189 memcpy(ptr, src + offset, len);
1190 kunmap_atomic(src);
1191
1192 ptr += len;
1193 batch_len -= len;
1194 offset = 0;
1195 }
1196 }
1197
1198 i915_gem_object_finish_access(src_obj);
1199
1200 /* dst_obj is returned with vmap pinned */
1201 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1202
1203 return dst;
1204}
1205
1206static bool check_cmd(const struct intel_engine_cs *engine,
1207 const struct drm_i915_cmd_descriptor *desc,
1208 const u32 *cmd, u32 length)
1209{
1210 if (desc->flags & CMD_DESC_SKIP)
1211 return true;
1212
1213 if (desc->flags & CMD_DESC_REJECT) {
1214 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1215 return false;
1216 }
1217
1218 if (desc->flags & CMD_DESC_REGISTER) {
1219 /*
1220 * Get the distance between individual register offset
1221 * fields if the command can perform more than one
1222 * access at a time.
1223 */
1224 const u32 step = desc->reg.step ? desc->reg.step : length;
1225 u32 offset;
1226
1227 for (offset = desc->reg.offset; offset < length;
1228 offset += step) {
1229 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1230 const struct drm_i915_reg_descriptor *reg =
1231 find_reg(engine, reg_addr);
1232
1233 if (!reg) {
1234 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1235 reg_addr, *cmd, engine->name);
1236 return false;
1237 }
1238
1239 /*
1240 * Check the value written to the register against the
1241 * allowed mask/value pair given in the whitelist entry.
1242 */
1243 if (reg->mask) {
1244 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1245 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1246 reg_addr);
1247 return false;
1248 }
1249
1250 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1251 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
1252 reg_addr);
1253 return false;
1254 }
1255
1256 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1257 (offset + 2 > length ||
1258 (cmd[offset + 1] & reg->mask) != reg->value)) {
1259 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1260 reg_addr);
1261 return false;
1262 }
1263 }
1264 }
1265 }
1266
1267 if (desc->flags & CMD_DESC_BITMASK) {
1268 int i;
1269
1270 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1271 u32 dword;
1272
1273 if (desc->bits[i].mask == 0)
1274 break;
1275
1276 if (desc->bits[i].condition_mask != 0) {
1277 u32 offset =
1278 desc->bits[i].condition_offset;
1279 u32 condition = cmd[offset] &
1280 desc->bits[i].condition_mask;
1281
1282 if (condition == 0)
1283 continue;
1284 }
1285
1286 if (desc->bits[i].offset >= length) {
1287 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1288 *cmd, engine->name);
1289 return false;
1290 }
1291
1292 dword = cmd[desc->bits[i].offset] &
1293 desc->bits[i].mask;
1294
1295 if (dword != desc->bits[i].expected) {
1296 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1297 *cmd,
1298 desc->bits[i].mask,
1299 desc->bits[i].expected,
1300 dword, engine->name);
1301 return false;
1302 }
1303 }
1304 }
1305
1306 return true;
1307}
1308
1309static int check_bbstart(const struct i915_gem_context *ctx,
1310 u32 *cmd, u32 offset, u32 length,
1311 u32 batch_len,
1312 u64 batch_start,
1313 u64 shadow_batch_start)
1314{
1315 u64 jump_offset, jump_target;
1316 u32 target_cmd_offset, target_cmd_index;
1317
1318 /* For igt compatibility on older platforms */
1319 if (CMDPARSER_USES_GGTT(ctx->i915)) {
1320 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n");
1321 return -EACCES;
1322 }
1323
1324 if (length != 3) {
1325 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n",
1326 length);
1327 return -EINVAL;
1328 }
1329
1330 jump_target = *(u64*)(cmd+1);
1331 jump_offset = jump_target - batch_start;
1332
1333 /*
1334 * Any underflow of jump_target is guaranteed to be outside the range
1335 * of a u32, so >= test catches both too large and too small
1336 */
1337 if (jump_offset >= batch_len) {
1338 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n",
1339 jump_target);
1340 return -EINVAL;
1341 }
1342
1343 /*
1344 * This cannot overflow a u32 because we already checked jump_offset
1345 * is within the BB, and the batch_len is a u32
1346 */
1347 target_cmd_offset = lower_32_bits(jump_offset);
1348 target_cmd_index = target_cmd_offset / sizeof(u32);
1349
1350 *(u64*)(cmd + 1) = shadow_batch_start + target_cmd_offset;
1351
1352 if (target_cmd_index == offset)
1353 return 0;
1354
1355 if (ctx->jump_whitelist_cmds <= target_cmd_index) {
1356 DRM_DEBUG("CMD: Rejecting BB_START - truncated whitelist array\n");
1357 return -EINVAL;
1358 } else if (!test_bit(target_cmd_index, ctx->jump_whitelist)) {
1359 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1360 jump_target);
1361 return -EINVAL;
1362 }
1363
1364 return 0;
1365}
1366
1367static void init_whitelist(struct i915_gem_context *ctx, u32 batch_len)
1368{
1369 const u32 batch_cmds = DIV_ROUND_UP(batch_len, sizeof(u32));
1370 const u32 exact_size = BITS_TO_LONGS(batch_cmds);
1371 u32 next_size = BITS_TO_LONGS(roundup_pow_of_two(batch_cmds));
1372 unsigned long *next_whitelist;
1373
1374 if (CMDPARSER_USES_GGTT(ctx->i915))
1375 return;
1376
1377 if (batch_cmds <= ctx->jump_whitelist_cmds) {
1378 bitmap_zero(ctx->jump_whitelist, batch_cmds);
1379 return;
1380 }
1381
1382again:
1383 next_whitelist = kcalloc(next_size, sizeof(long), GFP_KERNEL);
1384 if (next_whitelist) {
1385 kfree(ctx->jump_whitelist);
1386 ctx->jump_whitelist = next_whitelist;
1387 ctx->jump_whitelist_cmds =
1388 next_size * BITS_PER_BYTE * sizeof(long);
1389 return;
1390 }
1391
1392 if (next_size > exact_size) {
1393 next_size = exact_size;
1394 goto again;
1395 }
1396
1397 DRM_DEBUG("CMD: Failed to extend whitelist. BB_START may be disallowed\n");
1398 bitmap_zero(ctx->jump_whitelist, ctx->jump_whitelist_cmds);
1399
1400 return;
1401}
1402
1403#define LENGTH_BIAS 2
1404
1405/**
1406 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1407 * @ctx: the context in which the batch is to execute
1408 * @engine: the engine on which the batch is to execute
1409 * @batch_obj: the batch buffer in question
1410 * @batch_start: Canonical base address of batch
1411 * @batch_start_offset: byte offset in the batch at which execution starts
1412 * @batch_len: length of the commands in batch_obj
1413 * @shadow_batch_obj: copy of the batch buffer in question
1414 * @shadow_batch_start: Canonical base address of shadow_batch_obj
1415 *
1416 * Parses the specified batch buffer looking for privilege violations as
1417 * described in the overview.
1418 *
1419 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1420 * if the batch appears legal but should use hardware parsing
1421 */
1422
1423int intel_engine_cmd_parser(struct i915_gem_context *ctx,
1424 struct intel_engine_cs *engine,
1425 struct drm_i915_gem_object *batch_obj,
1426 u64 batch_start,
1427 u32 batch_start_offset,
1428 u32 batch_len,
1429 struct drm_i915_gem_object *shadow_batch_obj,
1430 u64 shadow_batch_start)
1431{
1432 u32 *cmd, *batch_end, offset = 0;
1433 struct drm_i915_cmd_descriptor default_desc = noop_desc;
1434 const struct drm_i915_cmd_descriptor *desc = &default_desc;
1435 bool needs_clflush_after = false;
1436 int ret = 0;
1437
1438 cmd = copy_batch(shadow_batch_obj, batch_obj,
1439 batch_start_offset, batch_len,
1440 &needs_clflush_after);
1441 if (IS_ERR(cmd)) {
1442 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1443 return PTR_ERR(cmd);
1444 }
1445
1446 init_whitelist(ctx, batch_len);
1447
1448 /*
1449 * We use the batch length as size because the shadow object is as
1450 * large or larger and copy_batch() will write MI_NOPs to the extra
1451 * space. Parsing should be faster in some cases this way.
1452 */
1453 batch_end = cmd + (batch_len / sizeof(*batch_end));
1454 do {
1455 u32 length;
1456
1457 if (*cmd == MI_BATCH_BUFFER_END)
1458 break;
1459
1460 desc = find_cmd(engine, *cmd, desc, &default_desc);
1461 if (!desc) {
1462 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1463 *cmd);
1464 ret = -EINVAL;
1465 goto err;
1466 }
1467
1468 if (desc->flags & CMD_DESC_FIXED)
1469 length = desc->length.fixed;
1470 else
1471 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1472
1473 if ((batch_end - cmd) < length) {
1474 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1475 *cmd,
1476 length,
1477 batch_end - cmd);
1478 ret = -EINVAL;
1479 goto err;
1480 }
1481
1482 if (!check_cmd(engine, desc, cmd, length)) {
1483 ret = -EACCES;
1484 goto err;
1485 }
1486
1487 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1488 ret = check_bbstart(ctx, cmd, offset, length,
1489 batch_len, batch_start,
1490 shadow_batch_start);
1491
1492 if (ret)
1493 goto err;
1494 break;
1495 }
1496
1497 if (ctx->jump_whitelist_cmds > offset)
1498 set_bit(offset, ctx->jump_whitelist);
1499
1500 cmd += length;
1501 offset += length;
1502 if (cmd >= batch_end) {
1503 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1504 ret = -EINVAL;
1505 goto err;
1506 }
1507 } while (1);
1508
1509 if (needs_clflush_after) {
1510 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);
1511
1512 drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr);
1513 }
1514
1515err:
1516 i915_gem_object_unpin_map(shadow_batch_obj);
1517 return ret;
1518}
1519
1520/**
1521 * i915_cmd_parser_get_version() - get the cmd parser version number
1522 * @dev_priv: i915 device private
1523 *
1524 * The cmd parser maintains a simple increasing integer version number suitable
1525 * for passing to userspace clients to determine what operations are permitted.
1526 *
1527 * Return: the current version number of the cmd parser
1528 */
1529int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1530{
1531 struct intel_engine_cs *engine;
1532 bool active = false;
1533
1534 /* If the command parser is not enabled, report 0 - unsupported */
1535 for_each_uabi_engine(engine, dev_priv) {
1536 if (intel_engine_using_cmd_parser(engine)) {
1537 active = true;
1538 break;
1539 }
1540 }
1541 if (!active)
1542 return 0;
1543
1544 /*
1545 * Command parser version history
1546 *
1547 * 1. Initial version. Checks batches and reports violations, but leaves
1548 * hardware parsing enabled (so does not allow new use cases).
1549 * 2. Allow access to the MI_PREDICATE_SRC0 and
1550 * MI_PREDICATE_SRC1 registers.
1551 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1552 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1553 * 5. GPGPU dispatch compute indirect registers.
1554 * 6. TIMESTAMP register and Haswell CS GPR registers
1555 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1556 * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1557 * rely on the HW to NOOP disallowed commands as it would without
1558 * the parser enabled.
1559 * 9. Don't whitelist or handle oacontrol specially, as ownership
1560 * for oacontrol state is moving to i915-perf.
1561 * 10. Support for Gen9 BCS Parsing
1562 */
1563 return 10;
1564}